[SPARC][IAS] Add definitions for v9 State Registers

[koakuma]

Summary

This adds definitions for SPARC v9 State Registers (privileged/nonprivileged, see v9 manual ch. 5).

Depends on D157230

[barannikov88]

llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

1316–1317

I guess this comment can be removed.

llvm/lib/Target/Sparc/SparcInstrAliases.td

526–527

Isn't this covered by the first InstAlias in the group?

llvm/lib/Target/Sparc/SparcRegisterInfo.td

135

It looks like these registers are actually aliases to %asrXX (or vice versa). They should use the corresponding functionality instead of being redefined.
See RegAltNameIndex in Target.td and how other targets use it.

378

See the comment above about RegAltNameIndex.

llvm/test/MC/Sparc/sparcv9-instructions.s

425–440

IIUC all of these should complain about missing feature on V8. This can probably be done by adding some checks to validateTargetOperandClass or checkTargetMatchPredicate.

[koakuma]

Merge unprivileged ASR definitions & remove some unused code.

llvm/lib/Target/Sparc/SparcRegisterInfo.td

135

The privileged ones are on a separate register file from the ASRs, so those need to be defined separately.

The unprivileged ones can be merged with the ASRs, however, I have a question about the handling of %tick/%asr4.
The same register can be viewed through nonprivileged (rd %tick/rd %asr4) or privileged (rdpr %tick) instructions, however, since the two are modeled using different objects, it is quite difficult to make it usable by both instructions.
Currently I am special casing it so that privileged TICK can also be read by rd. Is there any better way to do this or will this do for now?

llvm/test/MC/Sparc/sparcv9-instructions.s

425–440

How do I do this? Seems like in both functions I can only get the raw register number, I don't know how to recover the textual name (e.g whether it was originally referred to as %asi or %asr3)...

[barannikov88]

llvm/lib/Target/Sparc/SparcRegisterInfo.td

135

I can't suggest anything better. Do other assemblers accept %asr1-6? The manual says there are only %asr7-31 (with 7-15 reserved for future use).
Note that adding TICK to ASRRegs allows it to be used in wr instruction, which isn't allowed by the manual (A.63 Write State Register).

llvm/test/MC/Sparc/sparc-special-registers.s

52

RUN lines are conventionally at the start of a file. They can be combined with the existing RUN lines like this:

! RUN: llvm-mc %s -arch=sparc   -show-encoding | FileCheck %s --check-prefixes=CHECK,V8
! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefixes=CHECK,V9

Note the --check-prefixes option.

llvm/test/MC/Sparc/sparcv9-instructions.s

425–440

validateTargetOperandClass allows you to examine whatever you stored in SparcOperand. If the spelling is important, you can store that information there, see e.g. RegOp::RegisterKind.
The method should probably return Match_MissingFeature on failure.

[barannikov88]

llvm/test/MC/Sparc/sparcv9-instructions.s

425–440

There may be other solutions, but I'm not sure I understand the issue.

[koakuma]

llvm/lib/Target/Sparc/SparcRegisterInfo.td

135

GCC's assembler, at least, accepts the names %asr1-6 with both rd and wr, including the forbidden wr to %asr4/TICK and %asr5/PC.
Sun's, on the other hand, accepts the names %asr1-6 when using it with rd, but forbids it with wr.

llvm/test/MC/Sparc/sparcv9-instructions.s

425–440

The problem is that, for example, the two textual forms are encoded the same:

rd %asr5, %i0
rd %pc, %i0

But the latter form is only allowed when targeting V9, so I want to be able to recover the textual names instead of just the register number?
For comparison, GCC does disallow the %pc form when targeting non-V9 subarches (Sun's does not support targeting non-V9s in the first place).

[barannikov88]

llvm/test/MC/Sparc/sparcv9-instructions.s

425–440

When parsing a register (SparcAsmParser::matchRegisterName) you can record the spelling (as a flag/enum or string), pass it to SparcOperand::CreateReg and store in SparcOperand::RegOp, similar to RegisterKind. Then you can override checkEarlyTargetMatchPredicate where you can examine the spelling and filter out those that are invalid for the instruction and processor mode depending on the instruction opcode. If the opcode is not important (e.g. %pc is invalid for all instructions in V8 mode), then you can do the same in validateTargetOperandClass.

The tests should cover all register number/ register spelling / processor mode combinations, and there should also be disassembler tests for all combinations of registers / instructions / processor mode.

If all that sounds too difficult, can you add a TODO with the desired behavior somehwere? I.e. which processor mode / instruction allows which spelling?

[koakuma]

• Add remarks about odd behavior for V8 (it accepts V9 ASR alias names, which it shouldn't). This should not be a problem in practice - all existing V8 code will still be accepted, and people who write V8 code are unlikely to use V9 alias names. This will be addressed in a future patch, so for now we're focusing on enabling V9 assembly support.
• Add more tests for %asr2-%asr6 & their alternate names.

[barannikov88]

LGTM

[barannikov88]

@koakuma If you don't have commit access I think it's time to apply for it.

[brad]

In D157231#4635857, @barannikov88 wrote:

@koakuma If you don't have commit access I think it's time to apply for it.

I agree, that would be a good idea.

llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) {
         Op = SparcOperand::CreateToken("%cq", S);
         break;
       case Sparc::WIM:
         Op = SparcOperand::CreateToken("%wim", S);
         break;
       case Sparc::TBR:
         Op = SparcOperand::CreateToken("%tbr", S);
         break;
-      case Sparc::PC:
-        Op = SparcOperand::CreateToken("%pc", S);
-        break;
       case Sparc::ICC:
         if (name == "xcc")
           Op = SparcOperand::CreateToken("%xcc", S);
         else
           Op = SparcOperand::CreateToken("%icc", S);
         break;
       }
       break;
if (Tok.is(AsmToken::Identifier)) {
     }
 
     if (name.substr(0, 3).equals_insensitive("asr") &&
         !name.substr(3).getAsInteger(10, intVal) && intVal > 0 && intVal < 32) {
       RegNo = ASRRegs[intVal];
       RegKind = SparcOperand::rk_Special;
       return true;
     }
 
-    // %fprs is an alias of %asr6.
     if (name.equals("fprs")) {
-      RegNo = ASRRegs[6];
+      RegNo = Sparc::ASR6;
       RegKind = SparcOperand::rk_Special;
       return true;
     }
 
     if (name.equals("icc")) {
       RegNo = Sparc::ICC;
       RegKind = SparcOperand::rk_Special;
       return true;
if (name.equals("otherwin")) {
       return true;
     }
     if (name.equals("wstate")) {
       RegNo = Sparc::WSTATE;
       RegKind = SparcOperand::rk_Special;
       return true;
     }
     if (name.equals("pc")) {
-      RegNo = Sparc::PC;
+      RegNo = Sparc::ASR5;
+      RegKind = SparcOperand::rk_Special;
+      return true;
+    }
+    if (name.equals("asi")) {
+      RegNo = Sparc::ASR3;
+      RegKind = SparcOperand::rk_Special;
+      return true;
+    }
+    if (name.equals("ccr")) {
+      RegNo = Sparc::ASR2;
+      RegKind = SparcOperand::rk_Special;
+      return true;
+    }
+    if (name.equals("gl")) {
+      RegNo = Sparc::GL;
+      RegKind = SparcOperand::rk_Special;
+      return true;
+    }
+    if (name.equals("ver")) {
+      RegNo = Sparc::VER;
       RegKind = SparcOperand::rk_Special;
       return true;
     }
   }
   return false;
 }
 
 // Determine if an expression contains a reference to the symbol

llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp

static const unsigned QFPRegDecoderTable[] = {
   SP::Q5,  SP::Q13,  ~0U,  ~0U,
   SP::Q6,  SP::Q14,  ~0U,  ~0U,
   SP::Q7,  SP::Q15,  ~0U,  ~0U } ;
 
 static const unsigned FCCRegDecoderTable[] = {
   SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };
 
 static const unsigned ASRRegDecoderTable[] = {
-  SP::Y,     SP::ASR1,  SP::ASR2,  SP::ASR3,
-  SP::ASR4,  SP::ASR5,  SP::ASR6,  SP::ASR7,
-  SP::ASR8,  SP::ASR9,  SP::ASR10, SP::ASR11,
-  SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
-  SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
-  SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
-  SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
+    SP::Y,     SP::ASR1,  SP::ASR2,  SP::ASR3,  SP::ASR4,  SP::ASR5,  SP::ASR6,
+    SP::ASR7,  SP::ASR8,  SP::ASR9,  SP::ASR10, SP::ASR11, SP::ASR12, SP::ASR13,
+    SP::ASR14, SP::ASR15, SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19, SP::ASR20,
+    SP::ASR21, SP::ASR22, SP::ASR23, SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
     SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
 
 static const unsigned PRRegDecoderTable[] = {
-  SP::TPC, SP::TNPC, SP::TSTATE, SP::TT, SP::TICK, SP::TBA, SP::PSTATE,
-  SP::TL, SP::PIL, SP::CWP, SP::CANSAVE, SP::CANRESTORE, SP::CLEANWIN,
-  SP::OTHERWIN, SP::WSTATE, SP::PC
-};
+    SP::TPC,     SP::TNPC,       SP::TSTATE,   SP::TT,       SP::TICK,
+    SP::TBA,     SP::PSTATE,     SP::TL,       SP::PIL,      SP::CWP,
+    SP::CANSAVE, SP::CANRESTORE, SP::CLEANWIN, SP::OTHERWIN, SP::WSTATE};
 
 static const uint16_t IntPairDecoderTable[] = {
   SP::G0_G1, SP::G2_G3, SP::G4_G5, SP::G6_G7,
   SP::O0_O1, SP::O2_O3, SP::O4_O5, SP::O6_O7,
   SP::L0_L1, SP::L2_L3, SP::L4_L5, SP::L6_L7,
   SP::I0_I1, SP::I2_I3, SP::I4_I5, SP::I6_I7,
 };
 

llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h

 //===-- SparcInstPrinter.h - Convert Sparc MCInst to assembly syntax ------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This class prints an Sparc MCInst to a .s file.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCINSTPRINTER_H
 #define LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCINSTPRINTER_H
 
+#include "SparcMCTargetDesc.h"
 #include "llvm/MC/MCInstPrinter.h"
 
 namespace llvm {
 
 class SparcInstPrinter : public MCInstPrinter {
 public:
   SparcInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
                    const MCRegisterInfo &MRI)
       : MCInstPrinter(MAI, MII, MRI) {}
 
   void printRegName(raw_ostream &OS, MCRegister Reg) const override;
+  void printRegName(raw_ostream &OS, MCRegister Reg, unsigned AltIdx) const;
   void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
                  const MCSubtargetInfo &STI, raw_ostream &O) override;
   bool printSparcAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
                             raw_ostream &OS);
   bool isV9(const MCSubtargetInfo &STI) const;
 
   // Autogenerated by tblgen.
   std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
   void printInstruction(const MCInst *MI, uint64_t Address,
                         const MCSubtargetInfo &STI, raw_ostream &O);
   bool printAliasInstr(const MCInst *MI, uint64_t Address,
                        const MCSubtargetInfo &STI, raw_ostream &O);
   void printCustomAliasOperand(const MCInst *MI, uint64_t Address,
                                unsigned OpIdx, unsigned PrintMethodIdx,
                                const MCSubtargetInfo &STI, raw_ostream &O);
-  static const char *getRegisterName(MCRegister Reg);
+  static const char *getRegisterName(MCRegister Reg,
+                                     unsigned AltIdx = SP::NoRegAltName);
 
   void printOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
                     raw_ostream &OS);
   void printMemOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
                        raw_ostream &OS, const char *Modifier = nullptr);
   void printCCOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
                       raw_ostream &OS);
   bool printGetPCX(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
                    raw_ostream &OS);
   void printMembarTag(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
                       raw_ostream &O);
 };
 } // end namespace llvm
 
 #endif

llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp

 bool SparcInstPrinter::isV9(const MCSubtargetInfo &STI) const {
   return (STI.hasFeature(Sparc::FeatureV9)) != 0;
 }
 
 void SparcInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const {
   OS << '%' << StringRef(getRegisterName(Reg)).lower();
 }
 
+void SparcInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg,
+                                    unsigned AltIdx) const {
+  OS << '%' << StringRef(getRegisterName(Reg, AltIdx)).lower();
+}
+
 void SparcInstPrinter::printInst(const MCInst *MI, uint64_t Address,
                                  StringRef Annot, const MCSubtargetInfo &STI,
                                  raw_ostream &O) {
   if (!printAliasInstr(MI, Address, STI, O) &&
       !printSparcAliasInstr(MI, STI, O))
     printInstruction(MI, Address, STI, O);
   printAnnotation(O, Annot);
 }

 }
 
 void SparcInstPrinter::printOperand(const MCInst *MI, int opNum,
                                     const MCSubtargetInfo &STI,
                                     raw_ostream &O) {
   const MCOperand &MO = MI->getOperand (opNum);
 
   if (MO.isReg()) {
-    printRegName(O, MO.getReg());
+    unsigned Reg = MO.getReg();
+    if (isV9(STI))
+      printRegName(O, Reg, SP::RegNamesStateReg);
+    else
+      printRegName(O, Reg);
     return ;
   }
 
   if (MO.isImm()) {
     switch (MI->getOpcode()) {
       default:
         O << (int)MO.getImm();
         return;

llvm/lib/Target/Sparc/SparcInstrAliases.td

 // mov reg_or_imm, rd -> or %g0, reg_or_imm, rd
 def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>;
 def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>;
 
 // mov specialreg, rd -> rd specialreg, rd
 def : InstAlias<"mov $asr, $rd", (RDASR IntRegs:$rd, ASRRegs:$asr), 0>;
 def : InstAlias<"mov %psr, $rd", (RDPSR IntRegs:$rd), 0>;
 def : InstAlias<"mov %wim, $rd", (RDWIM IntRegs:$rd), 0>;
 def : InstAlias<"mov %tbr, $rd", (RDTBR IntRegs:$rd), 0>;
-def : InstAlias<"mov %pc, $rd", (RDPC IntRegs:$rd), 0>;
 
 // mov reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg
 def : InstAlias<"mov $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;
 def : InstAlias<"mov $simm13, $asr", (WRASRri ASRRegs:$asr, G0, i32imm:$simm13), 0>;
 def : InstAlias<"mov $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>;
 def : InstAlias<"mov $simm13, %psr", (WRPSRri G0, i32imm:$simm13), 0>;
 def : InstAlias<"mov $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>;
 def : InstAlias<"mov $simm13, %wim", (WRWIMri G0, i32imm:$simm13), 0>;
 def : InstAlias<"mov $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>;

llvm/lib/Target/Sparc/SparcInstrInfo.td

def RDWIM : F3_1<2, 0b101010,
          "rd %wim, $rd", []>;
 
   let rs2 = 0, rs1 = 0, Uses=[TBR] in
     def RDTBR : F3_1<2, 0b101011,
          (outs IntRegs:$rd), (ins),
          "rd %tbr, $rd", []>;
 }
 
-// PC don't exist on the SparcV8, only the V9.
-let Predicates = [HasV9] in {
-  let rs2 = 0, rs1 = 5 in
-    def RDPC : F3_1<2, 0b101000,
-         (outs IntRegs:$rd), (ins),
-         "rd %pc, $rd", []>;
-}
-
 // Section B.29 - Write State Register Instructions
 def WRASRrr : F3_1<2, 0b110000,
                  (outs ASRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
                  "wr $rs1, $rs2, $rd", []>;
 def WRASRri : F3_2<2, 0b110000,
                  (outs ASRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
                  "wr $rs1, $simm13, $rd", []>;
 

llvm/lib/Target/Sparc/SparcRegisterInfo.td

 //  Declarations that describe the Sparc register file
 //===----------------------------------------------------------------------===//
 
 class SparcReg<bits<16> Enc, string n> : Register<n> {
   let HWEncoding = Enc;
   let Namespace = "SP";
 }
 
-class SparcCtrlReg<bits<16> Enc, string n>: Register<n> {
+class SparcCtrlReg<bits<16> Enc, string n,
+                   list<string> altNames = []>: Register<n, altNames> {
   let HWEncoding = Enc;
   let Namespace = "SP";
 }
 
 let Namespace = "SP" in {
 def sub_even : SubRegIndex<32>;
 def sub_odd  : SubRegIndex<32, 32>;
 def sub_even64 : SubRegIndex<64>;
 def sub_odd64  : SubRegIndex<64, 64>;
 }
 
+let Namespace = "SP",
+    FallbackRegAltNameIndex = NoRegAltName in {
+  def RegNamesStateReg : RegAltNameIndex;
+}
+
 // Registers are identified with 5-bit ID numbers.
 // Ri - 32-bit integer registers
 class Ri<bits<16> Enc, string n> : SparcReg<Enc, n>;
 
 // Rdi - pairs of 32-bit integer registers
 class Rdi<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
   let SubRegs = subregs;
   let SubRegIndices = [sub_even, sub_odd];

 def CPSR : SparcCtrlReg<0, "CPSR">; // Co-processor state register.
 
 def CPQ : SparcCtrlReg<0, "CPQ">; // Co-processor queue.
 
 // Y register
 def Y : SparcCtrlReg<0, "Y">, DwarfRegNum<[64]>;
 // Ancillary state registers (implementation defined)
 def ASR1 : SparcCtrlReg<1, "ASR1">;
-def ASR2 : SparcCtrlReg<2, "ASR2">;
-def ASR3 : SparcCtrlReg<3, "ASR3">;
-def ASR4 : SparcCtrlReg<4, "ASR4">;
-def ASR5 : SparcCtrlReg<5, "ASR5">;
-def ASR6 : SparcCtrlReg<6, "ASR6">;
+let RegAltNameIndices = [RegNamesStateReg] in {
+def ASR2 : SparcCtrlReg<2, "ASR2", ["CCR"]>;
+def ASR3 : SparcCtrlReg<3, "ASR3", ["ASI"]>;
+def ASR4 : SparcCtrlReg<4, "ASR4", ["TICK"]>;
+def ASR5 : SparcCtrlReg<5, "ASR5", ["PC"]>;
+def ASR6 : SparcCtrlReg<6, "ASR6", ["FPRS"]>;
+}
 def ASR7 : SparcCtrlReg<7, "ASR7">;
 def ASR8 : SparcCtrlReg<8, "ASR8">;
 def ASR9 : SparcCtrlReg<9, "ASR9">;
 def ASR10 : SparcCtrlReg<10, "ASR10">;
 def ASR11 : SparcCtrlReg<11, "ASR11">;
 def ASR12 : SparcCtrlReg<12, "ASR12">;
 def ASR13 : SparcCtrlReg<13, "ASR13">;
 def ASR14 : SparcCtrlReg<14, "ASR14">;

 def ASR29 : SparcCtrlReg<29, "ASR29">;
 def ASR30 : SparcCtrlReg<30, "ASR30">;
 def ASR31 : SparcCtrlReg<31, "ASR31">;
 
 // Note that PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
 def PSR : SparcCtrlReg<0, "PSR">;
 def WIM : SparcCtrlReg<0, "WIM">;
 def TBR : SparcCtrlReg<0, "TBR">;
-// PC on the other hand is only available for SparcV9.
-def PC : SparcCtrlReg<5, "PC">;
 
-def TPC : SparcCtrlReg<0, "TPC">;
-def TNPC : SparcCtrlReg<1, "TNPC">;
-def TSTATE : SparcCtrlReg<2, "TSTATE">;
-def TT : SparcCtrlReg<3, "TT">;
-def TICK : SparcCtrlReg<4, "TICK">;
-def TBA : SparcCtrlReg<5, "TBA">;
-def PSTATE : SparcCtrlReg<6, "PSTATE">;
-def TL : SparcCtrlReg<7, "TL">;
-def PIL : SparcCtrlReg<8, "PIL">;
-def CWP : SparcCtrlReg<9, "CWP">;
-def CANSAVE : SparcCtrlReg<10, "CANSAVE">;
+// Privileged V9 state registers
+def TPC        : SparcCtrlReg<0, "TPC">;
+def TNPC       : SparcCtrlReg<1, "TNPC">;
+def TSTATE     : SparcCtrlReg<2, "TSTATE">;
+def TT         : SparcCtrlReg<3, "TT">;
+def TICK       : SparcCtrlReg<4, "TICK">;
+def TBA        : SparcCtrlReg<5, "TBA">;
+def PSTATE     : SparcCtrlReg<6, "PSTATE">;
+def TL         : SparcCtrlReg<7, "TL">;
+def PIL        : SparcCtrlReg<8, "PIL">;
+def CWP        : SparcCtrlReg<9, "CWP">;
+def CANSAVE    : SparcCtrlReg<10, "CANSAVE">;
 def CANRESTORE : SparcCtrlReg<11, "CANRESTORE">;
-def CLEANWIN : SparcCtrlReg<12, "CLEANWIN">;
-def OTHERWIN : SparcCtrlReg<13, "OTHERWIN">;
-def WSTATE : SparcCtrlReg<14, "WSTATE">;
+def CLEANWIN   : SparcCtrlReg<12, "CLEANWIN">;
+def OTHERWIN   : SparcCtrlReg<13, "OTHERWIN">;
+def WSTATE     : SparcCtrlReg<14, "WSTATE">;
+def GL         : SparcCtrlReg<16, "GL">;
+def VER        : SparcCtrlReg<31, "VER">;
 
 // Integer registers
 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]> {
   let isConstant = true;
 }
 def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
 def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>;
 def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>;

 def LowDFPRegs : RegisterClass<"SP", [f64], 64, (sequence "D%u", 0, 15)>;
 def LowQFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 7)>;
 
 // Floating point control register classes.
 def FCCRegs : RegisterClass<"SP", [i1], 1, (sequence "FCC%u", 0, 3)>;
 
 let isAllocatable = 0 in {
   // Ancillary state registers
+  // FIXME: TICK is special-cased here as it can be accessed
+  // from the ASR (as ASR4) or the privileged register set.
+  // For now this is required for the parser to work.
   def ASRRegs : RegisterClass<"SP", [i32], 32,
-                              (add Y, (sequence "ASR%u", 1, 31))>;
+                              (add Y, TICK, (sequence "ASR%u", 1, 31))>;
 
   // This register class should not be used to hold i64 values.
   def CoprocRegs : RegisterClass<"SP", [i32], 32,
                                 (add (sequence "C%u", 0, 31))>;
 
   // Should be in the same order as CoprocRegs.
   def CoprocPair : RegisterClass<"SP", [v2i32], 64,
     (add C0_C1,   C2_C3,   C4_C5,   C6_C7,
          C8_C9,   C10_C11, C12_C13, C14_C15,
          C16_C17, C18_C19, C20_C21, C22_C23,
          C24_C25, C26_C27, C28_C29, C30_C31)>;
 }
 
 // Privileged Registers
 def PRRegs : RegisterClass<"SP", [i64], 64,
     (add TPC, TNPC, TSTATE, TT, TICK, TBA, PSTATE, TL, PIL, CWP,
-         CANSAVE, CANRESTORE, CLEANWIN, OTHERWIN, WSTATE)>;
-
+         CANSAVE, CANRESTORE, CLEANWIN, OTHERWIN, WSTATE, GL, VER)>;

llvm/test/MC/Sparc/sparc-special-registers.s

-! RUN: llvm-mc %s -arch=sparc -show-encoding | FileCheck %s
+! RUN: llvm-mc %s -arch=sparc   -show-encoding | FileCheck %s
 ! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
 
         ! CHECK: rd %y, %i0            ! encoding: [0xb1,0x40,0x00,0x00]
         rd %y, %i0
 
         ! CHECK: rd %asr1, %i0         ! encoding: [0xb1,0x40,0x40,0x00]
         rd %asr1, %i0
 
! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
         wr %i0, 5, %psr
 
         ! CHECK: wr %i0, 5, %wim          ! encoding: [0x81,0x96,0x20,0x05]
         wr %i0, 5, %wim
 
         ! CHECK: wr %i0, 5, %tbr          ! encoding: [0x81,0x9e,0x20,0x05]
         wr %i0, 5, %tbr
 
-        ! CHECK: rd %asr6, %i0         ! encoding: [0xb1,0x41,0x80,0x00]
-        rd %fprs, %i0
-
-        ! CHECK: wr %i0, 7, %asr6      ! encoding: [0x8d,0x86,0x20,0x07]
-        wr %i0, 7, %fprs
-
         ! CHECK: ld [%g2+20], %fsr     ! encoding: [0xc1,0x08,0xa0,0x14]
         ld [%g2 + 20],%fsr
 
         ! CHECK: ld [%g2+%i5], %fsr    ! encoding: [0xc1,0x08,0x80,0x1d]
         ld [%g2 + %i5],%fsr
 
         ! CHECK: st %fsr, [%g2+20]     ! encoding: [0xc1,0x28,0xa0,0x14]
         st %fsr,[%g2 + 20]
 
         ! CHECK: st %fsr, [%g2+%i5]    ! encoding: [0xc1,0x28,0x80,0x1d]
         st %fsr,[%g2 + %i5]
 
         ! CHECK: std %fq, [%g6+%i2]    ! encoding: [0xc1,0x31,0x80,0x1a]
         std %fq, [%g6 + %i2]
+
+! RUN: llvm-mc %s -arch=sparc   -show-encoding | FileCheck %s --check-prefix=V8
+! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
+
+!! Those instructions are processed differently on V8 and V9
+
+! V8: rd %asr6, %i0         ! encoding: [0xb1,0x41,0x80,0x00]
+! V9: rd %fprs, %i0         ! encoding: [0xb1,0x41,0x80,0x00]
+rd %fprs, %i0
+
+! V8: wr %i0, 7, %asr6      ! encoding: [0x8d,0x86,0x20,0x07]
+! V9: wr %i0, 7, %fprs      ! encoding: [0x8d,0x86,0x20,0x07]
+wr %i0, 7, %fprs

llvm/test/MC/Sparc/sparcv9-instructions.s

! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
         ! V9: rdpr %otherwin, %i5       ! encoding: [0xbb,0x53,0x40,0x00]
         rdpr %otherwin,%i5
         ! V8:      error: instruction requires a CPU feature not currently enabled
         ! V8-NEXT: rdpr %wstate,%i5
         ! V9: rdpr %wstate, %i5         ! encoding: [0xbb,0x53,0x80,0x00]
         rdpr %wstate,%i5
 
         ! V8:      error: instruction requires a CPU feature not currently enabled
-        ! V8-NEXT: rd %pc, %o7
+        ! V8-NEXT: rdpr %ver,%i5
+        ! V9: rdpr %ver, %i5            ! encoding: [0xbb,0x57,0xc0,0x00]
+        rdpr %ver,%i5
+
         ! V9: rd %pc, %o7               ! encoding: [0x9f,0x41,0x40,0x00]
         rd %pc, %o7
+        ! V9: rd %asi, %g1              ! encoding: [0x83,0x40,0xc0,0x00]
+        rd %asi, %g1
+        ! V9: rd %ccr, %g1              ! encoding: [0x83,0x40,0x80,0x00]
+        rd %ccr, %g1
+        ! V9: rd %tick, %i5             ! encoding: [0xbb,0x41,0x00,0x00]
+        rd %tick,%i5
+
+        ! V9: wr %i0, %i1, %asi         ! encoding: [0x87,0x86,0x00,0x19]
+        wr %i0, %i1, %asi
+        ! V9: wr %i0, 1, %asi           ! encoding: [0x87,0x86,0x20,0x01]
+        wr %i0, 1, %asi
+        ! V9: wr %i0, %i1, %ccr         ! encoding: [0x85,0x86,0x00,0x19]
+        wr %i0, %i1, %ccr
+        ! V9: wr %i0, 1, %ccr           ! encoding: [0x85,0x86,0x20,0x01]
+        wr %i0, 1, %ccr
 
         ! V9: st %o1, [%o0]             ! encoding: [0xd2,0x22,0x00,0x00]
         stw %o1, [%o0]
 
         ! V8:      error: instruction requires a CPU feature not currently enabled
         ! V8-NEXT: prefetch  [ %i1 + 0xf80 ], 1
         ! V9: prefetch  [%i1+3968], 1  ! encoding: [0xc3,0x6e,0x6f,0x80]
         prefetch  [ %i1 + 0xf80 ], 1