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[SPARC][IAS] Add definitions for v9 State Registers
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Authored by koakuma on Aug 6 2023, 7:10 AM.

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Summary

This adds definitions for SPARC v9 State Registers (privileged/nonprivileged, see v9 manual ch. 5).

Depends on D157230

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Unit TestsFailed

Event Timeline

koakuma created this revision.Aug 6 2023, 7:10 AM
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koakuma requested review of this revision.Aug 6 2023, 7:10 AM
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barannikov88 added inline comments.Aug 6 2023, 1:12 PM
llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
1316–1317

I guess this comment can be removed.

llvm/lib/Target/Sparc/SparcInstrAliases.td
526–527

Isn't this covered by the first InstAlias in the group?

llvm/lib/Target/Sparc/SparcRegisterInfo.td
135

It looks like these registers are actually aliases to %asrXX (or vice versa). They should use the corresponding functionality instead of being redefined.
See RegAltNameIndex in Target.td and how other targets use it.

378

See the comment above about RegAltNameIndex.

llvm/test/MC/Sparc/sparcv9-instructions.s
425–440

IIUC all of these should complain about missing feature on V8. This can probably be done by adding some checks to validateTargetOperandClass or checkTargetMatchPredicate.

koakuma updated this revision to Diff 549694.Aug 13 2023, 6:08 AM
koakuma marked an inline comment as done.

Merge unprivileged ASR definitions & remove some unused code.

llvm/lib/Target/Sparc/SparcRegisterInfo.td
135

The privileged ones are on a separate register file from the ASRs, so those need to be defined separately.

The unprivileged ones can be merged with the ASRs, however, I have a question about the handling of %tick/%asr4.
The same register can be viewed through nonprivileged (rd %tick/rd %asr4) or privileged (rdpr %tick) instructions, however, since the two are modeled using different objects, it is quite difficult to make it usable by both instructions.
Currently I am special casing it so that privileged TICK can also be read by rd. Is there any better way to do this or will this do for now?

llvm/test/MC/Sparc/sparcv9-instructions.s
425–440

How do I do this? Seems like in both functions I can only get the raw register number, I don't know how to recover the textual name (e.g whether it was originally referred to as %asi or %asr3)...

barannikov88 added inline comments.Aug 15 2023, 5:24 AM
llvm/lib/Target/Sparc/SparcRegisterInfo.td
135

I can't suggest anything better. Do other assemblers accept %asr1-6? The manual says there are only %asr7-31 (with 7-15 reserved for future use).
Note that adding TICK to ASRRegs allows it to be used in wr instruction, which isn't allowed by the manual (A.63 Write State Register).

llvm/test/MC/Sparc/sparc-special-registers.s
52

RUN lines are conventionally at the start of a file. They can be combined with the existing RUN lines like this:

! RUN: llvm-mc %s -arch=sparc   -show-encoding | FileCheck %s --check-prefixes=CHECK,V8
! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefixes=CHECK,V9

Note the --check-prefixes option.

llvm/test/MC/Sparc/sparcv9-instructions.s
425–440

validateTargetOperandClass allows you to examine whatever you stored in SparcOperand. If the spelling is important, you can store that information there, see e.g. RegOp::RegisterKind.
The method should probably return Match_MissingFeature on failure.

barannikov88 added inline comments.Aug 16 2023, 1:03 AM
llvm/test/MC/Sparc/sparcv9-instructions.s
425–440

There may be other solutions, but I'm not sure I understand the issue.

koakuma marked 2 inline comments as not done.Aug 19 2023, 9:31 PM
koakuma added inline comments.
llvm/lib/Target/Sparc/SparcRegisterInfo.td
135

GCC's assembler, at least, accepts the names %asr1-6 with both rd and wr, including the forbidden wr to %asr4/TICK and %asr5/PC.
Sun's, on the other hand, accepts the names %asr1-6 when using it with rd, but forbids it with wr.

llvm/test/MC/Sparc/sparcv9-instructions.s
425–440

The problem is that, for example, the two textual forms are encoded the same:

rd %asr5, %i0
rd %pc, %i0

But the latter form is only allowed when targeting V9, so I want to be able to recover the textual names instead of just the register number?
For comparison, GCC does disallow the %pc form when targeting non-V9 subarches (Sun's does not support targeting non-V9s in the first place).

barannikov88 added inline comments.Aug 20 2023, 4:17 AM
llvm/test/MC/Sparc/sparcv9-instructions.s
425–440

When parsing a register (SparcAsmParser::matchRegisterName) you can record the spelling (as a flag/enum or string), pass it to SparcOperand::CreateReg and store in SparcOperand::RegOp, similar to RegisterKind. Then you can override checkEarlyTargetMatchPredicate where you can examine the spelling and filter out those that are invalid for the instruction and processor mode depending on the instruction opcode. If the opcode is not important (e.g. %pc is invalid for all instructions in V8 mode), then you can do the same in validateTargetOperandClass.

The tests should cover all register number/ register spelling / processor mode combinations, and there should also be disassembler tests for all combinations of registers / instructions / processor mode.

If all that sounds too difficult, can you add a TODO with the desired behavior somehwere? I.e. which processor mode / instruction allows which spelling?

koakuma updated this revision to Diff 555550.Sep 1 2023, 7:51 PM
  • Add remarks about odd behavior for V8 (it accepts V9 ASR alias names, which it shouldn't). This should not be a problem in practice - all existing V8 code will still be accepted, and people who write V8 code are unlikely to use V9 alias names. This will be addressed in a future patch, so for now we're focusing on enabling V9 assembly support.
  • Add more tests for %asr2-%asr6 & their alternate names.
This revision is now accepted and ready to land.Sep 1 2023, 8:23 PM

@koakuma If you don't have commit access I think it's time to apply for it.

brad added a comment.Sep 1 2023, 8:34 PM

@koakuma If you don't have commit access I think it's time to apply for it.

I agree, that would be a good idea.

This revision was automatically updated to reflect the committed changes.