MIPS: unwind, don't save/restore hi/lo for R6

[wzssyqa]

Summary

HI/LO registers have been removed in MIPSr6. Save and restore them only for pre-R6.

We keep the memory space for the registers so that we can use the same register indexes for
r6 and pre-r6.

Fixes: #60682

[jrtc27]

Should space for them still exist in Registers_mips_o32/newabi, UNW_MIPS_HI/LO still be defined and the various things in __libunwind_config.h still account for them?

[wzssyqa]

In D156283#4533871, @jrtc27 wrote:

Should space for them still exist in Registers_mips_o32/newabi, UNW_MIPS_HI/LO still be defined and the various things in __libunwind_config.h still account for them?

I think that we should keep them as, since it can make the code more simple.
The only problem of keeping them, is some few memory is wasted.
I don't think that it is a big problem.

[wzssyqa]

In D156283#4533871, @jrtc27 wrote:

Should space for them still exist in Registers_mips_o32/newabi, UNW_MIPS_HI/LO still be defined and the various things in __libunwind_config.h still account for them?

And I think that when we add more registers like MSA/DSP, should start from 66, so that we can use the same register indexes for both R6 and pre-R6.

[MaskRay]

wzssyqa removed a reviewer: libunwind.

Some projects like libc++/libc++abi/libunwind add a default reviewer group. This ensures #libunwind people know changes going into libunwind. They may not comment, but they can do so when a change increasing maintenance burden catches their eye.

[wzssyqa]

In D156283#4589972, @MaskRay wrote:

wzssyqa removed a reviewer: libunwind.

Some projects like libc++/libc++abi/libunwind add a default reviewer group. This ensures #libunwind people know changes going into libunwind. They may not comment, but they can do so when a change increasing maintenance burden catches their eye.

I added libunwind group back.
It was "blocking libunwind" previous. I have no idea what it means?

[MaskRay]

In D156283#4590529, @wzssyqa wrote:

In D156283#4589972, @MaskRay wrote:

wzssyqa removed a reviewer: libunwind.

Some projects like libc++/libc++abi/libunwind add a default reviewer group. This ensures #libunwind people know changes going into libunwind. They may not comment, but they can do so when a change increasing maintenance burden catches their eye.

I added libunwind group back.
It was "blocking libunwind" previous. I have no idea what it means?

Someone in the #libunwind needs to click Accept as libunwind to make the differential green, otherwise it is in the Needs Review state even if there is an approval.

[wzssyqa]

In D156283#4590543, @MaskRay wrote:

In D156283#4590529, @wzssyqa wrote:

In D156283#4589972, @MaskRay wrote:

wzssyqa removed a reviewer: libunwind.

Some projects like libc++/libc++abi/libunwind add a default reviewer group. This ensures #libunwind people know changes going into libunwind. They may not comment, but they can do so when a change increasing maintenance burden catches their eye.

I added libunwind group back.
It was "blocking libunwind" previous. I have no idea what it means?

Someone in the #libunwind needs to click Accept as libunwind to make the differential green, otherwise it is in the Needs Review state even if there is an approval.

How can I ping the #libunwind group?

[compnerd]

I think that @wzssyqa's analysis is correct - the extra space is fine to keep in the buffer.

[wzssyqa]

In D156283#4595487, @compnerd wrote:

I think that @wzssyqa's analysis is correct - the extra space is fine to keep in the buffer.

Can you help to push this patch into git? I have no permission to do so.

libunwind/include/libunwind.h

enum {
   UNW_MIPS_F24 = 56,
   UNW_MIPS_F25 = 57,
   UNW_MIPS_F26 = 58,
   UNW_MIPS_F27 = 59,
   UNW_MIPS_F28 = 60,
   UNW_MIPS_F29 = 61,
   UNW_MIPS_F30 = 62,
   UNW_MIPS_F31 = 63,
+  // HI,LO have been dropped since r6, we keep them here.
+  // So, when we add DSP/MSA etc, we can use the same register indexes
+  // for r6 and pre-r6.
   UNW_MIPS_HI = 64,
   UNW_MIPS_LO = 65,
 };
 
 // SPARC registers
 enum {
   UNW_SPARC_G0 = 0,
   UNW_SPARC_G1 = 1,

libunwind/src/Registers.hpp

inline bool Registers_mips_o32::validRegister(int regNum) const {
   if (regNum == UNW_REG_IP)
     return true;
   if (regNum == UNW_REG_SP)
     return true;
   if (regNum < 0)
     return false;
   if (regNum <= UNW_MIPS_R31)
     return true;
-#if __mips_isa_rev != 6
+#if __mips_isa_rev < 6
   if (regNum == UNW_MIPS_HI)
     return true;
   if (regNum == UNW_MIPS_LO)
     return true;
 #endif
 #if defined(__mips_hard_float) && __mips_fpr == 32
   if (regNum >= UNW_MIPS_F0 && regNum <= UNW_MIPS_F31)
     return true;
#if defined(__mips_hard_float) && __mips_fpr == 32
   }
 #endif
 
   switch (regNum) {
   case UNW_REG_IP:
     return _registers.__pc;
   case UNW_REG_SP:
     return _registers.__r[29];
+#if __mips_isa_rev < 6
   case UNW_MIPS_HI:
     return _registers.__hi;
   case UNW_MIPS_LO:
     return _registers.__lo;
+#endif
   }
   _LIBUNWIND_ABORT("unsupported mips_o32 register");
 }
 
 inline void Registers_mips_o32::setRegister(int regNum, uint32_t value) {
   if (regNum >= UNW_MIPS_R0 && regNum <= UNW_MIPS_R31) {
     _registers.__r[regNum - UNW_MIPS_R0] = value;
     return;
#endif
 
   switch (regNum) {
   case UNW_REG_IP:
     _registers.__pc = value;
     return;
   case UNW_REG_SP:
     _registers.__r[29] = value;
     return;
+#if __mips_isa_rev < 6
   case UNW_MIPS_HI:
     _registers.__hi = value;
     return;
   case UNW_MIPS_LO:
     _registers.__lo = value;
+#endif
     return;
   }
   _LIBUNWIND_ABORT("unsupported mips_o32 register");
 }
 
 inline bool Registers_mips_o32::validFloatRegister(int regNum) const {
 #if defined(__mips_hard_float) && __mips_fpr == 64
   if (regNum >= UNW_MIPS_F0 && regNum <= UNW_MIPS_F31)
inline const char *Registers_mips_o32::getRegisterName(int regNum) {
   case UNW_MIPS_F28:
     return "$f28";
   case UNW_MIPS_F29:
     return "$f29";
   case UNW_MIPS_F30:
     return "$f30";
   case UNW_MIPS_F31:
     return "$f31";
+#if __mips_isa_rev < 6
   case UNW_MIPS_HI:
     return "$hi";
   case UNW_MIPS_LO:
     return "$lo";
+#endif
   default:
     return "unknown register";
   }
 }
 #endif // _LIBUNWIND_TARGET_MIPS_O32
 
 #if defined(_LIBUNWIND_TARGET_MIPS_NEWABI)
 /// Registers_mips_newabi holds the register state of a thread in a
inline bool Registers_mips_newabi::validRegister(int regNum) const {
   if (regNum == UNW_REG_IP)
     return true;
   if (regNum == UNW_REG_SP)
     return true;
   if (regNum < 0)
     return false;
   if (regNum <= UNW_MIPS_R31)
     return true;
-#if __mips_isa_rev != 6
+#if __mips_isa_rev < 6
   if (regNum == UNW_MIPS_HI)
     return true;
   if (regNum == UNW_MIPS_LO)
     return true;
 #endif
   // FIXME: Hard float, DSP accumulator registers, MSA registers
   return false;
 }
 
 inline uint64_t Registers_mips_newabi::getRegister(int regNum) const {
   if (regNum >= UNW_MIPS_R0 && regNum <= UNW_MIPS_R31)
     return _registers.__r[regNum - UNW_MIPS_R0];
 
   switch (regNum) {
   case UNW_REG_IP:
     return _registers.__pc;
   case UNW_REG_SP:
     return _registers.__r[29];
+#if __mips_isa_rev < 6
   case UNW_MIPS_HI:
     return _registers.__hi;
   case UNW_MIPS_LO:
     return _registers.__lo;
+#endif
   }
   _LIBUNWIND_ABORT("unsupported mips_newabi register");
 }
 
 inline void Registers_mips_newabi::setRegister(int regNum, uint64_t value) {
   if (regNum >= UNW_MIPS_R0 && regNum <= UNW_MIPS_R31) {
     _registers.__r[regNum - UNW_MIPS_R0] = value;
     return;
   }
 
   switch (regNum) {
   case UNW_REG_IP:
     _registers.__pc = value;
     return;
   case UNW_REG_SP:
     _registers.__r[29] = value;
     return;
+#if __mips_isa_rev < 6
   case UNW_MIPS_HI:
     _registers.__hi = value;
     return;
   case UNW_MIPS_LO:
     _registers.__lo = value;
     return;
+#endif
   }
   _LIBUNWIND_ABORT("unsupported mips_newabi register");
 }
 
 inline bool Registers_mips_newabi::validFloatRegister(int regNum) const {
 #ifdef __mips_hard_float
   if (regNum >= UNW_MIPS_F0 && regNum <= UNW_MIPS_F31)
     return true;
inline const char *Registers_mips_newabi::getRegisterName(int regNum) {
   case UNW_MIPS_F28:
     return "$f28";
   case UNW_MIPS_F29:
     return "$f29";
   case UNW_MIPS_F30:
     return "$f30";
   case UNW_MIPS_F31:
     return "$f31";
+#if __mips_isa_rev < 6
   case UNW_MIPS_HI:
     return "$hi";
   case UNW_MIPS_LO:
     return "$lo";
+#endif
   default:
     return "unknown register";
   }
 }
 #endif // _LIBUNWIND_TARGET_MIPS_NEWABI
 
 #if defined(_LIBUNWIND_TARGET_SPARC)
 /// Registers_sparc holds the register state of a thread in a 32-bit Sparc

libunwind/src/UnwindRegistersRestore.S

#else
   ldc1  $f26, (4 * 36 + 8 * 26)($4)
   ldc1  $f27, (4 * 36 + 8 * 27)($4)
   ldc1  $f28, (4 * 36 + 8 * 28)($4)
   ldc1  $f29, (4 * 36 + 8 * 29)($4)
   ldc1  $f30, (4 * 36 + 8 * 30)($4)
   ldc1  $f31, (4 * 36 + 8 * 31)($4)
 #endif
 #endif
+#if __mips_isa_rev < 6
   // restore hi and lo
   lw    $8, (4 * 33)($4)
   mthi  $8
   lw    $8, (4 * 34)($4)
   mtlo  $8
+#endif
   // r0 is zero
   lw    $1, (4 * 1)($4)
   lw    $2, (4 * 2)($4)
   lw    $3, (4 * 3)($4)
   // skip a0 for now
   lw    $5, (4 * 5)($4)
   lw    $6, (4 * 6)($4)
   lw    $7, (4 * 7)($4)
DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind21Registers_mips_newabi6jumptoEv)
   .set noat
   .set noreorder
   .set nomacro
 #ifdef __mips_hard_float
   .irp i,FROM_0_TO_31
     ldc1 $f\i, (280+8*\i)($4)
   .endr
 #endif
+#if __mips_isa_rev < 6
   // restore hi and lo
   ld    $8, (8 * 33)($4)
   mthi  $8
   ld    $8, (8 * 34)($4)
   mtlo  $8
+#endif
   // r0 is zero
   ld    $1, (8 * 1)($4)
   ld    $2, (8 * 2)($4)
   ld    $3, (8 * 3)($4)
   // skip a0 for now
   .irp i,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
     ld $\i, (8 * \i)($4)
   .endr

libunwind/src/UnwindRegistersSave.S

DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
   sw    $26, (4 * 26)($4)
   sw    $27, (4 * 27)($4)
   sw    $28, (4 * 28)($4)
   sw    $29, (4 * 29)($4)
   sw    $30, (4 * 30)($4)
   sw    $31, (4 * 31)($4)
   # Store return address to pc
   sw    $31, (4 * 32)($4)
+#if __mips_isa_rev < 6
   # hi and lo
   mfhi  $8
   sw    $8,  (4 * 33)($4)
   mflo  $8
   sw    $8,  (4 * 34)($4)
+#endif
 #ifdef __mips_hard_float
 #if __mips_fpr != 64
   sdc1  $f0, (4 * 36 + 8 * 0)($4)
   sdc1  $f2, (4 * 36 + 8 * 2)($4)
   sdc1  $f4, (4 * 36 + 8 * 4)($4)
   sdc1  $f6, (4 * 36 + 8 * 6)($4)
   sdc1  $f8, (4 * 36 + 8 * 8)($4)
   sdc1  $f10, (4 * 36 + 8 * 10)($4)
DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
   .set noat
   .set noreorder
   .set nomacro
   .irp i,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
     sd $\i, (8 * \i)($4)
   .endr
   # Store return address to pc
   sd    $31, (8 * 32)($4)
+#if __mips_isa_rev < 6
   # hi and lo
   mfhi  $8
   sd    $8,  (8 * 33)($4)
   mflo  $8
   sd    $8,  (8 * 34)($4)
+#endif
 #ifdef __mips_hard_float
   .irp i,FROM_0_TO_31
     sdc1 $f\i, (280+8*\i)($4)
   .endr
 #endif
   jr  $31
   # return UNW_ESUCCESS
   or    $2, $0, $0