[BOLT] Implement createRelocation for AArch64

[Kepontry]

Summary

The implementation is based on the X86 version, with the same code
of symbol and addend extraction. The differences include the
support for RelType `R_AARCH64_CALL26` and the deletion of 8-bit
relocation.

[Kepontry]

clang-format

[yota9]

Hi, thanks for the patch! Can you please add test for this?

[Kepontry]

Fixed some compilation warnings. Now this patch is ready for review.

[Amir]

Can you please retitle it as "[BOLT] Implement createRelocation for AArch64"?

bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp

1207–1213

This part looks to be common for X86 and AArch64. Can you please factor it out (in a separate diff)?

[rafauler]

bolt/lib/Core/Relocation.cpp

349–351

What happens with this assert() when the call target is at a lower address than the call instruction? (PC > Value).

bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp

1207–1209

structured binding here too, just like D157217

[Kepontry]

bolt/lib/Core/Relocation.cpp

349–351

Oh, it was my mistake. This assert() now checks whether "Value(i.e., offset) + 128M" is less than 256M.

[Amir]

bolt/lib/Core/Relocation.cpp

350

[Kepontry]

ping.

[rafauler]

LGTM

bolt/lib/Core/Relocation.cpp

default:
     llvm_unreachable("unsupported relocation");
   case ELF::R_AARCH64_ABS32:
     break;
   case ELF::R_AARCH64_PREL16:
   case ELF::R_AARCH64_PREL32:
   case ELF::R_AARCH64_PREL64:
     Value -= PC;
     break;
+  case ELF::R_AARCH64_CALL26:
+    Value -= PC;
+    assert(((Value + 0x8000000ULL) & 0xfffffffff0000000ULL) == 0 &&
+           "only PC +/- 128MB is allowed for direct call");
+    // Immediate goes in bits 25:0 of BL.
+    // OP 1001_01 goes in bits 31:26 of BL.
+    Value = (Value >> 2) | 0x94000000ULL;
+    break;
   }
   return Value;
 }
 
 static uint64_t extractValueX86(uint64_t Type, uint64_t Contents, uint64_t PC) {
   if (Type == ELF::R_X86_64_32S)
     return SignExtend64<32>(Contents);
   if (Relocation::isPCRelative(Type))

bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp

 //===- bolt/Target/AArch64/AArch64MCPlusBuilder.cpp -----------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file provides AArch64-specific MCPlus builder.
 //
 //===----------------------------------------------------------------------===//
 
 #include "MCTargetDesc/AArch64AddressingModes.h"
+#include "MCTargetDesc/AArch64FixupKinds.h"
 #include "MCTargetDesc/AArch64MCExpr.h"
 #include "MCTargetDesc/AArch64MCTargetDesc.h"
 #include "Utils/AArch64BaseInfo.h"
 #include "bolt/Core/MCPlusBuilder.h"
 #include "llvm/BinaryFormat/ELF.h"
+#include "llvm/MC/MCFixupKindInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 
 #define DEBUG_TYPE "mcplus"
 
 using namespace llvm;
InstructionListType materializeAddress(const MCSymbol *Target, MCContext *Ctx,
     Insts[1].addOperand(MCOperand::createReg(RegName));
     Insts[1].addOperand(MCOperand::createReg(RegName));
     Insts[1].addOperand(MCOperand::createImm(0));
     Insts[1].addOperand(MCOperand::createImm(0));
     setOperandToSymbolRef(Insts[1], /* OpNum */ 2, Target, Addend, Ctx,
                           ELF::R_AARCH64_ADD_ABS_LO12_NC);
     return Insts;
   }
+
+  std::optional<Relocation>
+  createRelocation(const MCFixup &Fixup,
+                   const MCAsmBackend &MAB) const override {
+    const MCFixupKindInfo &FKI = MAB.getFixupKindInfo(Fixup.getKind());
+
+    assert(FKI.TargetOffset == 0 && "0-bit relocation offset expected");
+    const uint64_t RelOffset = Fixup.getOffset();
+
+    uint64_t RelType;
+    if (Fixup.getKind() == MCFixupKind(AArch64::fixup_aarch64_pcrel_call26))
+      RelType = ELF::R_AARCH64_CALL26;
+    else if (FKI.Flags & MCFixupKindInfo::FKF_IsPCRel) {
+      switch (FKI.TargetSize) {
+      default:
+        return std::nullopt;
+      case 16:
+        RelType = ELF::R_AARCH64_PREL16;
+        break;
+      case 32:
+        RelType = ELF::R_AARCH64_PREL32;
+        break;
+      case 64:
+        RelType = ELF::R_AARCH64_PREL64;
+        break;
+      }
+    } else {
+      switch (FKI.TargetSize) {
+      default:
+        return std::nullopt;
+      case 16:
+        RelType = ELF::R_AARCH64_ABS16;
+        break;
+      case 32:
+        RelType = ELF::R_AARCH64_ABS32;
+        break;
+      case 64:
+        RelType = ELF::R_AARCH64_ABS64;
+        break;
+      }
+    }
+
+    auto [RelSymbol, RelAddend] = extractFixupExpr(Fixup);
+
+    return Relocation({RelOffset, RelSymbol, RelType, RelAddend, 0});
+  }
 };
 
 } // end anonymous namespace
 
 namespace llvm {
 namespace bolt {
 
 MCPlusBuilder *createAArch64MCPlusBuilder(const MCInstrAnalysis *Analysis,
                                           const MCInstrInfo *Info,
                                           const MCRegisterInfo *RegInfo) {
   return new AArch64MCPlusBuilder(Analysis, Info, RegInfo);
 }
 
 } // namespace bolt
 } // namespace llvm

bolt/test/AArch64/reloc-call26.s

+## This test checks processing of R_AARCH64_CALL26 relocation
+## when option `--funcs` is enabled
+
+# REQUIRES: system-linux
+
+# RUN: llvm-mc -filetype=obj -triple aarch64-unknown-unknown \
+# RUN:   %s -o %t.o
+# RUN: %clang %cflags %t.o -o %t.exe -Wl,-q
+# RUN: llvm-bolt %t.exe -o %t.bolt --funcs=func1
+# RUN: llvm-objdump -d --disassemble-symbols='_start' %t.bolt | \
+# RUN:   FileCheck %s
+
+# CHECK: {{.*}} bl {{.*}} <func1>
+
+  .text
+  .align 4
+  .global _start
+  .type _start, %function
+_start:
+  bl func1
+  mov     w8, #93
+  svc     #0
+  .size _start, .-_start
+
+  .global func1
+  .type func1, %function
+func1:
+  ret
+  .size func1, .-func1