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Differential D155662

[X86] Promote VAES, SHA512, SM4 implied feature to AVX2
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Authored by FreddyYe on Jul 18 2023, 5:20 PM.

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Reviewers
craig.topper
pengfei
RKSimon
skan
Commits
rGdc7c0181ef8e: [X86] Promote VAES, SHA512, SM4 implied feature to AVX2

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Event Timeline

FreddyYe created this revision.Jul 18 2023, 5:20 PM
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FreddyYe requested review of this revision.Jul 18 2023, 5:20 PM
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FreddyYe added reviewers: craig.topper, pengfei, RKSimon, skan.Jul 18 2023, 5:23 PM

As we noticed in SHA512's spec, it mentions AVX in "CPUID Feature Flag" only, but from software view, we can promote it to AVX2 as all machines having SHA512 have AVX2. Just like VAES here.

FreddyYe mentioned this in D155146: [X86] Add SHA512 instructions..Jul 18 2023, 5:28 PM
skan added inline comments.Jul 18 2023, 7:33 PM
llvm/lib/TargetParser/X86TargetParser.cpp
624

If so ,shouldn't we update X86.td too?

FreddyYe updated this revision to Diff 541816.Jul 18 2023, 7:39 PM
FreddyYe marked an inline comment as done.

Address comment.

llvm/lib/TargetParser/X86TargetParser.cpp
624

Oh yes! Forgot!

skan added a comment.Jul 19 2023, 1:21 AM
In D155662#4512974, @FreddyYe wrote:

As we noticed in SHA512's spec, it mentions AVX in "CPUID Feature Flag" only, but from software view, we can promote it to AVX2 as all machines having SHA512 have AVX2. Just like VAES here.

Is it a good justification? Any pros from software view?

FreddyYe added a comment.Jul 19 2023, 1:36 AM
In D155662#4513714, @skan wrote:
In D155662#4512974, @FreddyYe wrote:

As we noticed in SHA512's spec, it mentions AVX in "CPUID Feature Flag" only, but from software view, we can promote it to AVX2 as all machines having SHA512 have AVX2. Just like VAES here.

Is it a good justification? Any pros from software view?

Like we did before for AVXNECONVERT, AVXIFMA, AVXVNNI. These ISA supports %ymm and operates on integers. And AVX2 is the first ISA is capable of that.

skan accepted this revision.Jul 19 2023, 1:40 AM

LGTM

This revision is now accepted and ready to land.Jul 19 2023, 1:40 AM
FreddyYe updated this revision to Diff 544651.Jul 27 2023, 1:37 AM

rebase and promote SHA512, SM4 as well.

FreddyYe requested review of this revision.Jul 27 2023, 1:44 AM
FreddyYe retitled this revision from [X86] Promote VAES implied feature to AVX2 to [X86] Promote VAES, SHA512, SM4 implied feature to AVX2.
skan accepted this revision.Jul 27 2023, 2:24 AM
This revision is now accepted and ready to land.Jul 27 2023, 2:24 AM
Harbormaster completed remote builds in B248470: Diff 544651.Jul 27 2023, 3:36 AM
This revision was landed with ongoing or failed builds.Aug 3 2023, 7:43 PM
Closed by commit rGdc7c0181ef8e: [X86] Promote VAES, SHA512, SM4 implied feature to AVX2 (authored by FreddyYe). · Explain Why
This revision was automatically updated to reflect the committed changes.
FreddyYe added a commit: rGdc7c0181ef8e: [X86] Promote VAES, SHA512, SM4 implied feature to AVX2.

Revision Contents

PathSize
llvm/
lib/
Target/
X86/
6 lines
TargetParser/
6 lines

Diff 547087

llvm/lib/Target/X86/X86.td

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def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem", def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
"HasSSEUnalignedMem", "true", "HasSSEUnalignedMem", "true",
"Allow unaligned memory operands with SSE instructions (this may require setting a configuration bit in the processor)">; "Allow unaligned memory operands with SSE instructions (this may require setting a configuration bit in the processor)">;
def FeatureAES : SubtargetFeature<"aes", "HasAES", "true", def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
"Enable AES instructions", "Enable AES instructions",
[FeatureSSE2]>; [FeatureSSE2]>;
def FeatureVAES : SubtargetFeature<"vaes", "HasVAES", "true", def FeatureVAES : SubtargetFeature<"vaes", "HasVAES", "true",
"Promote selected AES instructions to AVX512/AVX registers", "Promote selected AES instructions to AVX512/AVX registers",
[FeatureAVX, FeatureAES]>; [FeatureAVX2, FeatureAES]>;
def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true", def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true",
"Enable TBM instructions">; "Enable TBM instructions">;
def FeatureLWP : SubtargetFeature<"lwp", "HasLWP", "true", def FeatureLWP : SubtargetFeature<"lwp", "HasLWP", "true",
"Enable LWP instructions">; "Enable LWP instructions">;
def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true", def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
"Support MOVBE instruction">; "Support MOVBE instruction">;
def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true", def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
"Support RDRAND instruction">; "Support RDRAND instruction">;
Show All 9 Linesdef FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true",
"Support RTM instructions">; "Support RTM instructions">;
def FeatureADX : SubtargetFeature<"adx", "HasADX", "true", def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",
"Support ADX instructions">; "Support ADX instructions">;
def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true", def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true",
"Enable SHA instructions", "Enable SHA instructions",
[FeatureSSE2]>; [FeatureSSE2]>;
def FeatureSHA512 : SubtargetFeature<"sha512", "HasSHA512", "true", def FeatureSHA512 : SubtargetFeature<"sha512", "HasSHA512", "true",
"Support SHA512 instructions", "Support SHA512 instructions",
[FeatureAVX]>; [FeatureAVX2]>;
// Processor supports CET SHSTK - Control-Flow Enforcement Technology // Processor supports CET SHSTK - Control-Flow Enforcement Technology
// using Shadow Stack // using Shadow Stack
def FeatureSHSTK : SubtargetFeature<"shstk", "HasSHSTK", "true", def FeatureSHSTK : SubtargetFeature<"shstk", "HasSHSTK", "true",
"Support CET Shadow-Stack instructions">; "Support CET Shadow-Stack instructions">;
def FeatureSM3 : SubtargetFeature<"sm3", "HasSM3", "true", def FeatureSM3 : SubtargetFeature<"sm3", "HasSM3", "true",
"Support SM3 instructions", "Support SM3 instructions",
[FeatureAVX]>; [FeatureAVX]>;
def FeatureSM4 : SubtargetFeature<"sm4", "HasSM4", "true", def FeatureSM4 : SubtargetFeature<"sm4", "HasSM4", "true",
"Support SM4 instructions", "Support SM4 instructions",
[FeatureAVX]>; [FeatureAVX2]>;
def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true", def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
"Support PRFCHW instructions">; "Support PRFCHW instructions">;
def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true", def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",
"Support RDSEED instruction">; "Support RDSEED instruction">;
def FeatureLAHFSAHF64 : SubtargetFeature<"sahf", "HasLAHFSAHF64", "true", def FeatureLAHFSAHF64 : SubtargetFeature<"sahf", "HasLAHFSAHF64", "true",
"Support LAHF and SAHF instructions in 64-bit mode">; "Support LAHF and SAHF instructions in 64-bit mode">;
def FeatureMWAITX : SubtargetFeature<"mwaitx", "HasMWAITX", "true", def FeatureMWAITX : SubtargetFeature<"mwaitx", "HasMWAITX", "true",
"Enable MONITORX/MWAITX timer functionality">; "Enable MONITORX/MWAITX timer functionality">;
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llvm/lib/TargetParser/X86TargetParser.cpp

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// Vector extensions that build on SSE or AVX. // Vector extensions that build on SSE or AVX.
constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2; constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2;
constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX; constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX;
constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX; constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX;
constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2; constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2;
constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2; constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2;
constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2; constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2;
constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX; constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX2;
skanUnsubmitted
Done
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If so ,shouldn't we update X86.td too?

skan: If so ,shouldn't we update X86.td too?
FreddyYeAuthorUnsubmitted
Done
ReplyInline Actions

Oh yes! Forgot!

FreddyYe: Oh yes! Forgot!
constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL; constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL;
constexpr FeatureBitset ImpliedFeaturesSM3 = FeatureAVX; constexpr FeatureBitset ImpliedFeaturesSM3 = FeatureAVX;
constexpr FeatureBitset ImpliedFeaturesSM4 = FeatureAVX; constexpr FeatureBitset ImpliedFeaturesSM4 = FeatureAVX2;
// AVX512 features. // AVX512 features.
constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F; constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F;
constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F; constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F;
constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F; constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F;
constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F; constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F;
constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F; constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F;
constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F; constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F;
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constexpr FeatureBitset ImpliedFeaturesPREFETCHI = {}; constexpr FeatureBitset ImpliedFeaturesPREFETCHI = {};
constexpr FeatureBitset ImpliedFeaturesCMPCCXADD = {}; constexpr FeatureBitset ImpliedFeaturesCMPCCXADD = {};
constexpr FeatureBitset ImpliedFeaturesRAOINT = {}; constexpr FeatureBitset ImpliedFeaturesRAOINT = {};
constexpr FeatureBitset ImpliedFeaturesAVXVNNIINT16 = FeatureAVX2; constexpr FeatureBitset ImpliedFeaturesAVXVNNIINT16 = FeatureAVX2;
constexpr FeatureBitset ImpliedFeaturesAVXVNNIINT8 = FeatureAVX2; constexpr FeatureBitset ImpliedFeaturesAVXVNNIINT8 = FeatureAVX2;
constexpr FeatureBitset ImpliedFeaturesAVXIFMA = FeatureAVX2; constexpr FeatureBitset ImpliedFeaturesAVXIFMA = FeatureAVX2;
constexpr FeatureBitset ImpliedFeaturesAVXNECONVERT = FeatureAVX2; constexpr FeatureBitset ImpliedFeaturesAVXNECONVERT = FeatureAVX2;
constexpr FeatureBitset ImpliedFeaturesSHA512 = FeatureAVX; constexpr FeatureBitset ImpliedFeaturesSHA512 = FeatureAVX2;
constexpr FeatureBitset ImpliedFeaturesAVX512FP16 = constexpr FeatureBitset ImpliedFeaturesAVX512FP16 =
FeatureAVX512BW | FeatureAVX512DQ | FeatureAVX512VL; FeatureAVX512BW | FeatureAVX512DQ | FeatureAVX512VL;
// Key Locker Features // Key Locker Features
constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2; constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2;
constexpr FeatureBitset ImpliedFeaturesWIDEKL = FeatureKL; constexpr FeatureBitset ImpliedFeaturesWIDEKL = FeatureKL;
// AVXVNNI Features // AVXVNNI Features
constexpr FeatureBitset ImpliedFeaturesAVXVNNI = FeatureAVX2; constexpr FeatureBitset ImpliedFeaturesAVXVNNI = FeatureAVX2;
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