This is an archive of the discontinued LLVM Phabricator instance.

[RISCV] Remove unused classes VPseudoTernary, VPseudoTernaryNoMaskNoPolicy, and VPseudoConversionW_V
ClosedPublic

Authored by michaelmaitland on Jul 18 2023, 1:11 PM.

Download Raw Diff

Details

Reviewers

craig.topper
asb
reames

Commits

rGbe6380f017ac: [RISCV] Remove unused classes VPseudoTernary, VPseudoTernaryNoMaskNoPolicy, and…

Summary

This class is dead and can be removed.

Diff Detail

Repository: rG LLVM Github Monorepo

Event Timeline

michaelmaitland created this revision.Jul 18 2023, 1:11 PM

Herald added a project: Restricted Project. · View Herald TranscriptJul 18 2023, 1:11 PM

Herald added subscribers: jobnoorman, luke, VincentWu and 27 others. · View Herald Transcript

michaelmaitland requested review of this revision.Jul 18 2023, 1:11 PM

Herald added a project: Restricted Project. · View Herald TranscriptJul 18 2023, 1:11 PM

Herald added subscribers: llvm-commits, wangpc, eopXD, MaskRay. · View Herald Transcript

michaelmaitland retitled this revision from [RISCV] Remove unused class VPseudoTernary to [RISCV] Remove unused classes VPseudoTernary and VPseudoTernaryNoMaskNoPolicy.Jul 18 2023, 1:15 PM

Remove VPseudoTernaryNoMaskNoPolicy since it is dead too.

VPseudoConversionW_V

michaelmaitland retitled this revision from [RISCV] Remove unused classes VPseudoTernary and VPseudoTernaryNoMaskNoPolicy to [RISCV] Remove unused classes VPseudoTernary, VPseudoTernaryNoMaskNoPolicy, and VPseudoConversionW_V.Jul 18 2023, 3:13 PM

LGTM

This revision is now accepted and ready to land.Jul 18 2023, 4:08 PM

This revision was landed with ongoing or failed builds.Jul 18 2023, 4:38 PM

Closed by commit rGbe6380f017ac: [RISCV] Remove unused classes VPseudoTernary, VPseudoTernaryNoMaskNoPolicy, and… (authored by michaelmaitland). · Explain Why

This revision was automatically updated to reflect the committed changes.

michaelmaitland added a commit: rGbe6380f017ac: [RISCV] Remove unused classes VPseudoTernary, VPseudoTernaryNoMaskNoPolicy, and….

michaelmaitland mentioned this in D155654: [RISCV] Add SchedRead for Merge operands on MASK Pseudos.Jul 18 2023, 4:41 PM

Harbormaster completed remote builds in B246369: Diff 541754.Jul 18 2023, 9:28 PM

Revision Contents

Path

Size

llvm/

lib/

Target/

RISCV/

RISCVInstrInfoVPseudos.td

29 lines

Diff 541780

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

This file is larger than 256 KB, so syntax highlighting is disabled by default.

Show First 20 Lines • Show All 3,214 Lines • ▼ Show 20 Lines	defm "" : VPseudoBinaryV_WV<m>,
Sched<[WriteVNShiftV_MX, ReadVNShiftV_MX, ReadVNShiftV_MX, ReadVMask]>;		Sched<[WriteVNShiftV_MX, ReadVNShiftV_MX, ReadVNShiftV_MX, ReadVMask]>;
defm "" : VPseudoBinaryV_WX<m>,		defm "" : VPseudoBinaryV_WX<m>,
Sched<[WriteVNShiftX_MX, ReadVNShiftV_MX, ReadVNShiftX_MX, ReadVMask]>;		Sched<[WriteVNShiftX_MX, ReadVNShiftV_MX, ReadVNShiftX_MX, ReadVMask]>;
defm "" : VPseudoBinaryV_WI<m>,		defm "" : VPseudoBinaryV_WI<m>,
Sched<[WriteVNShiftI_MX, ReadVNShiftV_MX, ReadVMask]>;		Sched<[WriteVNShiftI_MX, ReadVNShiftV_MX, ReadVMask]>;
}		}
}		}

multiclass VPseudoTernary<VReg RetClass,
RegisterClass Op1Class,
DAGOperand Op2Class,
LMULInfo MInfo,
string Constraint = ""> {
let VLMul = MInfo.value in {
def "_" # MInfo.MX : VPseudoTernaryNoMask<RetClass, Op1Class, Op2Class, Constraint>;
def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMask<RetClass, Op1Class, Op2Class, Constraint>;
}
}

multiclass VPseudoTernaryNoMaskNoPolicy<VReg RetClass,
RegisterClass Op1Class,
DAGOperand Op2Class,
LMULInfo MInfo,
string Constraint = ""> {
let VLMul = MInfo.value in {
def "_" # MInfo.MX : VPseudoTernaryNoMask<RetClass, Op1Class, Op2Class, Constraint>;
def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class,
Constraint>;
}
}

multiclass VPseudoTernaryWithTailPolicy<VReg RetClass,		multiclass VPseudoTernaryWithTailPolicy<VReg RetClass,
RegisterClass Op1Class,		RegisterClass Op1Class,
DAGOperand Op2Class,		DAGOperand Op2Class,
LMULInfo MInfo,		LMULInfo MInfo,
int sew,		int sew,
string Constraint = "",		string Constraint = "",
bit Commutable = 0> {		bit Commutable = 0> {
let VLMul = MInfo.value in {		let VLMul = MInfo.value in {
▲ Show 20 Lines • Show All 549 Lines • ▼ Show 20 Lines	foreach m = MxListF in {
defvar WriteVFCvtIToFV_MX = !cast<SchedWrite>("WriteVFCvtIToFV_" # mx);		defvar WriteVFCvtIToFV_MX = !cast<SchedWrite>("WriteVFCvtIToFV_" # mx);
defvar ReadVFCvtIToFV_MX = !cast<SchedRead>("ReadVFCvtIToFV_" # mx);		defvar ReadVFCvtIToFV_MX = !cast<SchedRead>("ReadVFCvtIToFV_" # mx);

defm _V : VPseudoConversionRM<m.vrclass, m.vrclass, m>,		defm _V : VPseudoConversionRM<m.vrclass, m.vrclass, m>,
Sched<[WriteVFCvtIToFV_MX, ReadVFCvtIToFV_MX, ReadVMask]>;		Sched<[WriteVFCvtIToFV_MX, ReadVFCvtIToFV_MX, ReadVMask]>;
}		}
}		}

multiclass VPseudoConversionW_V {
defvar constraint = "@earlyclobber $rd";
foreach m = MxListW in
defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint>;
}

multiclass VPseudoVWCVTI_V {		multiclass VPseudoVWCVTI_V {
defvar constraint = "@earlyclobber $rd";		defvar constraint = "@earlyclobber $rd";
foreach m = MxListFW in {		foreach m = MxListFW in {
defvar mx = m.MX;		defvar mx = m.MX;
defvar WriteVFWCvtFToIV_MX = !cast<SchedWrite>("WriteVFWCvtFToIV_" # mx);		defvar WriteVFWCvtFToIV_MX = !cast<SchedWrite>("WriteVFWCvtFToIV_" # mx);
defvar ReadVFWCvtFToIV_MX = !cast<SchedRead>("ReadVFWCvtFToIV_" # mx);		defvar ReadVFWCvtFToIV_MX = !cast<SchedRead>("ReadVFWCvtFToIV_" # mx);

defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint>,		defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint>,
▲ Show 20 Lines • Show All 3,752 Lines • Show Last 20 Lines