This is an archive of the discontinued LLVM Phabricator instance.

Differential D155550

[RISCV] Add test coverage for peephole vmerge optimization of unmasked rvv instruction with a rounding mode (NFC)
ClosedPublic

Authored by eopXD on Jul 18 2023, 12:09 AM.

Details

Reviewers
fakepaper56
craig.topper
kito-cheng
Commits
rGca7245734607: [RISCV] Add test coverage for peephole vmerge optimization of unmasked rvv…
Summary

No functional change intended.

Diff Detail

Event Timeline

eopXD created this revision.Jul 18 2023, 12:09 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 18 2023, 12:09 AM
Herald added subscribers: jobnoorman, luke, VincentWu and 26 others. · View Herald Transcript
eopXD requested review of this revision.Jul 18 2023, 12:09 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 18 2023, 12:09 AM
Herald added subscribers: llvm-commits, wangpc, MaskRay. · View Herald Transcript
eopXD retitled this revision from [RISCV] Add test coverage for peephole vmerge optimization of unmasked rvv instruction with a rounding mode to [RISCV] Add test coverage for peephole vmerge optimization of unmasked rvv instruction with a rounding mode (NFC).Jul 18 2023, 12:09 AM
eopXD edited the summary of this revision. (Show Details)
fakepaper56 accepted this revision.Jul 18 2023, 1:28 AM

LGTM.

This revision is now accepted and ready to land.Jul 18 2023, 1:28 AM
Harbormaster completed remote builds in B246090: Diff 541344.Jul 18 2023, 3:19 AM
Closed by commit rGca7245734607: [RISCV] Add test coverage for peephole vmerge optimization of unmasked rvv… (authored by eopXD). · Explain WhyJul 18 2023, 10:04 AM
This revision was automatically updated to reflect the committed changes.
eopXD added a commit: rGca7245734607: [RISCV] Add test coverage for peephole vmerge optimization of unmasked rvv….

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
rvv/
16 lines

Diff 541613

llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll

Show First 20 Lines • Show All 954 Lines • ▼ Show 20 Linesentry:
%0 = call <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16.i64(<vscale x 32 x i16> undef, <vscale x 32 x i16>* null, i64 1) %0 = call <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16.i64(<vscale x 32 x i16> undef, <vscale x 32 x i16>* null, i64 1)
%1 = tail call <vscale x 32 x i8> @llvm.riscv.vssubu.mask.nxv32i8.i8.i64(<vscale x 32 x i8> zeroinitializer, <vscale x 32 x i8> zeroinitializer, i8 0, <vscale x 32 x i1> zeroinitializer, i64 0, i64 0) %1 = tail call <vscale x 32 x i8> @llvm.riscv.vssubu.mask.nxv32i8.i8.i64(<vscale x 32 x i8> zeroinitializer, <vscale x 32 x i8> zeroinitializer, i8 0, <vscale x 32 x i1> zeroinitializer, i64 0, i64 0)
%2 = tail call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %1, <vscale x 32 x i8> zeroinitializer, i64 0) %2 = tail call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> %1, <vscale x 32 x i8> zeroinitializer, i64 0)
%3 = tail call <vscale x 32 x i16> @llvm.riscv.vmerge.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> zeroinitializer, <vscale x 32 x i16> zeroinitializer, <vscale x 32 x i16> %0, <vscale x 32 x i1> %2, i64 1) %3 = tail call <vscale x 32 x i16> @llvm.riscv.vmerge.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> zeroinitializer, <vscale x 32 x i16> zeroinitializer, <vscale x 32 x i16> %0, <vscale x 32 x i1> %2, i64 1)
call void @llvm.riscv.vse.nxv32i16.i64(<vscale x 32 x i16> %3, <vscale x 32 x i16>* null, i64 0) call void @llvm.riscv.vse.nxv32i16.i64(<vscale x 32 x i16> %3, <vscale x 32 x i16>* null, i64 0)
ret void ret void
} }
define <vscale x 1 x i16> @test_vaaddu(<vscale x 1 x i16> %var_11, i16 zeroext %var_9, <vscale x 1 x i1> %var_5, <vscale x 1 x i16> %var_0) {
; CHECK-LABEL: test_vaaddu:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 3, e16, mf4, ta, mu
; CHECK-NEXT: csrwi vxrm, 0
; CHECK-NEXT: vaaddu.vx v9, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%0 = tail call <vscale x 1 x i16> @llvm.riscv.vaaddu.nxv1i16.i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %var_11, i16 %var_9, i64 0, i64 3)
%1 = tail call <vscale x 1 x i16> @llvm.riscv.vmerge.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %var_0, <vscale x 1 x i16> %0, <vscale x 1 x i1> %var_5, i64 3)
ret <vscale x 1 x i16> %1
}
declare <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16.i64(<vscale x 32 x i16>, <vscale x 32 x i16>* nocapture, i64) declare <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16.i64(<vscale x 32 x i16>, <vscale x 32 x i16>* nocapture, i64)
declare <vscale x 32 x i8> @llvm.riscv.vssubu.mask.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, <vscale x 32 x i1>, i64, i64 immarg) declare <vscale x 32 x i8> @llvm.riscv.vssubu.mask.nxv32i8.i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i8, <vscale x 32 x i1>, i64, i64 immarg)
declare <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64) declare <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>, <vscale x 32 x i8>, i64)
declare <vscale x 32 x i16> @llvm.riscv.vmerge.nxv32i16.nxv32i16.i64(<vscale x 32 x i16>, <vscale x 32 x i16>, <vscale x 32 x i16>, <vscale x 32 x i1>, i64) declare <vscale x 32 x i16> @llvm.riscv.vmerge.nxv32i16.nxv32i16.i64(<vscale x 32 x i16>, <vscale x 32 x i16>, <vscale x 32 x i16>, <vscale x 32 x i1>, i64)
declare void @llvm.riscv.vse.nxv32i16.i64(<vscale x 32 x i16>, <vscale x 32 x i16>* nocapture, i64) declare void @llvm.riscv.vse.nxv32i16.i64(<vscale x 32 x i16>, <vscale x 32 x i16>* nocapture, i64)
declare <vscale x 1 x i16> @llvm.riscv.vaaddu.nxv1i16.i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, i16, i64 immarg, i64)
declare <vscale x 1 x i16> @llvm.riscv.vmerge.nxv1i16.nxv1i16.i64(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)