[InstCombine] Allow SimplifyDemandedVectorElts to look through freeze

[nikic]

I think this is legal, but I believe we need to preserve the current results in shufflevector_freezepoison.ll -- it's a pattern we try to intentionally preserve to the backend.

[foad]

I think this is legal, but I believe we need to preserve the current results in shufflevector_freezepoison.ll -- it's a pattern we try to intentionally preserve to the backend.

I don't understand the bigger picture here. Why do we ever combine "freeze poison" into undef? In which cases do we not want to do that?

[nlopes]

llvm/test/Transforms/InstCombine/shufflevector_freezepoison.ll

17

this transformation isn't correct.
It replaces <a[0], a[1], freeze poison, freeze poison>
with: <a[0], a[1], poison, poison>.

OOB or poison indexes in the mask yield a poison element.

Not sure if the bug is in this patch or if it was already there though. The code needs probably needs to separate undef from poison elements.

llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp

if (VWidth == InVWidth) {
         if (SubUndef.popcount() == Ratio)
           UndefElts.setBit(OutIdx);
       }
     } else {
       llvm_unreachable("Unimp");
     }
     break;
   }
+  case Instruction::Freeze:
   case Instruction::FPTrunc:
   case Instruction::FPExt:
     simplifyAndSetOp(I, 0, DemandedElts, UndefElts);
     break;
 
   case Instruction::Call: {
     IntrinsicInst *II = dyn_cast<IntrinsicInst>(I);
     if (!II) break;

llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll

 ;
   %data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
   %elt0 = extractelement <2 x float> %data, i32 0
   ret float %elt0
 }
 
 define amdgpu_ps float @extract_elt0_freeze_buffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
 ; CHECK-LABEL: @extract_elt0_freeze_buffer_load_v2f32(
-; CHECK-NEXT:    [[DATA:%.*]] = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> [[RSRC:%.*]], i32 [[IDX:%.*]], i32 [[OFS:%.*]], i1 false, i1 false)
-; CHECK-NEXT:    [[FREEZE:%.*]] = freeze <2 x float> [[DATA]]
+; CHECK-NEXT:    [[DATA:%.*]] = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> [[RSRC:%.*]], i32 [[IDX:%.*]], i32 [[OFS:%.*]], i1 false, i1 false)
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x float> undef, float [[DATA]], i64 0
+; CHECK-NEXT:    [[FREEZE:%.*]] = freeze <2 x float> [[TMP1]]
 ; CHECK-NEXT:    [[ELT0:%.*]] = extractelement <2 x float> [[FREEZE]], i64 0
 ; CHECK-NEXT:    ret float [[ELT0]]
 ;
   %data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
   %freeze = freeze <2 x float> %data
   %elt0 = extractelement <2 x float> %freeze, i32 0
   ret float %elt0
 }

llvm/test/Transforms/InstCombine/shufflevector_freezepoison.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -passes='instcombine' -S %s | FileCheck %s
 
 
 define <4 x double> @shuffle_op0_freeze_poison(<2 x double> %a) {
 ; CHECK-LABEL: @shuffle_op0_freeze_poison(
-; CHECK-NEXT:    [[B:%.*]] = freeze <2 x double> poison
-; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <2 x double> [[B]], <2 x double> [[A:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <2 x double> [[A:%.*]], <2 x double> undef, <4 x i32> <i32 poison, i32 poison, i32 0, i32 1>
 ; CHECK-NEXT:    ret <4 x double> [[SHUFFLE]]
 ;
   %b = freeze <2 x double> poison
   %shuffle = shufflevector <2 x double> %b, <2 x double> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x double> %shuffle
 }
 
 define <4 x double> @shuffle_op1_freeze_poison(<2 x double> %a) {
 ; CHECK-LABEL: @shuffle_op1_freeze_poison(
-; CHECK-NEXT:    [[B:%.*]] = freeze <2 x double> poison
-; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <2 x double> [[A:%.*]], <2 x double> [[B]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <2 x double> [[A:%.*]], <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
 ; CHECK-NEXT:    ret <4 x double> [[SHUFFLE]]
 ;
   %b = freeze <2 x double> poison
   %shuffle = shufflevector <2 x double> %a, <2 x double> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x double> %shuffle
 }
 
 define <4 x double> @shuffle_op0_freeze_poison_use(<2 x double> %a) {
;
   %b = freeze <2 x double> undef
   call void @use(<2 x double> %b)
   %shuffle = shufflevector <2 x double> %a, <2 x double> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x double> %shuffle
 }
 
 define <4 x double> @shuffle_bc1(<2 x double>  %a)  {
 ; CHECK-LABEL: @shuffle_bc1(
-; CHECK-NEXT:    [[B:%.*]] = freeze <4 x float> poison
-; CHECK-NEXT:    [[B1:%.*]] = bitcast <4 x float> [[B]] to <2 x double>
-; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <2 x double> [[A:%.*]], <2 x double> [[B1]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <2 x double> [[A:%.*]], <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
 ; CHECK-NEXT:    ret <4 x double> [[SHUFFLE]]
 ;
   %b = freeze <4 x float> poison
   %b1 = bitcast <4 x float> %b to <2 x double>
   %shuffle = shufflevector <2 x double> %a, <2 x double> %b1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x double> %shuffle
 }
 

llvm/test/Transforms/InstCombine/vec_demanded_elts.ll

;
   %b_xy = sub nsw <2 x i4> %x, %y
   %b_xy0 = extractelement <2 x i4> %b_xy, i32 1
   call void @use(<2 x i4> %b_xshuf_y)
   ret i4 %b_xy0
 }
 
 define i32 @test_freeze(<4 x i32> %v, i32 %x) {
 ; CHECK-LABEL: @test_freeze(
-; CHECK-NEXT:    [[INS:%.*]] = insertelement <4 x i32> [[V:%.*]], i32 [[X:%.*]], i64 0
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <4 x i32> poison, i32 [[X:%.*]], i64 0
 ; CHECK-NEXT:    [[FR:%.*]] = freeze <4 x i32> [[INS]]
 ; CHECK-NEXT:    [[RET:%.*]] = extractelement <4 x i32> [[FR]], i64 0
 ; CHECK-NEXT:    ret i32 [[RET]]
 ;
   %ins = insertelement <4 x i32> %v, i32 %x, i64 0
   %fr = freeze <4 x i32> %ins
   %ret = extractelement  <4 x i32> %fr, i64 0
   ret i32 %ret
 }