This is an archive of the discontinued LLVM Phabricator instance.

Differential D155296

[InstCombine] Precommit tests for D155295
AcceptedPublic

Authored by foad on Jul 14 2023, 7:37 AM.

Details

Reviewers
nikic
arsenm
Group Reviewers
Restricted Project

Diff Detail

Event Timeline

foad created this revision.Jul 14 2023, 7:37 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 14 2023, 7:37 AM
Herald added subscribers: StephenFan, kerbowa, jvesely. · View Herald Transcript
foad requested review of this revision.Jul 14 2023, 7:37 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 14 2023, 7:37 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
foad added a child revision: D155295: [InstCombine] Allow SimplifyDemandedVectorElts to look through freeze.Jul 14 2023, 7:38 AM
Harbormaster completed remote builds in B245390: Diff 540415.Jul 14 2023, 9:01 AM
arsenm accepted this revision.Aug 1 2023, 5:51 PM
arsenm added a subscriber: arsenm.

Can't go wrong adding tests?

This revision is now accepted and ready to land.Aug 1 2023, 5:51 PM
Herald added a subscriber: wdng. · View Herald TranscriptAug 1 2023, 5:51 PM

Revision Contents

PathSize
llvm/
test/
Transforms/
InstCombine/
AMDGPU/
13 lines
13 lines

Diff 540415

llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> [[RSRC:%.*]], i32 [[IDX:%.*]], i32 [[OFS:%.*]], i1 false, i1 false) ; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> [[RSRC:%.*]], i32 [[IDX:%.*]], i32 [[OFS:%.*]], i1 false, i1 false)
; CHECK-NEXT: ret float [[DATA]] ; CHECK-NEXT: ret float [[DATA]]
; ;
%data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false) %data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
%elt0 = extractelement <2 x float> %data, i32 0 %elt0 = extractelement <2 x float> %data, i32 0
ret float %elt0 ret float %elt0
} }
define amdgpu_ps float @extract_elt0_freeze_buffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
; CHECK-LABEL: @extract_elt0_freeze_buffer_load_v2f32(
; CHECK-NEXT: [[DATA:%.*]] = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> [[RSRC:%.*]], i32 [[IDX:%.*]], i32 [[OFS:%.*]], i1 false, i1 false)
; CHECK-NEXT: [[FREEZE:%.*]] = freeze <2 x float> [[DATA]]
; CHECK-NEXT: [[ELT0:%.*]] = extractelement <2 x float> [[FREEZE]], i64 0
; CHECK-NEXT: ret float [[ELT0]]
;
%data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
%freeze = freeze <2 x float> %data
%elt0 = extractelement <2 x float> %freeze, i32 0
ret float %elt0
}
define amdgpu_ps float @extract_elt1_buffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 { define amdgpu_ps float @extract_elt1_buffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
; CHECK-LABEL: @extract_elt1_buffer_load_v2f32( ; CHECK-LABEL: @extract_elt1_buffer_load_v2f32(
; CHECK-NEXT: [[DATA:%.*]] = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> [[RSRC:%.*]], i32 [[IDX:%.*]], i32 [[OFS:%.*]], i1 false, i1 false) ; CHECK-NEXT: [[DATA:%.*]] = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> [[RSRC:%.*]], i32 [[IDX:%.*]], i32 [[OFS:%.*]], i1 false, i1 false)
; CHECK-NEXT: [[ELT1:%.*]] = extractelement <2 x float> [[DATA]], i64 1 ; CHECK-NEXT: [[ELT1:%.*]] = extractelement <2 x float> [[DATA]], i64 1
; CHECK-NEXT: ret float [[ELT1]] ; CHECK-NEXT: ret float [[ELT1]]
; ;
%data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false) %data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
%elt1 = extractelement <2 x float> %data, i32 1 %elt1 = extractelement <2 x float> %data, i32 1
▲ Show 20 Lines • Show All 6,003 Lines • Show Last 20 Lines

llvm/test/Transforms/InstCombine/vec_demanded_elts.ll

Show First 20 Lines • Show All 1,153 Lines • ▼ Show 20 Lines
; ;
%xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer %xshuf = shufflevector <2 x i4> %x, <2 x i4> poison, <2 x i32> zeroinitializer
%b_xshuf_y = sub <2 x i4> %xshuf, %y %b_xshuf_y = sub <2 x i4> %xshuf, %y
%b_xy = sub nsw <2 x i4> %x, %y %b_xy = sub nsw <2 x i4> %x, %y
%b_xy0 = extractelement <2 x i4> %b_xy, i32 1 %b_xy0 = extractelement <2 x i4> %b_xy, i32 1
call void @use(<2 x i4> %b_xshuf_y) call void @use(<2 x i4> %b_xshuf_y)
ret i4 %b_xy0 ret i4 %b_xy0
} }
define i32 @test_freeze(<4 x i32> %v, i32 %x) {
; CHECK-LABEL: @test_freeze(
; CHECK-NEXT: [[INS:%.*]] = insertelement <4 x i32> [[V:%.*]], i32 [[X:%.*]], i64 0
; CHECK-NEXT: [[FR:%.*]] = freeze <4 x i32> [[INS]]
; CHECK-NEXT: [[RET:%.*]] = extractelement <4 x i32> [[FR]], i64 0
; CHECK-NEXT: ret i32 [[RET]]
;
%ins = insertelement <4 x i32> %v, i32 %x, i64 0
%fr = freeze <4 x i32> %ins
%ret = extractelement <4 x i32> %fr, i64 0
ret i32 %ret
}