[RISCV] Add isMoveReg to vmv1r/vmv2r/vmv4r/vmv8r.v.

[craig.topper]

Summary

This allows TII isCopyInstrImpl to consider them copies.

[wangpc]

Is it possible to add a MIR test that performs MCP on vector registers?

[craig.topper]

Add a test that causes tail duplication to create a copy that can be removed.

[wangpc]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

def VRGATHEREI16_VV : VALUVV<0b001110, OPIVV, "vrgatherei16.vv">,
                              ReadVRGatherVV_index_WorstCase]>;
 } // Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather
 
 // Vector Compress Instruction
 let Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress in {
 defm VCOMPRESS_V : VCPR_MV_Mask<"vcompress", 0b010111>;
 } // Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress
 
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isMoveReg = 1,
     RVVConstraint = NoConstraint in {
 // A future extension may relax the vector register alignment restrictions.
 foreach n = [1, 2, 4, 8] in {
   defvar vrc = !cast<VReg>(!if(!eq(n, 1), "VR", "VRM"#n));
   def VMV#n#R_V  : RVInstV<0b100111, !add(n, -1), OPIVI, (outs vrc:$vd),
                            (ins vrc:$vs2), "vmv" # n # "r.v", "$vd, $vs2">,
                    VMVRSched<n> {
     let Uses = [];

llvm/test/CodeGen/RISCV/rvv/copyprop.mir

--- |
   ; CHECK-NEXT:  .LBB0_2: # %entry
   ; CHECK-NEXT:    vse64.v v8, (a1)
   ; CHECK-NEXT:    ret
   ; CHECK-NEXT:  .LBB0_3:
   ; CHECK-NEXT:    vmv.v.i v8, 0
   ; CHECK-NEXT:    li a2, 128
   ; CHECK-NEXT:    bgeu a0, a2, .LBB0_2
   ; CHECK-NEXT:  .LBB0_4: # %entry
-  ; CHECK-NEXT:    vmv1r.v v8, v9
-  ; CHECK-NEXT:    vse64.v v8, (a1)
+  ; CHECK-NEXT:    vse64.v v9, (a1)
   ; CHECK-NEXT:    ret
   entry:
     ret void
   }
 ...
 ---
 name:            foo
 tracksRegLiveness: true