[LegalizeDAG] Prevent LegalizeLoadOps from creating extloads that mix int and fp types.

[craig.topper]

Summary

For RISC-V, getRegisterType for fp16 returns i16. i16->fp64 extload
is considered legal because the LoadExtActions defaults to Legal
for all entries. Only fp/fp and int/int entries are changed to
Expand fore RISC-V.

This patch detects the FP-ness has changed and won't try to call
isLoadExtLegal.

Alternatively, we could add Expand for int/fp and fp/int, but that
seemed a little silly.

Fixes #63816

[wangpc]

LGTM

[asb]

LGTM.

llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

case TargetLowering::Legal:
       break;
 
     case TargetLowering::Expand: {
       EVT DestVT = Node->getValueType(0);
       if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) {
         // If the source type is not legal, see if there is a legal extload to
         // an intermediate type that we can then extend further.
         EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT());
-        if (TLI.isTypeLegal(SrcVT) || // Same as SrcVT == LoadVT?
-            TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) {
+        if ((LoadVT.isFloatingPoint() == SrcVT.isFloatingPoint()) &&
+            (TLI.isTypeLegal(SrcVT) || // Same as SrcVT == LoadVT?
+             TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT))) {
           // If we are loading a legal type, this is a non-extload followed by a
           // full extend.
           ISD::LoadExtType MidExtType =
               (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType;
 
           SDValue Load = DAG.getExtLoad(MidExtType, dl, LoadVT, Chain, Ptr,
                                         SrcVT, LD->getMemOperand());
           unsigned ExtendOp =

llvm/test/CodeGen/RISCV/pr63816.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc < %s -mtriple=riscv64 -mattr=+d | FileCheck %s
+
+define void @test(ptr %0, ptr %1) nounwind {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -80
+; CHECK-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s1, 56(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    fsd fs0, 48(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    fsd fs1, 40(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    fsd fs2, 32(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    fsd fs3, 24(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    fsd fs4, 16(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    fsd fs5, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    fsd fs6, 0(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    mv s0, a1
+; CHECK-NEXT:    mv s1, a0
+; CHECK-NEXT:    lhu a0, 12(a0)
+; CHECK-NEXT:    fmv.w.x fa0, a0
+; CHECK-NEXT:    call __extendhfsf2@plt
+; CHECK-NEXT:    fmv.s fs0, fa0
+; CHECK-NEXT:    lhu a0, 10(s1)
+; CHECK-NEXT:    fmv.w.x fa0, a0
+; CHECK-NEXT:    call __extendhfsf2@plt
+; CHECK-NEXT:    fmv.s fs1, fa0
+; CHECK-NEXT:    lhu a0, 8(s1)
+; CHECK-NEXT:    fmv.w.x fa0, a0
+; CHECK-NEXT:    call __extendhfsf2@plt
+; CHECK-NEXT:    fmv.s fs2, fa0
+; CHECK-NEXT:    lhu a0, 6(s1)
+; CHECK-NEXT:    fmv.w.x fa0, a0
+; CHECK-NEXT:    call __extendhfsf2@plt
+; CHECK-NEXT:    fmv.s fs3, fa0
+; CHECK-NEXT:    lhu a0, 4(s1)
+; CHECK-NEXT:    fmv.w.x fa0, a0
+; CHECK-NEXT:    call __extendhfsf2@plt
+; CHECK-NEXT:    fmv.s fs4, fa0
+; CHECK-NEXT:    lhu a0, 2(s1)
+; CHECK-NEXT:    fmv.w.x fa0, a0
+; CHECK-NEXT:    call __extendhfsf2@plt
+; CHECK-NEXT:    fmv.s fs5, fa0
+; CHECK-NEXT:    lhu a0, 0(s1)
+; CHECK-NEXT:    fmv.w.x fa0, a0
+; CHECK-NEXT:    call __extendhfsf2@plt
+; CHECK-NEXT:    fcvt.d.s fs6, fa0
+; CHECK-NEXT:    fcvt.d.s fs5, fs5
+; CHECK-NEXT:    fcvt.d.s fs4, fs4
+; CHECK-NEXT:    lhu a0, 14(s1)
+; CHECK-NEXT:    fcvt.d.s fs3, fs3
+; CHECK-NEXT:    fcvt.d.s fs2, fs2
+; CHECK-NEXT:    fcvt.d.s fs1, fs1
+; CHECK-NEXT:    fmv.w.x fa0, a0
+; CHECK-NEXT:    fcvt.d.s fs0, fs0
+; CHECK-NEXT:    call __extendhfsf2@plt
+; CHECK-NEXT:    fcvt.d.s fa5, fa0
+; CHECK-NEXT:    fsd fa5, 56(s0)
+; CHECK-NEXT:    fsd fs0, 48(s0)
+; CHECK-NEXT:    fsd fs1, 40(s0)
+; CHECK-NEXT:    fsd fs2, 32(s0)
+; CHECK-NEXT:    fsd fs3, 24(s0)
+; CHECK-NEXT:    fsd fs4, 16(s0)
+; CHECK-NEXT:    fsd fs5, 8(s0)
+; CHECK-NEXT:    fsd fs6, 0(s0)
+; CHECK-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s1, 56(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    fld fs0, 48(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    fld fs1, 40(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    fld fs2, 32(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    fld fs3, 24(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    fld fs4, 16(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    fld fs5, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    fld fs6, 0(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 80
+; CHECK-NEXT:    ret
+  %V1 = load <8 x half>, ptr %0
+  %V2 = fpext <8 x half> %V1 to <8 x double>
+  store <8 x double> %V2, ptr %1
+  ret void
+}
+