[ARM] Correctly handle execute-only in EmitStructByval

[john.brawn]

Summary

Currently when compiling for an execute-only target without movt then EmitStructByval will generate a constant pool load which isn't compatible with execute-only. Handle this by emitting tMOVi32imm, and also simplify the existing movt handling by emitting t2MOVi32imm or MOVi32imm.

[simonwallis2]

I've run some tests locally in various configurations. This patch fixes all the outstanding v6m XO faults that I know of.

[john.brawn]

Re-committed now that D155301 has been committed.

llvm/lib/Target/ARM/ARMISelLowering.cpp

ARMTargetLowering::EmitStructByval(MachineInstr &MI,
   // Transfer the remainder of BB and its successor edges to exitMBB.
   exitMBB->splice(exitMBB->begin(), BB,
                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
   exitMBB->transferSuccessorsAndUpdatePHIs(BB);
 
   // Load an immediate to varEnd.
   Register varEnd = MRI.createVirtualRegister(TRC);
   if (Subtarget->useMovt()) {
-    unsigned Vtmp = varEnd;
-    if ((LoopSize & 0xFFFF0000) != 0)
-      Vtmp = MRI.createVirtualRegister(TRC);
-    BuildMI(BB, dl, TII->get(IsThumb ? ARM::t2MOVi16 : ARM::MOVi16), Vtmp)
-        .addImm(LoopSize & 0xFFFF)
-        .add(predOps(ARMCC::AL));
-
-    if ((LoopSize & 0xFFFF0000) != 0)
-      BuildMI(BB, dl, TII->get(IsThumb ? ARM::t2MOVTi16 : ARM::MOVTi16), varEnd)
-          .addReg(Vtmp)
-          .addImm(LoopSize >> 16)
-          .add(predOps(ARMCC::AL));
+    BuildMI(BB, dl, TII->get(IsThumb ? ARM::t2MOVi32imm : ARM::MOVi32imm),
+            varEnd)
+        .addImm(LoopSize);
+  } else if (Subtarget->genExecuteOnly()) {
+    assert(IsThumb && "Non-thumb expected to have used movt");
+    BuildMI(BB, dl, TII->get(ARM::tMOVi32imm), varEnd).addImm(LoopSize);
   } else {
     MachineConstantPool *ConstantPool = MF->getConstantPool();
     Type *Int32Ty = Type::getInt32Ty(MF->getFunction().getContext());
     const Constant *C = ConstantInt::get(Int32Ty, LoopSize);
 
     // MachineConstantPool wants an explicit alignment.
     Align Alignment = MF->getDataLayout().getPrefTypeAlign(Int32Ty);
     unsigned Idx = ConstantPool->getConstantPoolIndex(C, Alignment);

llvm/test/CodeGen/ARM/execute-only.ll

 ; CHECK-T1: movs [[IMMDEST]], #34
 ; CHECK-T1-NEXT: lsls [[IMMDEST]], [[IMMDEST]], #8
 ; CHECK-T1-NEXT: adds [[IMMDEST]], #51
 ; CHECK-T1-NEXT: lsls [[IMMDEST]], [[IMMDEST]], #8
 ; CHECK-T1-NEXT: bx lr
 
   ret i32 u0x223300
 }
+
+; This struct is sized so that the byval call does an inline memcpy of
+; 0x10001 bytes.
+%struct.struct_t = type { [65553 x i8] }
+@byval_arg = global %struct.struct_t zeroinitializer
+declare void @byval_fn(ptr byval(%struct.struct_t))
+
+define void @test_byval_call() {
+entry:
+; CHECK-LABEL: test_byval_call:
+; CHECK-T2BASE: movw [[BYVAL_CPYSIZE:r[0-9]+]], #1
+; CHECK-T2: movs [[BYVAL_CPYSIZE:r[0-9]+]], #1
+; CHECK: movt [[BYVAL_CPYSIZE]], #1
+; CHECK-T1-LABEL: test_byval_call:
+; CHECK-T1: movs [[BYVAL_CPYSIZE:r[0-9]+]], #1
+; CHECK-T1: lsls [[BYVAL_CPYSIZE]], [[BYVAL_CPYSIZE]], #16
+; CHECK-T1: adds [[BYVAL_CPYSIZE]], #1
+
+  call void @byval_fn(ptr byval(%struct.struct_t) @byval_arg)
+  ret void
+}