[lldb][AArch64] Add SME's streaming vector control register

[DavidSpickett]

Summary

Software can tell if it is in streaming SVE mode by checking
the Streaming Vector Control Register (SVCR).

"E3.1.9 SVCR, Streaming Vector Control Register" in
"Arm® Architecture Reference Manual Supplement, The Scalable Matrix
Extension (SME), for Armv9-A"

https://developer.arm.com/documentation/ddi0616/latest/

This is especially useful for debug because the names of the
SVE registers are the same betweeen non-streaming and streaming mode.

The Linux Kernel chose to not put this register behind ptrace,
and it can be read from EL0. However, this would mean running code
in process to read it. That can be done but we already know all
the information just from ptrace.

So this is a pseudo register that matches the architectural
content. The name is just "svcr", which aligns with GDB's proposed naming,
and it's added to the existing SME register set.

The SVCR register contains two bits:
0 : Whether streaming SVE mode is enabled (SM)
1 : Whether the array storage is enabled (ZA)

Array storage can be active when streaming mode is not, so this register
can have any permutation of those bits.

This register is currently read only. We can emulate the result of
writing to it, using ptrace. However at this point the utility of that
is not obvious.

Existing tests have been updated to check for appropriate SVCR values
at various points.

Given that this register is a read only pseudo, there is no need
to save and restore it around expressions.

[omjavaid]

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp

325

typo: pseudo register?

1003

is there a need here to check if m_sve_state is valid?

[DavidSpickett]

Rebase, fix typo.

[DavidSpickett]

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp

1003

The only "invalid" state we can check at the moment is SVEState::Unknown. Which would translate here to a value of 0 in the register, which isn't incorrect, it's just pesimistic.

By the time you're printing this register you'd likely have checked the state fully. Maybe it would come back as SVEState::Disabled, but in that case you wouldn't have SME anyway so this register isn't available to you.

[DavidSpickett]

Add missing newline.

lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py

30

This is the check promised in the previous patch. It ensures that when we return from evaluating the expression we do restore the previous operating mode.

[omjavaid]

I guess there is not much gain from telling the user between sve/ssve mode for the moment. Can we defer this patch till SME registers are implemented?

[DavidSpickett]

In some sense it already is, it'll go in after the streaming mode SVE registers. Should we wait until we can show the full content including the ZA bit? Yeah, why not, we're in no rush.

I have a patch locally for ZA support that I'm working on. I'll reorder this to after that and when I update this, it will have the full SVCR contents.

[DavidSpickett]

Rebase and reimplement this on top of ZA/SVG.

[DavidSpickett]

Correct regiter -> register in comment.

[DavidSpickett]

Rebase

[DavidSpickett]

ZA is now part of the SME set so SVCR is stuck in before SVG.

SVCR
SVG
ZA

Updated the various indexes to reflect that.

[DavidSpickett]

Format with black.

[DavidSpickett]

Rebase

[DavidSpickett]

Rebase, use new sme_pseudo_regs naming.

[DavidSpickett]

Rebase

[omjavaid]

Are

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp

1012

Shouldnt we build a relevant error message here incase ReadSMEControl fails on ReadZAHeader

lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py

183 ↗

(On Diff #557011)

should we also add a svcr write test here?

[DavidSpickett]

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp

1012

I think this should be return error in fact, let me check what that does.

lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py

183 ↗

(On Diff #557011)

It's read only. We could allow writes but it introduces a lot more ways to change state, most of which aren't obviously useful for the user. If someone really wants it, it can be added.

I will note this in a comment here.

[DavidSpickett]

• Return error in SVCR read.
• Note absence of write tests of SVCR because it's read only.

[DavidSpickett]

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp

1012

I now return the underlying error so it won't fail silently.

lldb/test/API/commands/register/register/aarch64_za_register/za_save_restore/TestZARegisterSaveRestore.py

183 ↗

(On Diff #557011)

I've actually added comments to the other file, where it makes more sense that you might be writing to svcr.

Here the whole test is about having the program setup the registers, and modify them. So there's less expectation that you'd check writing here.

The fact that SVCR is read only (as is SVG) will be documented in fully https://github.com/llvm/llvm-project/pull/66767.

[omjavaid]

This is good too. Thanks!!!

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h

 //===-- NativeRegisterContextLinux_arm64.h ---------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
private:
   struct user_pac_mask {
     uint64_t data_mask;
     uint64_t insn_mask;
   };
 
   struct user_pac_mask m_pac_mask;
 
   uint64_t m_mte_ctrl_reg;
+  uint64_t m_sme_ctrl_reg;
 
   uint64_t m_tls_tpidr_reg;
 
   bool IsGPR(unsigned reg) const;
 
   bool IsFPR(unsigned reg) const;
 
   SVEStateData &CurrentSVEStateData() {
private:
   Status ReadMTEControl();
 
   Status WriteMTEControl();
 
   Status ReadTLSTPIDR();
 
   Status WriteTLSTPIDR();
 
+  // SVCR is a pseudo register and we do not allow writes to it.
+  Status ReadSMEControl();
+
   bool IsSVE(unsigned reg) const;
   bool IsPAuth(unsigned reg) const;
   bool IsMTE(unsigned reg) const;
   bool IsTLS(unsigned reg) const;
+  bool IsSME(unsigned reg) const;
 
   uint64_t GetSVERegVG() { return CurrentSVEStateData().m_header.vl / 8; }
 
   void SetSVERegVG(uint64_t vg) { CurrentSVEStateData().m_header.vl = vg * 8; }
 
   void *GetPACMask() { return &m_pac_mask; }
 
   void *GetMTEControl() { return &m_mte_ctrl_reg; }
 
   void *GetTLSTPIDR() { return &m_tls_tpidr_reg; }
 
+  void *GetSMEControl() { return &m_sme_ctrl_reg; }
+
   void *GetSVEBuffer() { return CurrentSVEStateData().m_buffer.data(); }
 
   size_t GetSVEBufferSize() { return CurrentSVEStateData().m_buffer.size(); }
 
   void *GetSVEHeader() { return &(CurrentSVEStateData().m_header); }
 
   size_t GetSVEHeaderSize() { return sizeof(CurrentSVEStateData().m_header); }
 
   size_t GetPACMaskSize() { return sizeof(m_pac_mask); }
 
   size_t GetMTEControlSize() { return sizeof(m_mte_ctrl_reg); }
 
   size_t GetTLSTPIDRSize() { return sizeof(m_tls_tpidr_reg); }
 
+  size_t GetSMEControlSize() { return sizeof(m_sme_ctrl_reg); }
+
   llvm::Error ReadHardwareDebugInfo() override;
 
   llvm::Error WriteHardwareDebugRegs(DREGType hwbType) override;
 
   uint32_t CalculateFprOffset(const RegisterInfo *reg_info) const;
 
   RegisterInfoPOSIX_arm64 &GetRegisterInfo() const;
 

lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp

 //===-- NativeRegisterContextLinux_arm64.cpp ------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
NativeRegisterContextLinux_arm64::NativeRegisterContextLinux_arm64(
   ::memset(&m_fpr, 0, sizeof(m_fpr));
   ::memset(&m_gpr_arm64, 0, sizeof(m_gpr_arm64));
   ::memset(&m_hwp_regs, 0, sizeof(m_hwp_regs));
   ::memset(&m_hbp_regs, 0, sizeof(m_hbp_regs));
   ::memset(&m_pac_mask, 0, sizeof(m_pac_mask));
 
   m_mte_ctrl_reg = 0;
   m_tls_tpidr_reg = 0;
+  m_sme_ctrl_reg = 0;
 
   // 16 is just a maximum value, query hardware for actual watchpoint count
   m_max_hwp_supported = 16;
   m_max_hbp_supported = 16;
 
   m_refresh_hwdebug_info = true;
 
   m_gpr_is_valid = false;
NativeRegisterContextLinux_arm64::ReadRegister(const RegisterInfo *reg_info,
   } else if (IsMTE(reg)) {
     error = ReadMTEControl();
     if (error.Fail())
       return error;
 
     offset = reg_info->byte_offset - GetRegisterInfo().GetMTEOffset();
     assert(offset < GetMTEControlSize());
     src = (uint8_t *)GetMTEControl() + offset;
+  } else if (IsSME(reg)) {
+    // This is a pseduo so it never fails.
+    ReadSMEControl();
+
+    offset = reg_info->byte_offset - GetRegisterInfo().GetSMEOffset();
+    assert(offset < GetSMEControlSize());
+    src = (uint8_t *)GetSMEControl() + offset;
   } else
     return Status("failed - register wasn't recognized to be a GPR or an FPR, "
                   "write strategy unknown");
 
   reg_value.SetFromMemoryData(*reg_info, src, reg_info->byte_size,
                               eByteOrderLittle, error);
 
   return error;
if (error.Fail())
       return error;
 
     offset = reg_info->byte_offset - GetRegisterInfo().GetTLSOffset();
     assert(offset < GetTLSTPIDRSize());
     dst = (uint8_t *)GetTLSTPIDR() + offset;
     ::memcpy(dst, reg_value.GetBytes(), reg_info->byte_size);
 
     return WriteTLSTPIDR();
+  } else if (IsSME(reg)) {
+    return Status("Writing to SVCR is not supported.");
   }
 
   return Status("Failed to write register value");
 }
 
 Status NativeRegisterContextLinux_arm64::ReadAllRegisterValues(
     lldb::WritableDataBufferSP &data_sp) {
   // AArch64 register data must contain GPRs, either FPR or SVE registers

 bool NativeRegisterContextLinux_arm64::IsMTE(unsigned reg) const {
   return GetRegisterInfo().IsMTEReg(reg);
 }
 
 bool NativeRegisterContextLinux_arm64::IsTLS(unsigned reg) const {
   return GetRegisterInfo().IsTLSReg(reg);
 }
 
+bool NativeRegisterContextLinux_arm64::IsSME(unsigned reg) const {
+  return GetRegisterInfo().IsSMEReg(reg);
+}
+
 llvm::Error NativeRegisterContextLinux_arm64::ReadHardwareDebugInfo() {
   if (!m_refresh_hwdebug_info) {
     return llvm::Error::success();
   }
 
   ::pid_t tid = m_thread.GetID();
 
   int regset = NT_ARM_HW_WATCH;
Status NativeRegisterContextLinux_arm64::WriteAllSVE() {
   // All SIMD/SVE/SSVE state must be re-read after doing this write.
   m_sve_state_data.Invalidate();
   m_ssve_state_data.Invalidate();
   m_fpu_is_valid = false;
 
   return WriteRegisterSet(&ioVec, state.m_buffer.size(), state.m_regset);
 }
 
+Status NativeRegisterContextLinux_arm64::ReadSMEControl() {
+  // The real register is SVCR and is accessible from EL0. However we don't want
+  // to have to JIT code into the target process so we'll just recreate it using
+  // what we know from ptrace.
+  // Bit 1 indicates whether streaming mode is active.
+  // Bit 2 indicates whether the array storage is active (not yet implemented).
+  m_sme_ctrl_reg = m_sve_state == SVEState::Streaming;
+  return {};
+}
+
 Status NativeRegisterContextLinux_arm64::ReadMTEControl() {
   Status error;
 
   if (m_mte_ctrl_is_valid)
     return error;
 
   struct iovec ioVec;
   ioVec.iov_base = GetMTEControl();
   ioVec.iov_len = GetMTEControlSize();
 
   error = ReadRegisterSet(&ioVec, GetMTEControlSize(), NT_ARM_TAGGED_ADDR_CTRL);
 
   if (error.Success())
     m_mte_ctrl_is_valid = true;

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h

 //===-- RegisterInfoPOSIX_arm64.h -------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
public:
   size_t GetRegisterSetFromRegisterIndex(uint32_t reg_index) const override;
 
   void AddRegSetPAuth();
 
   void AddRegSetMTE();
 
   void AddRegSetTLS();
 
+  void AddRegSetSME();
+
   uint32_t ConfigureVectorLength(uint32_t sve_vq);
 
   bool VectorSizeIsValid(uint32_t vq) {
     // coverity[unsigned_compare]
     if (vq >= eVectorQuadwordAArch64 && vq <= eVectorQuadwordAArch64SVEMax)
       return true;
     return false;
   }
 
   bool IsSVEEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskSVE); }
   bool IsSSVEEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskSSVE); }
   bool IsPAuthEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskPAuth); }
   bool IsMTEEnabled() const { return m_opt_regsets.AnySet(eRegsetMaskMTE); }
 
   bool IsSVEReg(unsigned reg) const;
   bool IsSVEZReg(unsigned reg) const;
   bool IsSVEPReg(unsigned reg) const;
   bool IsSVERegVG(unsigned reg) const;
   bool IsPAuthReg(unsigned reg) const;
   bool IsMTEReg(unsigned reg) const;
   bool IsTLSReg(unsigned reg) const;
+  bool IsSMEReg(unsigned reg) const;
 
   uint32_t GetRegNumSVEZ0() const;
   uint32_t GetRegNumSVEFFR() const;
   uint32_t GetRegNumFPCR() const;
   uint32_t GetRegNumFPSR() const;
   uint32_t GetRegNumSVEVG() const;
   uint32_t GetPAuthOffset() const;
   uint32_t GetMTEOffset() const;
   uint32_t GetTLSOffset() const;
+  uint32_t GetSMEOffset() const;
 
 private:
   typedef std::map<uint32_t, std::vector<lldb_private::RegisterInfo>>
       per_vq_register_infos;
 
   per_vq_register_infos m_per_vq_reg_infos;
 
   uint32_t m_vector_reg_vq = eVectorQuadwordAArch64;
private:
   lldb_private::Flags m_opt_regsets;
 
   std::vector<lldb_private::RegisterInfo> m_dynamic_reg_infos;
   std::vector<lldb_private::RegisterSet> m_dynamic_reg_sets;
 
   std::vector<uint32_t> pauth_regnum_collection;
   std::vector<uint32_t> m_mte_regnum_collection;
   std::vector<uint32_t> m_tls_regnum_collection;
+  std::vector<uint32_t> m_sme_regnum_collection;
 };
 
 #endif

lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp

 //===-- RegisterInfoPOSIX_arm64.cpp ---------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===---------------------------------------------------------------------===//
 
static lldb_private::RegisterInfo g_register_infos_pauth[] = {
     DEFINE_EXTENSION_REG(data_mask), DEFINE_EXTENSION_REG(code_mask)};
 
 static lldb_private::RegisterInfo g_register_infos_mte[] = {
     DEFINE_EXTENSION_REG(mte_ctrl)};
 
 static lldb_private::RegisterInfo g_register_infos_tls[] = {
     DEFINE_EXTENSION_REG(tpidr)};
 
+static lldb_private::RegisterInfo g_register_infos_sme[] = {
+    DEFINE_EXTENSION_REG(svcr)};
+
 // Number of register sets provided by this context.
 enum {
   k_num_gpr_registers = gpr_w28 - gpr_x0 + 1,
   k_num_fpr_registers = fpu_fpcr - fpu_v0 + 1,
   k_num_sve_registers = sve_ffr - sve_vg + 1,
   k_num_mte_register = 1,
   k_num_tls_register = 1,
   k_num_pauth_register = 2,
+  k_num_sme_register = 1,
   k_num_register_sets_default = 2,
   k_num_register_sets = 3
 };
 
 // ARM64 general purpose registers.
 static const uint32_t g_gpr_regnums_arm64[] = {
     gpr_x0,  gpr_x1,   gpr_x2,  gpr_x3,
     gpr_x4,  gpr_x5,   gpr_x6,  gpr_x7,
static const lldb_private::RegisterSet g_reg_set_pauth_arm64 = {
     "Pointer Authentication Registers", "pauth", k_num_pauth_register, nullptr};
 
 static const lldb_private::RegisterSet g_reg_set_mte_arm64 = {
     "MTE Control Register", "mte", k_num_mte_register, nullptr};
 
 static const lldb_private::RegisterSet g_reg_set_tls_arm64 = {
     "Thread Local Storage Registers", "tls", k_num_tls_register, nullptr};
 
+static const lldb_private::RegisterSet g_reg_set_sme_arm64 = {
+    "Scalable Matrix Extension Registers", "sme", k_num_sme_register, nullptr};
+
 RegisterInfoPOSIX_arm64::RegisterInfoPOSIX_arm64(
     const lldb_private::ArchSpec &target_arch, lldb_private::Flags opt_regsets)
     : lldb_private::RegisterInfoAndSetInterface(target_arch),
       m_opt_regsets(opt_regsets) {
   switch (target_arch.GetMachine()) {
   case llvm::Triple::aarch64:
   case llvm::Triple::aarch64_32: {
     m_register_set_p = g_reg_sets_arm64;
if (m_opt_regsets.AnySet(eRegsetMaskDynamic)) {
 
       if (m_opt_regsets.AllSet(eRegsetMaskMTE))
         AddRegSetMTE();
 
       // tpidr is always present, but in future there will be others so this is
       // done as a dynamic set.
       AddRegSetTLS();
 
+      if (m_opt_regsets.AllSet(eRegsetMaskSSVE))
+        AddRegSetSME();
+
       m_register_info_count = m_dynamic_reg_infos.size();
       m_register_info_p = m_dynamic_reg_infos.data();
       m_register_set_p = m_dynamic_reg_sets.data();
       m_register_set_count = m_dynamic_reg_sets.size();
     }
     break;
   }
   default:
void RegisterInfoPOSIX_arm64::AddRegSetTLS() {
   m_dynamic_reg_infos[tls_regnum].kinds[lldb::eRegisterKindLLDB] = tls_regnum;
 
   m_per_regset_regnum_range[m_register_set_count] =
       std::make_pair(tls_regnum, tls_regnum + 1);
   m_dynamic_reg_sets.push_back(g_reg_set_tls_arm64);
   m_dynamic_reg_sets.back().registers = m_tls_regnum_collection.data();
 }
 
+void RegisterInfoPOSIX_arm64::AddRegSetSME() {
+  uint32_t sme_regnum = m_dynamic_reg_infos.size();
+  m_sme_regnum_collection.push_back(sme_regnum);
+  m_dynamic_reg_infos.push_back(g_register_infos_sme[0]);
+  m_dynamic_reg_infos[sme_regnum].byte_offset =
+      m_dynamic_reg_infos[sme_regnum - 1].byte_offset +
+      m_dynamic_reg_infos[sme_regnum - 1].byte_size;
+  m_dynamic_reg_infos[sme_regnum].kinds[lldb::eRegisterKindLLDB] = sme_regnum;
+
+  m_per_regset_regnum_range[m_register_set_count] =
+      std::make_pair(sme_regnum, sme_regnum + 1);
+  m_dynamic_reg_sets.push_back(g_reg_set_sme_arm64);
+  m_dynamic_reg_sets.back().registers = m_sme_regnum_collection.data();
+}
+
 uint32_t RegisterInfoPOSIX_arm64::ConfigureVectorLength(uint32_t sve_vq) {
   // sve_vq contains SVE Quad vector length in context of AArch64 SVE.
   // SVE register infos if enabled cannot be disabled by selecting sve_vq = 0.
   // Also if an invalid or previously set vector length is passed to this
   // function then it will exit immediately with previously set vector length.
   if (!VectorSizeIsValid(sve_vq) || m_vector_reg_vq == sve_vq)
     return m_vector_reg_vq;
 

 bool RegisterInfoPOSIX_arm64::IsMTEReg(unsigned reg) const {
   return llvm::is_contained(m_mte_regnum_collection, reg);
 }
 
 bool RegisterInfoPOSIX_arm64::IsTLSReg(unsigned reg) const {
   return llvm::is_contained(m_tls_regnum_collection, reg);
 }
 
+bool RegisterInfoPOSIX_arm64::IsSMEReg(unsigned reg) const {
+  return llvm::is_contained(m_sme_regnum_collection, reg);
+}
+
 uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEZ0() const { return sve_z0; }
 
 uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEFFR() const { return sve_ffr; }
 
 uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPCR() const { return fpu_fpcr; }
 
 uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPSR() const { return fpu_fpsr; }
 
 uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEVG() const { return sve_vg; }
 
 uint32_t RegisterInfoPOSIX_arm64::GetPAuthOffset() const {
   return m_register_info_p[pauth_regnum_collection[0]].byte_offset;
 }
 
 uint32_t RegisterInfoPOSIX_arm64::GetMTEOffset() const {
   return m_register_info_p[m_mte_regnum_collection[0]].byte_offset;
 }
 
 uint32_t RegisterInfoPOSIX_arm64::GetTLSOffset() const {
   return m_register_info_p[m_tls_regnum_collection[0]].byte_offset;
 }
+
+uint32_t RegisterInfoPOSIX_arm64::GetSMEOffset() const {
+  return m_register_info_p[m_sme_regnum_collection[0]].byte_offset;
+}

lldb/test/API/commands/register/register/aarch64_sve_registers/rw_access_static_config/TestSVERegisters.py

def check_sve_register_size(self, set, name, expected):
         reg_value = set.GetChildMemberWithName(name)
         self.assertTrue(
             reg_value.IsValid(), 'Verify we have a register named "%s"' % (name)
         )
         self.assertEqual(
             reg_value.GetByteSize(), expected, 'Verify "%s" == %i' % (name, expected)
         )
 
-    def check_sve_regs_read(self, z_reg_size):
+    def check_sve_regs_read(self, z_reg_size, expected_mode):
+        if self.isAArch64SME():
+            expected_value = "1" if expected_mode == Mode.SSVE else "0"
+            self.expect("register read svcr", substrs=[
+                "0x000000000000000" + expected_value])
+
         p_reg_size = int(z_reg_size / 8)
 
         for i in range(32):
             z_regs_value = (
                 "{"
                 + " ".join("0x{:02x}".format(i + 1) for _ in range(z_reg_size))
                 + "}"
             )
def sve_registers_read_write_impl(self, start_mode, eval_mode):
         process = target.GetProcess()
 
         registerSets = process.GetThreadAtIndex(0).GetFrameAtIndex(0).GetRegisters()
         sve_registers = registerSets.GetFirstValueByName("Scalable Vector Extension Registers")
         self.assertTrue(sve_registers)
 
         vg_reg_value = sve_registers.GetChildMemberWithName("vg").GetValueAsUnsigned()
         z_reg_size = vg_reg_value * 8
-        self.check_sve_regs_read(z_reg_size)
+        self.check_sve_regs_read(z_reg_size, start_mode)
 
         # Evaluate simple expression and print function expr_eval_func address.
         self.expect("expression expr_eval_func", substrs=["= 0x"])
 
         # Evaluate expression call function expr_eval_func.
         self.expect_expr("expr_eval_func({})".format(
             "true" if (eval_mode == Mode.SSVE) else "false"), result_type="int",
             result_value="1")
 
         # We called a jitted function above which must not have changed SVE
         # vector length or register values.
-        self.check_sve_regs_read(z_reg_size)
+        self.check_sve_regs_read(z_reg_size, start_mode)
 
         self.check_sve_regs_read_after_write(z_reg_size)
 
     # The following tests all setup some register values then evaluate an
     # expression. After the expression, the mode and register values should be
     # the same as before. Finally they read/write some values in the registers.
     # The only difference is the mode we start the program in, and the mode
     # the expression function uses.
class RegisterCommandsTestCase(TestBase):
     def test_registers_expr_read_write_sve_ssve(self):
         self.sve_registers_read_write_impl(Mode.SVE, Mode.SSVE)
 
     @no_debug_info_test
     @skipIf(archs=no_match(["aarch64"]))
     @skipIf(oslist=no_match(["linux"]))
     def test_registers_expr_read_write_ssve_sve(self):
         self.sve_registers_read_write_impl(Mode.SSVE, Mode.SVE)
 No newline at end of file