[RISCV] Add back schedule to vmerge pseudos

[luke]

Summary

Looks like they might have been accidentally removed in d983e833dcbb

[michaelmaitland]

LGTM.

[reames]

Oops, thanks for catching!

LGTM as well.

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

foreach m = MxList in {
     defvar WriteVIMergeV_MX = !cast<SchedWrite>("WriteVIMergeV_" # mx);
     defvar WriteVIMergeX_MX = !cast<SchedWrite>("WriteVIMergeX_" # mx);
     defvar WriteVIMergeI_MX = !cast<SchedWrite>("WriteVIMergeI_" # mx);
     defvar ReadVIMergeV_MX = !cast<SchedRead>("ReadVIMergeV_" # mx);
     defvar ReadVIMergeX_MX = !cast<SchedRead>("ReadVIMergeX_" # mx);
 
     def "_VVM"  # "_" # m.MX :
       VPseudoBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
-                           m.vrclass, m.vrclass, m, 1, "">;
+                           m.vrclass, m.vrclass, m, 1, "">,
+      Sched<[WriteVIMergeV_MX, ReadVIMergeV_MX, ReadVIMergeV_MX, ReadVMask]>;
     def "_VXM" # "_" # m.MX :
       VPseudoBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
-                           m.vrclass, GPR, m, 1, "">;
+                           m.vrclass, GPR, m, 1, "">,
+      Sched<[WriteVIMergeX_MX, ReadVIMergeV_MX, ReadVIMergeX_MX, ReadVMask]>;
     def "_VIM" # "_" # m.MX :
       VPseudoBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
-                           m.vrclass, simm5, m, 1, "">;
+                           m.vrclass, simm5, m, 1, "">,
+      Sched<[WriteVIMergeI_MX, ReadVIMergeV_MX, ReadVMask]>;
     // Tied versions to allow codegen control over the tail elements
     def "_VVM" # "_" # m.MX # "_TU" :
       VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
-                               m.vrclass, m.vrclass, m, 1, "">;
+                               m.vrclass, m.vrclass, m, 1, "">,
+      Sched<[WriteVIMergeV_MX, ReadVIMergeV_MX, ReadVIMergeV_MX, ReadVMask]>;
     def "_VXM" # "_" # m.MX # "_TU":
       VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
-                               m.vrclass, GPR, m, 1, "">;
+                               m.vrclass, GPR, m, 1, "">,
+      Sched<[WriteVIMergeX_MX, ReadVIMergeV_MX, ReadVIMergeX_MX, ReadVMask]>;
     def "_VIM" # "_" # m.MX # "_TU":
       VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
-                               m.vrclass, simm5, m, 1, "">;
+                               m.vrclass, simm5, m, 1, "">,
+      Sched<[WriteVIMergeI_MX, ReadVIMergeV_MX, ReadVMask]>;
   }
 }
 
 multiclass VPseudoVCALU_VM_XM_IM {
   foreach m = MxList in {
     defvar mx = m.MX;
     defvar WriteVICALUV_MX = !cast<SchedWrite>("WriteVICALUV_" # mx);
     defvar WriteVICALUX_MX = !cast<SchedWrite>("WriteVICALUX_" # mx);