[RISCV] Check for alignment when selecting whole register loads/stores

[luke]

Summary

As per the specification, whole register vector loads and stores may raise a
misaligned address exception "if the base address is not naturally aligned to
the larger of the size of the encoded EEW in bytes (EEW/8) or the
implementation’s smallest supported SEW size in bytes (SEWMIN/8)."

This patch adds a predicate to ensure the alignment is greater than or equal to
the EEW in bytes. It doesn't check SEWMIN however since the smallest SEW can be
with the standard extensions is 8 bytes.

Note that this doesn't fix the issue raised here:
https://reviews.llvm.org/D154536#inline-1495073

[craig.topper]

So what we're saying is the -mattr=+unaligned-vector-mem that we made up does not apply to whole register load/store? but applies regular loads and store?

llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll

68

Couldn't we use vl1r.v?

239

Doesn't vs2r.v have an EEW of 8?

[luke]

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

69

I'm actually not sure if we need to do this for stores anymore. From the spec:

The load instructions have an EEW encoded in the mew and width elds following the pattern of regular unit-stride loads.
The vector whole register store instructions are encoded similar to unmasked unit-stride store of elements with EEW=8.

So the whole register stores don't have EEW encoded with them: So is their EEW always 8 or is it taken from SEW? If it's taken from SEW then I think we would need a pseudo to propagate this information to insertvsetvli. Otherwise we don't actually need to check the alignment here.

llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll

68

I think so. Will take a look

[luke]

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

69

A bit further down in section 7.9:

Implementations are allowed to raise a misaligned address exception on whole register loads and stores if the base address is not naturally aligned to ...

So does this imply that it is possible for the store's EEW to not be 8?

[luke]

These test cases are actually correct, I've misread the UNALIGNED checks

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

multiclass VPatUSLoadStoreSDNode<ValueType type,
   def : Pat<(type (load GPR:$rs1)),
             (load_instr (type (IMPLICIT_DEF)), GPR:$rs1, avl,
                         log2sew, TU_MU)>;
   // Store
   def : Pat<(store type:$rs2, GPR:$rs1),
             (store_instr reg_class:$rs2, GPR:$rs1, avl, log2sew)>;
 }
 
+defvar IsEEWAligned = [{
+  auto *MN = cast<MemSDNode>(N);
+  unsigned EEWSize =
+      MN->getMemoryVT().getVectorElementType().getSizeInBits() / 8;
+  return MN->getAlign() >= Align(EEWSize);
+}];
+
+def whole_reg_load : PatFrag<(ops node:$ptr), (load node:$ptr), IsEEWAligned>;
+def whole_reg_store : PatFrag<(ops node:$val, node:$ptr),
+                              (store node:$val, node:$ptr), IsEEWAligned>;
+
 multiclass VPatUSLoadStoreWholeVRSDNode<ValueType type,
                                         int log2sew,
                                         LMULInfo vlmul,
                                         VReg reg_class,
                                         int sew = !shl(1, log2sew)> {
   defvar load_instr =
     !cast<Instruction>("VL"#!substr(vlmul.MX, 1)#"RE"#sew#"_V");
   defvar store_instr =
     !cast<Instruction>("VS"#!substr(vlmul.MX, 1)#"R_V");
 
   // Load
-  def : Pat<(type (load GPR:$rs1)),
+  def : Pat<(type (whole_reg_load GPR:$rs1)),
             (load_instr GPR:$rs1)>;
   // Store
-  def : Pat<(store type:$rs2, GPR:$rs1),
+  def : Pat<(whole_reg_store type:$rs2, GPR:$rs1),
             (store_instr reg_class:$rs2, GPR:$rs1)>;
 }
 
 multiclass VPatUSLoadStoreMaskSDNode<MTypeInfo m> {
   defvar load_instr = !cast<Instruction>("PseudoVLM_V_"#m.BX);
   defvar store_instr = !cast<Instruction>("PseudoVSM_V_"#m.BX);
   // Load
   def : Pat<(m.Mask (load GPR:$rs1)),

 
 // 7.4. Vector Unit-Stride Instructions
 foreach vti = !listconcat(FractionalGroupIntegerVectors,
                           FractionalGroupFloatVectors) in
   let Predicates = GetVTypePredicates<vti>.Predicates in
   defm : VPatUSLoadStoreSDNode<vti.Vector, vti.Log2SEW, vti.LMul,
                                vti.AVL, vti.RegClass>;
 foreach vti = [VI8M1, VI16M1, VI32M1, VI64M1, VF16M1, VF32M1, VF64M1] in
-  let Predicates = GetVTypePredicates<vti>.Predicates in
+  let Predicates = GetVTypePredicates<vti>.Predicates in {
     defm : VPatUSLoadStoreWholeVRSDNode<vti.Vector, vti.Log2SEW, vti.LMul,
                                         vti.RegClass>;
+    defm : VPatUSLoadStoreSDNode<vti.Vector, vti.Log2SEW, vti.LMul, vti.AVL,
+                                 vti.RegClass>;
+  }
 foreach vti = !listconcat(GroupIntegerVectors, GroupFloatVectors) in
-  let Predicates = GetVTypePredicates<vti>.Predicates in 
+  let Predicates = GetVTypePredicates<vti>.Predicates in {
     defm : VPatUSLoadStoreWholeVRSDNode<vti.Vector, vti.Log2SEW, vti.LMul,
                                         vti.RegClass>;
+    defm : VPatUSLoadStoreSDNode<vti.Vector, vti.Log2SEW, vti.LMul, vti.AVL,
+                                 vti.RegClass>;
+  }
 foreach mti = AllMasks in
   let Predicates = [HasVInstructions] in
   defm : VPatUSLoadStoreMaskSDNode<mti>;
 
 // 11. Vector Integer Arithmetic Instructions
 
 // 11.1. Vector Single-Width Integer Add and Subtract
 defm : VPatBinarySDNode_VV_VX_VI<add, "PseudoVADD">;

llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll

 define <vscale x 1 x i64> @unaligned_load_nxv1i64_a1(<vscale x 1 x i64>* %ptr) {
 ; CHECK-LABEL: unaligned_load_nxv1i64_a1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vl1r.v v8, (a0)
 ; CHECK-NEXT:    ret
 ;
 ; UNALIGNED-LABEL: unaligned_load_nxv1i64_a1:
 ; UNALIGNED:       # %bb.0:
-; UNALIGNED-NEXT:    vl1re64.v v8, (a0)
+; UNALIGNED-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
+; UNALIGNED-NEXT:    vle64.v v8, (a0)
 ; UNALIGNED-NEXT:    ret
   %v = load <vscale x 1 x i64>, <vscale x 1 x i64>* %ptr, align 1
   ret <vscale x 1 x i64> %v
 }
 
 define <vscale x 1 x i64> @unaligned_load_nxv1i64_a4(<vscale x 1 x i64>* %ptr) {
 ; CHECK-LABEL: unaligned_load_nxv1i64_a4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vl1r.v v8, (a0)
 ; CHECK-NEXT:    ret
 ;
 ; UNALIGNED-LABEL: unaligned_load_nxv1i64_a4:
 ; UNALIGNED:       # %bb.0:
-; UNALIGNED-NEXT:    vl1re64.v v8, (a0)
+; UNALIGNED-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
+; UNALIGNED-NEXT:    vle64.v v8, (a0)
 ; UNALIGNED-NEXT:    ret
   %v = load <vscale x 1 x i64>, <vscale x 1 x i64>* %ptr, align 4
   ret <vscale x 1 x i64> %v
 }
 
 define <vscale x 1 x i64> @aligned_load_nxv1i64_a8(<vscale x 1 x i64>* %ptr) {
 ; CHECK-LABEL: aligned_load_nxv1i64_a8:
 ; CHECK:       # %bb.0:

 define <vscale x 2 x i64> @unaligned_load_nxv2i64_a1(<vscale x 2 x i64>* %ptr) {
 ; CHECK-LABEL: unaligned_load_nxv2i64_a1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vl2r.v v8, (a0)
 ; CHECK-NEXT:    ret
 ;
 ; UNALIGNED-LABEL: unaligned_load_nxv2i64_a1:
 ; UNALIGNED:       # %bb.0:
-; UNALIGNED-NEXT:    vl2re64.v v8, (a0)
+; UNALIGNED-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
+; UNALIGNED-NEXT:    vle64.v v8, (a0)
 ; UNALIGNED-NEXT:    ret
   %v = load <vscale x 2 x i64>, <vscale x 2 x i64>* %ptr, align 1
   ret <vscale x 2 x i64> %v
 }
 
 define <vscale x 2 x i64> @unaligned_load_nxv2i64_a4(<vscale x 2 x i64>* %ptr) {
 ; CHECK-LABEL: unaligned_load_nxv2i64_a4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vl2r.v v8, (a0)
 ; CHECK-NEXT:    ret
 ;
 ; UNALIGNED-LABEL: unaligned_load_nxv2i64_a4:
 ; UNALIGNED:       # %bb.0:
-; UNALIGNED-NEXT:    vl2re64.v v8, (a0)
+; UNALIGNED-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
+; UNALIGNED-NEXT:    vle64.v v8, (a0)
 ; UNALIGNED-NEXT:    ret
   %v = load <vscale x 2 x i64>, <vscale x 2 x i64>* %ptr, align 4
   ret <vscale x 2 x i64> %v
 }
 
 define <vscale x 2 x i64> @aligned_load_nxv2i64_a8(<vscale x 2 x i64>* %ptr) {
 ; CHECK-LABEL: aligned_load_nxv2i64_a8:
 ; CHECK:       # %bb.0:

 define <vscale x 4 x float> @unaligned_load_nxv4f32_a1(<vscale x 4 x float>* %ptr) {
 ; CHECK-LABEL: unaligned_load_nxv4f32_a1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vl2r.v v8, (a0)
 ; CHECK-NEXT:    ret
 ;
 ; UNALIGNED-LABEL: unaligned_load_nxv4f32_a1:
 ; UNALIGNED:       # %bb.0:
-; UNALIGNED-NEXT:    vl2re32.v v8, (a0)
+; UNALIGNED-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
+; UNALIGNED-NEXT:    vle32.v v8, (a0)
 ; UNALIGNED-NEXT:    ret
   %v = load <vscale x 4 x float>, <vscale x 4 x float>* %ptr, align 1
   ret <vscale x 4 x float> %v
 }
 
 define <vscale x 4 x float> @unaligned_load_nxv4f32_a2(<vscale x 4 x float>* %ptr) {
 ; CHECK-LABEL: unaligned_load_nxv4f32_a2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vl2r.v v8, (a0)
 ; CHECK-NEXT:    ret
 ;
 ; UNALIGNED-LABEL: unaligned_load_nxv4f32_a2:
 ; UNALIGNED:       # %bb.0:
-; UNALIGNED-NEXT:    vl2re32.v v8, (a0)
+; UNALIGNED-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
+; UNALIGNED-NEXT:    vle32.v v8, (a0)
 ; UNALIGNED-NEXT:    ret
   %v = load <vscale x 4 x float>, <vscale x 4 x float>* %ptr, align 2
   ret <vscale x 4 x float> %v
 }
 
 define <vscale x 4 x float> @aligned_load_nxv4f32_a4(<vscale x 4 x float>* %ptr) {
 ; CHECK-LABEL: aligned_load_nxv4f32_a4:
 ; CHECK:       # %bb.0:

 define <vscale x 8 x half> @unaligned_load_nxv8f16_a1(<vscale x 8 x half>* %ptr) {
 ; CHECK-LABEL: unaligned_load_nxv8f16_a1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vl2r.v v8, (a0)
 ; CHECK-NEXT:    ret
 ;
 ; UNALIGNED-LABEL: unaligned_load_nxv8f16_a1:
 ; UNALIGNED:       # %bb.0:
-; UNALIGNED-NEXT:    vl2re16.v v8, (a0)
+; UNALIGNED-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
+; UNALIGNED-NEXT:    vle16.v v8, (a0)
 ; UNALIGNED-NEXT:    ret
   %v = load <vscale x 8 x half>, <vscale x 8 x half>* %ptr, align 1
   ret <vscale x 8 x half> %v
 }
 
 define <vscale x 8 x half> @aligned_load_nxv8f16_a2(<vscale x 8 x half>* %ptr) {
 ; CHECK-LABEL: aligned_load_nxv8f16_a2:
 ; CHECK:       # %bb.0:

 define void @unaligned_store_nxv4i32_a1(<vscale x 4 x i32> %x, <vscale x 4 x i32>* %ptr) {
 ; CHECK-LABEL: unaligned_store_nxv4i32_a1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vs2r.v v8, (a0)
 ; CHECK-NEXT:    ret
 ;
 ; UNALIGNED-LABEL: unaligned_store_nxv4i32_a1:
 ; UNALIGNED:       # %bb.0:
-; UNALIGNED-NEXT:    vs2r.v v8, (a0)
+; UNALIGNED-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
+; UNALIGNED-NEXT:    vse32.v v8, (a0)
 ; UNALIGNED-NEXT:    ret
   store <vscale x 4 x i32> %x, <vscale x 4 x i32>* %ptr, align 1
   ret void
 }
 
 define void @unaligned_store_nxv4i32_a2(<vscale x 4 x i32> %x, <vscale x 4 x i32>* %ptr) {
 ; CHECK-LABEL: unaligned_store_nxv4i32_a2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vs2r.v v8, (a0)
 ; CHECK-NEXT:    ret
 ;
 ; UNALIGNED-LABEL: unaligned_store_nxv4i32_a2:
 ; UNALIGNED:       # %bb.0:
-; UNALIGNED-NEXT:    vs2r.v v8, (a0)
+; UNALIGNED-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
+; UNALIGNED-NEXT:    vse32.v v8, (a0)
 ; UNALIGNED-NEXT:    ret
   store <vscale x 4 x i32> %x, <vscale x 4 x i32>* %ptr, align 2
   ret void
 }
 
 define void @aligned_store_nxv4i32_a4(<vscale x 4 x i32> %x, <vscale x 4 x i32>* %ptr) {
 ; CHECK-LABEL: aligned_store_nxv4i32_a4:
 ; CHECK:       # %bb.0: