[PowerPC] Add DFP test instruction definitions and MC tests

[kamaub]

Summary

Adding the td definitions, and their associated assembly and disassembly
test cases for the decimal floating point test instructions defined in
section 5.6.3 of ISA 3.1

[kamaub]

Removing the "mayRaiseFPException" predicate as it does not apply to these instructions.

[amyk]

I think since we discussed offline that the Z22 forms extended opcode should start at 22, this LGTM.

llvm/lib/Target/PowerPC/PPCInstrFormats.td

1225

nit: Indentation

2191

nit: Indentation

[lei]

llvm/lib/Target/PowerPC/PPCInstrDFP.td

132

nit: indent the following 2 lines 1 more space

144

nit: the 2nd line for this and the next 3 instr require 1 more space in indent

160

nit: indent

[lei]

LGTM other then some nits.
Thx.

llvm/lib/Target/PowerPC/PPCInstrDFP.td

 } // mayRaiseFPException
 
 // 5.6.6 DFP none exception raising format instructions.
 defm DDEDPD: XForm_SP2_FRTB5r<59, 322, (outs f8rc:$FRT),
                               (ins u2imm:$SP, f8rc:$FRB),
                               "ddedpd", "$SP, $FRT, $FRB", []>;
 defm DDEDPDQ: XForm_SP2_FRTB5r<63, 322, (outs fpairrc:$FRT),
                                (ins u2imm:$SP, fpairrc:$FRB),
                                "ddedpdq", "$SP, $FRT, $FRB", []>;
 defm DXEX: XForm_26r<59, 354, (outs f8rc:$RST), (ins f8rc:$RB),
                      "dxex", "$RST, $RB", NoItinerary, []>;
 defm DXEXQ: XForm_26r<63, 354, (outs f8rc:$RST), (ins fpairrc:$RB),
                       "dxexq", "$RST, $RB", NoItinerary, []>;
 defm DIEX: XForm_base_r3xo_r<59, 866, (outs f8rc:$RST),
                              (ins f8rc:$RA, f8rc:$RB),
                              "diex", "$RST, $RA, $RB", []>;
 defm DIEXQ: XForm_base_r3xo_r<63, 866, (outs fpairrc:$RST),
                               (ins f8rc:$RA, fpairrc:$RB),
                               "diexq", "$RST, $RA, $RB", []>;
 defm DSCLI: Z22Form_FRTA5_SH6r<59, 66, (outs f8rc:$FRT),
                                (ins f8rc:$FRA, u6imm:$SH),
                                "dscli", "$FRT, $FRA, $SH", []>;
 defm DSCLIQ: Z22Form_FRTA5_SH6r<63, 66, (outs fpairrc:$FRT),
                                 (ins fpairrc:$FRA, u6imm:$SH),
                                 "dscliq", "$FRT, $FRA, $SH", []>;
 defm DSCRI: Z22Form_FRTA5_SH6r<59, 98, (outs f8rc:$FRT),
                                (ins f8rc:$FRA, u6imm:$SH),
                                "dscri", "$FRT, $FRA, $SH", []>;
 defm DSCRIQ: Z22Form_FRTA5_SH6r<63, 98, (outs fpairrc:$FRT),
                                 (ins fpairrc:$FRA, u6imm:$SH),
                                 "dscriq", "$FRT, $FRA, $SH", []>;
+
+// 5.6.3 DFP Test Instructions
+def DTSTDC : Z22Form_BF3_FRA5_DCM6<59, 194, (outs crrc:$BF),
+                                   (ins f8rc:$FRA, u6imm:$DCM),
+                                   "dtstdc $BF, $FRA, $DCM", IIC_FPCompare, []>;
+
+def DTSTDCQ : Z22Form_BF3_FRA5_DCM6<63, 194, (outs crrc:$BF),
+                                    (ins fpairrc:$FRA, u6imm:$DCM),
+                                    "dtstdcq $BF, $FRA, $DCM", IIC_FPCompare, []>;
+
+def DTSTDG : Z22Form_BF3_FRA5_DCM6<59, 226, (outs crrc:$BF),
+                                   (ins f8rc:$FRA, u6imm:$DCM),
+                                   "dtstdg $BF, $FRA, $DCM", IIC_FPCompare, []>;
+
+def DTSTDGQ : Z22Form_BF3_FRA5_DCM6<63, 226, (outs crrc:$BF),
+                                    (ins fpairrc:$FRA, u6imm:$DCM),
+                                    "dtstdgq $BF, $FRA, $DCM", IIC_FPCompare, []>;
+
+def DTSTEX : XForm_17<59, 162, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB),
+                      "dtstex $BF, $RA, $RB", IIC_FPCompare>;
+
+def DTSTEXQ : XForm_17<63, 162, (outs crrc:$BF), (ins fpairrc:$RA, fpairrc:$RB),
+                       "dtstexq $BF, $RA, $RB", IIC_FPCompare>;
+
+def DTSTSF : XForm_17<59, 674, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB),
+                      "dtstsf $BF, $RA, $RB", IIC_FPCompare>;
+
+def DTSTSFQ : XForm_17<63, 674, (outs crrc:$BF), (ins f8rc:$RA, fpairrc:$RB),
+                       "dtstsfq $BF, $RA, $RB", IIC_FPCompare>;
+
+def DTSTSFI : XForm_BF3_UIM6_FRB5<59, 675, (outs crrc:$BF),
+                                  (ins u6imm:$UIM, f8rc:$FRB),
+                                  "dtstsfi $BF, $UIM, $FRB", IIC_FPCompare, []>;
+
+def DTSTSFIQ : XForm_BF3_UIM6_FRB5<63, 675, (outs crrc:$BF),
+                                   (ins u6imm:$UIM, fpairrc:$FRB),
+                                   "dtstsfiq $BF, $UIM, $FRB", IIC_FPCompare, []>;
+
 } // hasNoSchedulingInfo

llvm/lib/Target/PowerPC/PPCInstrFormats.td

class XForm_XD6_RA5_RB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
 
   let Inst{6-10}  = D{4-0};  // D
   let Inst{11-15} = RA;
   let Inst{16-20} = RB;
   let Inst{21-30} = xo;
   let Inst{31}    = D{5};    // DX
 }
 
+class XForm_BF3_UIM6_FRB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
+                          string asmstr, InstrItinClass itin, list<dag> pattern>
+  : I<opcode, OOL, IOL, asmstr, itin> {
+  bits<3> BF;
+  bits<6> UIM;
+  bits<5> FRB;
+
+  let Pattern = pattern;
+
+  let Inst{6-8}   = BF;
+  let Inst{9}     = 0;
+  let Inst{10-15} = UIM;
+  let Inst{16-20} = FRB;
+  let Inst{21-30} = xo;
+  let Inst{31}    = 0;
+}
+
 class XForm_SP2_FRTB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
                   list<dag> pattern, InstrItinClass itin>
     : I<opcode, OOL, IOL, asmstr, itin> {
   bits<2> SP;
   bits<5> FRT;
   bits<5> FRB;
 
   let Pattern = pattern;
class VX_RD5_RSp5_PS1_XO9<bits<9> xo, dag OOL, dag IOL, string asmstr,
   let Inst{6-10}  = VD;
   let Inst{11-15} = VA;
   let Inst{16-20} = VB;
   let Inst{21}    = 1;
   let Inst{22}    = PS;
   let Inst{23-31} = xo;
 }
 
+class Z22Form_BF3_FRA5_DCM6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
+                            string asmstr, InstrItinClass itin,
+                            list<dag> pattern>
+  : I<opcode, OOL, IOL, asmstr, itin> {
+  bits<3> BF;
+  bits<5> FRA;
+  bits<6> DCM;
+
+  let Pattern = pattern;
+
+  let Inst{6-8}   = BF;
+  let Inst{9-10}  = 0;
+  let Inst{11-15} = FRA;
+  let Inst{16-21} = DCM;
+  let Inst{22-30} = xo;
+  let Inst{31}    = 0;
+}
+
 class Z22Form_FRTA5_SH6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
               string asmstr, list<dag> pattern, InstrItinClass itin>
     : I<opcode, OOL, IOL, asmstr, itin> {
 
   bits<5> FRT;
   bits<5> FRA;
   bits<6> SH;
 

llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt

 # CHECK: dscri. 16, 10, 50
 0xee 0x0a 0xc8 0xc5
 
 # CHECK: dscriq 16, 10, 50
 0xfe 0x0a 0xc8 0xc4
 
 # CHECK: dscriq. 16, 10, 50
 0xfe 0x0a 0xc8 0xc5
+
+# CHECK: dtstdc 2, 6, 4
+0xed,0x06,0x11,0x84
+
+# CHECK: dtstdcq 2, 6, 4
+0xfd,0x06,0x11,0x84
+
+# CHECK: dtstdg 2, 6, 4
+0xed,0x06,0x11,0xc4
+
+# CHECK: dtstdgq 2, 6, 4
+0xfd,0x06,0x11,0xc4
+
+# CHECK: dtstex 2, 6, 4
+0xed,0x06,0x21,0x44
+
+# CHECK: dtstexq 2, 6, 4
+0xfd,0x06,0x21,0x44
+
+# CHECK: dtstsf 2, 6, 4
+0xed,0x06,0x25,0x44
+
+# CHECK: dtstsfq 2, 6, 4
+0xfd,0x06,0x25,0x44
+
+# CHECK: dtstsfi 2, 6, 4
+0xed,0x06,0x25,0x46
+
+# CHECK: dtstsfiq 2, 6, 4
+0xfd,0x06,0x25,0x46

llvm/test/MC/PowerPC/ppc64-encoding-dfp.s

 # CHECK-LE: dscri. 16, 10, 50              # encoding: [0xc5,0xc8,0x0a,0xee]
             dscri. 16, 10, 50
 # CHECK-BE: dscriq 16, 10, 50              # encoding: [0xfe,0x0a,0xc8,0xc4]
 # CHECK-LE: dscriq 16, 10, 50              # encoding: [0xc4,0xc8,0x0a,0xfe]
             dscriq 16, 10, 50
 # CHECK-BE: dscriq. 16, 10, 50             # encoding: [0xfe,0x0a,0xc8,0xc5]
 # CHECK-LE: dscriq. 16, 10, 50             # encoding: [0xc5,0xc8,0x0a,0xfe]
             dscriq. 16, 10, 50
+# CHECK-BE: dtstdc 2, 6, 4                 # encoding: [0xed,0x06,0x11,0x84]
+# CHECK-LE: dtstdc 2, 6, 4                 # encoding: [0x84,0x11,0x06,0xed]
+            dtstdc 2, 6, 4
+# CHECK-BE: dtstdcq 2, 6, 4                # encoding: [0xfd,0x06,0x11,0x84]
+# CHECK-LE: dtstdcq 2, 6, 4                # encoding: [0x84,0x11,0x06,0xfd]
+            dtstdcq 2, 6, 4
+# CHECK-BE: dtstdg 2, 6, 4                 # encoding: [0xed,0x06,0x11,0xc4]
+# CHECK-LE: dtstdg 2, 6, 4                 # encoding: [0xc4,0x11,0x06,0xed]
+            dtstdg 2, 6, 4
+# CHECK-BE: dtstdgq 2, 6, 4                # encoding: [0xfd,0x06,0x11,0xc4]
+# CHECK-LE: dtstdgq 2, 6, 4                # encoding: [0xc4,0x11,0x06,0xfd]
+            dtstdgq 2, 6, 4
+# CHECK-BE: dtstex 2, 6, 4                 # encoding: [0xed,0x06,0x21,0x44]
+# CHECK-LE: dtstex 2, 6, 4                 # encoding: [0x44,0x21,0x06,0xed]
+            dtstex 2, 6, 4
+# CHECK-BE: dtstexq 2, 6, 4                # encoding: [0xfd,0x06,0x21,0x44]
+# CHECK-LE: dtstexq 2, 6, 4                # encoding: [0x44,0x21,0x06,0xfd]
+            dtstexq 2, 6, 4
+# CHECK-BE: dtstsf 2, 6, 4                 # encoding: [0xed,0x06,0x25,0x44]
+# CHECK-LE: dtstsf 2, 6, 4                 # encoding: [0x44,0x25,0x06,0xed]
+            dtstsf 2, 6, 4
+# CHECK-BE: dtstsfq 2, 6, 4                # encoding: [0xfd,0x06,0x25,0x44]
+# CHECK-LE: dtstsfq 2, 6, 4                # encoding: [0x44,0x25,0x06,0xfd]
+            dtstsfq 2, 6, 4
+# CHECK-BE: dtstsfi 2, 6, 4                # encoding: [0xed,0x06,0x25,0x46]
+# CHECK-LE: dtstsfi 2, 6, 4                # encoding: [0x46,0x25,0x06,0xed]
+            dtstsfi 2, 6, 4
+# CHECK-BE: dtstsfiq 2, 6, 4               # encoding: [0xfd,0x06,0x25,0x46]
+# CHECK-LE: dtstsfiq 2, 6, 4               # encoding: [0x46,0x25,0x06,0xfd]
+            dtstsfiq 2, 6, 4