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Differential D154577

[RISCV] Use 'long' in sha512 builtin tests. NFC
ClosedPublic

Authored by craig.topper on Jul 6 2023, 1:10 AM.

Details

Reviewers
kito-cheng
asb
VincentWu
Commits
rGa8a6a4947439: [RISCV] Use 'long' in sha512 builtin tests. NFC
Summary

This matches the data type of the intrinsics. This case be seen
from the removal of sext and trunc instructions from the IR.

Diff Detail

Event Timeline

craig.topper created this revision.Jul 6 2023, 1:10 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 6 2023, 1:10 AM
Herald added subscribers: jobnoorman, luke, vkmr and 24 others. · View Herald Transcript
craig.topper requested review of this revision.Jul 6 2023, 1:10 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 6 2023, 1:10 AM
Herald added subscribers: wangpc, eopXD, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B243398: Diff 537618.Jul 6 2023, 1:56 AM
asb accepted this revision.Jul 6 2023, 5:08 AM

LGTM.

This revision is now accepted and ready to land.Jul 6 2023, 5:08 AM
This revision was landed with ongoing or failed builds.Jul 6 2023, 7:37 AM
Closed by commit rGa8a6a4947439: [RISCV] Use 'long' in sha512 builtin tests. NFC (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rGa8a6a4947439: [RISCV] Use 'long' in sha512 builtin tests. NFC.

Revision Contents

PathSize
clang/
test/
CodeGen/
RISCV/
rvk-intrinsics/
56 lines

Diff 537723

clang/test/CodeGen/RISCV/rvk-intrinsics/riscv64-zknh.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple riscv64 -target-feature +zknh -emit-llvm %s -o - \ // RUN: %clang_cc1 -triple riscv64 -target-feature +zknh -emit-llvm %s -o - \
// RUN: | FileCheck %s -check-prefix=RV64ZKNH // RUN: | FileCheck %s -check-prefix=RV64ZKNH
// RV64ZKNH-LABEL: @sha512sig0( // RV64ZKNH-LABEL: @sha512sig0(
// RV64ZKNH-NEXT: entry: // RV64ZKNH-NEXT: entry:
// RV64ZKNH-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4 // RV64ZKNH-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
// RV64ZKNH-NEXT: store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4 // RV64ZKNH-NEXT: store i64 [[RS1:%.*]], ptr [[RS1_ADDR]], align 8
// RV64ZKNH-NEXT: [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4 // RV64ZKNH-NEXT: [[TMP0:%.*]] = load i64, ptr [[RS1_ADDR]], align 8
// RV64ZKNH-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i64 // RV64ZKNH-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.sha512sig0(i64 [[TMP0]])
// RV64ZKNH-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.sha512sig0(i64 [[CONV]]) // RV64ZKNH-NEXT: ret i64 [[TMP1]]
// RV64ZKNH-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// RV64ZKNH-NEXT: ret i32 [[CONV1]]
// //
int sha512sig0(int rs1) { long sha512sig0(long rs1) {
return __builtin_riscv_sha512sig0_64(rs1); return __builtin_riscv_sha512sig0_64(rs1);
} }
// RV64ZKNH-LABEL: @sha512sig1( // RV64ZKNH-LABEL: @sha512sig1(
// RV64ZKNH-NEXT: entry: // RV64ZKNH-NEXT: entry:
// RV64ZKNH-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4 // RV64ZKNH-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
// RV64ZKNH-NEXT: store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4 // RV64ZKNH-NEXT: store i64 [[RS1:%.*]], ptr [[RS1_ADDR]], align 8
// RV64ZKNH-NEXT: [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4 // RV64ZKNH-NEXT: [[TMP0:%.*]] = load i64, ptr [[RS1_ADDR]], align 8
// RV64ZKNH-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i64 // RV64ZKNH-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.sha512sig1(i64 [[TMP0]])
// RV64ZKNH-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.sha512sig1(i64 [[CONV]]) // RV64ZKNH-NEXT: ret i64 [[TMP1]]
// RV64ZKNH-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// RV64ZKNH-NEXT: ret i32 [[CONV1]]
// //
int sha512sig1(int rs1) { long sha512sig1(long rs1) {
return __builtin_riscv_sha512sig1_64(rs1); return __builtin_riscv_sha512sig1_64(rs1);
} }
// RV64ZKNH-LABEL: @sha512sum0( // RV64ZKNH-LABEL: @sha512sum0(
// RV64ZKNH-NEXT: entry: // RV64ZKNH-NEXT: entry:
// RV64ZKNH-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4 // RV64ZKNH-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
// RV64ZKNH-NEXT: store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4 // RV64ZKNH-NEXT: store i64 [[RS1:%.*]], ptr [[RS1_ADDR]], align 8
// RV64ZKNH-NEXT: [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4 // RV64ZKNH-NEXT: [[TMP0:%.*]] = load i64, ptr [[RS1_ADDR]], align 8
// RV64ZKNH-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i64 // RV64ZKNH-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.sha512sum0(i64 [[TMP0]])
// RV64ZKNH-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.sha512sum0(i64 [[CONV]]) // RV64ZKNH-NEXT: ret i64 [[TMP1]]
// RV64ZKNH-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// RV64ZKNH-NEXT: ret i32 [[CONV1]]
// //
int sha512sum0(int rs1) { long sha512sum0(long rs1) {
return __builtin_riscv_sha512sum0_64(rs1); return __builtin_riscv_sha512sum0_64(rs1);
} }
// RV64ZKNH-LABEL: @sha512sum1( // RV64ZKNH-LABEL: @sha512sum1(
// RV64ZKNH-NEXT: entry: // RV64ZKNH-NEXT: entry:
// RV64ZKNH-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4 // RV64ZKNH-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
// RV64ZKNH-NEXT: store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4 // RV64ZKNH-NEXT: store i64 [[RS1:%.*]], ptr [[RS1_ADDR]], align 8
// RV64ZKNH-NEXT: [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4 // RV64ZKNH-NEXT: [[TMP0:%.*]] = load i64, ptr [[RS1_ADDR]], align 8
// RV64ZKNH-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i64 // RV64ZKNH-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.sha512sum1(i64 [[TMP0]])
// RV64ZKNH-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.sha512sum1(i64 [[CONV]]) // RV64ZKNH-NEXT: ret i64 [[TMP1]]
// RV64ZKNH-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
// RV64ZKNH-NEXT: ret i32 [[CONV1]]
// //
int sha512sum1(int rs1) { long sha512sum1(long rs1) {
return __builtin_riscv_sha512sum1_64(rs1); return __builtin_riscv_sha512sum1_64(rs1);
} }
// RV64ZKNH-LABEL: @sha256sig0( // RV64ZKNH-LABEL: @sha256sig0(
// RV64ZKNH-NEXT: entry: // RV64ZKNH-NEXT: entry:
// RV64ZKNH-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8 // RV64ZKNH-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
// RV64ZKNH-NEXT: store i64 [[RS1:%.*]], ptr [[RS1_ADDR]], align 8 // RV64ZKNH-NEXT: store i64 [[RS1:%.*]], ptr [[RS1_ADDR]], align 8
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