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Differential D154493

[X86] Support some Intel CPUs for cpu_specific/dispatch feature
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Authored by FreddyYe on Jul 5 2023, 4:35 AM.

Details

Reviewers
RKSimon
pengfei
skan
craig.topper
Commits
rGa10dccf2712f: [X86] Support some Intel CPUs for cpu_specific/dispatch feature

Diff Detail

Unit TestsFailed

TimeTest
60,060 msx64 debian > ThreadSanitizer-x86_64.ThreadSanitizer-x86_64::restore_stack.cpp

Event Timeline

FreddyYe created this revision.Jul 5 2023, 4:35 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 5 2023, 4:35 AM
Herald added a subscriber: hiraditya. · View Herald Transcript
FreddyYe requested review of this revision.Jul 5 2023, 4:35 AM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptJul 5 2023, 4:35 AM
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FreddyYe added reviewers: RKSimon, pengfei, skan, craig.topper.Jul 5 2023, 4:37 AM
RKSimon added inline comments.Jul 5 2023, 5:12 AM
llvm/lib/TargetParser/X86TargetParser.cpp
333

add this as well?

Harbormaster completed remote builds in B243176: Diff 537293.Jul 5 2023, 5:21 AM
FreddyYe marked an inline comment as done.Jul 5 2023, 5:46 PM
FreddyYe added inline comments.
llvm/lib/TargetParser/X86TargetParser.cpp
333

cpu names contain '-' are not supported for cpu_specific/dispatch feature since '-' is not an identifier character. The solution here is creating a new name with '_' replacing and set the OnlyForCPUDispatchSpecific as true, like icelake-client, icelake-server and goldmont-plus

RKSimon accepted this revision.Jul 6 2023, 7:42 AM

LGTM

llvm/lib/TargetParser/X86TargetParser.cpp
333

Understood - cheers.

This revision is now accepted and ready to land.Jul 6 2023, 7:42 AM
skan accepted this revision.Jul 6 2023, 5:27 PM

LGTM

FreddyYe updated this revision to Diff 537957.Jul 6 2023, 8:01 PM
FreddyYe marked an inline comment as done.

Tuned some manglings. SPR should create a new mangling for its feature list.

FreddyYe added inline comments.Jul 6 2023, 8:06 PM
llvm/lib/TargetParser/X86TargetParser.cpp
419

SPR has AVX512BF16 comparing to icelake-server, which is a X86_FEATURE_COMPAT feature.

Harbormaster completed remote builds in B243641: Diff 537957.Jul 6 2023, 9:26 PM
FreddyYe updated this revision to Diff 537980.Jul 6 2023, 9:44 PM

Tune test as well.

This revision was landed with ongoing or failed builds.Jul 6 2023, 10:47 PM
Closed by commit rGa10dccf2712f: [X86] Support some Intel CPUs for cpu_specific/dispatch feature (authored by FreddyYe). · Explain Why
This revision was automatically updated to reflect the committed changes.
FreddyYe added a commit: rGa10dccf2712f: [X86] Support some Intel CPUs for cpu_specific/dispatch feature.
Harbormaster completed remote builds in B243656: Diff 537980.Jul 6 2023, 10:58 PM

Revision Contents

PathSize
clang/
test/
CodeGen/
34 lines
llvm/
lib/
TargetParser/
66 lines

Diff 537957

clang/test/CodeGen/attr-cpuspecific-cpus.c

Show All 31 Lines
ATTR(cpu_specific(core_4th_gen_avx_tsx)) void CPU(void){} ATTR(cpu_specific(core_4th_gen_avx_tsx)) void CPU(void){}
ATTR(cpu_specific(broadwell)) void CPU(void){} ATTR(cpu_specific(broadwell)) void CPU(void){}
ATTR(cpu_specific(core_5th_gen_avx_tsx)) void CPU(void){} ATTR(cpu_specific(core_5th_gen_avx_tsx)) void CPU(void){}
ATTR(cpu_specific(knl)) void CPU(void){} ATTR(cpu_specific(knl)) void CPU(void){}
ATTR(cpu_specific(skylake)) void CPU(void){} ATTR(cpu_specific(skylake)) void CPU(void){}
ATTR(cpu_specific(skylake_avx512)) void CPU(void){} ATTR(cpu_specific(skylake_avx512)) void CPU(void){}
ATTR(cpu_specific(cannonlake)) void CPU(void){} ATTR(cpu_specific(cannonlake)) void CPU(void){}
ATTR(cpu_specific(knm)) void CPU(void){} ATTR(cpu_specific(knm)) void CPU(void){}
ATTR(cpu_specific(cascadelake)) void CPU(void){}
ATTR(cpu_specific(cooperlake)) void CPU(void){}
ATTR(cpu_specific(icelake_client)) void CPU(void){}
ATTR(cpu_specific(tigerlake)) void CPU(void){}
ATTR(cpu_specific(alderlake)) void CPU(void){}
// ALIAS CPUs // ALIAS CPUs
ATTR(cpu_specific(pentium_iii_no_xmm_regs)) void CPU0(void){} ATTR(cpu_specific(pentium_iii_no_xmm_regs)) void CPU0(void){}
ATTR(cpu_specific(core_2nd_gen_avx)) void CPU1(void){} ATTR(cpu_specific(core_2nd_gen_avx)) void CPU1(void){}
ATTR(cpu_specific(core_3rd_gen_avx)) void CPU2(void){} ATTR(cpu_specific(core_3rd_gen_avx)) void CPU2(void){}
ATTR(cpu_specific(core_4th_gen_avx)) void CPU3(void){} ATTR(cpu_specific(core_4th_gen_avx)) void CPU3(void){}
ATTR(cpu_specific(core_5th_gen_avx)) void CPU4(void){} ATTR(cpu_specific(core_5th_gen_avx)) void CPU4(void){}
ATTR(cpu_specific(mic_avx512)) void CPU5(void){} ATTR(cpu_specific(mic_avx512)) void CPU5(void){}
ATTR(cpu_specific(pentiumpro)) void CPU6(void){}
ATTR(cpu_specific(pentium3)) void CPU7(void){}
ATTR(cpu_specific(pentium3m)) void CPU8(void){}
ATTR(cpu_specific(pentium4)) void CPU9(void){}
ATTR(cpu_specific(pentium4m)) void CPU10(void){}
ATTR(cpu_specific(yonah)) void CPU11(void){}
ATTR(cpu_specific(prescott)) void CPU12(void){}
ATTR(cpu_specific(nocona)) void CPU13(void){}
ATTR(cpu_specific(core2)) void CPU14(void){}
ATTR(cpu_specific(penryn)) void CPU15(void){}
ATTR(cpu_specific(bonnell)) void CPU16(void){}
ATTR(cpu_specific(silvermont)) void CPU17(void){}
ATTR(cpu_specific(slm)) void CPU18(void){}
ATTR(cpu_specific(goldmont_plus)) void CPU19(void){}
ATTR(cpu_specific(tremont)) void CPU20(void){}
ATTR(cpu_specific(nehalem)) void CPU21(void){}
ATTR(cpu_specific(corei7)) void CPU22(void){}
ATTR(cpu_specific(westmere)) void CPU23(void){}
ATTR(cpu_specific(sandybridge)) void CPU24(void){}
ATTR(cpu_specific(skx)) void CPU25(void){}
ATTR(cpu_specific(rocketlake)) void CPU26(void){}
ATTR(cpu_specific(icelake_server)) void CPU27(void){}
ATTR(cpu_specific(sapphirerapids)) void CPU28(void){}
ATTR(cpu_specific(raptorlake)) void CPU29(void){}
ATTR(cpu_specific(meteorlake)) void CPU30(void){}
ATTR(cpu_specific(sierraforest)) void CPU31(void){}
ATTR(cpu_specific(grandridge)) void CPU32(void){}
ATTR(cpu_specific(graniterapids)) void CPU33(void){}
ATTR(cpu_specific(emeraldrapids)) void CPU34(void){}

llvm/lib/TargetParser/X86TargetParser.cpp

Show First 20 Lines • Show All 324 Lines • ▼ Show 20 Lines // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility.
// i486-generation processors. // i486-generation processors.
{ {"i486"}, CK_i486, ~0U, FeatureX87, '\0', false }, { {"i486"}, CK_i486, ~0U, FeatureX87, '\0', false },
{ {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX, '\0', false }, { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX, '\0', false },
{ {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW, '\0', false }, { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW, '\0', false },
{ {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW, '\0', false }, { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW, '\0', false },
// i586-generation processors, P5 microarchitecture based. // i586-generation processors, P5 microarchitecture based.
{ {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B, '\0', false }, { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B, '\0', false },
{ {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B, 'B', false }, { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B, 'B', false },
{ {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX, '\0', false }, { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX, '\0', false },
RKSimonUnsubmitted
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add this as well?

RKSimon: add this as well?
FreddyYeAuthorUnsubmitted
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cpu names contain '-' are not supported for cpu_specific/dispatch feature since '-' is not an identifier character. The solution here is creating a new name with '_' replacing and set the OnlyForCPUDispatchSpecific as true, like icelake-client, icelake-server and goldmont-plus

FreddyYe: cpu names contain '-' are not supported for cpu_specific/dispatch feature since '-' is not an…
RKSimonUnsubmitted
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Understood - cheers.

RKSimon: Understood - cheers.
{ {"pentium_mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX, 'D', true }, { {"pentium_mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX, 'D', true },
// i686-generation processors, P6 / Pentium M microarchitecture based. // i686-generation processors, P6 / Pentium M microarchitecture based.
{ {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, '\0', false }, { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, 'C', false },
{ {"pentium_pro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, 'C', true }, { {"pentium_pro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, 'C', true },
{ {"i686"}, CK_i686, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, '\0', false }, { {"i686"}, CK_i686, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, '\0', false },
{ {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2, '\0', false }, { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2, 'E', false },
{ {"pentium_ii"}, CK_Pentium2, ~0U, FeaturesPentium2, 'E', true }, { {"pentium_ii"}, CK_Pentium2, ~0U, FeaturesPentium2, 'E', true },
{ {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3, '\0', false }, { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', false },
{ {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3, '\0', false }, { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', false },
{ {"pentium_iii"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', true }, { {"pentium_iii"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', true },
{ {"pentium_iii_no_xmm_regs"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', true }, { {"pentium_iii_no_xmm_regs"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', true },
{ {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4, '\0', false }, { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4, '\0', false },
{ {"pentium_m"}, CK_PentiumM, ~0U, FeaturesPentium4, 'K', true }, { {"pentium_m"}, CK_PentiumM, ~0U, FeaturesPentium4, 'K', true },
{ {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3, '\0', false }, { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3, '\0', false },
{ {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott, '\0', false }, { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott, 'L', false },
// Netburst microarchitecture based processors. // Netburst microarchitecture based processors.
{ {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4, '\0', false }, { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', false },
{ {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4, '\0', false }, { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', false },
{ {"pentium_4"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', true }, { {"pentium_4"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', true },
{ {"pentium_4_sse3"}, CK_Prescott, ~0U, FeaturesPrescott, 'L', true }, { {"pentium_4_sse3"}, CK_Prescott, ~0U, FeaturesPrescott, 'L', true },
{ {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott, '\0', false }, { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott, 'L', false },
{ {"nocona"}, CK_Nocona, ~0U, FeaturesNocona, '\0', false }, { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona, 'L', false },
// Core microarchitecture based processors. // Core microarchitecture based processors.
{ {"core2"}, CK_Core2, FEATURE_SSSE3, FeaturesCore2, '\0', false }, { {"core2"}, CK_Core2, FEATURE_SSSE3, FeaturesCore2, 'M', false },
{ {"core_2_duo_ssse3"}, CK_Core2, ~0U, FeaturesCore2, 'M', true }, { {"core_2_duo_ssse3"}, CK_Core2, ~0U, FeaturesCore2, 'M', true },
{ {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn, '\0', false }, { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn, 'N', false },
{ {"core_2_duo_sse4_1"}, CK_Penryn, ~0U, FeaturesPenryn, 'N', true }, { {"core_2_duo_sse4_1"}, CK_Penryn, ~0U, FeaturesPenryn, 'N', true },
// Atom processors // Atom processors
{ {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell, '\0', false }, { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell, 'O', false },
{ {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell, 'O', false }, { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell, 'O', false },
{ {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, '\0', false }, { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, 'c', false },
{ {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, '\0', false }, { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, 'c', false },
{ {"atom_sse4_2"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'c', true }, { {"atom_sse4_2"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'c', true },
{ {"atom_sse4_2_movbe"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont, 'd', true }, { {"atom_sse4_2_movbe"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont, 'd', true },
{ {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont, 'i', false }, { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont, 'i', false },
{ {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, '\0', false }, { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, '\0', false },
{ {"goldmont_plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, '\0', true }, { {"goldmont_plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, 'd', true },
{ {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont, '\0', false }, { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont, 'd', false },
// Nehalem microarchitecture based processors. // Nehalem microarchitecture based processors.
{ {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, '\0', false }, { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'P', false },
{ {"core_i7_sse4_2"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'P', true }, { {"core_i7_sse4_2"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'P', true },
{ {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, '\0', false }, { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'P', false },
// Westmere microarchitecture based processors. // Westmere microarchitecture based processors.
{ {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere, '\0', false }, { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere, 'Q', false },
{ {"core_aes_pclmulqdq"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'Q', true }, { {"core_aes_pclmulqdq"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'Q', true },
// Sandy Bridge microarchitecture based processors. // Sandy Bridge microarchitecture based processors.
{ {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge, 'R', false }, { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge, 'R', false },
{ {"core_2nd_gen_avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge, 'R', true }, { {"core_2nd_gen_avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge, 'R', true },
{ {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge, '\0', false }, { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge, '\0', false },
// Ivy Bridge microarchitecture based processors. // Ivy Bridge microarchitecture based processors.
{ {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge, 'S', false }, { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge, 'S', false },
{ {"core_3rd_gen_avx"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge, 'S', true }, { {"core_3rd_gen_avx"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge, 'S', true },
{ {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge, '\0', false }, { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge, '\0', false },
// Haswell microarchitecture based processors. // Haswell microarchitecture based processors.
{ {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, 'V', false }, { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, 'V', false },
{ {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, '\0', false }, { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, '\0', false },
{ {"core_4th_gen_avx"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, 'V', true }, { {"core_4th_gen_avx"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, 'V', true },
{ {"core_4th_gen_avx_tsx"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, 'W', true }, { {"core_4th_gen_avx_tsx"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, 'W', true },
// Broadwell microarchitecture based processors. // Broadwell microarchitecture based processors.
{ {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell, 'X', false }, { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell, 'X', false },
{ {"core_5th_gen_avx"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell, 'X', true }, { {"core_5th_gen_avx"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell, 'X', true },
{ {"core_5th_gen_avx_tsx"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell, 'Y', true }, { {"core_5th_gen_avx_tsx"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell, 'Y', true },
// Skylake client microarchitecture based processors. // Skylake client microarchitecture based processors.
{ {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient, 'b', false }, { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient, 'b', false },
// Skylake server microarchitecture based processors. // Skylake server microarchitecture based processors.
{ {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer, '\0', false }, { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer, '\0', false },
{ {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer, '\0', false }, { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer, 'a', false },
{ {"skylake_avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer, 'a', true }, { {"skylake_avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer, 'a', true },
// Cascadelake Server microarchitecture based processors. // Cascadelake Server microarchitecture based processors.
{ {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake, '\0', false }, { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake, 'o', false },
// Cooperlake Server microarchitecture based processors. // Cooperlake Server microarchitecture based processors.
{ {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake, '\0', false }, { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake, 'f', false },
// Cannonlake client microarchitecture based processors. // Cannonlake client microarchitecture based processors.
{ {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake, 'e', false }, { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake, 'e', false },
// Icelake client microarchitecture based processors. // Icelake client microarchitecture based processors.
{ {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient, '\0', false }, { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient, '\0', false },
{ {"icelake_client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient, 'k', true },
// Rocketlake microarchitecture based processors. // Rocketlake microarchitecture based processors.
{ {"rocketlake"}, CK_Rocketlake, FEATURE_AVX512VBMI2, FeaturesRocketlake, '\0', false }, { {"rocketlake"}, CK_Rocketlake, FEATURE_AVX512VBMI2, FeaturesRocketlake, 'k', false },
// Icelake server microarchitecture based processors. // Icelake server microarchitecture based processors.
{ {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer, '\0', false }, { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer, '\0', false },
{ {"icelake_server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer, 'k', true },
// Tigerlake microarchitecture based processors. // Tigerlake microarchitecture based processors.
{ {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake, '\0', false }, { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake, 'l', false },
// Sapphire Rapids microarchitecture based processors. // Sapphire Rapids microarchitecture based processors.
{ {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512BF16, FeaturesSapphireRapids, '\0', false }, { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512BF16, FeaturesSapphireRapids, 'n', false },
FreddyYeAuthorUnsubmitted
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SPR has AVX512BF16 comparing to icelake-server, which is a X86_FEATURE_COMPAT feature.

FreddyYe: SPR has AVX512BF16 comparing to icelake-server, which is a X86_FEATURE_COMPAT feature.
// Alderlake microarchitecture based processors. // Alderlake microarchitecture based processors.
{ {"alderlake"}, CK_Alderlake, FEATURE_AVX2, FeaturesAlderlake, '\0', false }, { {"alderlake"}, CK_Alderlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
// Raptorlake microarchitecture based processors. // Raptorlake microarchitecture based processors.
{ {"raptorlake"}, CK_Raptorlake, FEATURE_AVX2, FeaturesAlderlake, '\0', false }, { {"raptorlake"}, CK_Raptorlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
// Meteorlake microarchitecture based processors. // Meteorlake microarchitecture based processors.
{ {"meteorlake"}, CK_Meteorlake, FEATURE_AVX2, FeaturesAlderlake, '\0', false }, { {"meteorlake"}, CK_Meteorlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
// Sierraforest microarchitecture based processors. // Sierraforest microarchitecture based processors.
{ {"sierraforest"}, CK_Sierraforest, FEATURE_AVX2, FeaturesSierraforest, '\0', false }, { {"sierraforest"}, CK_Sierraforest, FEATURE_AVX2, FeaturesSierraforest, 'p', false },
// Grandridge microarchitecture based processors. // Grandridge microarchitecture based processors.
{ {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesGrandridge, '\0', false }, { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesGrandridge, 'p', false },
// Granite Rapids microarchitecture based processors. // Granite Rapids microarchitecture based processors.
{ {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512BF16, FeaturesGraniteRapids, '\0', false }, { {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512BF16, FeaturesGraniteRapids, 'n', false },
// Emerald Rapids microarchitecture based processors. // Emerald Rapids microarchitecture based processors.
{ {"emeraldrapids"}, CK_Emeraldrapids, FEATURE_AVX512BF16, FeaturesSapphireRapids, '\0', false }, { {"emeraldrapids"}, CK_Emeraldrapids, FEATURE_AVX512BF16, FeaturesSapphireRapids, 'n', false },
// Knights Landing processor. // Knights Landing processor.
{ {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL, 'Z', false }, { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL, 'Z', false },
{ {"mic_avx512"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL, 'Z', true }, { {"mic_avx512"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL, 'Z', true },
// Knights Mill processor. // Knights Mill processor.
{ {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM, 'j', false }, { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM, 'j', false },
// Lakemont microarchitecture based processors. // Lakemont microarchitecture based processors.
{ {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B, '\0', false }, { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B, '\0', false },
// K6 architecture processors. // K6 architecture processors.
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