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Differential D154232

[AArch64] NFC : Change the way SVE pseudos are appended
ClosedPublic

Authored by harviniriawan on Jun 30 2023, 9:39 AM.

Details

Reviewers
dmgreen
paulwalker-arm
Summary
  • SVE pseudos don't pick up the right latency information during MI scheduling as the regex do not match with instruction name.
  • Move UNDEF, PSEUDO, and ZERO to the end of actual SVE instruction
  • Some CPUs *td files will be fixed in the next commit

    Differential Revision: https://reviews.llvm.org/D154232

Diff Detail

Unit TestsFailed

TimeTest
3,740 msx64 debian > AddressSanitizer-x86_64-linux-dynamic.TestCases/Linux::auto_memory_profile_test.cpp
60,050 msx64 debian > ThreadSanitizer-x86_64.ThreadSanitizer-x86_64::restore_stack.cpp

Event Timeline

harviniriawan created this revision.Jun 30 2023, 9:39 AM
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Herald added subscribers: ctetreau, hiraditya, kristof.beyls. · View Herald Transcript
harviniriawan requested review of this revision.Jun 30 2023, 9:39 AM
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harviniriawan added a child revision: D154084: [AArch64] Modify SVE Pseudo appends.Jun 30 2023, 9:40 AM
Harbormaster completed remote builds in B242455: Diff 536294.Jun 30 2023, 10:50 AM
Matt added a subscriber: Matt.Jun 30 2023, 4:29 PM
dmgreen added a comment.Jul 3 2023, 1:03 AM

Remember to upload with context, it makes the patch easier to read in phabricator.

I think to make this an NFC the Neoverse-N2 changes would need to be included in this patch too.

dmgreen mentioned this in D154084: [AArch64] Modify SVE Pseudo appends.Jul 3 2023, 1:06 AM
harviniriawan updated this revision to Diff 536718.Jul 3 2023, 4:29 AM
harviniriawan retitled this revision from [AArch64] NFC : Change the way pseudos are appended to [AArch64] NFC : Change the way SVE pseudos are appended.
harviniriawan edited the summary of this revision. (Show Details)
paulwalker-arm added inline comments.Jul 3 2023, 5:14 AM
llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
2144–2146

This is one example, of many, that makes this patch not NFC because you're changing the scheduling information RSHR_ZPZI_*, which is presumably missing before this point. What I'd like to see is a simple NFC patch where the pseudo instructions have been renamed (as in a literal renaming of the instructions and their uses). Then following patch or patches that update the scheduling modes to increase their coverage of pseudo instructions.

rjj added a subscriber: rjj.Jul 3 2023, 5:57 AM
rjj added inline comments.
llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
2275

This match is unnecessary.

2552

This is repeated, and the same for the two instructions below.

Harbormaster completed remote builds in B242768: Diff 536718.Jul 3 2023, 6:12 AM
harviniriawan updated this revision to Diff 536748.Jul 3 2023, 6:34 AM
harviniriawan added inline comments.
llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
2144–2146

ok will change it

harviniriawan updated this revision to Diff 536768.Jul 3 2023, 7:38 AM
harviniriawan edited the summary of this revision. (Show Details)Jul 3 2023, 7:41 AM
Harbormaster completed remote builds in B242800: Diff 536768.Jul 3 2023, 10:23 AM
paulwalker-arm accepted this revision.Jul 3 2023, 11:00 AM
This revision is now accepted and ready to land.Jul 3 2023, 11:00 AM
dmgreen accepted this revision.Jul 4 2023, 1:12 AM

LGTM. Thanks

harviniriawan closed this revision.Jul 4 2023, 2:44 AM

Revision Contents

Diff 536768

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,362 Lines • ▼ Show 20 Lines def : Pat<(vt1 (op PPR:$gp, (AddrCP GPR64:$base, GPR64:$idx))),
(load_instr $gp, $base, $idx)>; (load_instr $gp, $base, $idx)>;
} }
defm : ld1rq_pat<nxv16i8, AArch64ld1rq_z, LD1RQ_B, am_sve_regreg_lsl0>; defm : ld1rq_pat<nxv16i8, AArch64ld1rq_z, LD1RQ_B, am_sve_regreg_lsl0>;
defm : ld1rq_pat<nxv8i16, AArch64ld1rq_z, LD1RQ_H, am_sve_regreg_lsl1>; defm : ld1rq_pat<nxv8i16, AArch64ld1rq_z, LD1RQ_H, am_sve_regreg_lsl1>;
defm : ld1rq_pat<nxv4i32, AArch64ld1rq_z, LD1RQ_W, am_sve_regreg_lsl2>; defm : ld1rq_pat<nxv4i32, AArch64ld1rq_z, LD1RQ_W, am_sve_regreg_lsl2>;
defm : ld1rq_pat<nxv2i64, AArch64ld1rq_z, LD1RQ_D, am_sve_regreg_lsl3>; defm : ld1rq_pat<nxv2i64, AArch64ld1rq_z, LD1RQ_D, am_sve_regreg_lsl3>;
def : Pat<(sext_inreg (nxv2i64 ZPR:$Zs), nxv2i32), (SXTW_ZPmZ_UNDEF_D (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$Zs)>; def : Pat<(sext_inreg (nxv2i64 ZPR:$Zs), nxv2i32), (SXTW_ZPmZ_D_UNDEF (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$Zs)>;
def : Pat<(sext_inreg (nxv2i64 ZPR:$Zs), nxv2i16), (SXTH_ZPmZ_UNDEF_D (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$Zs)>; def : Pat<(sext_inreg (nxv2i64 ZPR:$Zs), nxv2i16), (SXTH_ZPmZ_D_UNDEF (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$Zs)>;
def : Pat<(sext_inreg (nxv2i64 ZPR:$Zs), nxv2i8), (SXTB_ZPmZ_UNDEF_D (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$Zs)>; def : Pat<(sext_inreg (nxv2i64 ZPR:$Zs), nxv2i8), (SXTB_ZPmZ_D_UNDEF (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$Zs)>;
def : Pat<(sext_inreg (nxv4i32 ZPR:$Zs), nxv4i16), (SXTH_ZPmZ_UNDEF_S (IMPLICIT_DEF), (PTRUE_S 31), ZPR:$Zs)>; def : Pat<(sext_inreg (nxv4i32 ZPR:$Zs), nxv4i16), (SXTH_ZPmZ_S_UNDEF (IMPLICIT_DEF), (PTRUE_S 31), ZPR:$Zs)>;
def : Pat<(sext_inreg (nxv4i32 ZPR:$Zs), nxv4i8), (SXTB_ZPmZ_UNDEF_S (IMPLICIT_DEF), (PTRUE_S 31), ZPR:$Zs)>; def : Pat<(sext_inreg (nxv4i32 ZPR:$Zs), nxv4i8), (SXTB_ZPmZ_S_UNDEF (IMPLICIT_DEF), (PTRUE_S 31), ZPR:$Zs)>;
def : Pat<(sext_inreg (nxv8i16 ZPR:$Zs), nxv8i8), (SXTB_ZPmZ_UNDEF_H (IMPLICIT_DEF), (PTRUE_H 31), ZPR:$Zs)>; def : Pat<(sext_inreg (nxv8i16 ZPR:$Zs), nxv8i8), (SXTB_ZPmZ_H_UNDEF (IMPLICIT_DEF), (PTRUE_H 31), ZPR:$Zs)>;
// General case that we ideally never want to match. // General case that we ideally never want to match.
def : Pat<(vscale GPR64:$scale), (MADDXrrr (UBFMXri (RDVLI_XI 1), 4, 63), $scale, XZR)>; def : Pat<(vscale GPR64:$scale), (MADDXrrr (UBFMXri (RDVLI_XI 1), 4, 63), $scale, XZR)>;
let AddedComplexity = 5 in { let AddedComplexity = 5 in {
def : Pat<(vscale (i64 1)), (UBFMXri (RDVLI_XI 1), 4, 63)>; def : Pat<(vscale (i64 1)), (UBFMXri (RDVLI_XI 1), 4, 63)>;
def : Pat<(vscale (i64 -1)), (SBFMXri (RDVLI_XI -1), 4, 63)>; def : Pat<(vscale (i64 -1)), (SBFMXri (RDVLI_XI -1), 4, 63)>;
▲ Show 20 Lines • Show All 1,604 Lines • Show Last 20 Lines

llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td

Show First 20 Lines • Show All 2,059 Lines • ▼ Show 20 Lines
// Predicate zip/unzip // Predicate zip/unzip
def : InstRW<[V2Write_2cyc_1M], (instregex "^(ZIP|UZP)[12]_PPP_[BHSD]$")>; def : InstRW<[V2Write_2cyc_1M], (instregex "^(ZIP|UZP)[12]_PPP_[BHSD]$")>;
// SVE integer instructions // SVE integer instructions
// ----------------------------------------------------------------------------- // -----------------------------------------------------------------------------
// Arithmetic, absolute diff // Arithmetic, absolute diff
def : InstRW<[V2Write_2cyc_1V], (instregex "^[SU]ABD_ZPmZ_[BHSD]$", def : InstRW<[V2Write_2cyc_1V], (instregex "^[SU]ABD_ZPmZ_[BHSD]$",
"^[SU]ABD_ZPZZ_UNDEF_[BHSD]$")>; "^[SU]ABD_ZPZZ_[BHSD]_UNDEF$")>;
// Arithmetic, absolute diff accum // Arithmetic, absolute diff accum
def : InstRW<[V2Wr_ZA, V2Rd_ZA], (instregex "^[SU]ABA_ZZZ_[BHSD]$")>; def : InstRW<[V2Wr_ZA, V2Rd_ZA], (instregex "^[SU]ABA_ZZZ_[BHSD]$")>;
// Arithmetic, absolute diff accum long // Arithmetic, absolute diff accum long
def : InstRW<[V2Wr_ZA, V2Rd_ZA], (instregex "^[SU]ABAL[TB]_ZZZ_[HSD]$")>; def : InstRW<[V2Wr_ZA, V2Rd_ZA], (instregex "^[SU]ABAL[TB]_ZZZ_[HSD]$")>;
// Arithmetic, absolute diff long // Arithmetic, absolute diff long
def : InstRW<[V2Write_2cyc_1V], (instregex "^[SU]ABDL[TB]_ZZZ_[HSD]$")>; def : InstRW<[V2Write_2cyc_1V], (instregex "^[SU]ABDL[TB]_ZZZ_[HSD]$")>;
// Arithmetic, basic // Arithmetic, basic
def : InstRW<[V2Write_2cyc_1V], def : InstRW<[V2Write_2cyc_1V],
(instregex "^(ABS|ADD|CNOT|NEG|SUB|SUBR)_ZPmZ_[BHSD]$", (instregex "^(ABS|ADD|CNOT|NEG|SUB|SUBR)_ZPmZ_[BHSD]$",
"^(ABS|CNOT|NEG)_ZPmZ_UNDEF_[BHSD]$", "^(ABS|CNOT|NEG)_ZPmZ_[BHSD]_UNDEF$",
"^(ADD|SUB)_ZZZ_[BHSD]$", "^(ADD|SUB)_ZZZ_[BHSD]$",
"^(ADD|SUB|SUBR)_ZI_[BHSD]$", "^(ADD|SUB|SUBR)_ZI_[BHSD]$",
"^ADR_[SU]XTW_ZZZ_D_[0123]$", "^ADR_[SU]XTW_ZZZ_D_[0123]$",
"^ADR_LSL_ZZZ_[SD]_[0123]$", "^ADR_LSL_ZZZ_[SD]_[0123]$",
"^[SU](ADD|SUB)[LW][BT]_ZZZ_[HSD]$", "^[SU](ADD|SUB)[LW][BT]_ZZZ_[HSD]$",
"^SADDLBT_ZZZ_[HSD]$", "^SADDLBT_ZZZ_[HSD]$",
"^[SU]H(ADD|SUB|SUBR)_ZPmZ_[BHSD]$", "^[SU]H(ADD|SUB|SUBR)_ZPmZ_[BHSD]$",
"^SSUBL(BT|TB)_ZZZ_[HSD]$")>; "^SSUBL(BT|TB)_ZZZ_[HSD]$")>;
// Arithmetic, complex // Arithmetic, complex
def : InstRW<[V2Write_2cyc_1V], def : InstRW<[V2Write_2cyc_1V],
(instregex "^R?(ADD|SUB)HN[BT]_ZZZ_[BHS]$", (instregex "^R?(ADD|SUB)HN[BT]_ZZZ_[BHS]$",
"^SQ(ABS|ADD|NEG|SUB|SUBR)_ZPmZ_[BHSD]$", "^SQ(ABS|ADD|NEG|SUB|SUBR)_ZPmZ_[BHSD]$",
"^SQ(ABS|NEG)_ZPmZ_UNDEF_[BHSD]$", "^SQ(ABS|NEG)_ZPmZ_[BHSD]_UNDEF$",
"^[SU]Q(ADD|SUB)_ZZZ_[BHSD]$", "^[SU]Q(ADD|SUB)_ZZZ_[BHSD]$",
"^[SU]Q(ADD|SUB)_ZI_[BHSD]$", "^[SU]Q(ADD|SUB)_ZI_[BHSD]$",
"^(SRH|SUQ|UQ|USQ|URH)ADD_ZPmZ_[BHSD]$", "^(SRH|SUQ|UQ|USQ|URH)ADD_ZPmZ_[BHSD]$",
"^(UQSUB|UQSUBR)_ZPmZ_[BHSD]$")>; "^(UQSUB|UQSUBR)_ZPmZ_[BHSD]$")>;
// Arithmetic, large integer // Arithmetic, large integer
def : InstRW<[V2Write_2cyc_1V], (instregex "^(AD|SB)CL[BT]_ZZZ_[SD]$")>; def : InstRW<[V2Write_2cyc_1V], (instregex "^(AD|SB)CL[BT]_ZZZ_[SD]$")>;
// Arithmetic, pairwise add // Arithmetic, pairwise add
def : InstRW<[V2Write_2cyc_1V], (instregex "^ADDP_ZPmZ_[BHSD]$")>; def : InstRW<[V2Write_2cyc_1V], (instregex "^ADDP_ZPmZ_[BHSD]$")>;
// Arithmetic, pairwise add and accum long // Arithmetic, pairwise add and accum long
def : InstRW<[V2Wr_ZPA, ReadDefault, V2Rd_ZPA], def : InstRW<[V2Wr_ZPA, ReadDefault, V2Rd_ZPA],
(instregex "^[SU]ADALP_ZPmZ_[HSD]$")>; (instregex "^[SU]ADALP_ZPmZ_[HSD]$")>;
// Arithmetic, shift // Arithmetic, shift
def : InstRW<[V2Write_2cyc_1V13], def : InstRW<[V2Write_2cyc_1V13],
(instregex "^(ASR|LSL|LSR)_WIDE_ZPmZ_[BHS]$", (instregex "^(ASR|LSL|LSR)_WIDE_ZPmZ_[BHS]$",
"^(ASR|LSL|LSR)_WIDE_ZZZ_[BHS]$", "^(ASR|LSL|LSR)_WIDE_ZZZ_[BHS]$",
"^(ASR|LSL|LSR)_ZPmI_[BHSD]$", "^(ASR|LSL|LSR)_ZPmI_[BHSD]$",
"^(ASR|LSL|LSR)_ZPmZ_[BHSD]$", "^(ASR|LSL|LSR)_ZPmZ_[BHSD]$",
"^(ASR|LSL|LSR)_ZZI_[BHSD]$", "^(ASR|LSL|LSR)_ZZI_[BHSD]$",
"^(ASR|LSL|LSR)_ZPZ[IZ]_UNDEF_[BHSD]$", "^(ASR|LSL|LSR)_ZPZ[IZ]_[BHSD]_UNDEF$",
"^(ASRR|LSLR|LSRR)_ZPmZ_[BHSD]$")>; "^(ASRR|LSLR|LSRR)_ZPmZ_[BHSD]$")>;
// Arithmetic, shift and accumulate // Arithmetic, shift and accumulate
def : InstRW<[V2Wr_ZSA, V2Rd_ZSA], (instregex "^[SU]R?SRA_ZZI_[BHSD]$")>; def : InstRW<[V2Wr_ZSA, V2Rd_ZSA], (instregex "^[SU]R?SRA_ZZI_[BHSD]$")>;
// Arithmetic, shift by immediate // Arithmetic, shift by immediate
def : InstRW<[V2Write_2cyc_1V13], (instregex "^SHRN[BT]_ZZI_[BHS]$", def : InstRW<[V2Write_2cyc_1V13], (instregex "^SHRN[BT]_ZZI_[BHS]$",
"^[SU]SHLL[BT]_ZZI_[HSD]$")>; "^[SU]SHLL[BT]_ZZI_[HSD]$")>;
// Arithmetic, shift by immediate and insert // Arithmetic, shift by immediate and insert
def : InstRW<[V2Write_2cyc_1V13], (instregex "^(SLI|SRI)_ZZI_[BHSD]$")>; def : InstRW<[V2Write_2cyc_1V13], (instregex "^(SLI|SRI)_ZZI_[BHSD]$")>;
// Arithmetic, shift complex // Arithmetic, shift complex
def : InstRW<[V2Write_4cyc_1V13], def : InstRW<[V2Write_4cyc_1V13],
(instregex "^(SQ)?RSHRU?N[BT]_ZZI_[BHS]$", (instregex "^(SQ)?RSHRU?N[BT]_ZZI_[BHS]$",
"^(SQRSHL|SQRSHLR|SQSHL|SQSHLR|UQRSHL|UQRSHLR|UQSHL|UQSHLR)_ZPmZ_[BHSD]$", "^(SQRSHL|SQRSHLR|SQSHL|SQSHLR|UQRSHL|UQRSHLR|UQSHL|UQSHLR)_ZPmZ_[BHSD]$",
"^[SU]QR?SHL_ZPZZ_UNDEF_[BHSD]$", "^[SU]QR?SHL_ZPZZ_[BHSD]_UNDEF$",
"^(SQSHL|SQSHLU|UQSHL)_ZPmI_[BHSD]$", "^(SQSHL|SQSHLU|UQSHL)_ZPmI_[BHSD]$",
"^SQSHRU?N[BT]_ZZI_[BHS]$", "^SQSHRU?N[BT]_ZZI_[BHS]$",
"^UQR?SHRN[BT]_ZZI_[BHS]$")>; "^UQR?SHRN[BT]_ZZI_[BHS]$")>;
// Arithmetic, shift right for divide // Arithmetic, shift right for divide
def : InstRW<[V2Write_4cyc_1V13], (instregex "^ASRD_ZPmI_[BHSD]$")>; def : InstRW<[V2Write_4cyc_1V13], (instregex "^ASRD_ZPmI_[BHSD]$")>;
// Arithmetic, shift rounding // Arithmetic, shift rounding
def : InstRW<[V2Write_4cyc_1V13], (instregex "^[SU]RSHLR?_ZPmZ_[BHSD]$", def : InstRW<[V2Write_4cyc_1V13], (instregex "^[SU]RSHLR?_ZPmZ_[BHSD]$",
"^[SU]RSHL_ZPZZ_UNDEF_[BHSD]$", "^[SU]RSHL_ZPZZ_[BHSD]_UNDEF$",
paulwalker-armUnsubmitted
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This is one example, of many, that makes this patch not NFC because you're changing the scheduling information RSHR_ZPZI_*, which is presumably missing before this point. What I'd like to see is a simple NFC patch where the pseudo instructions have been renamed (as in a literal renaming of the instructions and their uses). Then following patch or patches that update the scheduling modes to increase their coverage of pseudo instructions.

paulwalker-arm: This is one example, of many, that makes this patch not NFC because you're changing the…
harviniriawanAuthorUnsubmitted
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ok will change it

harviniriawan: ok will change it
"^[SU]RSHR_ZPmI_[BHSD]$")>; "^[SU]RSHR_ZPmI_[BHSD]$")>;
// Bit manipulation // Bit manipulation
def : InstRW<[V2Write_6cyc_2V1], (instregex "^(BDEP|BEXT|BGRP)_ZZZ_[BHSD]$")>; def : InstRW<[V2Write_6cyc_2V1], (instregex "^(BDEP|BEXT|BGRP)_ZZZ_[BHSD]$")>;
// Bitwise select // Bitwise select
def : InstRW<[V2Write_2cyc_1V], (instregex "^(BSL|BSL1N|BSL2N|NBSL)_ZZZZ$")>; def : InstRW<[V2Write_2cyc_1V], (instregex "^(BSL|BSL1N|BSL2N|NBSL)_ZZZZ$")>;
// Count/reverse bits // Count/reverse bits
def : InstRW<[V2Write_2cyc_1V], (instregex "^(CLS|CLZ|CNT|RBIT)_ZPmZ_[BHSD]$", def : InstRW<[V2Write_2cyc_1V], (instregex "^(CLS|CLZ|CNT|RBIT)_ZPmZ_[BHSD]$",
"^(CLS|CLZ|CNT)_ZPmZ_UNDEF_[BHSD]$")>; "^(CLS|CLZ|CNT)_ZPmZ_[BHSD]_UNDEF$")>;
// Broadcast logical bitmask immediate to vector // Broadcast logical bitmask immediate to vector
def : InstRW<[V2Write_2cyc_1V], (instrs DUPM_ZI)>; def : InstRW<[V2Write_2cyc_1V], (instrs DUPM_ZI)>;
// Compare and set flags // Compare and set flags
def : InstRW<[V2Write_4or5cyc_1V0_1M0], def : InstRW<[V2Write_4or5cyc_1V0_1M0],
(instregex "^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_PPzZ[IZ]_[BHSD]$", (instregex "^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_PPzZ[IZ]_[BHSD]$",
"^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_WIDE_PPzZZ_[BHS]$")>; "^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_WIDE_PPzZZ_[BHS]$")>;
Show All 36 Lines
def : InstRW<[V2Write_5cyc_1M0_1V], (instregex "^CPY_ZPmR_[BHSD]$")>; def : InstRW<[V2Write_5cyc_1M0_1V], (instregex "^CPY_ZPmR_[BHSD]$")>;
// Copy, scalar SIMD&FP or imm // Copy, scalar SIMD&FP or imm
def : InstRW<[V2Write_2cyc_1V], (instregex "^CPY_ZPm[IV]_[BHSD]$", def : InstRW<[V2Write_2cyc_1V], (instregex "^CPY_ZPm[IV]_[BHSD]$",
"^CPY_ZPzI_[BHSD]$")>; "^CPY_ZPzI_[BHSD]$")>;
// Divides, 32 bit // Divides, 32 bit
def : InstRW<[V2Write_12cyc_1V0], (instregex "^[SU]DIVR?_ZPmZ_S$", def : InstRW<[V2Write_12cyc_1V0], (instregex "^[SU]DIVR?_ZPmZ_S$",
"^[SU]DIV_ZPZZ_UNDEF_S$")>; "^[SU]DIV_ZPZZ_S_UNDEF$")>;
// Divides, 64 bit // Divides, 64 bit
def : InstRW<[V2Write_20cyc_1V0], (instregex "^[SU]DIVR?_ZPmZ_D$", def : InstRW<[V2Write_20cyc_1V0], (instregex "^[SU]DIVR?_ZPmZ_D$",
"^[SU]DIV_ZPZZ_UNDEF_D$")>; "^[SU]DIV_ZPZZ_D_UNDEF$")>;
// Dot product, 8 bit // Dot product, 8 bit
def : InstRW<[V2Wr_ZDOTB, V2Rd_ZDOTB], (instregex "^[SU]DOT_ZZZI?_S$")>; def : InstRW<[V2Wr_ZDOTB, V2Rd_ZDOTB], (instregex "^[SU]DOT_ZZZI?_S$")>;
// Dot product, 8 bit, using signed and unsigned integers // Dot product, 8 bit, using signed and unsigned integers
def : InstRW<[V2Wr_ZDOTB, V2Rd_ZDOTB], (instrs SUDOT_ZZZI, USDOT_ZZZI, USDOT_ZZZ)>; def : InstRW<[V2Wr_ZDOTB, V2Rd_ZDOTB], (instrs SUDOT_ZZZI, USDOT_ZZZI, USDOT_ZZZ)>;
// Dot product, 16 bit // Dot product, 16 bit
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
// only / immediate, scalar operands // only / immediate, scalar operands
def : InstRW<[V2Write_8cyc_2M0_2V02], (instregex "^INDEX_(IR|RI|RR)_D$")>; def : InstRW<[V2Write_8cyc_2M0_2V02], (instregex "^INDEX_(IR|RI|RR)_D$")>;
// Logical // Logical
def : InstRW<[V2Write_2cyc_1V], def : InstRW<[V2Write_2cyc_1V],
(instregex "^(AND|EOR|ORR)_ZI$", (instregex "^(AND|EOR|ORR)_ZI$",
"^(AND|BIC|EOR|ORR)_ZZZ$", "^(AND|BIC|EOR|ORR)_ZZZ$",
"^EOR(BT|TB)_ZZZ_[BHSD]$", "^EOR(BT|TB)_ZZZ_[BHSD]$",
"^(AND|BIC|EOR|NOT|ORR)_ZPmZ_[BHSD]$", "^(AND|BIC|EOR|NOT|ORR)_ZPmZ_[BHSD]$",
rjjUnsubmitted
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This match is unnecessary.

rjj: This match is unnecessary.
"^NOT_ZPmZ_UNDEF_[BHSD]$")>; "^NOT_ZPmZ_[BHSD]_UNDEF$")>;
// Max/min, basic and pairwise // Max/min, basic and pairwise
def : InstRW<[V2Write_2cyc_1V], (instregex "^[SU](MAX|MIN)_ZI_[BHSD]$", def : InstRW<[V2Write_2cyc_1V], (instregex "^[SU](MAX|MIN)_ZI_[BHSD]$",
"^[SU](MAX|MIN)P?_ZPmZ_[BHSD]$", "^[SU](MAX|MIN)P?_ZPmZ_[BHSD]$",
"^[SU](MAX|MIN)_ZPZZ_UNDEF_[BHSD]$")>; "^[SU](MAX|MIN)_ZPZZ_[BHSD]_UNDEF$")>;
// Matching operations // Matching operations
// FIXME: SOG p. 44, n. 5: If the consuming instruction has a flag source, the // FIXME: SOG p. 44, n. 5: If the consuming instruction has a flag source, the
// latency for this instruction is 4 cycles. // latency for this instruction is 4 cycles.
def : InstRW<[V2Write_2or3cyc_1V0_1M], (instregex "^N?MATCH_PPzZZ_[BH]$")>; def : InstRW<[V2Write_2or3cyc_1V0_1M], (instregex "^N?MATCH_PPzZZ_[BH]$")>;
// Matrix multiply-accumulate // Matrix multiply-accumulate
def : InstRW<[V2Wr_ZMMA, V2Rd_ZMMA], (instrs SMMLA_ZZZ, UMMLA_ZZZ, USMMLA_ZZZ)>; def : InstRW<[V2Wr_ZMMA, V2Rd_ZMMA], (instrs SMMLA_ZZZ, UMMLA_ZZZ, USMMLA_ZZZ)>;
// Move prefix // Move prefix
def : InstRW<[V2Write_2cyc_1V], (instregex "^MOVPRFX_ZP[mz]Z_[BHSD]$", def : InstRW<[V2Write_2cyc_1V], (instregex "^MOVPRFX_ZP[mz]Z_[BHSD]$",
"^MOVPRFX_ZZ$")>; "^MOVPRFX_ZZ$")>;
// Multiply, B, H, S element size // Multiply, B, H, S element size
def : InstRW<[V2Write_4cyc_1V02], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_[BHS]$", def : InstRW<[V2Write_4cyc_1V02], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_[BHS]$",
"^MUL_ZPZZ_UNDEF_[BHS]$", "^MUL_ZPZZ_[BHS]_UNDEF$",
"^[SU]MULH_(ZPmZ|ZZZ)_[BHS]$", "^[SU]MULH_(ZPmZ|ZZZ)_[BHS]$",
"^[SU]MULH_ZPZZ_UNDEF_[BHS]$")>; "^[SU]MULH_ZPZZ_[BHS]_UNDEF$")>;
// Multiply, D element size // Multiply, D element size
def : InstRW<[V2Write_5cyc_2V02], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_D$", def : InstRW<[V2Write_5cyc_2V02], (instregex "^MUL_(ZI|ZPmZ|ZZZI|ZZZ)_D$",
"^MUL_ZPZZ_UNDEF_D$", "^MUL_ZPZZ_D_UNDEF$",
"^[SU]MULH_(ZPmZ|ZZZ)_D$", "^[SU]MULH_(ZPmZ|ZZZ)_D$",
"^[SU]MULH_ZPZZ_UNDEF_D$")>; "^[SU]MULH_ZPZZ_D_UNDEF$")>;
// Multiply long // Multiply long
def : InstRW<[V2Write_4cyc_1V02], (instregex "^[SU]MULL[BT]_ZZZI_[SD]$", def : InstRW<[V2Write_4cyc_1V02], (instregex "^[SU]MULL[BT]_ZZZI_[SD]$",
"^[SU]MULL[BT]_ZZZ_[HSD]$")>; "^[SU]MULL[BT]_ZZZ_[HSD]$")>;
// Multiply accumulate, B, H, S element size // Multiply accumulate, B, H, S element size
def : InstRW<[V2Wr_ZMABHS, V2Rd_ZMABHS], def : InstRW<[V2Wr_ZMABHS, V2Rd_ZMABHS],
(instregex "^ML[AS]_ZZZI_[HS]$", "^ML[AS]_ZPZZZ_UNDEF_[BHS]$")>; (instregex "^ML[AS]_ZZZI_[HS]$", "^ML[AS]_ZPZZZ_[BHS]_UNDEF$")>;
def : InstRW<[V2Wr_ZMABHS, ReadDefault, V2Rd_ZMABHS], def : InstRW<[V2Wr_ZMABHS, ReadDefault, V2Rd_ZMABHS],
(instregex "^(ML[AS]|MAD|MSB)_ZPmZZ_[BHS]$")>; (instregex "^(ML[AS]|MAD|MSB)_ZPmZZ_[BHS]$")>;
// Multiply accumulate, D element size // Multiply accumulate, D element size
def : InstRW<[V2Wr_ZMAD, V2Rd_ZMAD], def : InstRW<[V2Wr_ZMAD, V2Rd_ZMAD],
(instregex "^ML[AS]_ZZZI_D$", "^ML[AS]_ZPZZZ_UNDEF_D$")>; (instregex "^ML[AS]_ZZZI_D$", "^ML[AS]_ZPZZZ_D_UNDEF$")>;
def : InstRW<[V2Wr_ZMAD, ReadDefault, V2Rd_ZMAD], def : InstRW<[V2Wr_ZMAD, ReadDefault, V2Rd_ZMAD],
(instregex "^(ML[AS]|MAD|MSB)_ZPmZZ_D$")>; (instregex "^(ML[AS]|MAD|MSB)_ZPmZZ_D$")>;
// Multiply accumulate long // Multiply accumulate long
def : InstRW<[V2Wr_ZMAL, V2Rd_ZMAL], (instregex "^[SU]ML[AS]L[BT]_ZZZ_[HSD]$", def : InstRW<[V2Wr_ZMAL, V2Rd_ZMAL], (instregex "^[SU]ML[AS]L[BT]_ZZZ_[HSD]$",
"^[SU]ML[AS]L[BT]_ZZZI_[SD]$")>; "^[SU]ML[AS]L[BT]_ZZZI_[SD]$")>;
// Multiply accumulate saturating doubling long regular // Multiply accumulate saturating doubling long regular
Show All 35 Lines
def : InstRW<[V2Write_2cyc_1V23], (instregex "^PMUL_ZZZ_B$", def : InstRW<[V2Write_2cyc_1V23], (instregex "^PMUL_ZZZ_B$",
"^PMULL[BT]_ZZZ_[HDQ]$")>; "^PMULL[BT]_ZZZ_[HDQ]$")>;
// Predicate counting vector // Predicate counting vector
def : InstRW<[V2Write_2cyc_1V], (instregex "^([SU]Q)?(DEC|INC)[HWD]_ZPiI$")>; def : InstRW<[V2Write_2cyc_1V], (instregex "^([SU]Q)?(DEC|INC)[HWD]_ZPiI$")>;
// Reciprocal estimate // Reciprocal estimate
def : InstRW<[V2Write_4cyc_2V02], (instrs URECPE_ZPmZ_S, URSQRTE_ZPmZ_S, def : InstRW<[V2Write_4cyc_2V02], (instrs URECPE_ZPmZ_S, URSQRTE_ZPmZ_S,
URECPE_ZPmZ_UNDEF_S, URSQRTE_ZPmZ_UNDEF_S)>; URECPE_ZPmZ_S_UNDEF, URSQRTE_ZPmZ_S_UNDEF)>;
// Reduction, arithmetic, B form // Reduction, arithmetic, B form
def : InstRW<[V2Write_9cyc_2V_4V13], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_B")>; def : InstRW<[V2Write_9cyc_2V_4V13], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_B")>;
// Reduction, arithmetic, H form // Reduction, arithmetic, H form
def : InstRW<[V2Write_8cyc_2V_2V13], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_H")>; def : InstRW<[V2Write_8cyc_2V_2V13], (instregex "^[SU](ADD|MAX|MIN)V_VPZ_H")>;
// Reduction, arithmetic, S form // Reduction, arithmetic, S form
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// Zip/unzip // Zip/unzip
def : InstRW<[V2Write_2cyc_1V], (instregex "^(UZP|ZIP)[12]_ZZZ_[BHSDQ]$")>; def : InstRW<[V2Write_2cyc_1V], (instregex "^(UZP|ZIP)[12]_ZZZ_[BHSDQ]$")>;
// SVE floating-point instructions // SVE floating-point instructions
// ----------------------------------------------------------------------------- // -----------------------------------------------------------------------------
// Floating point absolute value/difference // Floating point absolute value/difference
def : InstRW<[V2Write_2cyc_1V], (instregex "^FAB[SD]_ZPmZ_[HSD]$", def : InstRW<[V2Write_2cyc_1V], (instregex "^FAB[SD]_ZPmZ_[HSD]$",
"^FABD_ZPZZ_UNDEF_[HSD]$", "^FABD_ZPZZ_[HSD]_UNDEF$",
"^FABS_ZPmZ_UNDEF_[HSD]$")>; "^FABS_ZPmZ_[HSD]_UNDEF$")>;
// Floating point arithmetic // Floating point arithmetic
def : InstRW<[V2Write_2cyc_1V], (instregex "^F(ADD|SUB)_(ZPm[IZ]|ZZZ)_[HSD]$", def : InstRW<[V2Write_2cyc_1V], (instregex "^F(ADD|SUB)_(ZPm[IZ]|ZZZ)_[HSD]$",
"^F(ADD|SUB)_ZPZ[IZ]_UNDEF_[HSD]$", "^F(ADD|SUB)_ZPZ[IZ]_[HSD]_UNDEF$",
"^FADDP_ZPmZZ_[HSD]$", "^FADDP_ZPmZZ_[HSD]$",
"^FNEG_ZPmZ(_UNDEF)?_[HSD]$", "^FNEG_ZPmZ(_UNDEF)?_[HSD]$",
"^FSUBR_ZPm[IZ]_[HSD]$", "^FSUBR_ZPm[IZ]_[HSD]$",
"^FSUBR_ZPZI_UNDEF_[HSD]$")>; "^FSUBR_ZPZI_[HSD]_UNDEF$")>;
// Floating point associative add, F16 // Floating point associative add, F16
def : InstRW<[V2Write_10cyc_1V1_9rc], (instrs FADDA_VPZ_H)>; def : InstRW<[V2Write_10cyc_1V1_9rc], (instrs FADDA_VPZ_H)>;
// Floating point associative add, F32 // Floating point associative add, F32
def : InstRW<[V2Write_6cyc_1V1_5rc], (instrs FADDA_VPZ_S)>; def : InstRW<[V2Write_6cyc_1V1_5rc], (instrs FADDA_VPZ_S)>;
// Floating point associative add, F64 // Floating point associative add, F64
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Linesdef : InstRW<[V2Write_3cyc_1V02],
(instregex "^FCVTZ[SU]_ZPmZ_(HtoD|StoD|DtoS|DtoD)(_UNDEF)?$")>; (instregex "^FCVTZ[SU]_ZPmZ_(HtoD|StoD|DtoS|DtoD)(_UNDEF)?$")>;
// Floating point copy // Floating point copy
def : InstRW<[V2Write_2cyc_1V], (instregex "^FCPY_ZPmI_[HSD]$", def : InstRW<[V2Write_2cyc_1V], (instregex "^FCPY_ZPmI_[HSD]$",
"^FDUP_ZI_[HSD]$")>; "^FDUP_ZI_[HSD]$")>;
// Floating point divide, F16 // Floating point divide, F16
def : InstRW<[V2Write_13cyc_1V02_12rc], (instregex "^FDIVR?_ZPmZ_H$", def : InstRW<[V2Write_13cyc_1V02_12rc], (instregex "^FDIVR?_ZPmZ_H$",
"^FDIV_ZPZZ_UNDEF_H$")>; "^FDIV_ZPZZ_H_UNDEF$")>;
// Floating point divide, F32 // Floating point divide, F32
def : InstRW<[V2Write_10cyc_1V02_9rc], (instregex "^FDIVR?_ZPmZ_S$", def : InstRW<[V2Write_10cyc_1V02_9rc], (instregex "^FDIVR?_ZPmZ_S$",
"^FDIV_ZPZZ_UNDEF_S$")>; "^FDIV_ZPZZ_S_UNDEF$")>;
// Floating point divide, F64 // Floating point divide, F64
def : InstRW<[V2Write_15cyc_1V02_14rc], (instregex "^FDIVR?_ZPmZ_D$", def : InstRW<[V2Write_15cyc_1V02_14rc], (instregex "^FDIVR?_ZPmZ_D$",
"^FDIV_ZPZZ_UNDEF_D$")>; "^FDIV_ZPZZ_D_UNDEF$")>;
// Floating point min/max pairwise // Floating point min/max pairwise
def : InstRW<[V2Write_2cyc_1V], (instregex "^F(MAX|MIN)(NM)?P_ZPmZZ_[HSD]$")>; def : InstRW<[V2Write_2cyc_1V], (instregex "^F(MAX|MIN)(NM)?P_ZPmZZ_[HSD]$")>;
// Floating point min/max // Floating point min/max
def : InstRW<[V2Write_2cyc_1V], (instregex "^F(MAX|MIN)(NM)?_ZPm[IZ]_[HSD]$", def : InstRW<[V2Write_2cyc_1V], (instregex "^F(MAX|MIN)(NM)?_ZPm[IZ]_[HSD]$",
"^F(MAX|MIN)(NM)?_ZPZ[IZ]_UNDEF_[HSD]$")>; "^F(MAX|MIN)(NM)?_ZPZ[IZ]_[HSD]_UNDEF$")>;
// Floating point multiply // Floating point multiply
def : InstRW<[V2Write_3cyc_1V], (instregex "^(FSCALE|FMULX)_ZPmZ_[HSD]$", def : InstRW<[V2Write_3cyc_1V], (instregex "^(FSCALE|FMULX)_ZPmZ_[HSD]$",
"^FMULX_ZPZZ_UNDEF_[HSD]$", "^FMULX_ZPZZ_[HSD]_UNDEF$",
"^FMUL_(ZPm[IZ]|ZZZI?)_[HSD]$", "^FMUL_(ZPm[IZ]|ZZZI?)_[HSD]$",
"^FMUL_ZPZ[IZ]_UNDEF_[HSD]$")>; "^FMUL_ZPZ[IZ]_[HSD]_UNDEF$")>;
// Floating point multiply accumulate // Floating point multiply accumulate
def : InstRW<[V2Wr_ZFMA, ReadDefault, V2Rd_ZFMA], def : InstRW<[V2Wr_ZFMA, ReadDefault, V2Rd_ZFMA],
(instregex "^FN?ML[AS]_ZPmZZ_[HSD]$", (instregex "^FN?ML[AS]_ZPmZZ_[HSD]$",
"^FN?(MAD|MSB)_ZPmZZ_[HSD]$")>; "^FN?(MAD|MSB)_ZPmZZ_[HSD]$")>;
def : InstRW<[V2Wr_ZFMA, V2Rd_ZFMA], def : InstRW<[V2Wr_ZFMA, V2Rd_ZFMA],
(instregex "^FML[AS]_ZZZI_[HSD]$", (instregex "^FML[AS]_ZZZI_[HSD]$",
"^FN?ML[AS]_ZPZZZ_UNDEF_[HSD]$")>; "^FN?ML[AS]_ZPZZZ_[HSD]_UNDEF$")>;
// Floating point multiply add/sub accumulate long // Floating point multiply add/sub accumulate long
def : InstRW<[V2Wr_ZFMAL, V2Rd_ZFMAL], (instregex "^FML[AS]L[BT]_ZZZI?_SHH$")>; def : InstRW<[V2Wr_ZFMAL, V2Rd_ZFMAL], (instregex "^FML[AS]L[BT]_ZZZI?_SHH$")>;
// Floating point reciprocal estimate, F16 // Floating point reciprocal estimate, F16
def : InstRW<[V2Write_6cyc_4V02], (instrs FRECPE_ZZ_H, FRECPX_ZPmZ_H, def : InstRW<[V2Write_6cyc_4V02], (instrs FRECPE_ZZ_H, FRECPX_ZPmZ_H,
FRSQRTE_ZZ_H, FRECPX_ZPmZ_UNDEF_H)>; FRSQRTE_ZZ_H, FRECPX_ZPmZ_H_UNDEF)>;
// Floating point reciprocal estimate, F32 // Floating point reciprocal estimate, F32
def : InstRW<[V2Write_4cyc_2V02], (instrs FRECPE_ZZ_S, FRECPX_ZPmZ_S, def : InstRW<[V2Write_4cyc_2V02], (instrs FRECPE_ZZ_S, FRECPX_ZPmZ_S,
FRSQRTE_ZZ_S, FRECPX_ZPmZ_UNDEF_S)>; FRSQRTE_ZZ_S, FRECPX_ZPmZ_S_UNDEF)>;
// Floating point reciprocal estimate, F64 // Floating point reciprocal estimate, F64
def : InstRW<[V2Write_3cyc_1V02], (instrs FRECPE_ZZ_D, FRECPX_ZPmZ_D, def : InstRW<[V2Write_3cyc_1V02], (instrs FRECPE_ZZ_D, FRECPX_ZPmZ_D,
FRSQRTE_ZZ_D, FRECPX_ZPmZ_UNDEF_D)>; FRSQRTE_ZZ_D, FRECPX_ZPmZ_D_UNDEF)>;
// Floating point reciprocal step // Floating point reciprocal step
def : InstRW<[V2Write_4cyc_1V], (instregex "^F(RECPS|RSQRTS)_ZZZ_[HSD]$")>; def : InstRW<[V2Write_4cyc_1V], (instregex "^F(RECPS|RSQRTS)_ZZZ_[HSD]$")>;
// Floating point reduction, F16 // Floating point reduction, F16
def : InstRW<[V2Write_8cyc_4V], def : InstRW<[V2Write_8cyc_4V],
(instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_H$")>; (instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_H$")>;
// Floating point reduction, F32 // Floating point reduction, F32
def : InstRW<[V2Write_6cyc_3V], def : InstRW<[V2Write_6cyc_3V],
(instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_S$")>; (instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_S$")>;
// Floating point reduction, F64 // Floating point reduction, F64
def : InstRW<[V2Write_4cyc_2V], def : InstRW<[V2Write_4cyc_2V],
(instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_D$")>; (instregex "^(FADDV|FMAXNMV|FMAXV|FMINNMV|FMINV)_VPZ_D$")>;
// Floating point round to integral, F16 // Floating point round to integral, F16
def : InstRW<[V2Write_6cyc_4V02], (instregex "^FRINT[AIMNPXZ]_ZPmZ(_UNDEF)?_H$")>; def : InstRW<[V2Write_6cyc_4V02], (instregex "^FRINT[AIMNPXZ]_ZPmZ(_UNDEF)?_H$")>;
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// Floating point round to integral, F32 // Floating point round to integral, F32
def : InstRW<[V2Write_4cyc_2V02], (instregex "^FRINT[AIMNPXZ]_ZPmZ(_UNDEF)?_S$")>; def : InstRW<[V2Write_4cyc_2V02], (instregex "^FRINT[AIMNPXZ]_ZPmZ(_UNDEF)?_S$")>;
// Floating point round to integral, F64 // Floating point round to integral, F64
def : InstRW<[V2Write_3cyc_1V02], (instregex "^FRINT[AIMNPXZ]_ZPmZ(_UNDEF)?_D$")>; def : InstRW<[V2Write_3cyc_1V02], (instregex "^FRINT[AIMNPXZ]_ZPmZ(_UNDEF)?_D$")>;
// Floating point square root, F16 // Floating point square root, F16
def : InstRW<[V2Write_13cyc_1V0_12rc], (instrs FSQRT_ZPmZ_H, FSQRT_ZPmZ_UNDEF_H)>; def : InstRW<[V2Write_13cyc_1V0_12rc], (instrs FSQRT_ZPmZ_H, FSQRT_ZPmZ_H_UNDEF)>;
// Floating point square root, F32 // Floating point square root, F32
def : InstRW<[V2Write_10cyc_1V0_9rc], (instrs FSQRT_ZPmZ_S, FSQRT_ZPmZ_UNDEF_S)>; def : InstRW<[V2Write_10cyc_1V0_9rc], (instrs FSQRT_ZPmZ_S, FSQRT_ZPmZ_S_UNDEF)>;
// Floating point square root, F64 // Floating point square root, F64
def : InstRW<[V2Write_16cyc_1V0_14rc], (instrs FSQRT_ZPmZ_D, FSQRT_ZPmZ_UNDEF_D)>; def : InstRW<[V2Write_16cyc_1V0_14rc], (instrs FSQRT_ZPmZ_D, FSQRT_ZPmZ_D_UNDEF)>;
// Floating point trigonometric exponentiation // Floating point trigonometric exponentiation
def : InstRW<[V2Write_3cyc_1V1], (instregex "^FEXPA_ZZ_[HSD]$")>; def : InstRW<[V2Write_3cyc_1V1], (instregex "^FEXPA_ZZ_[HSD]$")>;
// Floating point trigonometric multiply add // Floating point trigonometric multiply add
def : InstRW<[V2Write_4cyc_1V], (instregex "^FTMAD_ZZI_[HSD]$")>; def : InstRW<[V2Write_4cyc_1V], (instregex "^FTMAD_ZZI_[HSD]$")>;
// Floating point trigonometric, miscellaneous // Floating point trigonometric, miscellaneous
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llvm/lib/Target/AArch64/SVEInstrFormats.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,105 Lines • ▼ Show 20 Linesmulticlass sve_fp_2op_p_zds_fscale<bits<4> opc, string asm,
def _D : sve_fp_2op_p_zds<0b11, opc, asm, ZPR64>; def _D : sve_fp_2op_p_zds<0b11, opc, asm, ZPR64>;
def : SVE_3_Op_Pat<nxv8f16, op, nxv8i1, nxv8f16, nxv8i16, !cast<Instruction>(NAME # _H)>; def : SVE_3_Op_Pat<nxv8f16, op, nxv8i1, nxv8f16, nxv8i16, !cast<Instruction>(NAME # _H)>;
def : SVE_3_Op_Pat<nxv4f32, op, nxv4i1, nxv4f32, nxv4i32, !cast<Instruction>(NAME # _S)>; def : SVE_3_Op_Pat<nxv4f32, op, nxv4i1, nxv4f32, nxv4i32, !cast<Instruction>(NAME # _S)>;
def : SVE_3_Op_Pat<nxv2f64, op, nxv2i1, nxv2f64, nxv2i64, !cast<Instruction>(NAME # _D)>; def : SVE_3_Op_Pat<nxv2f64, op, nxv2i1, nxv2f64, nxv2i64, !cast<Instruction>(NAME # _D)>;
} }
multiclass sve_fp_2op_p_zds_zeroing_hsd<SDPatternOperator op> { multiclass sve_fp_2op_p_zds_zeroing_hsd<SDPatternOperator op> {
def _ZERO_H : PredTwoOpPseudo<NAME # _H, ZPR16, FalseLanesZero>; def _H_ZERO : PredTwoOpPseudo<NAME # _H, ZPR16, FalseLanesZero>;
def _ZERO_S : PredTwoOpPseudo<NAME # _S, ZPR32, FalseLanesZero>; def _S_ZERO : PredTwoOpPseudo<NAME # _S, ZPR32, FalseLanesZero>;
def _ZERO_D : PredTwoOpPseudo<NAME # _D, ZPR64, FalseLanesZero>; def _D_ZERO : PredTwoOpPseudo<NAME # _D, ZPR64, FalseLanesZero>;
def : SVE_3_Op_Pat_SelZero<nxv8f16, op, nxv8i1, nxv8f16, nxv8f16, !cast<Pseudo>(NAME # _ZERO_H)>; def : SVE_3_Op_Pat_SelZero<nxv8f16, op, nxv8i1, nxv8f16, nxv8f16, !cast<Pseudo>(NAME # _H_ZERO)>;
def : SVE_3_Op_Pat_SelZero<nxv4f32, op, nxv4i1, nxv4f32, nxv4f32, !cast<Pseudo>(NAME # _ZERO_S)>; def : SVE_3_Op_Pat_SelZero<nxv4f32, op, nxv4i1, nxv4f32, nxv4f32, !cast<Pseudo>(NAME # _S_ZERO)>;
def : SVE_3_Op_Pat_SelZero<nxv2f64, op, nxv2i1, nxv2f64, nxv2f64, !cast<Pseudo>(NAME # _ZERO_D)>; def : SVE_3_Op_Pat_SelZero<nxv2f64, op, nxv2i1, nxv2f64, nxv2f64, !cast<Pseudo>(NAME # _D_ZERO)>;
} }
class sve_fp_ftmad<bits<2> sz, string asm, ZPRRegOp zprty> class sve_fp_ftmad<bits<2> sz, string asm, ZPRRegOp zprty>
: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, timm32_0_7:$imm3), : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, timm32_0_7:$imm3),
asm, "\t$Zdn, $_Zdn, $Zm, $imm3", asm, "\t$Zdn, $_Zdn, $Zm, $imm3",
"", "",
[]>, Sched<[]> { []>, Sched<[]> {
bits<5> Zdn; bits<5> Zdn;
Show All 23 Lines def : Pat<(nxv8f16 (op (nxv8f16 ZPR16:$Zn), (nxv8f16 ZPR16:$Zm), (i32 timm32_0_7:$imm))),
(!cast<Instruction>(NAME # _H) ZPR16:$Zn, ZPR16:$Zm, timm32_0_7:$imm)>; (!cast<Instruction>(NAME # _H) ZPR16:$Zn, ZPR16:$Zm, timm32_0_7:$imm)>;
def : Pat<(nxv4f32 (op (nxv4f32 ZPR32:$Zn), (nxv4f32 ZPR32:$Zm), (i32 timm32_0_7:$imm))), def : Pat<(nxv4f32 (op (nxv4f32 ZPR32:$Zn), (nxv4f32 ZPR32:$Zm), (i32 timm32_0_7:$imm))),
(!cast<Instruction>(NAME # _S) ZPR32:$Zn, ZPR32:$Zm, timm32_0_7:$imm)>; (!cast<Instruction>(NAME # _S) ZPR32:$Zn, ZPR32:$Zm, timm32_0_7:$imm)>;
def : Pat<(nxv2f64 (op (nxv2f64 ZPR64:$Zn), (nxv2f64 ZPR64:$Zm), (i32 timm32_0_7:$imm))), def : Pat<(nxv2f64 (op (nxv2f64 ZPR64:$Zn), (nxv2f64 ZPR64:$Zm), (i32 timm32_0_7:$imm))),
(!cast<Instruction>(NAME # _D) ZPR64:$Zn, ZPR64:$Zm, timm32_0_7:$imm)>; (!cast<Instruction>(NAME # _D) ZPR64:$Zn, ZPR64:$Zm, timm32_0_7:$imm)>;
} }
multiclass sve_fp_2op_i_p_zds_hfd<Operand imm_ty, FPImmLeaf A, FPImmLeaf B, SDPatternOperator ir_op = null_frag> { multiclass sve_fp_2op_i_p_zds_hfd<Operand imm_ty, FPImmLeaf A, FPImmLeaf B, SDPatternOperator ir_op = null_frag> {
def _UNDEF_H : PredTwoOpImmPseudo<NAME # _H, ZPR16, imm_ty, FalseLanesUndef>; def _H_UNDEF : PredTwoOpImmPseudo<NAME # _H, ZPR16, imm_ty, FalseLanesUndef>;
def _UNDEF_S : PredTwoOpImmPseudo<NAME # _S, ZPR32, imm_ty, FalseLanesUndef>; def _S_UNDEF : PredTwoOpImmPseudo<NAME # _S, ZPR32, imm_ty, FalseLanesUndef>;
def _UNDEF_D : PredTwoOpImmPseudo<NAME # _D, ZPR64, imm_ty, FalseLanesUndef>; def _D_UNDEF : PredTwoOpImmPseudo<NAME # _D, ZPR64, imm_ty, FalseLanesUndef>;
def : SVE_2_Op_Fp_Imm_Pat<nxv8f16, ir_op, nxv8i1, f16, A, 0, !cast<Instruction>(NAME # "_UNDEF_H")>; def : SVE_2_Op_Fp_Imm_Pat<nxv8f16, ir_op, nxv8i1, f16, A, 0, !cast<Instruction>(NAME # "_H_UNDEF")>;
def : SVE_2_Op_Fp_Imm_Pat<nxv8f16, ir_op, nxv8i1, f16, B, 1, !cast<Instruction>(NAME # "_UNDEF_H")>; def : SVE_2_Op_Fp_Imm_Pat<nxv8f16, ir_op, nxv8i1, f16, B, 1, !cast<Instruction>(NAME # "_H_UNDEF")>;
def : SVE_2_Op_Fp_Imm_Pat<nxv4f16, ir_op, nxv4i1, f16, A, 0, !cast<Instruction>(NAME # "_UNDEF_H")>; def : SVE_2_Op_Fp_Imm_Pat<nxv4f16, ir_op, nxv4i1, f16, A, 0, !cast<Instruction>(NAME # "_H_UNDEF")>;
def : SVE_2_Op_Fp_Imm_Pat<nxv4f16, ir_op, nxv4i1, f16, B, 1, !cast<Instruction>(NAME # "_UNDEF_H")>; def : SVE_2_Op_Fp_Imm_Pat<nxv4f16, ir_op, nxv4i1, f16, B, 1, !cast<Instruction>(NAME # "_H_UNDEF")>;
def : SVE_2_Op_Fp_Imm_Pat<nxv2f16, ir_op, nxv2i1, f16, A, 0, !cast<Instruction>(NAME # "_UNDEF_H")>; def : SVE_2_Op_Fp_Imm_Pat<nxv2f16, ir_op, nxv2i1, f16, A, 0, !cast<Instruction>(NAME # "_H_UNDEF")>;
def : SVE_2_Op_Fp_Imm_Pat<nxv2f16, ir_op, nxv2i1, f16, B, 1, !cast<Instruction>(NAME # "_UNDEF_H")>; def : SVE_2_Op_Fp_Imm_Pat<nxv2f16, ir_op, nxv2i1, f16, B, 1, !cast<Instruction>(NAME # "_H_UNDEF")>;
def : SVE_2_Op_Fp_Imm_Pat<nxv4f32, ir_op, nxv4i1, f32, A, 0, !cast<Instruction>(NAME # "_UNDEF_S")>; def : SVE_2_Op_Fp_Imm_Pat<nxv4f32, ir_op, nxv4i1, f32, A, 0, !cast<Instruction>(NAME # "_S_UNDEF")>;
def : SVE_2_Op_Fp_Imm_Pat<nxv4f32, ir_op, nxv4i1, f32, B, 1, !cast<Instruction>(NAME # "_UNDEF_S")>; def : SVE_2_Op_Fp_Imm_Pat<nxv4f32, ir_op, nxv4i1, f32, B, 1, !cast<Instruction>(NAME # "_S_UNDEF")>;
def : SVE_2_Op_Fp_Imm_Pat<nxv2f32, ir_op, nxv2i1, f32, A, 0, !cast<Instruction>(NAME # "_UNDEF_S")>; def : SVE_2_Op_Fp_Imm_Pat<nxv2f32, ir_op, nxv2i1, f32, A, 0, !cast<Instruction>(NAME # "_S_UNDEF")>;
def : SVE_2_Op_Fp_Imm_Pat<nxv2f32, ir_op, nxv2i1, f32, B, 1, !cast<Instruction>(NAME # "_UNDEF_S")>; def : SVE_2_Op_Fp_Imm_Pat<nxv2f32, ir_op, nxv2i1, f32, B, 1, !cast<Instruction>(NAME # "_S_UNDEF")>;
def : SVE_2_Op_Fp_Imm_Pat<nxv2f64, ir_op, nxv2i1, f64, A, 0, !cast<Instruction>(NAME # "_UNDEF_D")>; def : SVE_2_Op_Fp_Imm_Pat<nxv2f64, ir_op, nxv2i1, f64, A, 0, !cast<Instruction>(NAME # "_D_UNDEF")>;
def : SVE_2_Op_Fp_Imm_Pat<nxv2f64, ir_op, nxv2i1, f64, B, 1, !cast<Instruction>(NAME # "_UNDEF_D")>; def : SVE_2_Op_Fp_Imm_Pat<nxv2f64, ir_op, nxv2i1, f64, B, 1, !cast<Instruction>(NAME # "_D_UNDEF")>;
} }
multiclass sve_fp_2op_i_p_zds_zeroing_hfd<Operand imm_ty, FPImmLeaf A, FPImmLeaf B, SDPatternOperator op> { multiclass sve_fp_2op_i_p_zds_zeroing_hfd<Operand imm_ty, FPImmLeaf A, FPImmLeaf B, SDPatternOperator op> {
def _ZERO_H : PredTwoOpImmPseudo<NAME # _H, ZPR16, imm_ty, FalseLanesZero>; def _H_ZERO : PredTwoOpImmPseudo<NAME # _H, ZPR16, imm_ty, FalseLanesZero>;
def _ZERO_S : PredTwoOpImmPseudo<NAME # _S, ZPR32, imm_ty, FalseLanesZero>; def _S_ZERO : PredTwoOpImmPseudo<NAME # _S, ZPR32, imm_ty, FalseLanesZero>;
def _ZERO_D : PredTwoOpImmPseudo<NAME # _D, ZPR64, imm_ty, FalseLanesZero>; def _D_ZERO : PredTwoOpImmPseudo<NAME # _D, ZPR64, imm_ty, FalseLanesZero>;
let AddedComplexity = 2 in { let AddedComplexity = 2 in {
def : SVE_2_Op_Fp_Imm_Pat_Zero<nxv8f16, op, nxv8i1, f16, A, 0, !cast<Instruction>(NAME # "_ZERO_H")>; def : SVE_2_Op_Fp_Imm_Pat_Zero<nxv8f16, op, nxv8i1, f16, A, 0, !cast<Instruction>(NAME # "_H_ZERO")>;
def : SVE_2_Op_Fp_Imm_Pat_Zero<nxv8f16, op, nxv8i1, f16, B, 1, !cast<Instruction>(NAME # "_ZERO_H")>; def : SVE_2_Op_Fp_Imm_Pat_Zero<nxv8f16, op, nxv8i1, f16, B, 1, !cast<Instruction>(NAME # "_H_ZERO")>;
def : SVE_2_Op_Fp_Imm_Pat_Zero<nxv4f32, op, nxv4i1, f32, A, 0, !cast<Instruction>(NAME # "_ZERO_S")>; def : SVE_2_Op_Fp_Imm_Pat_Zero<nxv4f32, op, nxv4i1, f32, A, 0, !cast<Instruction>(NAME # "_S_ZERO")>;
def : SVE_2_Op_Fp_Imm_Pat_Zero<nxv4f32, op, nxv4i1, f32, B, 1, !cast<Instruction>(NAME # "_ZERO_S")>; def : SVE_2_Op_Fp_Imm_Pat_Zero<nxv4f32, op, nxv4i1, f32, B, 1, !cast<Instruction>(NAME # "_S_ZERO")>;
def : SVE_2_Op_Fp_Imm_Pat_Zero<nxv2f64, op, nxv2i1, f64, A, 0, !cast<Instruction>(NAME # "_ZERO_D")>; def : SVE_2_Op_Fp_Imm_Pat_Zero<nxv2f64, op, nxv2i1, f64, A, 0, !cast<Instruction>(NAME # "_D_ZERO")>;
def : SVE_2_Op_Fp_Imm_Pat_Zero<nxv2f64, op, nxv2i1, f64, B, 1, !cast<Instruction>(NAME # "_ZERO_D")>; def : SVE_2_Op_Fp_Imm_Pat_Zero<nxv2f64, op, nxv2i1, f64, B, 1, !cast<Instruction>(NAME # "_D_ZERO")>;
} }
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SVE Floating Point Arithmetic - Unpredicated Group // SVE Floating Point Arithmetic - Unpredicated Group
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class sve_fp_3op_u_zd<bits<2> sz, bits<3> opc, string asm, ZPRRegOp zprty> class sve_fp_3op_u_zd<bits<2> sz, bits<3> opc, string asm, ZPRRegOp zprty>
▲ Show 20 Lines • Show All 732 Lines • ▼ Show 20 Linesmulticlass sve_fp_2op_p_zd_HSD<bits<5> opc, string asm, SDPatternOperator op> {
def : SVE_1_Op_Passthru_Pat<nxv8f16, op, nxv8i1, nxv8f16, !cast<Instruction>(NAME # _H)>; def : SVE_1_Op_Passthru_Pat<nxv8f16, op, nxv8i1, nxv8f16, !cast<Instruction>(NAME # _H)>;
def : SVE_1_Op_Passthru_Pat<nxv4f16, op, nxv4i1, nxv4f16, !cast<Instruction>(NAME # _H)>; def : SVE_1_Op_Passthru_Pat<nxv4f16, op, nxv4i1, nxv4f16, !cast<Instruction>(NAME # _H)>;
def : SVE_1_Op_Passthru_Pat<nxv2f16, op, nxv2i1, nxv2f16, !cast<Instruction>(NAME # _H)>; def : SVE_1_Op_Passthru_Pat<nxv2f16, op, nxv2i1, nxv2f16, !cast<Instruction>(NAME # _H)>;
def : SVE_1_Op_Passthru_Pat<nxv4f32, op, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S)>; def : SVE_1_Op_Passthru_Pat<nxv4f32, op, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S)>;
def : SVE_1_Op_Passthru_Pat<nxv2f32, op, nxv2i1, nxv2f32, !cast<Instruction>(NAME # _S)>; def : SVE_1_Op_Passthru_Pat<nxv2f32, op, nxv2i1, nxv2f32, !cast<Instruction>(NAME # _S)>;
def : SVE_1_Op_Passthru_Pat<nxv2f64, op, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>; def : SVE_1_Op_Passthru_Pat<nxv2f64, op, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>;
def _UNDEF_H : PredOneOpPassthruPseudo<NAME # _H, ZPR16>; def _H_UNDEF : PredOneOpPassthruPseudo<NAME # _H, ZPR16>;
def _UNDEF_S : PredOneOpPassthruPseudo<NAME # _S, ZPR32>; def _S_UNDEF : PredOneOpPassthruPseudo<NAME # _S, ZPR32>;
def _UNDEF_D : PredOneOpPassthruPseudo<NAME # _D, ZPR64>; def _D_UNDEF : PredOneOpPassthruPseudo<NAME # _D, ZPR64>;
defm : SVE_1_Op_PassthruUndef_Pat<nxv8f16, op, nxv8i1, nxv8f16, !cast<Instruction>(NAME # _UNDEF_H)>; defm : SVE_1_Op_PassthruUndef_Pat<nxv8f16, op, nxv8i1, nxv8f16, !cast<Instruction>(NAME # _H_UNDEF)>;
defm : SVE_1_Op_PassthruUndef_Pat<nxv4f16, op, nxv4i1, nxv4f16, !cast<Instruction>(NAME # _UNDEF_H)>; defm : SVE_1_Op_PassthruUndef_Pat<nxv4f16, op, nxv4i1, nxv4f16, !cast<Instruction>(NAME # _H_UNDEF)>;
defm : SVE_1_Op_PassthruUndef_Pat<nxv2f16, op, nxv2i1, nxv2f16, !cast<Instruction>(NAME # _UNDEF_H)>; defm : SVE_1_Op_PassthruUndef_Pat<nxv2f16, op, nxv2i1, nxv2f16, !cast<Instruction>(NAME # _H_UNDEF)>;
defm : SVE_1_Op_PassthruUndef_Pat<nxv4f32, op, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _UNDEF_S)>; defm : SVE_1_Op_PassthruUndef_Pat<nxv4f32, op, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S_UNDEF)>;
defm : SVE_1_Op_PassthruUndef_Pat<nxv2f32, op, nxv2i1, nxv2f32, !cast<Instruction>(NAME # _UNDEF_S)>; defm : SVE_1_Op_PassthruUndef_Pat<nxv2f32, op, nxv2i1, nxv2f32, !cast<Instruction>(NAME # _S_UNDEF)>;
defm : SVE_1_Op_PassthruUndef_Pat<nxv2f64, op, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _UNDEF_D)>; defm : SVE_1_Op_PassthruUndef_Pat<nxv2f64, op, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D_UNDEF)>;
} }
multiclass sve2_fp_flogb<string asm, string Ps, SDPatternOperator op> { multiclass sve2_fp_flogb<string asm, string Ps, SDPatternOperator op> {
def _H : sve_fp_2op_p_zd<0b0011010, asm, ZPR16, ZPR16, ElementSizeH>, def _H : sve_fp_2op_p_zd<0b0011010, asm, ZPR16, ZPR16, ElementSizeH>,
SVEPseudo2Instr<Ps # _H, 1>; SVEPseudo2Instr<Ps # _H, 1>;
def _S : sve_fp_2op_p_zd<0b0011100, asm, ZPR32, ZPR32, ElementSizeS>, def _S : sve_fp_2op_p_zd<0b0011100, asm, ZPR32, ZPR32, ElementSizeS>,
SVEPseudo2Instr<Ps # _S, 1>; SVEPseudo2Instr<Ps # _S, 1>;
def _D : sve_fp_2op_p_zd<0b0011110, asm, ZPR64, ZPR64, ElementSizeD>, def _D : sve_fp_2op_p_zd<0b0011110, asm, ZPR64, ZPR64, ElementSizeD>,
SVEPseudo2Instr<Ps # _D, 1>; SVEPseudo2Instr<Ps # _D, 1>;
def : SVE_3_Op_Pat<nxv8i16, op, nxv8i16, nxv8i1, nxv8f16, !cast<Instruction>(NAME # _H)>; def : SVE_3_Op_Pat<nxv8i16, op, nxv8i16, nxv8i1, nxv8f16, !cast<Instruction>(NAME # _H)>;
def : SVE_3_Op_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S)>; def : SVE_3_Op_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S)>;
def : SVE_3_Op_Pat<nxv2i64, op, nxv2i64, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>; def : SVE_3_Op_Pat<nxv2i64, op, nxv2i64, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>;
} }
multiclass sve2_fp_un_pred_zeroing_hsd<SDPatternOperator op> { multiclass sve2_fp_un_pred_zeroing_hsd<SDPatternOperator op> {
def _ZERO_H : PredOneOpPassthruPseudo<NAME # _H, ZPR16, FalseLanesZero>; def _H_ZERO : PredOneOpPassthruPseudo<NAME # _H, ZPR16, FalseLanesZero>;
def _ZERO_S : PredOneOpPassthruPseudo<NAME # _S, ZPR32, FalseLanesZero>; def _S_ZERO : PredOneOpPassthruPseudo<NAME # _S, ZPR32, FalseLanesZero>;
def _ZERO_D : PredOneOpPassthruPseudo<NAME # _D, ZPR64, FalseLanesZero>; def _D_ZERO : PredOneOpPassthruPseudo<NAME # _D, ZPR64, FalseLanesZero>;
def : SVE_1_Op_PassthruZero_Pat<nxv8i16, op, nxv8i1, nxv8f16, !cast<Pseudo>(NAME # _ZERO_H)>; def : SVE_1_Op_PassthruZero_Pat<nxv8i16, op, nxv8i1, nxv8f16, !cast<Pseudo>(NAME # _H_ZERO)>;
def : SVE_1_Op_PassthruZero_Pat<nxv4i32, op, nxv4i1, nxv4f32, !cast<Pseudo>(NAME # _ZERO_S)>; def : SVE_1_Op_PassthruZero_Pat<nxv4i32, op, nxv4i1, nxv4f32, !cast<Pseudo>(NAME # _S_ZERO)>;
def : SVE_1_Op_PassthruZero_Pat<nxv2i64, op, nxv2i1, nxv2f64, !cast<Pseudo>(NAME # _ZERO_D)>; def : SVE_1_Op_PassthruZero_Pat<nxv2i64, op, nxv2i1, nxv2f64, !cast<Pseudo>(NAME # _D_ZERO)>;
} }
multiclass sve2_fp_convert_down_odd_rounding<string asm, string op> { multiclass sve2_fp_convert_down_odd_rounding<string asm, string op> {
def _DtoS : sve_fp_2op_p_zd<0b0001010, asm, ZPR64, ZPR32, ElementSizeD>; def _DtoS : sve_fp_2op_p_zd<0b0001010, asm, ZPR64, ZPR32, ElementSizeD>;
def : SVE_3_Op_Pat<nxv4f32, !cast<SDPatternOperator>(op # _f32f64), nxv4f32, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _DtoS)>; def : SVE_3_Op_Pat<nxv4f32, !cast<SDPatternOperator>(op # _f32f64), nxv4f32, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _DtoS)>;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 241 Lines • ▼ Show 20 Linesmulticlass sve_int_mlas_vvv_pred<bits<1> opc, string asm, SDPatternOperator op,
def : SVE_4_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>; def : SVE_4_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
def : SVE_4_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>; def : SVE_4_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
def : SVE_4_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>; def : SVE_4_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
def : SVE_4_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>; def : SVE_4_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
} }
//class for generating pseudo for SVE MLA/MAD/MLS/MSB //class for generating pseudo for SVE MLA/MAD/MLS/MSB
multiclass sve_int_3op_p_mladdsub<SDPatternOperator op> { multiclass sve_int_3op_p_mladdsub<SDPatternOperator op> {
def _UNDEF_B : PredThreeOpPseudo<NAME # _B, ZPR8, FalseLanesUndef>; def _B_UNDEF : PredThreeOpPseudo<NAME # _B, ZPR8, FalseLanesUndef>;
def _UNDEF_H : PredThreeOpPseudo<NAME # _H, ZPR16, FalseLanesUndef>; def _H_UNDEF : PredThreeOpPseudo<NAME # _H, ZPR16, FalseLanesUndef>;
def _UNDEF_S : PredThreeOpPseudo<NAME # _S, ZPR32, FalseLanesUndef>; def _S_UNDEF : PredThreeOpPseudo<NAME # _S, ZPR32, FalseLanesUndef>;
def _UNDEF_D : PredThreeOpPseudo<NAME # _D, ZPR64, FalseLanesUndef>; def _D_UNDEF : PredThreeOpPseudo<NAME # _D, ZPR64, FalseLanesUndef>;
let AddedComplexity = 9 in { let AddedComplexity = 9 in {
def : SVE_4_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _UNDEF_B)>; def : SVE_4_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B_UNDEF)>;
def : SVE_4_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _UNDEF_H)>; def : SVE_4_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H_UNDEF)>;
def : SVE_4_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _UNDEF_S)>; def : SVE_4_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S_UNDEF)>;
def : SVE_4_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _UNDEF_D)>; def : SVE_4_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D_UNDEF)>;
} }
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SVE2 Integer Multiply-Add - Unpredicated Group // SVE2 Integer Multiply-Add - Unpredicated Group
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class sve2_int_mla<bits<2> sz, bits<5> opc, string asm, class sve2_int_mla<bits<2> sz, bits<5> opc, string asm,
▲ Show 20 Lines • Show All 554 Lines • ▼ Show 20 Lines
multiclass sve2_int_un_pred_arit_s<bits<3> opc, string asm, multiclass sve2_int_un_pred_arit_s<bits<3> opc, string asm,
SDPatternOperator op> { SDPatternOperator op> {
def _S : sve2_int_un_pred_arit<0b10, opc{2}, opc{1-0}, asm, ZPR32>, def _S : sve2_int_un_pred_arit<0b10, opc{2}, opc{1-0}, asm, ZPR32>,
SVEPseudo2Instr<NAME # _S, 1>; SVEPseudo2Instr<NAME # _S, 1>;
def : SVE_3_Op_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>; def : SVE_3_Op_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
def _UNDEF_S : PredOneOpPassthruPseudo<NAME # _S, ZPR32>; def _S_UNDEF : PredOneOpPassthruPseudo<NAME # _S, ZPR32>;
defm : SVE_3_Op_Undef_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4i32, !cast<Pseudo>(NAME # _UNDEF_S)>; defm : SVE_3_Op_Undef_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4i32, !cast<Pseudo>(NAME # _S_UNDEF)>;
} }
multiclass sve2_int_un_pred_arit<bits<3> opc, string asm, SDPatternOperator op> { multiclass sve2_int_un_pred_arit<bits<3> opc, string asm, SDPatternOperator op> {
def _B : sve2_int_un_pred_arit<0b00, opc{2}, opc{1-0}, asm, ZPR8>, def _B : sve2_int_un_pred_arit<0b00, opc{2}, opc{1-0}, asm, ZPR8>,
SVEPseudo2Instr<NAME # _B, 1>; SVEPseudo2Instr<NAME # _B, 1>;
def _H : sve2_int_un_pred_arit<0b01, opc{2}, opc{1-0}, asm, ZPR16>, def _H : sve2_int_un_pred_arit<0b01, opc{2}, opc{1-0}, asm, ZPR16>,
SVEPseudo2Instr<NAME # _H, 1>; SVEPseudo2Instr<NAME # _H, 1>;
def _S : sve2_int_un_pred_arit<0b10, opc{2}, opc{1-0}, asm, ZPR32>, def _S : sve2_int_un_pred_arit<0b10, opc{2}, opc{1-0}, asm, ZPR32>,
SVEPseudo2Instr<NAME # _S, 1>; SVEPseudo2Instr<NAME # _S, 1>;
def _D : sve2_int_un_pred_arit<0b11, opc{2}, opc{1-0}, asm, ZPR64>, def _D : sve2_int_un_pred_arit<0b11, opc{2}, opc{1-0}, asm, ZPR64>,
SVEPseudo2Instr<NAME # _D, 1>; SVEPseudo2Instr<NAME # _D, 1>;
def : SVE_3_Op_Pat<nxv16i8, op, nxv16i8, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>; def : SVE_3_Op_Pat<nxv16i8, op, nxv16i8, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>;
def : SVE_3_Op_Pat<nxv8i16, op, nxv8i16, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H)>; def : SVE_3_Op_Pat<nxv8i16, op, nxv8i16, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H)>;
def : SVE_3_Op_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>; def : SVE_3_Op_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
def : SVE_3_Op_Pat<nxv2i64, op, nxv2i64, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>; def : SVE_3_Op_Pat<nxv2i64, op, nxv2i64, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
def _UNDEF_B : PredOneOpPassthruPseudo<NAME # _B, ZPR8>; def _B_UNDEF : PredOneOpPassthruPseudo<NAME # _B, ZPR8>;
def _UNDEF_H : PredOneOpPassthruPseudo<NAME # _H, ZPR16>; def _H_UNDEF : PredOneOpPassthruPseudo<NAME # _H, ZPR16>;
def _UNDEF_S : PredOneOpPassthruPseudo<NAME # _S, ZPR32>; def _S_UNDEF : PredOneOpPassthruPseudo<NAME # _S, ZPR32>;
def _UNDEF_D : PredOneOpPassthruPseudo<NAME # _D, ZPR64>; def _D_UNDEF : PredOneOpPassthruPseudo<NAME # _D, ZPR64>;
defm : SVE_3_Op_Undef_Pat<nxv16i8, op, nxv16i8, nxv16i1, nxv16i8, !cast<Pseudo>(NAME # _UNDEF_B)>; defm : SVE_3_Op_Undef_Pat<nxv16i8, op, nxv16i8, nxv16i1, nxv16i8, !cast<Pseudo>(NAME # _B_UNDEF)>;
defm : SVE_3_Op_Undef_Pat<nxv8i16, op, nxv8i16, nxv8i1, nxv8i16, !cast<Pseudo>(NAME # _UNDEF_H)>; defm : SVE_3_Op_Undef_Pat<nxv8i16, op, nxv8i16, nxv8i1, nxv8i16, !cast<Pseudo>(NAME # _H_UNDEF)>;
defm : SVE_3_Op_Undef_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4i32, !cast<Pseudo>(NAME # _UNDEF_S)>; defm : SVE_3_Op_Undef_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4i32, !cast<Pseudo>(NAME # _S_UNDEF)>;
defm : SVE_3_Op_Undef_Pat<nxv2i64, op, nxv2i64, nxv2i1, nxv2i64, !cast<Pseudo>(NAME # _UNDEF_D)>; defm : SVE_3_Op_Undef_Pat<nxv2i64, op, nxv2i64, nxv2i1, nxv2i64, !cast<Pseudo>(NAME # _D_UNDEF)>;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SVE2 Widening Integer Arithmetic Group // SVE2 Widening Integer Arithmetic Group
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class sve2_wide_int_arith<bits<2> sz, bits<5> opc, string asm, class sve2_wide_int_arith<bits<2> sz, bits<5> opc, string asm,
ZPRRegOp zprty1, ZPRRegOp zprty2, ZPRRegOp zprty3> ZPRRegOp zprty1, ZPRRegOp zprty2, ZPRRegOp zprty3>
▲ Show 20 Lines • Show All 631 Lines • ▼ Show 20 Linesmulticlass sve_int_un_pred_arit_0<bits<3> opc, string asm,
def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>, def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>,
SVEPseudo2Instr<NAME # _D, 1>; SVEPseudo2Instr<NAME # _D, 1>;
def : SVE_1_Op_Passthru_Pat<nxv16i8, op, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>; def : SVE_1_Op_Passthru_Pat<nxv16i8, op, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>;
def : SVE_1_Op_Passthru_Pat<nxv8i16, op, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H)>; def : SVE_1_Op_Passthru_Pat<nxv8i16, op, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H)>;
def : SVE_1_Op_Passthru_Pat<nxv4i32, op, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>; def : SVE_1_Op_Passthru_Pat<nxv4i32, op, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
def : SVE_1_Op_Passthru_Pat<nxv2i64, op, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>; def : SVE_1_Op_Passthru_Pat<nxv2i64, op, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
def _UNDEF_B : PredOneOpPassthruPseudo<NAME # _B, ZPR8>; def _B_UNDEF : PredOneOpPassthruPseudo<NAME # _B, ZPR8>;
def _UNDEF_H : PredOneOpPassthruPseudo<NAME # _H, ZPR16>; def _H_UNDEF : PredOneOpPassthruPseudo<NAME # _H, ZPR16>;
def _UNDEF_S : PredOneOpPassthruPseudo<NAME # _S, ZPR32>; def _S_UNDEF : PredOneOpPassthruPseudo<NAME # _S, ZPR32>;
def _UNDEF_D : PredOneOpPassthruPseudo<NAME # _D, ZPR64>; def _D_UNDEF : PredOneOpPassthruPseudo<NAME # _D, ZPR64>;
defm : SVE_1_Op_PassthruUndef_Pat<nxv16i8, op, nxv16i1, nxv16i8, !cast<Pseudo>(NAME # _UNDEF_B)>; defm : SVE_1_Op_PassthruUndef_Pat<nxv16i8, op, nxv16i1, nxv16i8, !cast<Pseudo>(NAME # _B_UNDEF)>;
defm : SVE_1_Op_PassthruUndef_Pat<nxv8i16, op, nxv8i1, nxv8i16, !cast<Pseudo>(NAME # _UNDEF_H)>; defm : SVE_1_Op_PassthruUndef_Pat<nxv8i16, op, nxv8i1, nxv8i16, !cast<Pseudo>(NAME # _H_UNDEF)>;
defm : SVE_1_Op_PassthruUndef_Pat<nxv4i32, op, nxv4i1, nxv4i32, !cast<Pseudo>(NAME # _UNDEF_S)>; defm : SVE_1_Op_PassthruUndef_Pat<nxv4i32, op, nxv4i1, nxv4i32, !cast<Pseudo>(NAME # _S_UNDEF)>;
defm : SVE_1_Op_PassthruUndef_Pat<nxv2i64, op, nxv2i1, nxv2i64, !cast<Pseudo>(NAME # _UNDEF_D)>; defm : SVE_1_Op_PassthruUndef_Pat<nxv2i64, op, nxv2i1, nxv2i64, !cast<Pseudo>(NAME # _D_UNDEF)>;
} }
multiclass sve_int_un_pred_arit_0_h<bits<3> opc, string asm, multiclass sve_int_un_pred_arit_0_h<bits<3> opc, string asm,
SDPatternOperator op> { SDPatternOperator op> {
def _H : sve_int_un_pred_arit<0b01, { opc, 0b0 }, asm, ZPR16>, def _H : sve_int_un_pred_arit<0b01, { opc, 0b0 }, asm, ZPR16>,
SVEPseudo2Instr<NAME # _H, 1>; SVEPseudo2Instr<NAME # _H, 1>;
def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>, def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>,
SVEPseudo2Instr<NAME # _S, 1>; SVEPseudo2Instr<NAME # _S, 1>;
def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>, def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>,
SVEPseudo2Instr<NAME # _D, 1>; SVEPseudo2Instr<NAME # _D, 1>;
def : SVE_InReg_Extend<nxv8i16, op, nxv8i1, nxv8i8, !cast<Instruction>(NAME # _H)>; def : SVE_InReg_Extend<nxv8i16, op, nxv8i1, nxv8i8, !cast<Instruction>(NAME # _H)>;
def : SVE_InReg_Extend<nxv4i32, op, nxv4i1, nxv4i8, !cast<Instruction>(NAME # _S)>; def : SVE_InReg_Extend<nxv4i32, op, nxv4i1, nxv4i8, !cast<Instruction>(NAME # _S)>;
def : SVE_InReg_Extend<nxv2i64, op, nxv2i1, nxv2i8, !cast<Instruction>(NAME # _D)>; def : SVE_InReg_Extend<nxv2i64, op, nxv2i1, nxv2i8, !cast<Instruction>(NAME # _D)>;
def _UNDEF_H : PredOneOpPassthruPseudo<NAME # _H, ZPR16>; def _H_UNDEF : PredOneOpPassthruPseudo<NAME # _H, ZPR16>;
def _UNDEF_S : PredOneOpPassthruPseudo<NAME # _S, ZPR32>; def _S_UNDEF : PredOneOpPassthruPseudo<NAME # _S, ZPR32>;
def _UNDEF_D : PredOneOpPassthruPseudo<NAME # _D, ZPR64>; def _D_UNDEF : PredOneOpPassthruPseudo<NAME # _D, ZPR64>;
defm : SVE_InReg_Extend_PassthruUndef<nxv8i16, op, nxv8i1, nxv8i8, !cast<Pseudo>(NAME # _UNDEF_H)>; defm : SVE_InReg_Extend_PassthruUndef<nxv8i16, op, nxv8i1, nxv8i8, !cast<Pseudo>(NAME # _H_UNDEF)>;
defm : SVE_InReg_Extend_PassthruUndef<nxv4i32, op, nxv4i1, nxv4i8, !cast<Pseudo>(NAME # _UNDEF_S)>; defm : SVE_InReg_Extend_PassthruUndef<nxv4i32, op, nxv4i1, nxv4i8, !cast<Pseudo>(NAME # _S_UNDEF)>;
defm : SVE_InReg_Extend_PassthruUndef<nxv2i64, op, nxv2i1, nxv2i8, !cast<Pseudo>(NAME # _UNDEF_D)>; defm : SVE_InReg_Extend_PassthruUndef<nxv2i64, op, nxv2i1, nxv2i8, !cast<Pseudo>(NAME # _D_UNDEF)>;
} }
multiclass sve_int_un_pred_arit_0_w<bits<3> opc, string asm, multiclass sve_int_un_pred_arit_0_w<bits<3> opc, string asm,
SDPatternOperator op> { SDPatternOperator op> {
def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>, def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>,
SVEPseudo2Instr<NAME # _S, 1>; SVEPseudo2Instr<NAME # _S, 1>;
def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>, def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>,
SVEPseudo2Instr<NAME # _D, 1>; SVEPseudo2Instr<NAME # _D, 1>;
def : SVE_InReg_Extend<nxv4i32, op, nxv4i1, nxv4i16, !cast<Instruction>(NAME # _S)>; def : SVE_InReg_Extend<nxv4i32, op, nxv4i1, nxv4i16, !cast<Instruction>(NAME # _S)>;
def : SVE_InReg_Extend<nxv2i64, op, nxv2i1, nxv2i16, !cast<Instruction>(NAME # _D)>; def : SVE_InReg_Extend<nxv2i64, op, nxv2i1, nxv2i16, !cast<Instruction>(NAME # _D)>;
def _UNDEF_S : PredOneOpPassthruPseudo<NAME # _S, ZPR32>; def _S_UNDEF : PredOneOpPassthruPseudo<NAME # _S, ZPR32>;
def _UNDEF_D : PredOneOpPassthruPseudo<NAME # _D, ZPR64>; def _D_UNDEF : PredOneOpPassthruPseudo<NAME # _D, ZPR64>;
defm : SVE_InReg_Extend_PassthruUndef<nxv4i32, op, nxv4i1, nxv4i16, !cast<Pseudo>(NAME # _UNDEF_S)>; defm : SVE_InReg_Extend_PassthruUndef<nxv4i32, op, nxv4i1, nxv4i16, !cast<Pseudo>(NAME # _S_UNDEF)>;
defm : SVE_InReg_Extend_PassthruUndef<nxv2i64, op, nxv2i1, nxv2i16, !cast<Pseudo>(NAME # _UNDEF_D)>; defm : SVE_InReg_Extend_PassthruUndef<nxv2i64, op, nxv2i1, nxv2i16, !cast<Pseudo>(NAME # _D_UNDEF)>;
} }
multiclass sve_int_un_pred_arit_0_d<bits<3> opc, string asm, multiclass sve_int_un_pred_arit_0_d<bits<3> opc, string asm,
SDPatternOperator op> { SDPatternOperator op> {
def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>, def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>,
SVEPseudo2Instr<NAME # _D, 1>; SVEPseudo2Instr<NAME # _D, 1>;
def : SVE_InReg_Extend<nxv2i64, op, nxv2i1, nxv2i32, !cast<Instruction>(NAME # _D)>; def : SVE_InReg_Extend<nxv2i64, op, nxv2i1, nxv2i32, !cast<Instruction>(NAME # _D)>;
def _UNDEF_D : PredOneOpPassthruPseudo<NAME # _D, ZPR64>; def _D_UNDEF : PredOneOpPassthruPseudo<NAME # _D, ZPR64>;
defm : SVE_InReg_Extend_PassthruUndef<nxv2i64, op, nxv2i1, nxv2i32, !cast<Pseudo>(NAME # _UNDEF_D)>; defm : SVE_InReg_Extend_PassthruUndef<nxv2i64, op, nxv2i1, nxv2i32, !cast<Pseudo>(NAME # _D_UNDEF)>;
} }
multiclass sve_int_un_pred_arit_1<bits<3> opc, string asm, multiclass sve_int_un_pred_arit_1<bits<3> opc, string asm,
SDPatternOperator op> { SDPatternOperator op> {
def _B : sve_int_un_pred_arit<0b00, { opc, 0b1 }, asm, ZPR8>, def _B : sve_int_un_pred_arit<0b00, { opc, 0b1 }, asm, ZPR8>,
SVEPseudo2Instr<NAME # _B, 1>; SVEPseudo2Instr<NAME # _B, 1>;
def _H : sve_int_un_pred_arit<0b01, { opc, 0b1 }, asm, ZPR16>, def _H : sve_int_un_pred_arit<0b01, { opc, 0b1 }, asm, ZPR16>,
SVEPseudo2Instr<NAME # _H, 1>; SVEPseudo2Instr<NAME # _H, 1>;
def _S : sve_int_un_pred_arit<0b10, { opc, 0b1 }, asm, ZPR32>, def _S : sve_int_un_pred_arit<0b10, { opc, 0b1 }, asm, ZPR32>,
SVEPseudo2Instr<NAME # _S, 1>; SVEPseudo2Instr<NAME # _S, 1>;
def _D : sve_int_un_pred_arit<0b11, { opc, 0b1 }, asm, ZPR64>, def _D : sve_int_un_pred_arit<0b11, { opc, 0b1 }, asm, ZPR64>,
SVEPseudo2Instr<NAME # _D, 1>; SVEPseudo2Instr<NAME # _D, 1>;
def : SVE_1_Op_Passthru_Pat<nxv16i8, op, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>; def : SVE_1_Op_Passthru_Pat<nxv16i8, op, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>;
def : SVE_1_Op_Passthru_Pat<nxv8i16, op, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H)>; def : SVE_1_Op_Passthru_Pat<nxv8i16, op, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H)>;
def : SVE_1_Op_Passthru_Pat<nxv4i32, op, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>; def : SVE_1_Op_Passthru_Pat<nxv4i32, op, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
def : SVE_1_Op_Passthru_Pat<nxv2i64, op, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>; def : SVE_1_Op_Passthru_Pat<nxv2i64, op, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
def _UNDEF_B : PredOneOpPassthruPseudo<NAME # _B, ZPR8>; def _B_UNDEF : PredOneOpPassthruPseudo<NAME # _B, ZPR8>;
def _UNDEF_H : PredOneOpPassthruPseudo<NAME # _H, ZPR16>; def _H_UNDEF : PredOneOpPassthruPseudo<NAME # _H, ZPR16>;
def _UNDEF_S : PredOneOpPassthruPseudo<NAME # _S, ZPR32>; def _S_UNDEF : PredOneOpPassthruPseudo<NAME # _S, ZPR32>;
def _UNDEF_D : PredOneOpPassthruPseudo<NAME # _D, ZPR64>; def _D_UNDEF : PredOneOpPassthruPseudo<NAME # _D, ZPR64>;
defm : SVE_1_Op_PassthruUndef_Pat<nxv16i8, op, nxv16i1, nxv16i8, !cast<Pseudo>(NAME # _UNDEF_B)>; defm : SVE_1_Op_PassthruUndef_Pat<nxv16i8, op, nxv16i1, nxv16i8, !cast<Pseudo>(NAME # _B_UNDEF)>;
defm : SVE_1_Op_PassthruUndef_Pat<nxv8i16, op, nxv8i1, nxv8i16, !cast<Pseudo>(NAME # _UNDEF_H)>; defm : SVE_1_Op_PassthruUndef_Pat<nxv8i16, op, nxv8i1, nxv8i16, !cast<Pseudo>(NAME # _H_UNDEF)>;
defm : SVE_1_Op_PassthruUndef_Pat<nxv4i32, op, nxv4i1, nxv4i32, !cast<Pseudo>(NAME # _UNDEF_S)>; defm : SVE_1_Op_PassthruUndef_Pat<nxv4i32, op, nxv4i1, nxv4i32, !cast<Pseudo>(NAME # _S_UNDEF)>;
defm : SVE_1_Op_PassthruUndef_Pat<nxv2i64, op, nxv2i1, nxv2i64, !cast<Pseudo>(NAME # _UNDEF_D)>; defm : SVE_1_Op_PassthruUndef_Pat<nxv2i64, op, nxv2i1, nxv2i64, !cast<Pseudo>(NAME # _D_UNDEF)>;
} }
multiclass sve_int_un_pred_arit_1_fp<bits<3> opc, string asm, SDPatternOperator op> { multiclass sve_int_un_pred_arit_1_fp<bits<3> opc, string asm, SDPatternOperator op> {
def _H : sve_int_un_pred_arit<0b01, { opc, 0b1 }, asm, ZPR16>, def _H : sve_int_un_pred_arit<0b01, { opc, 0b1 }, asm, ZPR16>,
SVEPseudo2Instr<NAME # _H, 1>; SVEPseudo2Instr<NAME # _H, 1>;
def _S : sve_int_un_pred_arit<0b10, { opc, 0b1 }, asm, ZPR32>, def _S : sve_int_un_pred_arit<0b10, { opc, 0b1 }, asm, ZPR32>,
SVEPseudo2Instr<NAME # _S, 1>; SVEPseudo2Instr<NAME # _S, 1>;
def _D : sve_int_un_pred_arit<0b11, { opc, 0b1 }, asm, ZPR64>, def _D : sve_int_un_pred_arit<0b11, { opc, 0b1 }, asm, ZPR64>,
SVEPseudo2Instr<NAME # _D, 1>; SVEPseudo2Instr<NAME # _D, 1>;
def : SVE_1_Op_Passthru_Pat<nxv8f16, op, nxv8i1, nxv8f16, !cast<Instruction>(NAME # _H)>; def : SVE_1_Op_Passthru_Pat<nxv8f16, op, nxv8i1, nxv8f16, !cast<Instruction>(NAME # _H)>;
def : SVE_1_Op_Passthru_Pat<nxv4f16, op, nxv4i1, nxv4f16, !cast<Instruction>(NAME # _H)>; def : SVE_1_Op_Passthru_Pat<nxv4f16, op, nxv4i1, nxv4f16, !cast<Instruction>(NAME # _H)>;
def : SVE_1_Op_Passthru_Pat<nxv2f16, op, nxv2i1, nxv2f16, !cast<Instruction>(NAME # _H)>; def : SVE_1_Op_Passthru_Pat<nxv2f16, op, nxv2i1, nxv2f16, !cast<Instruction>(NAME # _H)>;
def : SVE_1_Op_Passthru_Pat<nxv4f32, op, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S)>; def : SVE_1_Op_Passthru_Pat<nxv4f32, op, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S)>;
def : SVE_1_Op_Passthru_Pat<nxv2f32, op, nxv2i1, nxv2f32, !cast<Instruction>(NAME # _S)>; def : SVE_1_Op_Passthru_Pat<nxv2f32, op, nxv2i1, nxv2f32, !cast<Instruction>(NAME # _S)>;
def : SVE_1_Op_Passthru_Pat<nxv2f64, op, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>; def : SVE_1_Op_Passthru_Pat<nxv2f64, op, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>;
def _UNDEF_H : PredOneOpPassthruPseudo<NAME # _H, ZPR16>; def _H_UNDEF : PredOneOpPassthruPseudo<NAME # _H, ZPR16>;
def _UNDEF_S : PredOneOpPassthruPseudo<NAME # _S, ZPR32>; def _S_UNDEF : PredOneOpPassthruPseudo<NAME # _S, ZPR32>;
def _UNDEF_D : PredOneOpPassthruPseudo<NAME # _D, ZPR64>; def _D_UNDEF : PredOneOpPassthruPseudo<NAME # _D, ZPR64>;
defm : SVE_1_Op_PassthruUndef_Pat<nxv8f16, op, nxv8i1, nxv8f16, !cast<Pseudo>(NAME # _UNDEF_H)>; defm : SVE_1_Op_PassthruUndef_Pat<nxv8f16, op, nxv8i1, nxv8f16, !cast<Pseudo>(NAME # _H_UNDEF)>;
defm : SVE_1_Op_PassthruUndef_Pat<nxv4f16, op, nxv4i1, nxv4f16, !cast<Pseudo>(NAME # _UNDEF_H)>; defm : SVE_1_Op_PassthruUndef_Pat<nxv4f16, op, nxv4i1, nxv4f16, !cast<Pseudo>(NAME # _H_UNDEF)>;
defm : SVE_1_Op_PassthruUndef_Pat<nxv2f16, op, nxv2i1, nxv2f16, !cast<Pseudo>(NAME # _UNDEF_H)>; defm : SVE_1_Op_PassthruUndef_Pat<nxv2f16, op, nxv2i1, nxv2f16, !cast<Pseudo>(NAME # _H_UNDEF)>;
defm : SVE_1_Op_PassthruUndef_Pat<nxv4f32, op, nxv4i1, nxv4f32, !cast<Pseudo>(NAME # _UNDEF_S)>; defm : SVE_1_Op_PassthruUndef_Pat<nxv4f32, op, nxv4i1, nxv4f32, !cast<Pseudo>(NAME # _S_UNDEF)>;
defm : SVE_1_Op_PassthruUndef_Pat<nxv2f32, op, nxv2i1, nxv2f32, !cast<Pseudo>(NAME # _UNDEF_S)>; defm : SVE_1_Op_PassthruUndef_Pat<nxv2f32, op, nxv2i1, nxv2f32, !cast<Pseudo>(NAME # _S_UNDEF)>;
defm : SVE_1_Op_PassthruUndef_Pat<nxv2f64, op, nxv2i1, nxv2f64, !cast<Pseudo>(NAME # _UNDEF_D)>; defm : SVE_1_Op_PassthruUndef_Pat<nxv2f64, op, nxv2i1, nxv2f64, !cast<Pseudo>(NAME # _D_UNDEF)>;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SVE Integer Wide Immediate - Unpredicated Group // SVE Integer Wide Immediate - Unpredicated Group
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class sve_int_dup_imm<bits<2> sz8_64, string asm, class sve_int_dup_imm<bits<2> sz8_64, string asm,
ZPRRegOp zprty, Operand immtype> ZPRRegOp zprty, Operand immtype>
: I<(outs zprty:$Zd), (ins immtype:$imm), : I<(outs zprty:$Zd), (ins immtype:$imm),
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: sve_int_bin_pred_shift_imm_left<opc, asm, Ps, null_frag> { : sve_int_bin_pred_shift_imm_left<opc, asm, Ps, null_frag> {
def : SVE_Shift_DupImm_Pred_Pat<nxv16i8, op, nxv16i1, i32, SVEShiftImmL8, !cast<Instruction>(NAME # _B)>; def : SVE_Shift_DupImm_Pred_Pat<nxv16i8, op, nxv16i1, i32, SVEShiftImmL8, !cast<Instruction>(NAME # _B)>;
def : SVE_Shift_DupImm_Pred_Pat<nxv8i16, op, nxv8i1, i32, SVEShiftImmL16, !cast<Instruction>(NAME # _H)>; def : SVE_Shift_DupImm_Pred_Pat<nxv8i16, op, nxv8i1, i32, SVEShiftImmL16, !cast<Instruction>(NAME # _H)>;
def : SVE_Shift_DupImm_Pred_Pat<nxv4i32, op, nxv4i1, i32, SVEShiftImmL32, !cast<Instruction>(NAME # _S)>; def : SVE_Shift_DupImm_Pred_Pat<nxv4i32, op, nxv4i1, i32, SVEShiftImmL32, !cast<Instruction>(NAME # _S)>;
def : SVE_Shift_DupImm_Pred_Pat<nxv2i64, op, nxv2i1, i64, SVEShiftImmL64, !cast<Instruction>(NAME # _D)>; def : SVE_Shift_DupImm_Pred_Pat<nxv2i64, op, nxv2i1, i64, SVEShiftImmL64, !cast<Instruction>(NAME # _D)>;
} }
multiclass sve_int_bin_pred_shift_imm_left_zeroing_bhsd<SDPatternOperator op> { multiclass sve_int_bin_pred_shift_imm_left_zeroing_bhsd<SDPatternOperator op> {
def _ZERO_B : PredTwoOpImmPseudo<NAME # _B, ZPR8, tvecshiftL8, FalseLanesZero>; def _B_ZERO : PredTwoOpImmPseudo<NAME # _B, ZPR8, tvecshiftL8, FalseLanesZero>;
def _ZERO_H : PredTwoOpImmPseudo<NAME # _H, ZPR16, tvecshiftL16, FalseLanesZero>; def _H_ZERO : PredTwoOpImmPseudo<NAME # _H, ZPR16, tvecshiftL16, FalseLanesZero>;
def _ZERO_S : PredTwoOpImmPseudo<NAME # _S, ZPR32, tvecshiftL32, FalseLanesZero>; def _S_ZERO : PredTwoOpImmPseudo<NAME # _S, ZPR32, tvecshiftL32, FalseLanesZero>;
def _ZERO_D : PredTwoOpImmPseudo<NAME # _D, ZPR64, tvecshiftL64, FalseLanesZero>; def _D_ZERO : PredTwoOpImmPseudo<NAME # _D, ZPR64, tvecshiftL64, FalseLanesZero>;
def : SVE_3_Op_Pat_Shift_Imm_SelZero<nxv16i8, op, nxv16i1, nxv16i8, tvecshiftL8, !cast<Pseudo>(NAME # _ZERO_B)>; def : SVE_3_Op_Pat_Shift_Imm_SelZero<nxv16i8, op, nxv16i1, nxv16i8, tvecshiftL8, !cast<Pseudo>(NAME # _B_ZERO)>;
def : SVE_3_Op_Pat_Shift_Imm_SelZero<nxv8i16, op, nxv8i1, nxv8i16, tvecshiftL16, !cast<Pseudo>(NAME # _ZERO_H)>; def : SVE_3_Op_Pat_Shift_Imm_SelZero<nxv8i16, op, nxv8i1, nxv8i16, tvecshiftL16, !cast<Pseudo>(NAME # _H_ZERO)>;
def : SVE_3_Op_Pat_Shift_Imm_SelZero<nxv4i32, op, nxv4i1, nxv4i32, tvecshiftL32, !cast<Pseudo>(NAME # _ZERO_S)>; def : SVE_3_Op_Pat_Shift_Imm_SelZero<nxv4i32, op, nxv4i1, nxv4i32, tvecshiftL32, !cast<Pseudo>(NAME # _S_ZERO)>;
def : SVE_3_Op_Pat_Shift_Imm_SelZero<nxv2i64, op, nxv2i1, nxv2i64, tvecshiftL64, !cast<Pseudo>(NAME # _ZERO_D)>; def : SVE_3_Op_Pat_Shift_Imm_SelZero<nxv2i64, op, nxv2i1, nxv2i64, tvecshiftL64, !cast<Pseudo>(NAME # _D_ZERO)>;
} }
multiclass sve_int_bin_pred_shift_imm_right<bits<4> opc, string asm, string Ps, multiclass sve_int_bin_pred_shift_imm_right<bits<4> opc, string asm, string Ps,
SDPatternOperator op = null_frag> { SDPatternOperator op = null_frag> {
def _B : SVEPseudo2Instr<Ps # _B, 1>, def _B : SVEPseudo2Instr<Ps # _B, 1>,
sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>; sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>;
def _H : SVEPseudo2Instr<Ps # _H, 1>, def _H : SVEPseudo2Instr<Ps # _H, 1>,
sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> { sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> {
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: sve_int_bin_pred_shift_imm_right<opc, asm, Ps, null_frag> { : sve_int_bin_pred_shift_imm_right<opc, asm, Ps, null_frag> {
def : SVE_Shift_DupImm_Pred_Pat<nxv16i8, op, nxv16i1, i32, SVEShiftImmR8, !cast<Instruction>(NAME # _B)>; def : SVE_Shift_DupImm_Pred_Pat<nxv16i8, op, nxv16i1, i32, SVEShiftImmR8, !cast<Instruction>(NAME # _B)>;
def : SVE_Shift_DupImm_Pred_Pat<nxv8i16, op, nxv8i1, i32, SVEShiftImmR16, !cast<Instruction>(NAME # _H)>; def : SVE_Shift_DupImm_Pred_Pat<nxv8i16, op, nxv8i1, i32, SVEShiftImmR16, !cast<Instruction>(NAME # _H)>;
def : SVE_Shift_DupImm_Pred_Pat<nxv4i32, op, nxv4i1, i32, SVEShiftImmR32, !cast<Instruction>(NAME # _S)>; def : SVE_Shift_DupImm_Pred_Pat<nxv4i32, op, nxv4i1, i32, SVEShiftImmR32, !cast<Instruction>(NAME # _S)>;
def : SVE_Shift_DupImm_Pred_Pat<nxv2i64, op, nxv2i1, i64, SVEShiftImmR64, !cast<Instruction>(NAME # _D)>; def : SVE_Shift_DupImm_Pred_Pat<nxv2i64, op, nxv2i1, i64, SVEShiftImmR64, !cast<Instruction>(NAME # _D)>;
} }
multiclass sve_int_bin_pred_shift_imm_right_zeroing_bhsd<SDPatternOperator op = null_frag> { multiclass sve_int_bin_pred_shift_imm_right_zeroing_bhsd<SDPatternOperator op = null_frag> {
def _ZERO_B : PredTwoOpImmPseudo<NAME # _B, ZPR8, vecshiftR8, FalseLanesZero>; def _B_ZERO : PredTwoOpImmPseudo<NAME # _B, ZPR8, vecshiftR8, FalseLanesZero>;
def _ZERO_H : PredTwoOpImmPseudo<NAME # _H, ZPR16, vecshiftR16, FalseLanesZero>; def _H_ZERO : PredTwoOpImmPseudo<NAME # _H, ZPR16, vecshiftR16, FalseLanesZero>;
def _ZERO_S : PredTwoOpImmPseudo<NAME # _S, ZPR32, vecshiftR32, FalseLanesZero>; def _S_ZERO : PredTwoOpImmPseudo<NAME # _S, ZPR32, vecshiftR32, FalseLanesZero>;
def _ZERO_D : PredTwoOpImmPseudo<NAME # _D, ZPR64, vecshiftR64, FalseLanesZero>; def _D_ZERO : PredTwoOpImmPseudo<NAME # _D, ZPR64, vecshiftR64, FalseLanesZero>;
def : SVE_3_Op_Pat_Shift_Imm_SelZero<nxv16i8, op, nxv16i1, nxv16i8, tvecshiftR8, !cast<Pseudo>(NAME # _ZERO_B)>; def : SVE_3_Op_Pat_Shift_Imm_SelZero<nxv16i8, op, nxv16i1, nxv16i8, tvecshiftR8, !cast<Pseudo>(NAME # _B_ZERO)>;
def : SVE_3_Op_Pat_Shift_Imm_SelZero<nxv8i16, op, nxv8i1, nxv8i16, tvecshiftR16, !cast<Pseudo>(NAME # _ZERO_H)>; def : SVE_3_Op_Pat_Shift_Imm_SelZero<nxv8i16, op, nxv8i1, nxv8i16, tvecshiftR16, !cast<Pseudo>(NAME # _H_ZERO)>;
def : SVE_3_Op_Pat_Shift_Imm_SelZero<nxv4i32, op, nxv4i1, nxv4i32, tvecshiftR32, !cast<Pseudo>(NAME # _ZERO_S)>; def : SVE_3_Op_Pat_Shift_Imm_SelZero<nxv4i32, op, nxv4i1, nxv4i32, tvecshiftR32, !cast<Pseudo>(NAME # _S_ZERO)>;
def : SVE_3_Op_Pat_Shift_Imm_SelZero<nxv2i64, op, nxv2i1, nxv2i64, tvecshiftR64, !cast<Pseudo>(NAME # _ZERO_D)>; def : SVE_3_Op_Pat_Shift_Imm_SelZero<nxv2i64, op, nxv2i1, nxv2i64, tvecshiftR64, !cast<Pseudo>(NAME # _D_ZERO)>;
} }
class sve_int_bin_pred_shift<bits<2> sz8_64, bit wide, bits<3> opc, class sve_int_bin_pred_shift<bits<2> sz8_64, bit wide, bits<3> opc,
string asm, ZPRRegOp zprty, ZPRRegOp zprty2> string asm, ZPRRegOp zprty, ZPRRegOp zprty2>
: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty2:$Zm), : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty2:$Zm),
asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm",
"", "",
[]>, Sched<[]> { []>, Sched<[]> {
Show All 30 Linesmulticlass sve_int_bin_pred_shift<bits<3> opc, string asm, string Ps,
} }
def : SVE_3_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>; def : SVE_3_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
def : SVE_3_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>; def : SVE_3_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>; def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>; def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
} }
multiclass sve_int_bin_pred_zeroing_bhsd<SDPatternOperator op> { multiclass sve_int_bin_pred_zeroing_bhsd<SDPatternOperator op> {
def _ZERO_B : PredTwoOpPseudo<NAME # _B, ZPR8, FalseLanesZero>; def _B_ZERO : PredTwoOpPseudo<NAME # _B, ZPR8, FalseLanesZero>;
def _ZERO_H : PredTwoOpPseudo<NAME # _H, ZPR16, FalseLanesZero>; def _H_ZERO : PredTwoOpPseudo<NAME # _H, ZPR16, FalseLanesZero>;
def _ZERO_S : PredTwoOpPseudo<NAME # _S, ZPR32, FalseLanesZero>; def _S_ZERO : PredTwoOpPseudo<NAME # _S, ZPR32, FalseLanesZero>;
def _ZERO_D : PredTwoOpPseudo<NAME # _D, ZPR64, FalseLanesZero>; def _D_ZERO : PredTwoOpPseudo<NAME # _D, ZPR64, FalseLanesZero>;
def : SVE_3_Op_Pat_SelZero<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Pseudo>(NAME # _ZERO_B)>; def : SVE_3_Op_Pat_SelZero<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Pseudo>(NAME # _B_ZERO)>;
def : SVE_3_Op_Pat_SelZero<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, !cast<Pseudo>(NAME # _ZERO_H)>; def : SVE_3_Op_Pat_SelZero<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, !cast<Pseudo>(NAME # _H_ZERO)>;
def : SVE_3_Op_Pat_SelZero<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Pseudo>(NAME # _ZERO_S)>; def : SVE_3_Op_Pat_SelZero<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Pseudo>(NAME # _S_ZERO)>;
def : SVE_3_Op_Pat_SelZero<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Pseudo>(NAME # _ZERO_D)>; def : SVE_3_Op_Pat_SelZero<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Pseudo>(NAME # _D_ZERO)>;
} }
multiclass sve_int_bin_pred_imm_zeroing_bhsd<SDPatternOperator op, multiclass sve_int_bin_pred_imm_zeroing_bhsd<SDPatternOperator op,
ComplexPattern imm_b, ComplexPattern imm_h, ComplexPattern imm_b, ComplexPattern imm_h,
ComplexPattern imm_s, ComplexPattern imm_d> { ComplexPattern imm_s, ComplexPattern imm_d> {
def _ZERO_B : PredTwoOpImmPseudo<NAME # _B, ZPR8, Operand<i32>, FalseLanesZero>; def _B_ZERO : PredTwoOpImmPseudo<NAME # _B, ZPR8, Operand<i32>, FalseLanesZero>;
def _ZERO_H : PredTwoOpImmPseudo<NAME # _H, ZPR16, Operand<i32>, FalseLanesZero>; def _H_ZERO : PredTwoOpImmPseudo<NAME # _H, ZPR16, Operand<i32>, FalseLanesZero>;
def _ZERO_S : PredTwoOpImmPseudo<NAME # _S, ZPR32, Operand<i32>, FalseLanesZero>; def _S_ZERO : PredTwoOpImmPseudo<NAME # _S, ZPR32, Operand<i32>, FalseLanesZero>;
def _ZERO_D : PredTwoOpImmPseudo<NAME # _D, ZPR64, Operand<i32>, FalseLanesZero>; def _D_ZERO : PredTwoOpImmPseudo<NAME # _D, ZPR64, Operand<i32>, FalseLanesZero>;
def : SVE_2_Op_Imm_Pat_Zero<nxv16i8, op, nxv16i1, i32, imm_b, !cast<Pseudo>(NAME # _ZERO_B)>; def : SVE_2_Op_Imm_Pat_Zero<nxv16i8, op, nxv16i1, i32, imm_b, !cast<Pseudo>(NAME # _B_ZERO)>;
def : SVE_2_Op_Imm_Pat_Zero<nxv8i16, op, nxv8i1, i32, imm_h, !cast<Pseudo>(NAME # _ZERO_H)>; def : SVE_2_Op_Imm_Pat_Zero<nxv8i16, op, nxv8i1, i32, imm_h, !cast<Pseudo>(NAME # _H_ZERO)>;
def : SVE_2_Op_Imm_Pat_Zero<nxv4i32, op, nxv4i1, i32, imm_s, !cast<Pseudo>(NAME # _ZERO_S)>; def : SVE_2_Op_Imm_Pat_Zero<nxv4i32, op, nxv4i1, i32, imm_s, !cast<Pseudo>(NAME # _S_ZERO)>;
def : SVE_2_Op_Imm_Pat_Zero<nxv2i64, op, nxv2i1, i64, imm_d, !cast<Pseudo>(NAME # _ZERO_D)>; def : SVE_2_Op_Imm_Pat_Zero<nxv2i64, op, nxv2i1, i64, imm_d, !cast<Pseudo>(NAME # _D_ZERO)>;
} }
multiclass sve_int_bin_pred_shift_wide<bits<3> opc, string asm, multiclass sve_int_bin_pred_shift_wide<bits<3> opc, string asm,
SDPatternOperator op> { SDPatternOperator op> {
def _B : sve_int_bin_pred_shift<0b00, 0b1, opc, asm, ZPR8, ZPR64>; def _B : sve_int_bin_pred_shift<0b00, 0b1, opc, asm, ZPR8, ZPR64>;
def _H : sve_int_bin_pred_shift<0b01, 0b1, opc, asm, ZPR16, ZPR64>; def _H : sve_int_bin_pred_shift<0b01, 0b1, opc, asm, ZPR16, ZPR64>;
def _S : sve_int_bin_pred_shift<0b10, 0b1, opc, asm, ZPR32, ZPR64>; def _S : sve_int_bin_pred_shift<0b10, 0b1, opc, asm, ZPR32, ZPR64>;
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def am_sve_regreg_lsl0 : ComplexPattern<iPTR, 2, "SelectSVERegRegAddrMode<0>", []>; def am_sve_regreg_lsl0 : ComplexPattern<iPTR, 2, "SelectSVERegRegAddrMode<0>", []>;
def am_sve_regreg_lsl1 : ComplexPattern<iPTR, 2, "SelectSVERegRegAddrMode<1>", []>; def am_sve_regreg_lsl1 : ComplexPattern<iPTR, 2, "SelectSVERegRegAddrMode<1>", []>;
def am_sve_regreg_lsl2 : ComplexPattern<iPTR, 2, "SelectSVERegRegAddrMode<2>", []>; def am_sve_regreg_lsl2 : ComplexPattern<iPTR, 2, "SelectSVERegRegAddrMode<2>", []>;
def am_sve_regreg_lsl3 : ComplexPattern<iPTR, 2, "SelectSVERegRegAddrMode<3>", []>; def am_sve_regreg_lsl3 : ComplexPattern<iPTR, 2, "SelectSVERegRegAddrMode<3>", []>;
def am_sve_regreg_lsl4 : ComplexPattern<iPTR, 2, "SelectSVERegRegAddrMode<4>", []>; def am_sve_regreg_lsl4 : ComplexPattern<iPTR, 2, "SelectSVERegRegAddrMode<4>", []>;
// Predicated pseudo floating point two operand instructions. // Predicated pseudo floating point two operand instructions.
multiclass sve_fp_bin_pred_hfd<SDPatternOperator op> { multiclass sve_fp_bin_pred_hfd<SDPatternOperator op> {
def _UNDEF_H : PredTwoOpPseudo<NAME # _H, ZPR16, FalseLanesUndef>; def _H_UNDEF : PredTwoOpPseudo<NAME # _H, ZPR16, FalseLanesUndef>;
def _UNDEF_S : PredTwoOpPseudo<NAME # _S, ZPR32, FalseLanesUndef>; def _S_UNDEF : PredTwoOpPseudo<NAME # _S, ZPR32, FalseLanesUndef>;
def _UNDEF_D : PredTwoOpPseudo<NAME # _D, ZPR64, FalseLanesUndef>; def _D_UNDEF : PredTwoOpPseudo<NAME # _D, ZPR64, FalseLanesUndef>;
def : SVE_3_Op_Pat<nxv8f16, op, nxv8i1, nxv8f16, nxv8f16, !cast<Pseudo>(NAME # _UNDEF_H)>; def : SVE_3_Op_Pat<nxv8f16, op, nxv8i1, nxv8f16, nxv8f16, !cast<Pseudo>(NAME # _H_UNDEF)>;
def : SVE_3_Op_Pat<nxv4f16, op, nxv4i1, nxv4f16, nxv4f16, !cast<Pseudo>(NAME # _UNDEF_H)>; def : SVE_3_Op_Pat<nxv4f16, op, nxv4i1, nxv4f16, nxv4f16, !cast<Pseudo>(NAME # _H_UNDEF)>;
def : SVE_3_Op_Pat<nxv2f16, op, nxv2i1, nxv2f16, nxv2f16, !cast<Pseudo>(NAME # _UNDEF_H)>; def : SVE_3_Op_Pat<nxv2f16, op, nxv2i1, nxv2f16, nxv2f16, !cast<Pseudo>(NAME # _H_UNDEF)>;
def : SVE_3_Op_Pat<nxv4f32, op, nxv4i1, nxv4f32, nxv4f32, !cast<Pseudo>(NAME # _UNDEF_S)>; def : SVE_3_Op_Pat<nxv4f32, op, nxv4i1, nxv4f32, nxv4f32, !cast<Pseudo>(NAME # _S_UNDEF)>;
def : SVE_3_Op_Pat<nxv2f32, op, nxv2i1, nxv2f32, nxv2f32, !cast<Pseudo>(NAME # _UNDEF_S)>; def : SVE_3_Op_Pat<nxv2f32, op, nxv2i1, nxv2f32, nxv2f32, !cast<Pseudo>(NAME # _S_UNDEF)>;
def : SVE_3_Op_Pat<nxv2f64, op, nxv2i1, nxv2f64, nxv2f64, !cast<Pseudo>(NAME # _UNDEF_D)>; def : SVE_3_Op_Pat<nxv2f64, op, nxv2i1, nxv2f64, nxv2f64, !cast<Pseudo>(NAME # _D_UNDEF)>;
} }
// Predicated pseudo floating point three operand instructions. // Predicated pseudo floating point three operand instructions.
multiclass sve_fp_3op_pred_hfd<SDPatternOperator op> { multiclass sve_fp_3op_pred_hfd<SDPatternOperator op> {
def _UNDEF_H : PredThreeOpPseudo<NAME # _H, ZPR16, FalseLanesUndef>; def _H_UNDEF : PredThreeOpPseudo<NAME # _H, ZPR16, FalseLanesUndef>;
def _UNDEF_S : PredThreeOpPseudo<NAME # _S, ZPR32, FalseLanesUndef>; def _S_UNDEF : PredThreeOpPseudo<NAME # _S, ZPR32, FalseLanesUndef>;
def _UNDEF_D : PredThreeOpPseudo<NAME # _D, ZPR64, FalseLanesUndef>; def _D_UNDEF : PredThreeOpPseudo<NAME # _D, ZPR64, FalseLanesUndef>;
def : SVE_4_Op_Pat<nxv8f16, op, nxv8i1, nxv8f16, nxv8f16, nxv8f16, !cast<Instruction>(NAME # _UNDEF_H)>; def : SVE_4_Op_Pat<nxv8f16, op, nxv8i1, nxv8f16, nxv8f16, nxv8f16, !cast<Instruction>(NAME # _H_UNDEF)>;
def : SVE_4_Op_Pat<nxv4f16, op, nxv4i1, nxv4f16, nxv4f16, nxv4f16, !cast<Instruction>(NAME # _UNDEF_H)>; def : SVE_4_Op_Pat<nxv4f16, op, nxv4i1, nxv4f16, nxv4f16, nxv4f16, !cast<Instruction>(NAME # _H_UNDEF)>;
def : SVE_4_Op_Pat<nxv2f16, op, nxv2i1, nxv2f16, nxv2f16, nxv2f16, !cast<Instruction>(NAME # _UNDEF_H)>; def : SVE_4_Op_Pat<nxv2f16, op, nxv2i1, nxv2f16, nxv2f16, nxv2f16, !cast<Instruction>(NAME # _H_UNDEF)>;
def : SVE_4_Op_Pat<nxv4f32, op, nxv4i1, nxv4f32, nxv4f32, nxv4f32, !cast<Instruction>(NAME # _UNDEF_S)>; def : SVE_4_Op_Pat<nxv4f32, op, nxv4i1, nxv4f32, nxv4f32, nxv4f32, !cast<Instruction>(NAME # _S_UNDEF)>;
def : SVE_4_Op_Pat<nxv2f32, op, nxv2i1, nxv2f32, nxv2f32, nxv2f32, !cast<Instruction>(NAME # _UNDEF_S)>; def : SVE_4_Op_Pat<nxv2f32, op, nxv2i1, nxv2f32, nxv2f32, nxv2f32, !cast<Instruction>(NAME # _S_UNDEF)>;
def : SVE_4_Op_Pat<nxv2f64, op, nxv2i1, nxv2f64, nxv2f64, nxv2f64, !cast<Instruction>(NAME # _UNDEF_D)>; def : SVE_4_Op_Pat<nxv2f64, op, nxv2i1, nxv2f64, nxv2f64, nxv2f64, !cast<Instruction>(NAME # _D_UNDEF)>;
} }
// Predicated pseudo integer two operand instructions. // Predicated pseudo integer two operand instructions.
multiclass sve_int_bin_pred_bhsd<SDPatternOperator op> { multiclass sve_int_bin_pred_bhsd<SDPatternOperator op> {
def _UNDEF_B : PredTwoOpPseudo<NAME # _B, ZPR8, FalseLanesUndef>; def _B_UNDEF : PredTwoOpPseudo<NAME # _B, ZPR8, FalseLanesUndef>;
def _UNDEF_H : PredTwoOpPseudo<NAME # _H, ZPR16, FalseLanesUndef>; def _H_UNDEF : PredTwoOpPseudo<NAME # _H, ZPR16, FalseLanesUndef>;
def _UNDEF_S : PredTwoOpPseudo<NAME # _S, ZPR32, FalseLanesUndef>; def _S_UNDEF : PredTwoOpPseudo<NAME # _S, ZPR32, FalseLanesUndef>;
def _UNDEF_D : PredTwoOpPseudo<NAME # _D, ZPR64, FalseLanesUndef>; def _D_UNDEF : PredTwoOpPseudo<NAME # _D, ZPR64, FalseLanesUndef>;
def : SVE_3_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Pseudo>(NAME # _UNDEF_B)>; def : SVE_3_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Pseudo>(NAME # _B_UNDEF)>;
def : SVE_3_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, !cast<Pseudo>(NAME # _UNDEF_H)>; def : SVE_3_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, !cast<Pseudo>(NAME # _H_UNDEF)>;
def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Pseudo>(NAME # _UNDEF_S)>; def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Pseudo>(NAME # _S_UNDEF)>;
def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Pseudo>(NAME # _UNDEF_D)>; def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Pseudo>(NAME # _D_UNDEF)>;
} }
// As sve_int_bin_pred but when only i32 and i64 vector types are required. // As sve_int_bin_pred but when only i32 and i64 vector types are required.
multiclass sve_int_bin_pred_sd<SDPatternOperator op> { multiclass sve_int_bin_pred_sd<SDPatternOperator op> {
def _UNDEF_S : PredTwoOpPseudo<NAME # _S, ZPR32, FalseLanesUndef>; def _S_UNDEF : PredTwoOpPseudo<NAME # _S, ZPR32, FalseLanesUndef>;
def _UNDEF_D : PredTwoOpPseudo<NAME # _D, ZPR64, FalseLanesUndef>; def _D_UNDEF : PredTwoOpPseudo<NAME # _D, ZPR64, FalseLanesUndef>;
def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Pseudo>(NAME # _UNDEF_S)>; def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Pseudo>(NAME # _S_UNDEF)>;
def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Pseudo>(NAME # _UNDEF_D)>; def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Pseudo>(NAME # _D_UNDEF)>;
} }
// Predicated pseudo integer two operand instructions. Second operand is an // Predicated pseudo integer two operand instructions. Second operand is an
// immediate specified by imm_[bhsd]. // immediate specified by imm_[bhsd].
multiclass sve_int_shift_pred_bhsd<SDPatternOperator op, multiclass sve_int_shift_pred_bhsd<SDPatternOperator op,
ComplexPattern imm_b, ComplexPattern imm_h, ComplexPattern imm_b, ComplexPattern imm_h,
ComplexPattern imm_s, ComplexPattern imm_d> { ComplexPattern imm_s, ComplexPattern imm_d> {
def _UNDEF_B : PredTwoOpImmPseudo<NAME # _B, ZPR8, Operand<i32>, FalseLanesUndef>; def _B_UNDEF : PredTwoOpImmPseudo<NAME # _B, ZPR8, Operand<i32>, FalseLanesUndef>;
def _UNDEF_H : PredTwoOpImmPseudo<NAME # _H, ZPR16, Operand<i32>, FalseLanesUndef>; def _H_UNDEF : PredTwoOpImmPseudo<NAME # _H, ZPR16, Operand<i32>, FalseLanesUndef>;
def _UNDEF_S : PredTwoOpImmPseudo<NAME # _S, ZPR32, Operand<i32>, FalseLanesUndef>; def _S_UNDEF : PredTwoOpImmPseudo<NAME # _S, ZPR32, Operand<i32>, FalseLanesUndef>;
def _UNDEF_D : PredTwoOpImmPseudo<NAME # _D, ZPR64, Operand<i32>, FalseLanesUndef>; def _D_UNDEF : PredTwoOpImmPseudo<NAME # _D, ZPR64, Operand<i32>, FalseLanesUndef>;
def : SVE_Shift_DupImm_Pred_Pat<nxv16i8, op, nxv16i1, i32, imm_b, !cast<Instruction>(NAME # _UNDEF_B)>; def : SVE_Shift_DupImm_Pred_Pat<nxv16i8, op, nxv16i1, i32, imm_b, !cast<Instruction>(NAME # _B_UNDEF)>;
def : SVE_Shift_DupImm_Pred_Pat<nxv8i16, op, nxv8i1, i32, imm_h, !cast<Instruction>(NAME # _UNDEF_H)>; def : SVE_Shift_DupImm_Pred_Pat<nxv8i16, op, nxv8i1, i32, imm_h, !cast<Instruction>(NAME # _H_UNDEF)>;
def : SVE_Shift_DupImm_Pred_Pat<nxv4i32, op, nxv4i1, i32, imm_s, !cast<Instruction>(NAME # _UNDEF_S)>; def : SVE_Shift_DupImm_Pred_Pat<nxv4i32, op, nxv4i1, i32, imm_s, !cast<Instruction>(NAME # _S_UNDEF)>;
def : SVE_Shift_DupImm_Pred_Pat<nxv2i64, op, nxv2i1, i64, imm_d, !cast<Instruction>(NAME # _UNDEF_D)>; def : SVE_Shift_DupImm_Pred_Pat<nxv2i64, op, nxv2i1, i64, imm_d, !cast<Instruction>(NAME # _D_UNDEF)>;
} }
multiclass sve_int_bin_pred_all_active_bhsd<SDPatternOperator op> { multiclass sve_int_bin_pred_all_active_bhsd<SDPatternOperator op> {
def _UNDEF_B : PredTwoOpPseudo<NAME # _B, ZPR8, FalseLanesUndef>; def _B_UNDEF : PredTwoOpPseudo<NAME # _B, ZPR8, FalseLanesUndef>;
def _UNDEF_H : PredTwoOpPseudo<NAME # _H, ZPR16, FalseLanesUndef>; def _H_UNDEF : PredTwoOpPseudo<NAME # _H, ZPR16, FalseLanesUndef>;
def _UNDEF_S : PredTwoOpPseudo<NAME # _S, ZPR32, FalseLanesUndef>; def _S_UNDEF : PredTwoOpPseudo<NAME # _S, ZPR32, FalseLanesUndef>;
def _UNDEF_D : PredTwoOpPseudo<NAME # _D, ZPR64, FalseLanesUndef>; def _D_UNDEF : PredTwoOpPseudo<NAME # _D, ZPR64, FalseLanesUndef>;
def : SVE_2_Op_Pred_All_Active_Pt<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Pseudo>(NAME # _UNDEF_B)>; def : SVE_2_Op_Pred_All_Active_Pt<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Pseudo>(NAME # _B_UNDEF)>;
def : SVE_2_Op_Pred_All_Active_Pt<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, !cast<Pseudo>(NAME # _UNDEF_H)>; def : SVE_2_Op_Pred_All_Active_Pt<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, !cast<Pseudo>(NAME # _H_UNDEF)>;
def : SVE_2_Op_Pred_All_Active_Pt<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Pseudo>(NAME # _UNDEF_S)>; def : SVE_2_Op_Pred_All_Active_Pt<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Pseudo>(NAME # _S_UNDEF)>;
def : SVE_2_Op_Pred_All_Active_Pt<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Pseudo>(NAME # _UNDEF_D)>; def : SVE_2_Op_Pred_All_Active_Pt<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Pseudo>(NAME # _D_UNDEF)>;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SME2 or SVE2.1 Instructions // SME2 or SVE2.1 Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class sve2p1_fclamp<string asm, bits<2> sz, ZPRRegOp zpr_ty> class sve2p1_fclamp<string asm, bits<2> sz, ZPRRegOp zpr_ty>
: I<(outs zpr_ty:$Zd), (ins zpr_ty:$_Zd, zpr_ty:$Zn, zpr_ty:$Zm), : I<(outs zpr_ty:$Zd), (ins zpr_ty:$_Zd, zpr_ty:$Zn, zpr_ty:$Zm),
▲ Show 20 Lines • Show All 911 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-merging.mir

Show All 28 Lines bb.0 (%ir-block.0):
; CHECK: liveins: $p0, $z0 ; CHECK: liveins: $p0, $z0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: BUNDLE implicit-def $z0, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $h0, implicit-def $b0, implicit-def $z0_hi, implicit killed $p0, implicit $z0 { ; CHECK-NEXT: BUNDLE implicit-def $z0, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $h0, implicit-def $b0, implicit-def $z0_hi, implicit killed $p0, implicit $z0 {
; CHECK-NEXT: $z0 = MOVPRFX_ZPzZ_H $p0, $z0 ; CHECK-NEXT: $z0 = MOVPRFX_ZPzZ_H $p0, $z0
; CHECK-NEXT: $z0 = LSL_ZPmI_H killed renamable $p0, internal $z0, 0 ; CHECK-NEXT: $z0 = LSL_ZPmI_H killed renamable $p0, internal $z0, 0
; CHECK-NEXT: $z0 = BIC_ZPmZ_H killed renamable $p0, internal killed $z0, internal killed renamable $z0 ; CHECK-NEXT: $z0 = BIC_ZPmZ_H killed renamable $p0, internal killed $z0, internal killed renamable $z0
; CHECK-NEXT: } ; CHECK-NEXT: }
; CHECK-NEXT: RET undef $lr, implicit $z0 ; CHECK-NEXT: RET undef $lr, implicit $z0
renamable $z0 = BIC_ZPZZ_ZERO_H killed renamable $p0, killed renamable $z0, killed renamable $z0 renamable $z0 = BIC_ZPZZ_H_ZERO killed renamable $p0, killed renamable $z0, killed renamable $z0
RET_ReallyLR implicit $z0 RET_ReallyLR implicit $z0
... ...

llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryComm-merging.mir

Show All 28 Lines bb.0 (%ir-block.0):
; CHECK: liveins: $p0, $z0 ; CHECK: liveins: $p0, $z0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: BUNDLE implicit-def $z0, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $h0, implicit-def $b0, implicit-def $z0_hi, implicit $p0, implicit $z0 { ; CHECK-NEXT: BUNDLE implicit-def $z0, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $h0, implicit-def $b0, implicit-def $z0_hi, implicit $p0, implicit $z0 {
; CHECK-NEXT: $z0 = MOVPRFX_ZPzZ_S $p0, $z0 ; CHECK-NEXT: $z0 = MOVPRFX_ZPzZ_S $p0, $z0
; CHECK-NEXT: $z0 = LSL_ZPmI_S renamable $p0, internal $z0, 0 ; CHECK-NEXT: $z0 = LSL_ZPmI_S renamable $p0, internal $z0, 0
; CHECK-NEXT: $z0 = FMUL_ZPmZ_S renamable $p0, internal killed $z0, internal killed renamable $z0 ; CHECK-NEXT: $z0 = FMUL_ZPmZ_S renamable $p0, internal killed $z0, internal killed renamable $z0
; CHECK-NEXT: } ; CHECK-NEXT: }
; CHECK-NEXT: RET undef $lr, implicit $z0 ; CHECK-NEXT: RET undef $lr, implicit $z0
renamable $z0 = nnan ninf nsz arcp contract afn reassoc FMUL_ZPZZ_ZERO_S renamable $p0, killed renamable $z0, renamable $z0 renamable $z0 = nnan ninf nsz arcp contract afn reassoc FMUL_ZPZZ_S_ZERO renamable $p0, killed renamable $z0, renamable $z0
RET_ReallyLR implicit $z0 RET_ReallyLR implicit $z0
... ...

llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryCommWithRev-merging.mir

Show All 30 Lines bb.0 (%ir-block.0):
; CHECK: liveins: $p0, $z0 ; CHECK: liveins: $p0, $z0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: BUNDLE implicit-def $z0, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $h0, implicit-def $b0, implicit-def $z0_hi, implicit $p0, implicit $z0 { ; CHECK-NEXT: BUNDLE implicit-def $z0, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $h0, implicit-def $b0, implicit-def $z0_hi, implicit $p0, implicit $z0 {
; CHECK-NEXT: $z0 = MOVPRFX_ZPzZ_S $p0, $z0 ; CHECK-NEXT: $z0 = MOVPRFX_ZPzZ_S $p0, $z0
; CHECK-NEXT: $z0 = LSL_ZPmI_S renamable $p0, internal $z0, 0 ; CHECK-NEXT: $z0 = LSL_ZPmI_S renamable $p0, internal $z0, 0
; CHECK-NEXT: $z0 = FSUBR_ZPmZ_S renamable $p0, internal killed $z0, internal killed renamable $z0 ; CHECK-NEXT: $z0 = FSUBR_ZPmZ_S renamable $p0, internal killed $z0, internal killed renamable $z0
; CHECK-NEXT: } ; CHECK-NEXT: }
; CHECK-NEXT: RET undef $lr, implicit $z0 ; CHECK-NEXT: RET undef $lr, implicit $z0
renamable $z0 = nnan ninf nsz arcp contract afn reassoc FSUB_ZPZZ_ZERO_S renamable $p0, killed renamable $z0, renamable $z0 renamable $z0 = nnan ninf nsz arcp contract afn reassoc FSUB_ZPZZ_S_ZERO renamable $p0, killed renamable $z0, renamable $z0
RET_ReallyLR implicit $z0 RET_ReallyLR implicit $z0
... ...

llvm/test/CodeGen/AArch64/sve-pseudos-expand-undef.mir

Show All 10 Lines
body: | body: |
bb.0: bb.0:
liveins: $p0, $z0 liveins: $p0, $z0
; CHECK: add_x ; CHECK: add_x
; CHECK-NOT: MOVPRFX ; CHECK-NOT: MOVPRFX
; CHECK: $z0 = FADD_ZPmZ_S renamable $p0, killed $z0, renamable $z0 ; CHECK: $z0 = FADD_ZPmZ_S renamable $p0, killed $z0, renamable $z0
; CHECK-NEXT: RET ; CHECK-NEXT: RET
renamable $z0 = FADD_ZPZZ_UNDEF_S renamable $p0, renamable $z0, killed renamable $z0 renamable $z0 = FADD_ZPZZ_S_UNDEF renamable $p0, renamable $z0, killed renamable $z0
RET_ReallyLR RET_ReallyLR
... ...
# CHECK: {{.*}} MSB_ZPmZZ_B {{.*}} # CHECK: {{.*}} MSB_ZPmZZ_B {{.*}}
--- ---
name: expand_mls_to_msb name: expand_mls_to_msb
body: | body: |
bb.0: bb.0:
renamable $p0 = PTRUE_B 31 renamable $p0 = PTRUE_B 31
renamable $z0 = MLS_ZPZZZ_UNDEF_B killed renamable $p0, killed renamable $z2, killed renamable $z0, killed renamable $z1 renamable $z0 = MLS_ZPZZZ_B_UNDEF killed renamable $p0, killed renamable $z2, killed renamable $z0, killed renamable $z1
RET_ReallyLR implicit $z0 RET_ReallyLR implicit $z0
... ...
# CHECK: {{.*}} MAD_ZPmZZ_B {{.*}} # CHECK: {{.*}} MAD_ZPmZZ_B {{.*}}
--- ---
name: expand_mla_to_mad name: expand_mla_to_mad
body: | body: |
bb.0: bb.0:
renamable $p0 = PTRUE_B 31 renamable $p0 = PTRUE_B 31
renamable $z0 = MLA_ZPZZZ_UNDEF_B killed renamable $p0, killed renamable $z2, killed renamable $z0, killed renamable $z1 renamable $z0 = MLA_ZPZZZ_B_UNDEF killed renamable $p0, killed renamable $z2, killed renamable $z0, killed renamable $z1
RET_ReallyLR implicit $z0 RET_ReallyLR implicit $z0
... ...