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Differential D15418

[mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions and add CodeGen support
ClosedPublic

Authored by zbuljan on Dec 10 2015, 7:02 AM.

Details

Reviewers
dsanders
sdardis
vkalintiris
zoran.jovanovic
hvarga
Commits
rL269883: [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions and add…
Summary

The patch implements microMIPSr6 LH, LHE, LHU and LHUE instructions.

There was a problem with previous implementation of this instructions (D9824) and because of that commit rL254897 was reverted.

After commit of previous patch, test-suite failed with error message in the form of:

fatal error: error in backend: Cannot select: t124: i32,ch = load<LD2[%d](tbaa=<0x94acc48>), sext from i16> t0, t2, undef:i32

There was problem with selecting lh and lhu instructions in LLVM backend.

For that reason I decided to revert commit rL254897 and make this patch which besides implementation of instructions and standard regression tests also includes CodeGen tests (lh_lhu.ll).

Diff Detail

Event Timeline

zbuljan updated this revision to Diff 42428.Dec 10 2015, 7:02 AM
zbuljan retitled this revision from to [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions.
zbuljan updated this object.
zbuljan added reviewers: dsanders, hvarga, zoran.jovanovic.
zbuljan added subscribers: petarj, llvm-commits.
Herald added a subscriber: dsanders. · View Herald TranscriptDec 10 2015, 7:02 AM
zbuljan updated this revision to Diff 50405.Mar 11 2016, 1:55 AM

Rebased to work with top of the tree.

Herald added a reviewer: vkalintiris. · View Herald TranscriptMar 11 2016, 1:55 AM
sdardis added a reviewer: sdardis.Apr 14 2016, 6:08 AM
sdardis requested changes to this revision.Apr 15 2016, 7:12 AM
sdardis edited edge metadata.

Hi,

After applying this patch and checking lh_lhu.ll with "-asm-show-inst" I see:

lh      $2, %lo(us)($2)         # <MCInst #1187 LH
                                #  <MCOperand Reg:321>
                                #  <MCOperand Reg:321>
                                #  <MCOperand Expr:(us@ABS_LO)>>

Shouldn't LLVM have picked LH_MM? The rest are small nits regarding some style issues and the ordering of instructions in test files.

lib/Target/Mips/MicroMips32r6InstrFormats.td
883 ↗(On Diff #50405)

Can you redo this definition in the style of SB32_SH32_STORE_FM_MMR6 ? You split addr into base and offset, then assign to Inst.

lib/Target/Mips/MicroMips32r6InstrInfo.td
173–174 ↗(On Diff #50405)

Can you use the 0bxxx style of specifying opcodes here? It makes it somewhat easier to check and is more consistent with the overall MIPS backend.

test/MC/Disassembler/Mips/micromips32r6/valid.txt
271–274

Can you sort these alphabetically into the existing instructions?

test/MC/Mips/micromips-invalid.s
105 ↗(On Diff #50405)

Can you add some out of range negative tests for these instructions as well? This applies to the other invalid tests as well.

test/MC/Mips/micromips32r6/valid.s
272–275

Can you sort these alphabetically into the first 100~ instructions.

This revision now requires changes to proceed.Apr 15 2016, 7:12 AM
zbuljan updated this revision to Diff 55564.Apr 29 2016, 4:20 AM
zbuljan retitled this revision from [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions to [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions and add CodeGen support.
zbuljan edited edge metadata.

Rebased to work with TOT.
Removed microMIPS32r6 implementation of LH and LHU instructions because it is not required.
Added required DAG patterns for microMIPS LH and LHU instructions so they can be selected properly.
Expanded .ll test with load atomic to check added DAG pattern.
Tests for the standard encodings are sorted in alphabetical order.
Added invalid tests for the negative ranges.

Herald added a subscriber: sdardis. · View Herald TranscriptApr 29 2016, 4:20 AM
sdardis requested changes to this revision.May 5 2016, 7:17 AM
sdardis edited edge metadata.

One nit and one small change, comments are inlined.

lib/Target/Mips/MicroMipsInstrFormats.td
1026

This class needs to inherit from MMArch, so that this instruction ends up in the Std2MicroMips mapping table from direct object emission.

You can verify the mapping by looking at the Std2MicroMips function in $BUILDDIR/lib/Target/Mips/MipsGenDAGISel.inc and/or the records from llvm-tblgen for the string Arch = in the defs of the instructions.

You'll also have to remove the line "list<Pattern> = []" from the definition of MMArch, otherwise the DAG pattern doesn't get set properly and the instruction cannot be selected in the common case.

Removing that line from the MMArch definition will cause test failures as the selection mechanism be arranged and some 16bit instructions will not be chosen. Some of the test failures are fixed in D19906.

test/CodeGen/Mips/llvm-ir/lh_lhu.ll
3

Check microMIPS64r6 as well.

This revision now requires changes to proceed.May 5 2016, 7:17 AM
zbuljan updated this revision to Diff 57453.May 17 2016, 3:56 AM
zbuljan edited edge metadata.

Rebased to work with TOT.
Changed LH_LHU_FM_MM format class to inherit from MMArch.
Removed the line "list<Pattern> = []" from the definition of MMArch class.
Added "int AddedComplexity = 1" parameter to definition of 16-bit instructions.
Updated lh_lhu.ll with test for microMIPS64r6.

sdardis accepted this revision.May 17 2016, 9:15 AM
sdardis edited edge metadata.

LGTM.

This revision is now accepted and ready to land.May 17 2016, 9:15 AM
Closed by commit rL269883: [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions and add… (authored by zbuljan). · Explain WhyMay 18 2016, 12:01 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
Mips/
14 lines
21 lines
23 lines
test/
CodeGen/
Mips/
llvm-ir/
31 lines
MC/
Disassembler/
Mips/
micromips32r6/
4 lines
micromips64r6/
4 lines
Mips/
micromips/
16 lines
micromips32r6/
16 lines
4 lines
micromips64r6/
16 lines
4 lines
mips32r6/
16 lines
mips64r6/
16 lines

Diff 55564

lib/Target/Mips/MicroMipsInstrFormats.td

Show First 20 Lines • Show All 1,016 Lines • ▼ Show 20 Linesclass ADDIUPC_FM_MM {
bits<23> imm; bits<23> imm;
bits<32> Inst; bits<32> Inst;
let Inst{31-26} = 0x1e; let Inst{31-26} = 0x1e;
let Inst{25-23} = rs; let Inst{25-23} = rs;
let Inst{22-0} = imm; let Inst{22-0} = imm;
} }
class LH_LHU_FM_MM<bits<6> op> {
sdardisUnsubmitted
Not Done
ReplyInline Actions

This class needs to inherit from MMArch, so that this instruction ends up in the Std2MicroMips mapping table from direct object emission.

You can verify the mapping by looking at the Std2MicroMips function in $BUILDDIR/lib/Target/Mips/MipsGenDAGISel.inc and/or the records from llvm-tblgen for the string Arch = in the defs of the instructions.

You'll also have to remove the line "list<Pattern> = []" from the definition of MMArch, otherwise the DAG pattern doesn't get set properly and the instruction cannot be selected in the common case.

Removing that line from the MMArch definition will cause test failures as the selection mechanism be arranged and some 16bit instructions will not be chosen. Some of the test failures are fixed in D19906.

sdardis: This class needs to inherit from MMArch, so that this instruction ends up in the Std2MicroMips…
bits<5> rt;
bits<21> addr;
bits<5> base = addr{20-16};
bits<16> offset = addr{15-0};
bits<32> Inst;
let Inst{31-26} = op;
let Inst{25-21} = rt;
let Inst{20-16} = base;
let Inst{15-0} = offset;
}

lib/Target/Mips/MicroMipsInstrInfo.td

Show First 20 Lines • Show All 719 Lines • ▼ Show 20 Lines def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
SRA_FM_MM<0xc0, 0>; SRA_FM_MM<0xc0, 0>;
def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>, def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
SRLV_FM_MM<0xd0, 0>; SRLV_FM_MM<0xd0, 0>;
/// Load and Store Instructions - aligned /// Load and Store Instructions - aligned
let DecoderMethod = "DecodeMemMMImm16" in { let DecoderMethod = "DecodeMemMMImm16" in {
def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>; def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>; def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
def LH_MM : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>; def LH_MM : LoadMemory<"lh", GPR32Opnd, mem_simm16, sextloadi16, II_LH,
def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>; addrDefault>, MMRel, LH_LHU_FM_MM<0xf>;
def LHu_MM : LoadMemory<"lhu", GPR32Opnd, mem_simm16, zextloadi16, II_LHU>,
MMRel, LH_LHU_FM_MM<0xd>;
def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>; def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>; def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>; def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>; def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
} }
let DecoderMethod = "DecodeMemMMImm9" in { let DecoderMethod = "DecodeMemMMImm9" in {
def LBE_MM : Load<"lbe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>; def LBE_MM : Load<"lbe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>;
def LBuE_MM : Load<"lbue", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>; def LBuE_MM : Load<"lbue", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>;
def LHE_MM : Load<"lhe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>; def LHE_MM : LoadMemory<"lhe", GPR32Opnd, mem_simm9>,
def LHuE_MM : Load<"lhue", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>; POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>;
def LHuE_MM : LoadMemory<"lhue", GPR32Opnd, mem_simm9>,
POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>;
def LWE_MM : LoadMemory<"lwe", GPR32Opnd, mem_simm9>, def LWE_MM : LoadMemory<"lwe", GPR32Opnd, mem_simm9>,
POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>; POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>;
def SBE_MM : StoreMemory<"sbe", GPR32Opnd, mem_simm9>, def SBE_MM : StoreMemory<"sbe", GPR32Opnd, mem_simm9>,
POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>; POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>;
def SHE_MM : StoreMemory<"she", GPR32Opnd, mem_simm9>, def SHE_MM : StoreMemory<"she", GPR32Opnd, mem_simm9>,
POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>; POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>;
def SWE_MM : StoreMemory<"swe", GPR32Opnd, mem_simm9>, def SWE_MM : StoreMemory<"swe", GPR32Opnd, mem_simm9>,
POOL32C_LHUE_FM_MM<0x18, 0xa, 0x7>; POOL32C_LHUE_FM_MM<0x18, 0xa, 0x7>;
▲ Show 20 Lines • Show All 248 Lines • ▼ Show 20 Lines
def : MipsPat<(load addrimm4lsl2:$addr), def : MipsPat<(load addrimm4lsl2:$addr),
(LW16_MM addrimm4lsl2:$addr)>; (LW16_MM addrimm4lsl2:$addr)>;
def : MipsPat<(load addr:$addr), def : MipsPat<(load addr:$addr),
(LW_MM addr:$addr)>; (LW_MM addr:$addr)>;
def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs), def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
(SUBu_MM GPR32:$lhs, GPR32:$rhs)>; (SUBu_MM GPR32:$lhs, GPR32:$rhs)>;
let AddedComplexity = 40 in {
def : MipsPat<(i32 (sextloadi16 addrRegImm:$a)),
(LH_MM addrRegImm:$a)>;
}
def : MipsPat<(atomic_load_16 addr:$a),
(LH_MM addr:$a)>;
def : MipsPat<(i32 (extloadi16 addr:$src)),
(LHu_MM addr:$src)>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// MicroMips instruction aliases // MicroMips instruction aliases
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class UncondBranchMMPseudo<string opstr> : class UncondBranchMMPseudo<string opstr> :
MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset), MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
!strconcat(opstr, "\t$offset")>; !strconcat(opstr, "\t$offset")>;
▲ Show 20 Lines • Show All 46 Lines • Show Last 20 Lines

lib/Target/Mips/MipsInstrInfo.td

Show First 20 Lines • Show All 1,701 Lines • ▼ Show 20 Lines
def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>, def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
SRLV_FM<6, 1>, ISA_MIPS32R2; SRLV_FM<6, 1>, ISA_MIPS32R2;
/// Load and Store Instructions /// Load and Store Instructions
/// aligned /// aligned
def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>; def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel, def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
LW_FM<0x24>; LW_FM<0x24>;
def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
LW_FM<0x21>;
def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def LH : LoadMemory<"lh", GPR32Opnd, mem_simm16, sextloadi16, II_LH,
addrDefault>, MMRel, LW_FM<0x21>;
def LHu : LoadMemory<"lhu", GPR32Opnd, mem_simm16, zextloadi16, II_LHU>,
MMRel, LW_FM<0x25>;
def LW : StdMMR6Rel, Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel, def LW : StdMMR6Rel, Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
LW_FM<0x23>; LW_FM<0x23>;
} }
def SB : StdMMR6Rel, Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, def SB : StdMMR6Rel, Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel,
LW_FM<0x28>; LW_FM<0x28>;
def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>; def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>; def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
} }
▲ Show 20 Lines • Show All 749 Lines • ▼ Show 20 Lines
// Mips does not have "not", so we expand our way // Mips does not have "not", so we expand our way
def : MipsPat<(not GPR32:$in), def : MipsPat<(not GPR32:$in),
(NOR GPR32Opnd:$in, ZERO)>; (NOR GPR32Opnd:$in, ZERO)>;
} }
// extended loads // extended loads
def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
let AdditionalPredicates = [NotInMicroMips] in {
def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
}
// peepholes // peepholes
def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
// brcond patterns // brcond patterns
multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
Instruction SLTiuOp, Register ZEROReg> { Instruction SLTiuOp, Register ZEROReg> {
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
defm : SetgeImmPats<GPR32, SLTi, SLTiu>; defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
// bswap pattern // bswap pattern
def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>; def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
// Load halfword/word patterns. // Load halfword/word patterns.
let AddedComplexity = 40 in { let AddedComplexity = 40 in {
def : LoadRegImmPat<LBu, i32, zextloadi8>; def : LoadRegImmPat<LBu, i32, zextloadi8>;
def : LoadRegImmPat<LH, i32, sextloadi16>;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def : LoadRegImmPat<LH, i32, sextloadi16>;
def : LoadRegImmPat<LW, i32, load>; def : LoadRegImmPat<LW, i32, load>;
} }
} }
// Atomic load patterns. // Atomic load patterns.
def : MipsPat<(atomic_load_8 addr:$a), (LB addr:$a)>; def : MipsPat<(atomic_load_8 addr:$a), (LB addr:$a)>;
let AdditionalPredicates = [NotInMicroMips] in {
def : MipsPat<(atomic_load_16 addr:$a), (LH addr:$a)>; def : MipsPat<(atomic_load_16 addr:$a), (LH addr:$a)>;
}
def : MipsPat<(atomic_load_32 addr:$a), (LW addr:$a)>; def : MipsPat<(atomic_load_32 addr:$a), (LW addr:$a)>;
// Atomic store patterns. // Atomic store patterns.
def : MipsPat<(atomic_store_8 addr:$a, GPR32:$v), (SB GPR32:$v, addr:$a)>; def : MipsPat<(atomic_store_8 addr:$a, GPR32:$v), (SB GPR32:$v, addr:$a)>;
def : MipsPat<(atomic_store_16 addr:$a, GPR32:$v), (SH GPR32:$v, addr:$a)>; def : MipsPat<(atomic_store_16 addr:$a, GPR32:$v), (SH GPR32:$v, addr:$a)>;
def : MipsPat<(atomic_store_32 addr:$a, GPR32:$v), (SW GPR32:$v, addr:$a)>; def : MipsPat<(atomic_store_32 addr:$a, GPR32:$v), (SW GPR32:$v, addr:$a)>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 44 Lines • Show Last 20 Lines

test/CodeGen/Mips/llvm-ir/lh_lhu.ll

  • This file was added.
; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips -relocation-model=pic | FileCheck %s
; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s
sdardisUnsubmitted
Not Done
ReplyInline Actions

Check microMIPS64r6 as well.

sdardis: Check microMIPS64r6 as well.
@us = global i16 0, align 2
define i32 @lhfunc() {
entry:
; CHECK-LABEL: lhfunc
; CHECK: lh $[[REG1:[0-9]+]], 0(${{[0-9]+}})
%0 = load i16, i16* @us, align 2
%conv = sext i16 %0 to i32
ret i32 %conv
}
define i16 @lhfunc_atomic() {
entry:
; CHECK-LABEL: lhfunc_atomic
; CHECK: lh $[[REG1:[0-9]+]], 0(${{[0-9]+}})
%0 = load atomic i16, i16* @us acquire, align 2
ret i16 %0
}
define i32 @lhufunc() {
entry:
; CHECK-LABEL: lhufunc
; CHECK: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
%0 = load i16, i16* @us, align 2
%conv = zext i16 %0 to i32
ret i32 %conv
}

test/MC/Disassembler/Mips/micromips32r6/valid.txt

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
0x00 0xa4 0x19 0x98 # CHECK: divu $3, $4, $5 0x00 0xa4 0x19 0x98 # CHECK: divu $3, $4, $5
0x00 0x00 0x18 0x00 # CHECK: ehb 0x00 0x00 0x18 0x00 # CHECK: ehb
0x00 0x00 0x57 0x7c # CHECK: ei 0x00 0x00 0x57 0x7c # CHECK: ei
0x00 0x0a 0x57 0x7c # CHECK: ei $10 0x00 0x0a 0x57 0x7c # CHECK: ei $10
0x00 0x00 0xf3 0x7c # CHECK: eret 0x00 0x00 0xf3 0x7c # CHECK: eret
0x00 0x01 0xf3 0x7c # CHECK: eretnc 0x00 0x01 0xf3 0x7c # CHECK: eretnc
0x80 0x05 0x01 0x00 # CHECK: jialc $5, 256 0x80 0x05 0x01 0x00 # CHECK: jialc $5, 256
0xa0 0x05 0x01 0x00 # CHECK: jic $5, 256 0xa0 0x05 0x01 0x00 # CHECK: jic $5, 256
0x3c 0x44 0x00 0x08 # CHECK: lh $2, 8($4)
0x60 0x82 0x6a 0x08 # CHECK: lhe $4, 8($2)
0x34 0x82 0x00 0x08 # CHECK: lhu $4, 8($2)
0x60 0x82 0x62 0x08 # CHECK: lhue $4, 8($2)
0x78 0x48 0x00 0x43 # CHECK: lwpc $2, 268 0x78 0x48 0x00 0x43 # CHECK: lwpc $2, 268
0x00 0x43 0x26 0x0f # CHECK: lsa $2, $3, $4, 4 0x00 0x43 0x26 0x0f # CHECK: lsa $2, $3, $4, 4
0x00 0xa4 0x19 0x58 # CHECK: mod $3, $4, $5 0x00 0xa4 0x19 0x58 # CHECK: mod $3, $4, $5
0x00 0xa4 0x19 0xd8 # CHECK: modu $3, $4, $5 0x00 0xa4 0x19 0xd8 # CHECK: modu $3, $4, $5
0x00 0xa4 0x18 0x18 # CHECK: mul $3, $4, $5 0x00 0xa4 0x18 0x18 # CHECK: mul $3, $4, $5
0x00 0xa4 0x18 0x58 # CHECK: muh $3, $4, $5 0x00 0xa4 0x18 0x58 # CHECK: muh $3, $4, $5
0x00 0xa4 0x18 0x98 # CHECK: mulu $3, $4, $5 0x00 0xa4 0x18 0x98 # CHECK: mulu $3, $4, $5
0x00 0xa4 0x18 0xd8 # CHECK: muhu $3, $4, $5 0x00 0xa4 0x18 0xd8 # CHECK: muhu $3, $4, $5
▲ Show 20 Lines • Show All 179 Lines • ▼ Show 20 Lines
0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3 0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3
0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8 0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8
0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3 0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3
0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4 0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4
0x00 0x00 0x47 0x7c # CHECK: di 0x00 0x00 0x47 0x7c # CHECK: di
0x00 0x0f 0x47 0x7c # CHECK: di $15 0x00 0x0f 0x47 0x7c # CHECK: di $15
0x00 0x00 0x43 0x7c # CHECK: tlbinv 0x00 0x00 0x43 0x7c # CHECK: tlbinv
0x00 0x00 0x53 0x7c # CHECK: tlbinvf 0x00 0x00 0x53 0x7c # CHECK: tlbinvf
0x00 0xa9 0x02 0xfc # CHECK: mtc0 $5, $9, 0 0x00 0xa9 0x02 0xfc # CHECK: mtc0 $5, $9, 0
0x00 0xa9 0x02 0xfc # CHECK: mtc0 $5, $9 0x00 0xa9 0x02 0xfc # CHECK: mtc0 $5, $9
0x00 0x22 0x3a 0xfc # CHECK: mtc0 $1, $2, 7 0x00 0x22 0x3a 0xfc # CHECK: mtc0 $1, $2, 7
0x54 0x64 0x28 0x3b # CHECK: mtc1 $3, $f4 0x54 0x64 0x28 0x3b # CHECK: mtc1 $3, $f4
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Can you sort these alphabetically into the existing instructions?

sdardis: Can you sort these alphabetically into the existing instructions?
0x00 0xa6 0x5d 0x3c # CHECK: mtc2 $5, $6 0x00 0xa6 0x5d 0x3c # CHECK: mtc2 $5, $6
0x00 0xe8 0x02 0xf4 # CHECK: mthc0 $7, $8, 0 0x00 0xe8 0x02 0xf4 # CHECK: mthc0 $7, $8, 0
0x00 0xe8 0x02 0xf4 # CHECK: mthc0 $7, $8 0x00 0xe8 0x02 0xf4 # CHECK: mthc0 $7, $8
0x01 0x2a 0x0a 0xf4 # CHECK: mthc0 $9, $10, 1 0x01 0x2a 0x0a 0xf4 # CHECK: mthc0 $9, $10, 1
0x55 0x6c 0x38 0x3b # CHECK: mthc1 $11, $f12 0x55 0x6c 0x38 0x3b # CHECK: mthc1 $11, $f12
0x01 0xae 0x9d 0x3c # CHECK: mthc2 $13, $14 0x01 0xae 0x9d 0x3c # CHECK: mthc2 $13, $14
0x00 0x67 0x00 0xfc # CHECK: mfc0 $3, $7, 0 0x00 0x67 0x00 0xfc # CHECK: mfc0 $3, $7, 0
0x00 0x67 0x18 0xfc # CHECK: mfc0 $3, $7, 3 0x00 0x67 0x18 0xfc # CHECK: mfc0 $3, $7, 3
Show All 21 Lines

test/MC/Disassembler/Mips/micromips64r6/valid.txt

Show First 20 Lines • Show All 232 Lines • ▼ Show 20 Lines
0x00 0x83 0x38 0x40 # CHECK: srl $4, $3, 7 0x00 0x83 0x38 0x40 # CHECK: srl $4, $3, 7
0x00 0x65 0x10 0x50 # CHECK: srlv $2, $3, $5 0x00 0x65 0x10 0x50 # CHECK: srlv $2, $3, $5
0x58 0x62 0x09 0x90 # CHECK: dsub $1, $2, $3 0x58 0x62 0x09 0x90 # CHECK: dsub $1, $2, $3
0x59 0xe7 0x19 0xd0 # CHECK: dsubu $3, $7, $15 0x59 0xe7 0x19 0xd0 # CHECK: dsubu $3, $7, $15
0x59 0xe0 0x39 0x90 # CHECK: dneg $7, $15 0x59 0xe0 0x39 0x90 # CHECK: dneg $7, $15
0x59 0x40 0x51 0x90 # CHECK: dneg $10, $10 0x59 0x40 0x51 0x90 # CHECK: dneg $10, $10
0x59 0x60 0x09 0xd0 # CHECK: dnegu $1, $11 0x59 0x60 0x09 0xd0 # CHECK: dnegu $1, $11
0x58 0xa0 0x29 0xd0 # CHECK: dnegu $5, $5 0x58 0xa0 0x29 0xd0 # CHECK: dnegu $5, $5
0x3c 0x44 0x00 0x08 # CHECK: lh $2, 8($4)
0x60 0x82 0x6a 0x08 # CHECK: lhe $4, 8($2)
0x34 0x82 0x00 0x08 # CHECK: lhu $4, 8($2)
0x60 0x82 0x62 0x08 # CHECK: lhue $4, 8($2)

test/MC/Mips/micromips/invalid.s

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Lines# RUN: FileCheck %s < %t1
sce $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction sce $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
sce $4, 8($33) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset sce $4, 8($33) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
sce $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset sce $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
sce $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset sce $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
she $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction she $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
she $4, 8($33) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset she $4, 8($33) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
she $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset she $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
she $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset she $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
lh $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhe $34, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhu $35, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhue $36, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lh $2, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
lhe $4, 8($33) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
lhu $4, 8($35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
lhue $4, 8($37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
lh $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
lh $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
lhe $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
lhe $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
lhu $4, -65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
lhu $4, 65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
lhue $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset

test/MC/Mips/micromips32r6/invalid.s

Show First 20 Lines • Show All 166 Lines • ▼ Show 20 Lines# RUN: FileCheck %s < %t1
sce $4, 8($33) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset sce $4, 8($33) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
sce $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset sce $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
sce $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset sce $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
she $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction she $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
she $4, 8($33) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset she $4, 8($33) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
she $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset she $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
she $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset she $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
swe $5, -513($4) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset swe $5, -513($4) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
lh $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhe $34, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhu $35, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhue $36, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lh $2, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
lhe $4, 8($33) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
lhu $4, 8($35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
lhue $4, 8($37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
lh $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
lh $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
lhe $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
lhe $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
lhu $4, -65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
lhu $4, 65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
lhue $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset

test/MC/Mips/micromips32r6/valid.s

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips | FileCheck %s
di $15 # CHECK: di $15 # encoding: [0x00,0x0f,0x47,0x7c] di $15 # CHECK: di $15 # encoding: [0x00,0x0f,0x47,0x7c]
eret # CHECK: eret # encoding: [0x00,0x00,0xf3,0x7c] eret # CHECK: eret # encoding: [0x00,0x00,0xf3,0x7c]
eretnc # CHECK: eretnc # encoding: [0x00,0x01,0xf3,0x7c] eretnc # CHECK: eretnc # encoding: [0x00,0x01,0xf3,0x7c]
jalr $9 # CHECK: jalr $9 # encoding: [0x45,0x2b] jalr $9 # CHECK: jalr $9 # encoding: [0x45,0x2b]
jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0x80,0x05,0x01,0x00] jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0x80,0x05,0x01,0x00]
jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xa0,0x05,0x01,0x00] jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xa0,0x05,0x01,0x00]
jrc16 $9 # CHECK: jrc16 $9 # encoding: [0x45,0x23] jrc16 $9 # CHECK: jrc16 $9 # encoding: [0x45,0x23]
jrcaddiusp 20 # CHECK: jrcaddiusp 20 # encoding: [0x44,0xb3] jrcaddiusp 20 # CHECK: jrcaddiusp 20 # encoding: [0x44,0xb3]
lh $2, 8($4) # CHECK: lh $2, 8($4) # encoding: [0x3c,0x44,0x00,0x08]
lhe $4, 8($2) # CHECK: lhe $4, 8($2) # encoding: [0x60,0x82,0x6a,0x08]
lhu $4, 8($2) # CHECK: lhu $4, 8($2) # encoding: [0x34,0x82,0x00,0x08]
lhue $4, 8($2) # CHECK: lhue $4, 8($2) # encoding: [0x60,0x82,0x62,0x08]
lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x43,0x24,0x0f] lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x43,0x24,0x0f]
lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0x78,0x48,0x00,0x43] lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0x78,0x48,0x00,0x43]
lwm $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22] lwm $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22]
lwm16 $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22] lwm16 $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22]
mod $3, $4, $5 # CHECK: mod $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x58] mod $3, $4, $5 # CHECK: mod $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x58]
modu $3, $4, $5 # CHECK: modu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xd8] modu $3, $4, $5 # CHECK: modu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xd8]
mul $3, $4, $5 # CHECK mul $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x18] mul $3, $4, $5 # CHECK mul $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x18]
muh $3, $4, $5 # CHECK muh $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x58] muh $3, $4, $5 # CHECK muh $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x58]
▲ Show 20 Lines • Show All 188 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips | FileCheck %s
seleqz.d $f2, $f4, $f8 # CHECK: seleqz.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x38] seleqz.d $f2, $f4, $f8 # CHECK: seleqz.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x38]
selnez.s $f1, $f2, $f3 # CHECK: selnez.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x78] selnez.s $f1, $f2, $f3 # CHECK: selnez.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x78]
selnez.d $f2, $f4, $f8 # CHECK: selnez.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x78] selnez.d $f2, $f4, $f8 # CHECK: selnez.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x78]
class.s $f2, $f3 # CHECK: class.s $f2, $f3 # encoding: [0x54,0x62,0x00,0x60] class.s $f2, $f3 # CHECK: class.s $f2, $f3 # encoding: [0x54,0x62,0x00,0x60]
class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x54,0x82,0x02,0x60] class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x54,0x82,0x02,0x60]
deret # CHECK: deret # encoding: [0x00,0x00,0xe3,0x7c] deret # CHECK: deret # encoding: [0x00,0x00,0xe3,0x7c]
tlbinv # CHECK: tlbinv # encoding: [0x00,0x00,0x43,0x7c] tlbinv # CHECK: tlbinv # encoding: [0x00,0x00,0x43,0x7c]
tlbinvf # CHECK: tlbinvf # encoding: [0x00,0x00,0x53,0x7c] tlbinvf # CHECK: tlbinvf # encoding: [0x00,0x00,0x53,0x7c]
mtc0 $5, $9 # CHECK: mtc0 $5, $9, 0 # encoding: [0x00,0xa9,0x02,0xfc] mtc0 $5, $9 # CHECK: mtc0 $5, $9, 0 # encoding: [0x00,0xa9,0x02,0xfc]
mtc0 $1, $2, 7 # CHECK: mtc0 $1, $2, 7 # encoding: [0x00,0x22,0x3a,0xfc] mtc0 $1, $2, 7 # CHECK: mtc0 $1, $2, 7 # encoding: [0x00,0x22,0x3a,0xfc]
mtc1 $3, $f4 # CHECK: mtc1 $3, $f4 # encoding: [0x54,0x64,0x28,0x3b] mtc1 $3, $f4 # CHECK: mtc1 $3, $f4 # encoding: [0x54,0x64,0x28,0x3b]
mtc2 $5, $6 # CHECK: mtc2 $5, $6 # encoding: [0x00,0xa6,0x5d,0x3c] mtc2 $5, $6 # CHECK: mtc2 $5, $6 # encoding: [0x00,0xa6,0x5d,0x3c]
sdardisUnsubmitted
Not Done
ReplyInline Actions

Can you sort these alphabetically into the first 100~ instructions.

sdardis: Can you sort these alphabetically into the first 100~ instructions.
mthc0 $7, $8 # CHECK: mthc0 $7, $8, 0 # encoding: [0x00,0xe8,0x02,0xf4] mthc0 $7, $8 # CHECK: mthc0 $7, $8, 0 # encoding: [0x00,0xe8,0x02,0xf4]
mthc0 $9, $10, 1 # CHECK: mthc0 $9, $10, 1 # encoding: [0x01,0x2a,0x0a,0xf4] mthc0 $9, $10, 1 # CHECK: mthc0 $9, $10, 1 # encoding: [0x01,0x2a,0x0a,0xf4]
mthc1 $11, $f12 # CHECK: mthc1 $11, $f12 # encoding: [0x55,0x6c,0x38,0x3b] mthc1 $11, $f12 # CHECK: mthc1 $11, $f12 # encoding: [0x55,0x6c,0x38,0x3b]
mthc2 $13, $14 # CHECK: mthc2 $13, $14 # encoding: [0x01,0xae,0x9d,0x3c] mthc2 $13, $14 # CHECK: mthc2 $13, $14 # encoding: [0x01,0xae,0x9d,0x3c]
mfc0 $3, $7 # CHECK: mfc0 $3, $7, 0 # encoding: [0x00,0x67,0x00,0xfc] mfc0 $3, $7 # CHECK: mfc0 $3, $7, 0 # encoding: [0x00,0x67,0x00,0xfc]
mfc0 $3, $7, 3 # CHECK: mfc0 $3, $7, 3 # encoding: [0x00,0x67,0x18,0xfc] mfc0 $3, $7, 3 # CHECK: mfc0 $3, $7, 3 # encoding: [0x00,0x67,0x18,0xfc]
mfc1 $5, $f10 # CHECK: mfc1 $5, $f10 # encoding: [0x54,0xaa,0x20,0x3b] mfc1 $5, $f10 # CHECK: mfc1 $5, $f10 # encoding: [0x54,0xaa,0x20,0x3b]
mfc2 $15, $5 # CHECK: mfc2 $15, $5 # encoding: [0x01,0xe5,0x4d,0x3c] mfc2 $15, $5 # CHECK: mfc2 $15, $5 # encoding: [0x01,0xe5,0x4d,0x3c]
Show All 28 Lines

test/MC/Mips/micromips64r6/invalid.s

Show First 20 Lines • Show All 198 Lines • ▼ Show 20 Lines# RUN: FileCheck %s < %t1
she $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction she $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
she $4, 8($33) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset she $4, 8($33) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
she $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset she $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
she $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset she $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
swe $33, 8($4) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction swe $33, 8($4) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
swe $5, 8($34) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset swe $5, 8($34) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
swe $5, 512($4) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset swe $5, 512($4) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
swe $5, -513($4) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset swe $5, -513($4) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
lh $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhe $34, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhu $35, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhue $36, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lh $2, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
lhe $4, 8($33) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
lhu $4, 8($35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
lhue $4, 8($37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
lh $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
lh $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
lhe $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
lhe $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
lhu $4, -65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
lhu $4, 65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
lhue $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset

test/MC/Mips/micromips64r6/valid.s

Show First 20 Lines • Show All 154 Lines • ▼ Show 20 Linesa:
ceil.l.d $f1, $f3 # CHECK: ceil.l.d $f1, $f3 # encoding: [0x54,0x23,0x53,0x3b] ceil.l.d $f1, $f3 # CHECK: ceil.l.d $f1, $f3 # encoding: [0x54,0x23,0x53,0x3b]
floor.l.s $f1, $f3 # CHECK: floor.l.s $f1, $f3 # encoding: [0x54,0x23,0x03,0x3b] floor.l.s $f1, $f3 # CHECK: floor.l.s $f1, $f3 # encoding: [0x54,0x23,0x03,0x3b]
floor.l.d $f1, $f3 # CHECK: floor.l.d $f1, $f3 # encoding: [0x54,0x23,0x43,0x3b] floor.l.d $f1, $f3 # CHECK: floor.l.d $f1, $f3 # encoding: [0x54,0x23,0x43,0x3b]
tlbinv # CHECK: tlbinv # encoding: [0x00,0x00,0x43,0x7c] tlbinv # CHECK: tlbinv # encoding: [0x00,0x00,0x43,0x7c]
tlbinvf # CHECK: tlbinvf # encoding: [0x00,0x00,0x53,0x7c] tlbinvf # CHECK: tlbinvf # encoding: [0x00,0x00,0x53,0x7c]
dinsu $4, $2, 32, 5 # CHECK: dinsu $4, $2, 32, 5 # encoding: [0x58,0x82,0x20,0x34] dinsu $4, $2, 32, 5 # CHECK: dinsu $4, $2, 32, 5 # encoding: [0x58,0x82,0x20,0x34]
dinsm $4, $2, 3, 5 # CHECK: dinsm $4, $2, 3, 5 # encoding: [0x58,0x82,0x38,0xc4] dinsm $4, $2, 3, 5 # CHECK: dinsm $4, $2, 3, 5 # encoding: [0x58,0x82,0x38,0xc4]
dins $4, $2, 3, 5 # CHECK: dins $4, $2, 3, 5 # encoding: [0x58,0x82,0x38,0xcc] dins $4, $2, 3, 5 # CHECK: dins $4, $2, 3, 5 # encoding: [0x58,0x82,0x38,0xcc]
lh $2, 8($4) # CHECK: lh $2, 8($4) # encoding: [0x3c,0x44,0x00,0x08]
lhe $4, 8($2) # CHECK: lhe $4, 8($2) # encoding: [0x60,0x82,0x6a,0x08]
lhu $4, 8($2) # CHECK: lhu $4, 8($2) # encoding: [0x34,0x82,0x00,0x08]
lhue $4, 8($2) # CHECK: lhue $4, 8($2) # encoding: [0x60,0x82,0x62,0x08]
mtc0 $5, $9 # CHECK: mtc0 $5, $9, 0 # encoding: [0x00,0xa9,0x02,0xfc] mtc0 $5, $9 # CHECK: mtc0 $5, $9, 0 # encoding: [0x00,0xa9,0x02,0xfc]
mtc0 $1, $2, 7 # CHECK: mtc0 $1, $2, 7 # encoding: [0x00,0x22,0x3a,0xfc] mtc0 $1, $2, 7 # CHECK: mtc0 $1, $2, 7 # encoding: [0x00,0x22,0x3a,0xfc]
mtc1 $3, $f4 # CHECK: mtc1 $3, $f4 # encoding: [0x54,0x64,0x28,0x3b] mtc1 $3, $f4 # CHECK: mtc1 $3, $f4 # encoding: [0x54,0x64,0x28,0x3b]
mtc2 $5, $6 # CHECK: mtc2 $5, $6 # encoding: [0x00,0xa6,0x5d,0x3c] mtc2 $5, $6 # CHECK: mtc2 $5, $6 # encoding: [0x00,0xa6,0x5d,0x3c]
mthc0 $7, $8 # CHECK: mthc0 $7, $8, 0 # encoding: [0x00,0xe8,0x02,0xf4] mthc0 $7, $8 # CHECK: mthc0 $7, $8, 0 # encoding: [0x00,0xe8,0x02,0xf4]
mthc0 $9, $10, 1 # CHECK: mthc0 $9, $10, 1 # encoding: [0x01,0x2a,0x0a,0xf4] mthc0 $9, $10, 1 # CHECK: mthc0 $9, $10, 1 # encoding: [0x01,0x2a,0x0a,0xf4]
mthc1 $11, $f12 # CHECK: mthc1 $11, $f12 # encoding: [0x55,0x6c,0x38,0x3b] mthc1 $11, $f12 # CHECK: mthc1 $11, $f12 # encoding: [0x55,0x6c,0x38,0x3b]
mthc2 $13, $14 # CHECK: mthc2 $13, $14 # encoding: [0x01,0xae,0x9d,0x3c] mthc2 $13, $14 # CHECK: mthc2 $13, $14 # encoding: [0x01,0xae,0x9d,0x3c]
▲ Show 20 Lines • Show All 63 Lines • Show Last 20 Lines

test/MC/Mips/mips32r6/invalid.s

Show All 14 Lineslocal_label:
swc2 $25,24880($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled swc2 $25,24880($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
break -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate break -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
break 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate break 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
break -1, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate break -1, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
break 1024, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate break 1024, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
break 7, -1 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate break 7, -1 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate
break 7, 1024 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate break 7, 1024 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate
break 1024, 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate break 1024, 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
lh $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhe $34, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhu $35, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhue $36, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lh $2, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
lhe $4, 8($33) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
lhu $4, 8($35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
lhue $4, 8($37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
lh $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
lh $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
lhe $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
lhe $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
lhu $4, -65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
lhu $4, 65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
lhue $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
// FIXME: Following tests are temporarely disabled, until "PredicateControl not in hierarchy" problem is resolved // FIXME: Following tests are temporarely disabled, until "PredicateControl not in hierarchy" problem is resolved
bltl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bltl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bltul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bltul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
blel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled blel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bleul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bleul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bgel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bgel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bgeul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bgeul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bgtl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bgtl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Show All 23 Lines

test/MC/Mips/mips64r6/invalid.s

Show All 14 Lines .set noat
ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
break -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate break -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
break 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate break 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
break -1, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate break -1, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
break 1024, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate break 1024, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
break 7, -1 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate break 7, -1 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate
break 7, 1024 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate break 7, 1024 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate
break 1024, 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate break 1024, 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
lh $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhe $34, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhu $35, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhue $36, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lh $2, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
lhe $4, 8($33) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
lhu $4, 8($35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
lhue $4, 8($37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
lh $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
lh $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
lhe $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
lhe $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
lhu $4, -65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
lhu $4, 65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
lhue $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
// FIXME: Following tests are temporarely disabled, until "PredicateControl not in hierarchy" problem is resolved // FIXME: Following tests are temporarely disabled, until "PredicateControl not in hierarchy" problem is resolved
bltl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bltl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bltul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bltul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
blel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled blel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bleul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bleul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bgel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bgel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bgeul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bgeul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bgtl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bgtl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Show All 19 Lines