[mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructions

[hvarga]

Summary

This patch implements microMIPS32r6 SLT, SLTI, SLTIU and SLTU instructions.

There was a problem with the previous implementation of this patch (D19354) and because of that commit rL267137 was reverted.
After committing of the previous patch, test-suite failed with error message in the form of:

fatal error: error in backend: Cannot select: t21: i32 = setcc t2, Constant:i32<6>, setgt:ch

There was a problem with selecting SLT instruction in LLVM backend.

For that reason, it is decided to revert commit rL267137 and make this patch which besides implementation of instructions and standard regression tests also includes one additional CodeGen test (slt.ll).

[sdardis]

Some nits. Can you extend the rest of the set*.ll tests?

lib/Target/Mips/MicroMipsInstrInfo.td

1009 ↗

(On Diff #56103)

The SetgeImmPats patterns can be included for microMIPS if you extend that parameter list to include XOR_MM like the SeqeqPats patterns.

1047 ↗

(On Diff #56103)

Also include the "sltu $rs, $rt, $imm" alias.

lib/Target/Mips/MipsInstrInfo.td

2189–2191 ↗

(On Diff #56103)

This alias should be included in [NotinMicroMips].

2576 ↗

(On Diff #56103)

See my above comment on extending SetgeImmPats.

test/CodeGen/Mips/slt.ll

4 ↗

(On Diff #56103)

Use a CHECK-LABEL: to match the function here, and write a CHECK line that matches slt taking $4 as one of it operands as its an argument register or just "CHECK: slt".

9 ↗

(On Diff #56103)

Same here.

[hvarga]

Added MipsPats for conditional branches in MicroMips.
Added predicate NotInMicroMips for existing Mips implementations.
Added cases for BNE_MM and BEQ_MM in getAnalyzableBrOpc, getEquivalentCompactForm and getOppositeBranchOpc.
Added tests for microMips in set*.ll files.

This update has been contributed by @mamidzic.

[sdardis]

Two major points: The multiclass patterns you've copied can instead be extended. LUi is also covered in a NotInMicroMips predicate. The rest is just formatting nits over the assembly. More details inline.

Thanks.

lib/Target/Mips/MicroMipsInstrInfo.td

1040–1069 ↗

(On Diff #62472)

This multiclass definition is unnecessary. Instead, change BrcondPats in MipsInstrInfo.td so that the pattern is using BEQ instead use BEQOp. You can then instantiate the pattern for microMIPS.

1071–1077 ↗

(On Diff #62472)

Similarly here. You can extend SetgeImmPats in MipsInstrInfo.td to take and XORiOp parameter.

1082–1086 ↗

(On Diff #62472)

With the changes you've made here, some of those patterns (SetlePats, SetgtPats) combine microMIPS and MIPS instructions.

For these multiclass instantiations, extend the definitions in MipsInstroInfo.td to take an XORiOp parameter.

1123–1126 ↗

(On Diff #62472)

Align the simm32_relaxed:$imm under GPR32Opnd like:

def : MipsInstAlias<"sltu $rs, $rt, $imm",
                    (SLTiu_MM GPR32Opnd:$rs, GPR32Opnd:$rt,
                              simm32_relaxed:$imm), 0>;

lib/Target/Mips/MipsInstrInfo.td

1694 ↗

(On Diff #62472)

Move LUi out of this NotInMicromips block.

test/CodeGen/Mips/brconlt.ll

17 ↗

(On Diff #62472)

Formatting: line up the sltius in the immediate block so that they are all in the same column, one space after the longest check prefix. And in the other cases below.

test/CodeGen/Mips/setcc-se.ll

9 ↗

(On Diff #62472)

Can you instead match this with "<MCInst #{{[0-9]+}} SLTiu_MM" ? And the other cases below, as it a better match to the expected output.

[hvarga]

Reworked BrcondPats, SetlePats, SetgePats and SetgeImmPats multiclasses so that they can work for microMips too without interfering with the existing implementations.
Micromips now extends Mips BrcondPats, SeteqPats, SetlePats, SetgtPats, SetgePats and SetgeImmPats multiclasses.
Fixed LUi being in the notInMicroMips predicate block.
Changed the indentations on test files according to the comments.

This update has been contributed by @mamidzic.

[sdardis]

LGTM with two things: move the BrcondPats out of the NotInMicroMips block, otherwise we get the same bug that this patch addresses, except it affects microMIPS64R6. The second is the placement of a comment. More details inline.

lib/Target/Mips/Mips64InstrInfo.td

539–540 ↗

(On Diff #63777)

By moving the pattern instantiation into the block covered by NotInMicroMips, LLVM cannot fall back to picking MIPS64R6 instructions for microMIPS64R6. The instruction mapping tables will correct this for direct object emission and the assembly is identical for microMIPS64R6.

Can you move this out of the NotInMicroMips block?

549 ↗

(On Diff #63777)

Place this comment above the 'let AdditionalPredicates..' line.

llvm/trunk/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp

case Mips::BEQ_MM:
     // beq $r0, $zero, $L2 => beqz $r0, $L2
     return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) &&
             printAlias("b", MI, 2, OS)) ||
            (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS));
   case Mips::BEQ64:
     // beq $r0, $zero, $L2 => beqz $r0, $L2
     return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS);
   case Mips::BNE:
+  case Mips::BNE_MM:
     // bne $r0, $zero, $L2 => bnez $r0, $L2
     return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
   case Mips::BNE64:
     // bne $r0, $zero, $L2 => bnez $r0, $L2
     return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
   case Mips::BGEZAL:
     // bgezal $zero, $L1 => bal $L1
     return isReg<Mips::ZERO>(MI, 0) && printAlias("bal", MI, 1, OS);

llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td

let AddedComplexity = 40 in {
   def : MipsPat<(i32 (sextloadi16 addrRegImm:$a)),
                 (LH_MM addrRegImm:$a)>;
 }
 def : MipsPat<(atomic_load_16 addr:$a),
               (LH_MM addr:$a)>;
 def : MipsPat<(i32 (extloadi16 addr:$src)),
               (LHu_MM addr:$src)>;
 
+defm : BrcondPats<GPR32, BEQ_MM, BEQ_MM, BNE_MM, SLT_MM, SLTu_MM, SLTi_MM,
+                  SLTiu_MM, ZERO>;
+
+defm : SeteqPats<GPR32, SLTiu_MM, XOR_MM, SLTu_MM, ZERO>;
+defm : SetlePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>;
+defm : SetgtPats<GPR32, SLT_MM, SLTu_MM>;
+defm : SetgePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>;
+defm : SetgeImmPats<GPR32, XORi_MM, SLTi_MM, SLTiu_MM>;
+
 //===----------------------------------------------------------------------===//
 // MicroMips instruction aliases
 //===----------------------------------------------------------------------===//
 
 class UncondBranchMMPseudo<string opstr> :
   MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
                     !strconcat(opstr, "\t$offset")>;
 
let Predicates = [InMicroMips] in {
   def : MipsInstAlias<"tgeu $rs, $rt",
                       (TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
   def : MipsInstAlias<"tlt $rs, $rt",
                       (TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
   def : MipsInstAlias<"tltu $rs, $rt",
                       (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
   def : MipsInstAlias<"tne $rs, $rt",
                       (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
+  def : MipsInstAlias<"slt $rs, $rt, $imm",
+                      (SLTi_MM GPR32Opnd:$rs, GPR32Opnd:$rt,
+                               simm32_relaxed:$imm), 0>;
+  def : MipsInstAlias<"sltu $rs, $rt, $imm",
+                      (SLTiu_MM GPR32Opnd:$rs, GPR32Opnd:$rt,
+                                simm32_relaxed:$imm), 0>;
   def : MipsInstAlias<"sll $rd, $rt, $rs",
                       (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
   def : MipsInstAlias<"sra $rd, $rt, $rs",
                       (SRAV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
   def : MipsInstAlias<"srl $rd, $rt, $rs",
                       (SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
   def : MipsInstAlias<"sll $rd, $rt",
                       (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
let Predicates = [InMicroMips] in {
   def : MipsInstAlias<"or $rs, $imm",
                       (ORi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
   def : MipsInstAlias<"xor $rs, $rt, $imm",
                       (XORi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
   def : MipsInstAlias<"xor $rs, $imm",
                       (XORi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
   def : MipsInstAlias<"not $rt, $rs",
                       (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
+  def : MipsInstAlias<"bnez $rs,$offset",
+                      (BNE_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
+  def : MipsInstAlias<"beqz $rs,$offset",
+                      (BEQ_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
 }

llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td

let AdditionalPredicates = [NotInMicroMips] in {
   def : WrapperPat<tglobaladdr, DADDiu, GPR64>;
   def : WrapperPat<tconstpool, DADDiu, GPR64>;
   def : WrapperPat<texternalsym, DADDiu, GPR64>;
   def : WrapperPat<tblockaddress, DADDiu, GPR64>;
   def : WrapperPat<tjumptable, DADDiu, GPR64>;
   def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>;
 }
 
-defm : BrcondPats<GPR64, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
+defm : BrcondPats<GPR64, BEQ64, BEQ, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
                   ZERO_64>;
-
 def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
               (BLEZ64 i64:$lhs, bb:$dst)>;
 def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
               (BGEZ64 i64:$lhs, bb:$dst)>;
 
 // setcc patterns
+let AdditionalPredicates = [NotInMicroMips] in {
   defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>;
-defm : SetlePats<GPR64, SLT64, SLTu64>;
+  defm : SetlePats<GPR64, XORi, SLT64, SLTu64>;
   defm : SetgtPats<GPR64, SLT64, SLTu64>;
-defm : SetgePats<GPR64, SLT64, SLTu64>;
-defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>;
-
+  defm : SetgePats<GPR64, XORi, SLT64, SLTu64>;
+  defm : SetgeImmPats<GPR64, XORi, SLTi64, SLTiu64>;
+}
 // truncate
 def : MipsPat<(trunc (assertsext GPR64:$src)),
               (EXTRACT_SUBREG GPR64:$src, sub_32)>;
 // The forward compatibility strategy employed by MIPS requires us to treat
 // values as being sign extended to an infinite number of bits. This allows
 // existing software to run without modification on any future MIPS
 // implementation (e.g. 128-bit, or 1024-bit). Being compatible with this
 // strategy requires that truncation acts as a sign-extension for values being

llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp

 unsigned MipsInstrInfo::getEquivalentCompactForm(
     const MachineBasicBlock::iterator I) const {
   unsigned Opcode = I->getOpcode();
   bool canUseShortMicroMipsCTI = false;
 
   if (Subtarget.inMicroMipsMode()) {
     switch (Opcode) {
     case Mips::BNE:
+    case Mips::BNE_MM:
     case Mips::BEQ:
+    case Mips::BEQ_MM:
     // microMIPS has NE,EQ branches that do not have delay slots provided one
     // of the operands is zero.
       if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg())
         canUseShortMicroMipsCTI = true;
       break;
     // For microMIPS the PseudoReturn and PseudoIndirectBranch are always
     // expanded to JR_MM, so they can be replaced with JRC16_MM.
     case Mips::JR:
unsigned MipsInstrInfo::getEquivalentCompactForm(
 
   if (Subtarget.hasMips32r6() || canUseShortMicroMipsCTI) {
     switch (Opcode) {
     case Mips::B:
       return Mips::BC;
     case Mips::BAL:
       return Mips::BALC;
     case Mips::BEQ:
+    case Mips::BEQ_MM:
       if (canUseShortMicroMipsCTI)
         return Mips::BEQZC_MM;
       else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
         return 0;
       return Mips::BEQC;
     case Mips::BNE:
+    case Mips::BNE_MM:
       if (canUseShortMicroMipsCTI)
         return Mips::BNEZC_MM;
       else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
         return 0;
       return Mips::BNEC;
     case Mips::BGE:
       if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
         return 0;

llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

def ORi  : MMRel, StdMMR6Rel,
              ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, or>,
              ADDI_FM<0xd>;
   def XORi : MMRel, StdMMR6Rel,
              ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, xor>,
              ADDI_FM<0xe>;
 }
 def ADDi  : MMRel, ArithLogicI<"addi", simm16_relaxed, GPR32Opnd, II_ADDI>, ADDI_FM<0x8>,
             ISA_MIPS1_NOT_32R6_64R6;
+let AdditionalPredicates = [NotInMicroMips] in {
   def SLTi  : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
               SLTI_FM<0xa>;
   def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
               SLTI_FM<0xb>;
+}
 def LUi   : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM;
 let AdditionalPredicates = [NotInMicroMips] in {
   /// Arithmetic Instructions (3-Operand, R-Type)
   def ADDu  : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
               ADD_FM<0, 0x21>;
   def SUBu  : MMRel, StdMMR6Rel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
               ADD_FM<0, 0x23>;
 }
 let Defs = [HI0, LO0] in
 def MUL   : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
             ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
 def ADD   : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd, 1, II_ADD>, ADD_FM<0, 0x20>;
 def SUB   : MMRel, StdMMR6Rel, ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>, ADD_FM<0, 0x22>;
+let AdditionalPredicates = [NotInMicroMips] in {
   def SLT   : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
   def SLTu  : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
-let AdditionalPredicates = [NotInMicroMips] in {
   def AND   : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
               ADD_FM<0, 0x24>;
   def OR    : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
               ADD_FM<0, 0x25>;
   def XOR   : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
               ADD_FM<0, 0x26>;
   def NOR   : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
 }
 
 /// Shift Instructions
 let AdditionalPredicates = [NotInMicroMips] in {
 def SLL  : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
                                    immZExt5>, SRA_FM<0, 0>;
 def SRL  : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
                                    immZExt5>, SRA_FM<2, 0>;

 }
 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32;
 def : MipsInstAlias<"neg $rt, $rs",
                     (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
 def : MipsInstAlias<"negu $rt",
                     (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
 def : MipsInstAlias<"negu $rt, $rs",
                     (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
+let AdditionalPredicates = [NotInMicroMips] in {
   def : MipsInstAlias<
           "slt $rs, $rt, $imm",
           (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
   def : MipsInstAlias<
           "sltu $rt, $rs, $imm",
           (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
-let AdditionalPredicates = [NotInMicroMips] in {
   def : MipsInstAlias<
           "and $rs, $rt, $imm",
           (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
   def : MipsInstAlias<
           "and $rs, $imm",
           (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
   def : MipsInstAlias<
           "xor $rs, $rt, $imm",

 let AdditionalPredicates = [NotInMicroMips] in {
   def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
 }
 
 // peepholes
 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
 
 // brcond patterns
-multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
-                      Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
-                      Instruction SLTiuOp, Register ZEROReg> {
+multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BEQOp1,
+                      Instruction BNEOp, Instruction SLTOp, Instruction SLTuOp,
+                      Instruction SLTiOp, Instruction SLTiuOp,
+                      Register ZEROReg> {
 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
               (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
               (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
 
 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
-              (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
+              (BEQOp1 (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
-              (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
+              (BEQOp1 (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
-              (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
+              (BEQOp1 (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
-              (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
+              (BEQOp1 (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
-              (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
+              (BEQOp1 (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
-              (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
+              (BEQOp1 (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
 
 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
-              (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
+              (BEQOp1 (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
-              (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
+              (BEQOp1 (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
 
 def : MipsPat<(brcond RC:$cond, bb:$dst),
               (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
 }
-
-defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
-
+let AdditionalPredicates = [NotInMicroMips] in {
+  defm : BrcondPats<GPR32, BEQ, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
+}
 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
               (BLEZ i32:$lhs, bb:$dst)>;
 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
               (BGEZ i32:$lhs, bb:$dst)>;
 
 // setcc patterns
 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
                      Instruction SLTuOp, Register ZEROReg> {
   def : MipsPat<(seteq RC:$lhs, 0),
                 (SLTiuOp RC:$lhs, 1)>;
   def : MipsPat<(setne RC:$lhs, 0),
                 (SLTuOp ZEROReg, RC:$lhs)>;
   def : MipsPat<(seteq RC:$lhs, RC:$rhs),
                 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
   def : MipsPat<(setne RC:$lhs, RC:$rhs),
                 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
 }
 
-multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
+multiclass SetlePats<RegisterClass RC, Instruction XORiOp, Instruction SLTOp,
+                     Instruction SLTuOp> {
   def : MipsPat<(setle RC:$lhs, RC:$rhs),
-                (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
+                (XORiOp (SLTOp RC:$rhs, RC:$lhs), 1)>;
   def : MipsPat<(setule RC:$lhs, RC:$rhs),
-                (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
+                (XORiOp (SLTuOp RC:$rhs, RC:$lhs), 1)>;
 }
 
 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
   def : MipsPat<(setgt RC:$lhs, RC:$rhs),
                 (SLTOp RC:$rhs, RC:$lhs)>;
   def : MipsPat<(setugt RC:$lhs, RC:$rhs),
                 (SLTuOp RC:$rhs, RC:$lhs)>;
 }
 
-multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
+multiclass SetgePats<RegisterClass RC, Instruction XORiOp, Instruction SLTOp,
+                     Instruction SLTuOp> {
   def : MipsPat<(setge RC:$lhs, RC:$rhs),
-                (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
+                (XORiOp (SLTOp RC:$lhs, RC:$rhs), 1)>;
   def : MipsPat<(setuge RC:$lhs, RC:$rhs),
-                (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
+                (XORiOp (SLTuOp RC:$lhs, RC:$rhs), 1)>;
 }
 
-multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
-                        Instruction SLTiuOp> {
+multiclass SetgeImmPats<RegisterClass RC, Instruction XORiOp,
+                        Instruction SLTiOp, Instruction SLTiuOp> {
   def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
-                (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
+                (XORiOp (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
   def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
-                (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
+                (XORiOp (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
 }
 
+let AdditionalPredicates = [NotInMicroMips] in {
   defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
-defm : SetlePats<GPR32, SLT, SLTu>;
+  defm : SetlePats<GPR32, XORi, SLT, SLTu>;
   defm : SetgtPats<GPR32, SLT, SLTu>;
-defm : SetgePats<GPR32, SLT, SLTu>;
-defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
+  defm : SetgePats<GPR32, XORi, SLT, SLTu>;
+  defm : SetgeImmPats<GPR32, XORi, SLTi, SLTiu>;
+}
 
 // bswap pattern
 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
 
 // Load halfword/word patterns.
 let AddedComplexity = 40 in {
   def : LoadRegImmPat<LBu, i32, zextloadi8>;
   let AdditionalPredicates = [NotInMicroMips] in {

llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp

 }
 
 /// getOppositeBranchOpc - Return the inverse of the specified
 /// opcode, e.g. turning BEQ to BNE.
 unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
   switch (Opc) {
   default:           llvm_unreachable("Illegal opcode!");
   case Mips::BEQ:    return Mips::BNE;
+  case Mips::BEQ_MM: return Mips::BNE_MM;
   case Mips::BNE:    return Mips::BEQ;
+  case Mips::BNE_MM: return Mips::BEQ_MM;
   case Mips::BGTZ:   return Mips::BLEZ;
   case Mips::BGEZ:   return Mips::BLTZ;
   case Mips::BLTZ:   return Mips::BGEZ;
   case Mips::BLEZ:   return Mips::BGTZ;
   case Mips::BEQ64:  return Mips::BNE64;
   case Mips::BNE64:  return Mips::BEQ64;
   case Mips::BGTZ64: return Mips::BLEZ64;
   case Mips::BGEZ64: return Mips::BLTZ64;
unsigned MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
 
   if (LastInstrIsADDiu)
     *NewImm = Inst->ImmOpnd;
 
   return Reg;
 }
 
 unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
-  return (Opc == Mips::BEQ    || Opc == Mips::BNE    || Opc == Mips::BGTZ   ||
-          Opc == Mips::BGEZ   || Opc == Mips::BLTZ   || Opc == Mips::BLEZ   ||
-          Opc == Mips::BEQ64  || Opc == Mips::BNE64  || Opc == Mips::BGTZ64 ||
-          Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 ||
-          Opc == Mips::BC1T   || Opc == Mips::BC1F   || Opc == Mips::B      ||
-          Opc == Mips::J  || Opc == Mips::BEQZC_MM || Opc == Mips::BNEZC_MM ||
-          Opc == Mips::BEQC   || Opc == Mips::BNEC   || Opc == Mips::BLTC   ||
-          Opc == Mips::BGEC   || Opc == Mips::BLTUC  || Opc == Mips::BGEUC  ||
-          Opc == Mips::BGTZC  || Opc == Mips::BLEZC  || Opc == Mips::BGEZC  ||
-          Opc == Mips::BLTZC  || Opc == Mips::BEQZC  || Opc == Mips::BNEZC  ||
+  return (Opc == Mips::BEQ    || Opc == Mips::BEQ_MM || Opc == Mips::BNE    ||
+          Opc == Mips::BNE_MM || Opc == Mips::BGTZ   || Opc == Mips::BGEZ   ||
+          Opc == Mips::BLTZ   || Opc == Mips::BLEZ   || Opc == Mips::BEQ64  ||
+          Opc == Mips::BNE64  || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 ||
+          Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T   ||
+          Opc == Mips::BC1F   || Opc == Mips::B      || Opc == Mips::J      ||
+          Opc == Mips::BEQZC_MM || Opc == Mips::BNEZC_MM || Opc == Mips::BEQC ||
+          Opc == Mips::BNEC   || Opc == Mips::BLTC   || Opc == Mips::BGEC   ||
+          Opc == Mips::BLTUC  || Opc == Mips::BGEUC  || Opc == Mips::BGTZC  ||
+          Opc == Mips::BLEZC  || Opc == Mips::BGEZC  || Opc == Mips::BLTZC  ||
+          Opc == Mips::BEQZC  || Opc == Mips::BNEZC  ||
           Opc == Mips::BC) ? Opc : 0;
 }
 
 void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator I) const {
   if (Subtarget.isGP64bit())
     BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64))
         .addReg(Mips::RA_64);

llvm/trunk/test/CodeGen/Mips/brconlt.ll

 ; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -march=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MM32R6
 
 @i = global i32 5, align 4
 @j = global i32 10, align 4
 @k = global i32 5, align 4
 @result = global i32 0, align 4
 
 define void @test() nounwind {
 entry:
   %0 = load i32, i32* @j, align 4
   %1 = load i32, i32* @i, align 4
   %cmp = icmp slt i32 %0, %1
   br i1 %cmp, label %if.end, label %if.then
 
-; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
-; 16: btnez $[[LABEL:[0-9A-Ba-b_]+]]
-; 16: $[[LABEL]]:
+; 16:     slt   ${{[0-9]+}}, ${{[0-9]+}}
+; MM32R6: slt   ${{[0-9]+}}, ${{[0-9]+}}
+; 16:     btnez $[[LABEL:[0-9A-Ba-b_]+]]
+; 16:     $[[LABEL]]:
 
 if.then:                                          ; preds = %entry
   store i32 1, i32* @result, align 4
   br label %if.end
 
 if.end:                                           ; preds = %entry, %if.then
   ret void
 }
 
 

llvm/trunk/test/CodeGen/Mips/setcc-se.ll

 ; RUN: llc -march=mipsel < %s | FileCheck %s
+; RUN: llc  -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic < %s -asm-show-inst | FileCheck %s -check-prefix=MMR6
 
 @g1 = external global i32
 
 ; CHECK-LABEL: seteq0:
-; CHECK: sltiu ${{[0-9]+}}, $4, 1
+; CHECK:  sltiu ${{[0-9]+}}, $4, 1
+; MMR6:   sltiu ${{[0-9]+}}, $4, 1
+; MMR6:   <MCInst #{{[0-9]+}} SLTiu_MM
 
 define i32 @seteq0(i32 %a) {
 entry:
   %cmp = icmp eq i32 %a, 0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 ; CHECK-LABEL: setne0:
-; CHECK: sltu ${{[0-9]+}}, $zero, $4
+; CHECK:  sltu ${{[0-9]+}}, $zero, $4
+; MMR6:   sltu ${{[0-9]+}}, $zero, $4
+; MMR6:   <MCInst #{{[0-9]+}} SLTu_MM
 
 define i32 @setne0(i32 %a) {
 entry:
   %cmp = icmp ne i32 %a, 0
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 ; CHECK-LABEL: slti_beq0:
-; CHECK: slti $[[R0:[0-9]+]], $4, -32768
-; CHECK: beqz $[[R0]]
+; CHECK:  slti $[[R0:[0-9]+]], $4, -32768
+; MMR6:   slti $[[R0:[0-9]+]], $4, -32768
+; MMR6:   <MCInst #{{[0-9]+}} SLTi_MM
+; CHECK:  beqz $[[R0]]
 
 define void @slti_beq0(i32 %a) {
 entry:
   %cmp = icmp slt i32 %a, -32768
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:
   store i32 %a, i32* @g1, align 4
   br label %if.end
 
 if.end:
   ret void
 }
 
 ; CHECK-LABEL: slti_beq1:
-; CHECK: slt ${{[0-9]+}}
+; CHECK:  slt ${{[0-9]+}}
+; MMR6:   slt ${{[0-9]+}}
+; MMR6:   <MCInst #{{[0-9]+}} SLT_MM
 
 define void @slti_beq1(i32 %a) {
 entry:
   %cmp = icmp slt i32 %a, -32769
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:
   store i32 %a, i32* @g1, align 4
   br label %if.end
 
 if.end:
   ret void
 }
 
 ; CHECK-LABEL: slti_beq2:
-; CHECK: slti $[[R0:[0-9]+]], $4, 32767
-; CHECK: beqz $[[R0]]
+; CHECK:  slti $[[R0:[0-9]+]], $4, 32767
+; MMR6:   slti $[[R0:[0-9]+]], $4, 32767
+; MMR6:   <MCInst #{{[0-9]+}} SLTi_MM
+; CHECK:  beqz $[[R0]]
 
 define void @slti_beq2(i32 %a) {
 entry:
   %cmp = icmp slt i32 %a, 32767
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:
   store i32 %a, i32* @g1, align 4
   br label %if.end
 
 if.end:
   ret void
 }
 
 ; CHECK-LABEL: slti_beq3:
-; CHECK: slt ${{[0-9]+}}
+; CHECK:  slt ${{[0-9]+}}
+; MMR6:   slt ${{[0-9]+}}
+; MMR6:   <MCInst #{{[0-9]+}} SLT_MM
 
 define void @slti_beq3(i32 %a) {
 entry:
   %cmp = icmp slt i32 %a, 32768
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:
   store i32 %a, i32* @g1, align 4
   br label %if.end
 
 if.end:
   ret void
 }
 
 ; CHECK-LABEL: sltiu_beq0:
-; CHECK: sltiu $[[R0:[0-9]+]], $4, 32767
-; CHECK: beqz $[[R0]]
+; CHECK:  sltiu $[[R0:[0-9]+]], $4, 32767
+; MMR6:   sltiu $[[R0:[0-9]+]], $4, 32767
+; MMR6:   <MCInst #{{[0-9]+}} SLTiu_MM
+; CHECK:  beqz $[[R0]]
 
 define void @sltiu_beq0(i32 %a) {
 entry:
   %cmp = icmp ult i32 %a, 32767
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:
   store i32 %a, i32* @g1, align 4
   br label %if.end
 
 if.end:
   ret void
 }
 
 ; CHECK-LABEL: sltiu_beq1:
-; CHECK: sltu ${{[0-9]+}}
+; CHECK:  sltu ${{[0-9]+}}
+; MMR6:   sltu ${{[0-9]+}}
+; MMR6:   <MCInst #{{[0-9]+}} SLTu_MM
 
 define void @sltiu_beq1(i32 %a) {
 entry:
   %cmp = icmp ult i32 %a, 32768
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:
   store i32 %a, i32* @g1, align 4
   br label %if.end
 
 if.end:
   ret void
 }
 
 ; CHECK-LABEL: sltiu_beq2:
-; CHECK: sltiu $[[R0:[0-9]+]], $4, -32768
-; CHECK: beqz $[[R0]]
+; CHECK:  sltiu $[[R0:[0-9]+]], $4, -32768
+; MMR6:   sltiu $[[R0:[0-9]+]], $4, -32768
+; MMR6:   <MCInst #{{[0-9]+}} SLTiu_MM
+; CHECK:  beqz $[[R0]]
 
 define void @sltiu_beq2(i32 %a) {
 entry:
   %cmp = icmp ult i32 %a, -32768
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:
   store i32 %a, i32* @g1, align 4
   br label %if.end
 
 if.end:
   ret void
 }
 
 ; CHECK-LABEL: sltiu_beq3:
-; CHECK: sltu ${{[0-9]+}}
+; CHECK:  sltu ${{[0-9]+}}
+; MMR6:   sltu ${{[0-9]+}}
+; MMR6:   <MCInst #{{[0-9]+}} SLTu_MM
 
 define void @sltiu_beq3(i32 %a) {
 entry:
   %cmp = icmp ult i32 %a, -32769
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:
   store i32 %a, i32* @g1, align 4
   br label %if.end
 
 if.end:
   ret void
 }

llvm/trunk/test/CodeGen/Mips/seteq.ll

 ; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
 
 @i = global i32 1, align 4
 @j = global i32 10, align 4
 @k = global i32 1, align 4
 @r1 = common global i32 0, align 4
 @r2 = common global i32 0, align 4
 
 define void @test() nounwind {
 entry:
   %0 = load i32, i32* @i, align 4
   %1 = load i32, i32* @k, align 4
   %cmp = icmp eq i32 %0, %1
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
-; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}}
-; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1
-; 16: move  ${{[0-9]+}}, $24
+; 16:   xor     $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}}
+; 16:   sltiu   $[[REGISTER:[0-9A-Ba-b_]+]], 1
+; MMR6: sltiu   ${{[0-9]+}}, ${{[0-9]+}}, 1
+; 16:   move    ${{[0-9]+}}, $24
   ret void
 }
 

llvm/trunk/test/CodeGen/Mips/seteqz.ll

 ; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
 
 @i = global i32 0, align 4
 @j = global i32 99, align 4
 @r1 = common global i32 0, align 4
 @r2 = common global i32 0, align 4
 
 define void @test() nounwind {
 entry:
   %0 = load i32, i32* @i, align 4
   %cmp = icmp eq i32 %0, 0
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
-; 16: sltiu ${{[0-9]+}}, 1
-; 16: move  ${{[0-9]+}}, $24
+; 16:   sltiu   ${{[0-9]+}}, 1
+; MMR6: sltiu   ${{[0-9]+}}, ${{[0-9]+}}, 1
+; 16:   move    ${{[0-9]+}}, $24
   %1 = load i32, i32* @j, align 4
   %cmp1 = icmp eq i32 %1, 99
   %conv2 = zext i1 %cmp1 to i32
   store i32 %conv2, i32* @r2, align 4
-; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}}
-; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1
-; 16: move  ${{[0-9]+}}, $24
+; 16:   xor     $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}}
+; 16:   sltiu   $[[REGISTER:[0-9A-Ba-b_]+]], 1
+; MMR6: sltiu   ${{[0-9]+}}, ${{[0-9]+}}, 1
+; 16:   move    ${{[0-9]+}}, $24
   ret void
 }

llvm/trunk/test/CodeGen/Mips/setge.ll

 ; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
 
 @j = global i32 -5, align 4
 @k = global i32 10, align 4
 @l = global i32 20, align 4
 @m = global i32 10, align 4
 @r1 = common global i32 0, align 4
 @r2 = common global i32 0, align 4
 @r3 = common global i32 0, align 4
 @.str = private unnamed_addr constant [22 x i8] c"1 = %i\0A1 = %i\0A0 = %i\0A\00", align 1
 
 define void @test() nounwind {
 entry:
   %0 = load i32, i32* @k, align 4
   %1 = load i32, i32* @j, align 4
   %cmp = icmp sge i32 %0, %1
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
-; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
-; 16: move  $[[REGISTER:[0-9]+]], $24
-; 16: xor $[[REGISTER]], ${{[0-9]+}}
+; 16:   slt   ${{[0-9]+}}, ${{[0-9]+}}
+; MMR6: slt   ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; 16:   move  $[[REGISTER:[0-9]+]], $24
+; 16:   xor   $[[REGISTER]], ${{[0-9]+}}
   %2 = load i32, i32* @m, align 4
   %cmp1 = icmp sge i32 %0, %2
   %conv2 = zext i1 %cmp1 to i32
   store i32 %conv2, i32* @r2, align 4
   ret void
 }

llvm/trunk/test/CodeGen/Mips/setgek.ll

 ; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
 
 @k = global i32 10, align 4
 @r1 = common global i32 0, align 4
 @r2 = common global i32 0, align 4
 @r3 = common global i32 0, align 4
 
 define void @test() nounwind {
 entry:
   %0 = load i32, i32* @k, align 4
   %cmp = icmp sgt i32 %0, -32769
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
-; 16: slti  ${{[0-9]+}}, -32768
-; 16: move  ${{[0-9]+}}, $24
-; 16: xor ${{[0-9]+}}, ${{[0-9]+}}
+; 16:   slti    ${{[0-9]+}}, -32768
+; MMR6: slt     ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; 16:   move    ${{[0-9]+}}, $24
+; 16:   xor     ${{[0-9]+}}, ${{[0-9]+}}
   ret void
 }

llvm/trunk/test/CodeGen/Mips/setle.ll

 ; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
 
 @j = global i32 -5, align 4
 @k = global i32 10, align 4
 @l = global i32 20, align 4
 @m = global i32 10, align 4
 @r1 = common global i32 0, align 4
 @r2 = common global i32 0, align 4
 @r3 = common global i32 0, align 4
 
 define void @test() nounwind {
 entry:
   %0 = load i32, i32* @j, align 4
   %1 = load i32, i32* @k, align 4
   %cmp = icmp sle i32 %0, %1
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
-; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
-; 16: move  $[[REGISTER:[0-9]+]], $24
-; 16: xor $[[REGISTER]], ${{[0-9]+}}
+; 16:   slt   ${{[0-9]+}}, ${{[0-9]+}}
+; MMR6: slt   ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; 16:   move  $[[REGISTER:[0-9]+]], $24
+; 16:   xor   $[[REGISTER]], ${{[0-9]+}}
   %2 = load i32, i32* @m, align 4
   %cmp1 = icmp sle i32 %2, %1
   %conv2 = zext i1 %cmp1 to i32
   store i32 %conv2, i32* @r2, align 4
   ret void
 }

llvm/trunk/test/CodeGen/Mips/setlt.ll

 ; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
 
 @j = global i32 -5, align 4
 @k = global i32 10, align 4
 @l = global i32 20, align 4
 @m = global i32 10, align 4
 @r1 = common global i32 0, align 4
 @r2 = common global i32 0, align 4
 @r3 = common global i32 0, align 4
 
 define void @test() nounwind {
 entry:
   %0 = load i32, i32* @j, align 4
   %1 = load i32, i32* @k, align 4
   %cmp = icmp slt i32 %0, %1
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
-; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
-; 16: move  ${{[0-9]+}}, $24
+; 16:   slt     ${{[0-9]+}}, ${{[0-9]+}}
+; MMR6: slt     ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; 16:   move    ${{[0-9]+}}, $24
   ret void
 }

llvm/trunk/test/CodeGen/Mips/setltk.ll

 ; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -march=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
 
 @j = global i32 -5, align 4
 @k = global i32 10, align 4
 @l = global i32 20, align 4
 @m = global i32 10, align 4
 @r1 = common global i32 0, align 4
 @r2 = common global i32 0, align 4
 @r3 = common global i32 0, align 4
 
 define void @test() nounwind {
 entry:
   %0 = load i32, i32* @j, align 4
   %cmp = icmp slt i32 %0, 10
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
-; 16: slti  $[[REGISTER:[0-9]+]], 10
-; 16: move  $[[REGISTER]], $24
+; 16:   slti    $[[REGISTER:[0-9]+]], 10
+; MMR6: slti    $[[REGISTER:[0-9]+]], $[[REGISTER:[0-9]+]], 10
+; 16:   move    $[[REGISTER]], $24
   ret void
 }

llvm/trunk/test/CodeGen/Mips/setne.ll

 ; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
 
 @i = global i32 1, align 4
 @j = global i32 10, align 4
 @k = global i32 1, align 4
 @r1 = common global i32 0, align 4
 @r2 = common global i32 0, align 4
 
 define void @test() nounwind {
 entry:
   %0 = load i32, i32* @i, align 4
   %1 = load i32, i32* @k, align 4
   %cmp = icmp ne i32 %0, %1
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
-; 16: xor $[[REGISTER:[0-9]+]], ${{[0-9]+}}
-; 16: sltu  ${{[0-9]+}}, $[[REGISTER]]
-; 16: move  ${{[0-9]+}}, $24
+; 16:   xor     $[[REGISTER:[0-9]+]], ${{[0-9]+}}
+; 16:   sltu    ${{[0-9]+}}, $[[REGISTER]]
+; MMR6: sltu    ${{[0-9]+}}, $zero, ${{[0-9]+}}
+; 16:   move    ${{[0-9]+}}, $24
   ret void
 }

llvm/trunk/test/CodeGen/Mips/setuge.ll

 ; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
 
 @j = global i32 5, align 4
 @k = global i32 10, align 4
 @l = global i32 20, align 4
 @m = global i32 10, align 4
 @r1 = common global i32 0, align 4
 @r2 = common global i32 0, align 4
 @r3 = common global i32 0, align 4
 
 define void @test() nounwind {
 entry:
   %0 = load i32, i32* @k, align 4
   %1 = load i32, i32* @j, align 4
   %cmp = icmp uge i32 %0, %1
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
-; 16: sltu  ${{[0-9]+}}, ${{[0-9]+}}
-; 16: move    $[[REGISTER:[0-9]+]], $24
-; 16: xor $[[REGISTER]], ${{[0-9]+}}
+; 16:   sltu  ${{[0-9]+}}, ${{[0-9]+}}
+; MMR6: sltu  ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; 16:   move  $[[REGISTER:[0-9]+]], $24
+; 16:   xor   $[[REGISTER]], ${{[0-9]+}}
   %2 = load i32, i32* @m, align 4
   %cmp1 = icmp uge i32 %0, %2
   %conv2 = zext i1 %cmp1 to i32
   store i32 %conv2, i32* @r2, align 4
   ret void
 }

llvm/trunk/test/CodeGen/Mips/setugt.ll

 ; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
 
 @j = global i32 5, align 4
 @k = global i32 10, align 4
 @l = global i32 20, align 4
 @m = global i32 10, align 4
 @r1 = common global i32 0, align 4
 @r2 = common global i32 0, align 4
 @r3 = common global i32 0, align 4
 
 define void @test() nounwind {
 entry:
   %0 = load i32, i32* @k, align 4
   %1 = load i32, i32* @j, align 4
   %cmp = icmp ugt i32 %0, %1
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
-; 16: sltu  ${{[0-9]+}}, ${{[0-9]+}}
-; 16: move    ${{[0-9]+}}, $24
+; 16:   sltu    ${{[0-9]+}}, ${{[0-9]+}}
+; MMR6: sltu    ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; 16:   move    ${{[0-9]+}}, $24
   ret void
 }

llvm/trunk/test/CodeGen/Mips/setule.ll

 ; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
 
 @j = global i32 5, align 4
 @k = global i32 10, align 4
 @l = global i32 20, align 4
 @m = global i32 10, align 4
 @r1 = common global i32 0, align 4
 @r2 = common global i32 0, align 4
 @r3 = common global i32 0, align 4
 
 define void @test() nounwind {
 entry:
   %0 = load i32, i32* @j, align 4
   %1 = load i32, i32* @k, align 4
   %cmp = icmp ule i32 %0, %1
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
-; 16: sltu  ${{[0-9]+}}, ${{[0-9]+}}
-; 16: move  $[[REGISTER:[0-9]+]], $24
-; 16: xor $[[REGISTER]], ${{[0-9]+}}
+; 16:   sltu  ${{[0-9]+}}, ${{[0-9]+}}
+; MMR6: sltu  ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; 16:   move  $[[REGISTER:[0-9]+]], $24
+; 16:   xor   $[[REGISTER]], ${{[0-9]+}}
   %2 = load i32, i32* @m, align 4
   %cmp1 = icmp ule i32 %2, %1
   %conv2 = zext i1 %cmp1 to i32
   store i32 %conv2, i32* @r2, align 4
   ret void
 }

llvm/trunk/test/CodeGen/Mips/setult.ll

 ; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
 
 @j = global i32 5, align 4
 @k = global i32 10, align 4
 @l = global i32 20, align 4
 @m = global i32 10, align 4
 @r1 = common global i32 0, align 4
 @r2 = common global i32 0, align 4
 @r3 = common global i32 0, align 4
 
 define void @test() nounwind {
 entry:
   %0 = load i32, i32* @j, align 4
   %1 = load i32, i32* @k, align 4
   %cmp = icmp ult i32 %0, %1
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
-; 16: sltu  ${{[0-9]+}}, ${{[0-9]+}}
-; 16: move  ${{[0-9]+}}, $24
+; 16:   sltu    ${{[0-9]+}}, ${{[0-9]+}}
+; MMR6: sltu    ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; 16:   move    ${{[0-9]+}}, $24
   ret void
 }

llvm/trunk/test/CodeGen/Mips/setultk.ll

 ; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
 
 @j = global i32 5, align 4
 @k = global i32 10, align 4
 @l = global i32 20, align 4
 @m = global i32 10, align 4
 @r1 = common global i32 0, align 4
 @r2 = common global i32 0, align 4
 @r3 = common global i32 0, align 4
 
 define void @test() nounwind {
 entry:
   %0 = load i32, i32* @j, align 4
   %cmp = icmp ult i32 %0, 10
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
-; 16: sltiu ${{[0-9]+}}, 10 # 16 bit inst
-; 16: move  ${{[0-9]+}}, $24
+; 16:   sltiu   ${{[0-9]+}}, 10 # 16 bit inst
+; MMR6: sltiu   ${{[0-9]+}}, ${{[0-9]+}}, 1
+; 16:   move    ${{[0-9]+}}, $24
   ret void
 }

llvm/trunk/test/CodeGen/Mips/slt.ll

+; RUN: llc -march=mips -mcpu=mips32r3 -mattr=micromips -relocation-model=pic < %s | FileCheck %s
+
+define i32 @slt(i32 signext %a) nounwind readnone {
+  %1 = icmp slt i32 %a, 7
+  ; CHECK-LABEL: slt:
+  ; CHECK: slt ${{[0-9]+}}, ${{[0-9]+}}, $4
+  %2 = select i1 %1, i32 3, i32 4
+  ret i32 %2
+}
+
+define i32 @sgt(i32 signext %a) {
+entry:
+  ; CHECK-LABEL: sgt:
+  %cmp = icmp sgt i32 %a, 32767
+  ; CHECK: slt ${{[0-9]+}}, ${{[0-9]+}}, $4
+  %cond = select i1 %cmp, i32 7, i32 5
+  ret i32 %cond
+}

llvm/trunk/test/MC/Disassembler/Mips/micromips32r6/valid.txt

 0x54 0x44 0x3b 0x3b # CHECK: round.w.s $f2, $f4
 0x54 0x44 0x7b 0x3b # CHECK: round.w.d $f2, $f4
 0x54 0x41 0x08 0xb8 # CHECK: sel.s $f1, $f1, $f2
 0x54 0x82 0x02 0xb8 # CHECK: sel.d $f0, $f2, $f4
 0x54 0x62 0x08 0x38 # CHECK: seleqz.s $f1, $f2, $f3
 0x55 0x04 0x12 0x38 # CHECK: seleqz.d $f2, $f4, $f8
 0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3
 0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8
+0x00 0xa4 0x1b 0x50 # CHECK: slt $3, $4, $5
+0x90 0x64 0x01 0x00 # CHECK: slti $3, $4, 256
+0xb0 0x64 0x01 0x00 # CHECK: sltiu $3, $4, 256
+0x00 0xa4 0x1b 0x90 # CHECK: sltu $3, $4, $5
 0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3
 0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4
 0x00 0x00 0x47 0x7c # CHECK: di
 0x00 0x0f 0x47 0x7c # CHECK: di $15
 0x00 0x00 0x43 0x7c # CHECK: tlbinv
 0x00 0x00 0x53 0x7c # CHECK: tlbinvf
 0x00 0xa9 0x02 0xfc # CHECK: mtc0 $5, $9, 0
 0x00 0xa9 0x02 0xfc # CHECK: mtc0 $5, $9

llvm/trunk/test/MC/Mips/micromips-el-fixup-data.s

# byte order.
     .type   main,@function
     .set    micromips
     .set    nomips16
     .ent    main
 main:
     addiu   $sp, $sp, -16
     bnez    $9, lab1
 
-# CHECK:    09 b4 04 00    bne $9, $zero, 8
+# CHECK:    09 b4 04 00    bnez $9, 8
 
     addu    $zero, $zero, $zero
 lab1:
     jr  $ra
     addiu   $sp, $sp, 16
     .end    main

llvm/trunk/test/MC/Mips/micromips32r6/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips | FileCheck %s
   round.w.s $f2, $f4       # CHECK: round.w.s $f2, $f4  # encoding: [0x54,0x44,0x3b,0x3b]
   round.w.d $f2, $f4       # CHECK: round.w.d $f2, $f4  # encoding: [0x54,0x44,0x7b,0x3b]
   sel.s $f1, $f1, $f2      # CHECK: sel.s $f1, $f1, $f2 # encoding: [0x54,0x41,0x08,0xb8]
   sel.d $f0, $f2, $f4      # CHECK: sel.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x02,0xb8]
   seleqz.s $f1, $f2, $f3   # CHECK: seleqz.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x38]
   seleqz.d $f2, $f4, $f8   # CHECK: seleqz.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x38]
   selnez.s $f1, $f2, $f3   # CHECK: selnez.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x78]
   selnez.d $f2, $f4, $f8   # CHECK: selnez.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x78]
+  slt $3, $4, $5           # CHECK: slt $3, $4, $5         # encoding: [0x00,0xa4,0x1b,0x50]
+  slti $3, $4, 256         # CHECK: slti $3, $4, 256       # encoding: [0x90,0x64,0x01,0x00]
+  sltiu $3, $4, 256        # CHECK: sltiu $3, $4, 256      # encoding: [0xb0,0x64,0x01,0x00]
+  sltu $3, $4, $5          # CHECK: sltu $3, $4, $5        # encoding: [0x00,0xa4,0x1b,0x90]
   class.s $f2, $f3         # CHECK: class.s $f2, $f3       # encoding: [0x54,0x62,0x00,0x60]
   class.d $f2, $f4         # CHECK: class.d $f2, $f4       # encoding: [0x54,0x82,0x02,0x60]
   deret                    # CHECK: deret                  # encoding: [0x00,0x00,0xe3,0x7c]
   tlbinv                   # CHECK: tlbinv                 # encoding: [0x00,0x00,0x43,0x7c]
   tlbinvf                  # CHECK: tlbinvf                # encoding: [0x00,0x00,0x53,0x7c]
   mtc0 $5, $9              # CHECK: mtc0 $5, $9, 0         # encoding: [0x00,0xa9,0x02,0xfc]
   mtc0 $1, $2, 7           # CHECK: mtc0 $1, $2, 7         # encoding: [0x00,0x22,0x3a,0xfc]
   mtc1 $3, $f4             # CHECK: mtc1 $3, $f4           # encoding: [0x54,0x64,0x28,0x3b]