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Differential D15418

[mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions and add CodeGen support
ClosedPublic

Authored by zbuljan on Dec 10 2015, 7:02 AM.

Details

Reviewers
dsanders
sdardis
vkalintiris
zoran.jovanovic
hvarga
Commits
rL269883: [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions and add…
Summary

The patch implements microMIPSr6 LH, LHE, LHU and LHUE instructions.

There was a problem with previous implementation of this instructions (D9824) and because of that commit rL254897 was reverted.

After commit of previous patch, test-suite failed with error message in the form of:

fatal error: error in backend: Cannot select: t124: i32,ch = load<LD2[%d](tbaa=<0x94acc48>), sext from i16> t0, t2, undef:i32

There was problem with selecting lh and lhu instructions in LLVM backend.

For that reason I decided to revert commit rL254897 and make this patch which besides implementation of instructions and standard regression tests also includes CodeGen tests (lh_lhu.ll).

Diff Detail

Event Timeline

zbuljan updated this revision to Diff 42428.Dec 10 2015, 7:02 AM
zbuljan retitled this revision from to [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions.
zbuljan updated this object.
zbuljan added reviewers: dsanders, hvarga, zoran.jovanovic.
zbuljan added subscribers: petarj, llvm-commits.
Herald added a subscriber: dsanders. · View Herald TranscriptDec 10 2015, 7:02 AM
zbuljan updated this revision to Diff 50405.Mar 11 2016, 1:55 AM

Rebased to work with top of the tree.

Herald added a reviewer: vkalintiris. · View Herald TranscriptMar 11 2016, 1:55 AM
sdardis added a reviewer: sdardis.Apr 14 2016, 6:08 AM
sdardis requested changes to this revision.Apr 15 2016, 7:12 AM
sdardis edited edge metadata.

Hi,

After applying this patch and checking lh_lhu.ll with "-asm-show-inst" I see:

lh      $2, %lo(us)($2)         # <MCInst #1187 LH
                                #  <MCOperand Reg:321>
                                #  <MCOperand Reg:321>
                                #  <MCOperand Expr:(us@ABS_LO)>>

Shouldn't LLVM have picked LH_MM? The rest are small nits regarding some style issues and the ordering of instructions in test files.

lib/Target/Mips/MicroMips32r6InstrFormats.td
871

Can you redo this definition in the style of SB32_SH32_STORE_FM_MMR6 ? You split addr into base and offset, then assign to Inst.

lib/Target/Mips/MicroMips32r6InstrInfo.td
169–170

Can you use the 0bxxx style of specifying opcodes here? It makes it somewhat easier to check and is more consistent with the overall MIPS backend.

test/MC/Disassembler/Mips/micromips32r6/valid.txt
256–259

Can you sort these alphabetically into the existing instructions?

test/MC/Mips/micromips-invalid.s
105

Can you add some out of range negative tests for these instructions as well? This applies to the other invalid tests as well.

test/MC/Mips/micromips32r6/valid.s
249–252

Can you sort these alphabetically into the first 100~ instructions.

This revision now requires changes to proceed.Apr 15 2016, 7:12 AM
zbuljan updated this revision to Diff 55564.Apr 29 2016, 4:20 AM
zbuljan retitled this revision from [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions to [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions and add CodeGen support.
zbuljan edited edge metadata.

Rebased to work with TOT.
Removed microMIPS32r6 implementation of LH and LHU instructions because it is not required.
Added required DAG patterns for microMIPS LH and LHU instructions so they can be selected properly.
Expanded .ll test with load atomic to check added DAG pattern.
Tests for the standard encodings are sorted in alphabetical order.
Added invalid tests for the negative ranges.

Herald added a subscriber: sdardis. · View Herald TranscriptApr 29 2016, 4:20 AM
sdardis requested changes to this revision.May 5 2016, 7:17 AM
sdardis edited edge metadata.

One nit and one small change, comments are inlined.

lib/Target/Mips/MicroMipsInstrFormats.td
1026 ↗(On Diff #55564)

This class needs to inherit from MMArch, so that this instruction ends up in the Std2MicroMips mapping table from direct object emission.

You can verify the mapping by looking at the Std2MicroMips function in $BUILDDIR/lib/Target/Mips/MipsGenDAGISel.inc and/or the records from llvm-tblgen for the string Arch = in the defs of the instructions.

You'll also have to remove the line "list<Pattern> = []" from the definition of MMArch, otherwise the DAG pattern doesn't get set properly and the instruction cannot be selected in the common case.

Removing that line from the MMArch definition will cause test failures as the selection mechanism be arranged and some 16bit instructions will not be chosen. Some of the test failures are fixed in D19906.

test/CodeGen/Mips/llvm-ir/lh_lhu.ll
4

Check microMIPS64r6 as well.

This revision now requires changes to proceed.May 5 2016, 7:17 AM
zbuljan updated this revision to Diff 57453.May 17 2016, 3:56 AM
zbuljan edited edge metadata.

Rebased to work with TOT.
Changed LH_LHU_FM_MM format class to inherit from MMArch.
Removed the line "list<Pattern> = []" from the definition of MMArch class.
Added "int AddedComplexity = 1" parameter to definition of 16-bit instructions.
Updated lh_lhu.ll with test for microMIPS64r6.

sdardis accepted this revision.May 17 2016, 9:15 AM
sdardis edited edge metadata.

LGTM.

This revision is now accepted and ready to land.May 17 2016, 9:15 AM
Closed by commit rL269883: [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions and add… (authored by zbuljan). · Explain WhyMay 18 2016, 12:01 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
Mips/
12 lines
7 lines
12 lines
33 lines
test/
CodeGen/
Mips/
llvm-ir/
23 lines
MC/
Disassembler/
Mips/
micromips32r6/
4 lines
micromips64r6/
4 lines
Mips/
12 lines
micromips32r6/
12 lines
4 lines
micromips64r6/
12 lines
4 lines
mips32r6/
12 lines
mips64r6/
12 lines

Diff 42428

lib/Target/Mips/MicroMips32r6InstrFormats.td

Show First 20 Lines • Show All 852 Lines • ▼ Show 20 Linesclass POOL32F_CLASS_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>
let Inst{31-26} = 0b010101; let Inst{31-26} = 0b010101;
let Inst{25-21} = fs; let Inst{25-21} = fs;
let Inst{20-16} = fd; let Inst{20-16} = fd;
let Inst{15-11} = 0b00000; let Inst{15-11} = 0b00000;
let Inst{10-9} = fmt; let Inst{10-9} = fmt;
let Inst{8-0} = funct; let Inst{8-0} = funct;
} }
class LH32_LHU32_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
bits<5> rt;
bits<21> addr;
bits<32> Inst;
let Inst{31-26} = op;
let Inst{25-21} = rt;
let Inst{20-16} = addr{20-16};
let Inst{15-0} = addr{15-0};
sdardisUnsubmitted
Not Done
ReplyInline Actions

Can you redo this definition in the style of SB32_SH32_STORE_FM_MMR6 ? You split addr into base and offset, then assign to Inst.

sdardis: Can you redo this definition in the style of SB32_SH32_STORE_FM_MMR6 ? You split addr into base…
}

lib/Target/Mips/MicroMips32r6InstrInfo.td

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class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>, MicroMipsR6Inst16; class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>, MicroMipsR6Inst16;
class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>, MicroMipsR6Inst16; class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>, MicroMipsR6Inst16;
class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>; class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>;
class LI16_MMR6_ENC : LI_FM_MM16; class LI16_MMR6_ENC : LI_FM_MM16;
class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>; class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>;
class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>; class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>;
class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6; class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6;
class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>; class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>;
class LH_MMR6_ENC : LH32_LHU32_FM_MMR6<"lh", 0xf>;
class LHu_MMR6_ENC : LH32_LHU32_FM_MMR6<"lhu", 0xd>;
sdardisUnsubmitted
Not Done
ReplyInline Actions

Can you use the 0bxxx style of specifying opcodes here? It makes it somewhat easier to check and is more consistent with the overall MIPS backend.

sdardis: Can you use the 0bxxx style of specifying opcodes here? It makes it somewhat easier to check…
class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd, class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
RegisterOperand GPROpnd> RegisterOperand GPROpnd>
: BRANCH_DESC_BASE, MMR6Arch<instr_asm> { : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
dag InOperandList = (ins GPROpnd:$rt, opnd:$offset); dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
dag OutOperandList = (outs); dag OutOperandList = (outs);
string AsmString = !strconcat(instr_asm, "\t$rt, $offset"); string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
list<Register> Defs = [AT]; list<Register> Defs = [AT];
▲ Show 20 Lines • Show All 738 Lines • ▼ Show 20 Lines
class SWSP_MMR6_DESC class SWSP_MMR6_DESC
: MicroMipsInst16<(outs), (ins GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset), : MicroMipsInst16<(outs), (ins GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset),
!strconcat("sw", "\t$rt, $offset"), [], II_SW, FrmI>, !strconcat("sw", "\t$rt, $offset"), [], II_SW, FrmI>,
MMR6Arch<"sw">, MicroMipsR6Inst16 { MMR6Arch<"sw">, MicroMipsR6Inst16 {
let DecoderMethod = "DecodeMemMMSPImm5Lsl2"; let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
let mayStore = 1; let mayStore = 1;
} }
class LH_MMR6_DESC : LoadMemory<"lh", GPR32Opnd, mem_simm16gpr>;
class LHu_MMR6_DESC : LoadMemory<"lhu", GPR32Opnd, mem_simm16gpr>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// Instruction Definitions // Instruction Definitions
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let DecoderNamespace = "MicroMipsR6" in { let DecoderNamespace = "MicroMipsR6" in {
def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6; def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines
def SYNC_MMR6 : StdMMR6Rel, SYNC_MMR6_DESC, SYNC_MMR6_ENC, ISA_MICROMIPS32R6; def SYNC_MMR6 : StdMMR6Rel, SYNC_MMR6_DESC, SYNC_MMR6_ENC, ISA_MICROMIPS32R6;
def SYNCI_MMR6 : StdMMR6Rel, SYNCI_MMR6_DESC, SYNCI_MMR6_ENC, ISA_MICROMIPS32R6; def SYNCI_MMR6 : StdMMR6Rel, SYNCI_MMR6_DESC, SYNCI_MMR6_ENC, ISA_MICROMIPS32R6;
def RDPGPR_MMR6 : R6MMR6Rel, RDPGPR_MMR6_DESC, RDPGPR_MMR6_ENC, def RDPGPR_MMR6 : R6MMR6Rel, RDPGPR_MMR6_DESC, RDPGPR_MMR6_ENC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def SDBBP_MMR6 : R6MMR6Rel, SDBBP_MMR6_DESC, SDBBP_MMR6_ENC, ISA_MICROMIPS32R6; def SDBBP_MMR6 : R6MMR6Rel, SDBBP_MMR6_DESC, SDBBP_MMR6_ENC, ISA_MICROMIPS32R6;
def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6; def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6; def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
let DecoderMethod = "DecodeMemMMImm16" in { let DecoderMethod = "DecodeMemMMImm16" in {
def LH_MMR6 : StdMMR6Rel, LH_MMR6_DESC, LH_MMR6_ENC, ISA_MICROMIPS32R6;
def LHu_MMR6 : StdMMR6Rel, LHu_MMR6_DESC, LHu_MMR6_ENC, ISA_MICROMIPS32R6;
def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6; def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6;
} }
let DecoderMethod = "DecodeMemMMImm9" in { let DecoderMethod = "DecodeMemMMImm9" in {
def SWE_MMR6 : StdMMR6Rel, SWE_MMR6_DESC, SWE_MMR6_ENC, ISA_MICROMIPS32R6; def SWE_MMR6 : StdMMR6Rel, SWE_MMR6_DESC, SWE_MMR6_ENC, ISA_MICROMIPS32R6;
} }
/// Floating Point Instructions /// Floating Point Instructions
def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC, def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
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lib/Target/Mips/MicroMipsInstrInfo.td

Show First 20 Lines • Show All 732 Lines • ▼ Show 20 Lines def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
SRA_FM_MM<0xc0, 0>; SRA_FM_MM<0xc0, 0>;
def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>, def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
SRLV_FM_MM<0xd0, 0>; SRLV_FM_MM<0xd0, 0>;
/// Load and Store Instructions - aligned /// Load and Store Instructions - aligned
let DecoderMethod = "DecodeMemMMImm16" in { let DecoderMethod = "DecodeMemMMImm16" in {
def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>; def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>; def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
def LH_MM : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>; def LH_MM : LoadMemory<"lh", GPR32Opnd, mem_simm16gpr>, MMRel,
def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>; LW_FM_MM<0xf>;
def LHu_MM : LoadMemory<"lhu", GPR32Opnd, mem_simm16gpr>, MMRel,
LW_FM_MM<0xd>;
def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>; def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>; def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>; def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>; def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
} }
let DecoderMethod = "DecodeMemMMImm9" in { let DecoderMethod = "DecodeMemMMImm9" in {
def LBE_MM : Load<"lbe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>; def LBE_MM : Load<"lbe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>;
def LBuE_MM : Load<"lbue", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>; def LBuE_MM : Load<"lbue", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>;
def LHE_MM : Load<"lhe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>; def LHE_MM : LoadMemory<"lhe", GPR32Opnd, mem_simm9gpr>,
def LHuE_MM : Load<"lhue", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>; POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>;
def LHuE_MM : LoadMemory<"lhue", GPR32Opnd, mem_simm9gpr>,
POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>;
def LWE_MM : Load<"lwe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>; def LWE_MM : Load<"lwe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>;
def SBE_MM : Store<"sbe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>; def SBE_MM : Store<"sbe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>;
def SHE_MM : Store<"she", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>; def SHE_MM : Store<"she", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>;
def SWE_MM : StoreMemory<"swe", GPR32Opnd, mem_simm9gpr>, def SWE_MM : StoreMemory<"swe", GPR32Opnd, mem_simm9gpr>,
POOL32C_LHUE_FM_MM<0x18, 0xa, 0x7>; POOL32C_LHUE_FM_MM<0x18, 0xa, 0x7>;
} }
def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>; def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>;
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lib/Target/Mips/MipsInstrInfo.td

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def MipsMemSimm16AsmOperand : AsmOperandClass { def MipsMemSimm16AsmOperand : AsmOperandClass {
let Name = "MemOffsetSimm16"; let Name = "MemOffsetSimm16";
let SuperClasses = [MipsMemAsmOperand]; let SuperClasses = [MipsMemAsmOperand];
let RenderMethod = "addMemOperands"; let RenderMethod = "addMemOperands";
let ParserMethod = "parseMemOperand"; let ParserMethod = "parseMemOperand";
let PredicateMethod = "isMemWithSimmOffset<16>"; let PredicateMethod = "isMemWithSimmOffset<16>";
} }
def MipsMemSimm16GPRAsmOperand : AsmOperandClass {
let Name = "MemOffsetSimm16GPR";
let SuperClasses = [MipsMemAsmOperand];
let RenderMethod = "addMemOperands";
let ParserMethod = "parseMemOperand";
let PredicateMethod = "isMemWithSimmOffsetGPR<16>";
}
def MipsInvertedImmoperand : AsmOperandClass { def MipsInvertedImmoperand : AsmOperandClass {
let Name = "InvNum"; let Name = "InvNum";
let RenderMethod = "addImmOperands"; let RenderMethod = "addImmOperands";
let ParserMethod = "parseInvNum"; let ParserMethod = "parseInvNum";
} }
def InvertedImOperand : Operand<i32> { def InvertedImOperand : Operand<i32> {
let ParserMatchClass = MipsInvertedImmoperand; let ParserMatchClass = MipsInvertedImmoperand;
Show All 39 Lines
} }
def mem_simm16 : mem_generic { def mem_simm16 : mem_generic {
let MIOperandInfo = (ops ptr_rc, simm16); let MIOperandInfo = (ops ptr_rc, simm16);
let EncoderMethod = "getMemEncoding"; let EncoderMethod = "getMemEncoding";
let ParserMatchClass = MipsMemSimm16AsmOperand; let ParserMatchClass = MipsMemSimm16AsmOperand;
} }
def mem_simm16gpr : mem_generic {
let MIOperandInfo = (ops ptr_rc, simm16);
let EncoderMethod = "getMemEncoding";
let ParserMatchClass = MipsMemSimm16GPRAsmOperand;
}
def mem_ea : Operand<iPTR> { def mem_ea : Operand<iPTR> {
let PrintMethod = "printMemOperandEA"; let PrintMethod = "printMemOperandEA";
let MIOperandInfo = (ops ptr_rc, simm16); let MIOperandInfo = (ops ptr_rc, simm16);
let EncoderMethod = "getMemEncoding"; let EncoderMethod = "getMemEncoding";
let OperandType = "OPERAND_MEMORY"; let OperandType = "OPERAND_MEMORY";
} }
def PtrRC : Operand<iPTR> { def PtrRC : Operand<iPTR> {
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class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>: class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
[], II_LUI, FrmI, opstr>, IsAsCheapAsAMove { [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
let hasSideEffects = 0; let hasSideEffects = 0;
let isReMaterializable = 1; let isReMaterializable = 1;
} }
// Memory Load/Store // Memory Load/Store
class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag, class LoadMemory<string opstr, DAGOperand RO, DAGOperand MO,
InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : SDPatternOperator OpNode = null_frag,
InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), InstrItinClass Itin = NoItinerary,
ComplexPattern Addr = addr> :
InstSE<(outs RO:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
[(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> { [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
let DecoderMethod = "DecodeMem"; let DecoderMethod = "DecodeMem";
let canFoldAsLoad = 1; let canFoldAsLoad = 1;
let mayLoad = 1; let mayLoad = 1;
} }
class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
LoadMemory<opstr, RO, mem, OpNode, Itin, Addr>;
class StoreMemory<string opstr, DAGOperand RO, DAGOperand MO, class StoreMemory<string opstr, DAGOperand RO, DAGOperand MO,
SDPatternOperator OpNode = null_frag, SDPatternOperator OpNode = null_frag,
InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"), InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
[(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> { [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
let DecoderMethod = "DecodeMem"; let DecoderMethod = "DecodeMem";
let mayStore = 1; let mayStore = 1;
} }
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def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>, def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
SRLV_FM<6, 1>, ISA_MIPS32R2; SRLV_FM<6, 1>, ISA_MIPS32R2;
/// Load and Store Instructions /// Load and Store Instructions
/// aligned /// aligned
def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>; def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel, def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
LW_FM<0x24>; LW_FM<0x24>;
def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel, def LH : LoadMemory<"lh", GPR32Opnd, mem_simm16gpr, sextloadi16, II_LH,
LW_FM<0x21>; addrDefault>, MMRel, LW_FM<0x21>;
def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>; def LHu : LoadMemory<"lhu", GPR32Opnd, mem_simm16gpr, zextloadi16, II_LHU>,
MMRel, LW_FM<0x25>;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def LW : StdMMR6Rel, Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel, def LW : StdMMR6Rel, Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
LW_FM<0x23>; LW_FM<0x23>;
} }
def SB : StdMMR6Rel, Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, def SB : StdMMR6Rel, Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel,
LW_FM<0x28>; LW_FM<0x28>;
def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>; def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
▲ Show 20 Lines • Show All 882 Lines • Show Last 20 Lines

test/CodeGen/Mips/llvm-ir/lh_lhu.ll

  • This file was added.
; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips | FileCheck %s
; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s
sdardisUnsubmitted
Not Done
ReplyInline Actions

Check microMIPS64r6 as well.

sdardis: Check microMIPS64r6 as well.
@us = global i16 0, align 2
define i32 @lhfunc() {
entry:
; CHECK-LABEL: lhfunc
; CHECK: lh $[[REG1:[0-9]+]], 0(${{[0-9]+}})
%0 = load i16, i16* @us, align 2
%conv = sext i16 %0 to i32
ret i32 %conv
}
define i32 @lhufunc() {
entry:
; CHECK-LABEL: lhufunc
; CHECK: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
%0 = load i16, i16* @us, align 2
%conv = zext i16 %0 to i32
ret i32 %conv
}

test/MC/Disassembler/Mips/micromips32r6/valid.txt

Show First 20 Lines • Show All 247 Lines • ▼ Show 20 Lines
0x54 0x41 0x08 0xb8 # CHECK: sel.s $f1, $f1, $f2 0x54 0x41 0x08 0xb8 # CHECK: sel.s $f1, $f1, $f2
0x54 0x82 0x02 0xb8 # CHECK: sel.d $f0, $f2, $f4 0x54 0x82 0x02 0xb8 # CHECK: sel.d $f0, $f2, $f4
0x54 0x62 0x08 0x38 # CHECK: seleqz.s $f1, $f2, $f3 0x54 0x62 0x08 0x38 # CHECK: seleqz.s $f1, $f2, $f3
0x55 0x04 0x12 0x38 # CHECK: seleqz.d $f2, $f4, $f8 0x55 0x04 0x12 0x38 # CHECK: seleqz.d $f2, $f4, $f8
0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3 0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3
0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8 0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8
0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3 0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3
0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4 0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4
0x3c 0x44 0x00 0x08 # CHECK: lh $2, 8($4)
0x60 0x82 0x6a 0x08 # CHECK: lhe $4, 8($2)
0x34 0x82 0x00 0x08 # CHECK: lhu $4, 8($2)
0x60 0x82 0x62 0x08 # CHECK: lhue $4, 8($2)
sdardisUnsubmitted
Not Done
ReplyInline Actions

Can you sort these alphabetically into the existing instructions?

sdardis: Can you sort these alphabetically into the existing instructions?

test/MC/Disassembler/Mips/micromips64r6/valid.txt

Show First 20 Lines • Show All 160 Lines • ▼ Show 20 Lines
0x54 0x41 0x08 0xb8 # CHECK: sel.s $f1, $f1, $f2 0x54 0x41 0x08 0xb8 # CHECK: sel.s $f1, $f1, $f2
0x54 0x82 0x02 0xb8 # CHECK: sel.d $f0, $f2, $f4 0x54 0x82 0x02 0xb8 # CHECK: sel.d $f0, $f2, $f4
0x54 0x62 0x08 0x38 # CHECK: seleqz.s $f1, $f2, $f3 0x54 0x62 0x08 0x38 # CHECK: seleqz.s $f1, $f2, $f3
0x55 0x04 0x12 0x38 # CHECK: seleqz.d $f2, $f4, $f8 0x55 0x04 0x12 0x38 # CHECK: seleqz.d $f2, $f4, $f8
0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3 0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3
0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8 0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8
0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3 0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3
0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4 0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4
0x3c 0x44 0x00 0x08 # CHECK: lh $2, 8($4)
0x60 0x82 0x6a 0x08 # CHECK: lhe $4, 8($2)
0x34 0x82 0x00 0x08 # CHECK: lhu $4, 8($2)
0x60 0x82 0x62 0x08 # CHECK: lhue $4, 8($2)

test/MC/Mips/micromips-invalid.s

Show First 20 Lines • Show All 85 Lines • ▼ Show 20 Lines# RUN: FileCheck %s < %t1
jraddiusp 2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 jraddiusp 2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4
jraddiusp 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 jraddiusp 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4
jraddiusp 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 jraddiusp 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4
jraddiusp 18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 jraddiusp 18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4
jraddiusp 31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 jraddiusp 31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4
jraddiusp 33 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 jraddiusp 33 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4
jraddiusp 125 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 jraddiusp 125 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4
jraddiusp 132 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 jraddiusp 132 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4
lh $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhe $34, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhu $35, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhue $36, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lh $2, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhe $4, 8($33) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhu $4, 8($35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhue $4, 8($37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lh $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhe $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhu $4, 65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
sdardisUnsubmitted
Not Done
ReplyInline Actions

Can you add some out of range negative tests for these instructions as well? This applies to the other invalid tests as well.

sdardis: Can you add some out of range negative tests for these instructions as well? This applies to…

test/MC/Mips/micromips32r6/invalid.s

Show First 20 Lines • Show All 103 Lines • ▼ Show 20 Lines# RUN: FileCheck %s < %t1
swm16 $5, $6, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected swm16 $5, $6, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
swm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected swm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
swm16 $16-$25, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand swm16 $16-$25, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
swm16 $16, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swm16 $16, $17, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16, $17, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lh $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhe $34, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhu $35, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhue $36, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lh $2, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhe $4, 8($33) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhu $4, 8($35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhue $4, 8($37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lh $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhe $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhu $4, 65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

test/MC/Mips/micromips32r6/valid.s

Show First 20 Lines • Show All 240 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips | FileCheck %s
sel.s $f1, $f1, $f2 # CHECK: sel.s $f1, $f1, $f2 # encoding: [0x54,0x41,0x08,0xb8] sel.s $f1, $f1, $f2 # CHECK: sel.s $f1, $f1, $f2 # encoding: [0x54,0x41,0x08,0xb8]
sel.d $f0, $f2, $f4 # CHECK: sel.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x02,0xb8] sel.d $f0, $f2, $f4 # CHECK: sel.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x02,0xb8]
seleqz.s $f1, $f2, $f3 # CHECK: seleqz.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x38] seleqz.s $f1, $f2, $f3 # CHECK: seleqz.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x38]
seleqz.d $f2, $f4, $f8 # CHECK: seleqz.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x38] seleqz.d $f2, $f4, $f8 # CHECK: seleqz.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x38]
selnez.s $f1, $f2, $f3 # CHECK: selnez.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x78] selnez.s $f1, $f2, $f3 # CHECK: selnez.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x78]
selnez.d $f2, $f4, $f8 # CHECK: selnez.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x78] selnez.d $f2, $f4, $f8 # CHECK: selnez.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x78]
class.s $f2, $f3 # CHECK: class.s $f2, $f3 # encoding: [0x54,0x62,0x00,0x60] class.s $f2, $f3 # CHECK: class.s $f2, $f3 # encoding: [0x54,0x62,0x00,0x60]
class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x54,0x82,0x02,0x60] class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x54,0x82,0x02,0x60]
lh $2, 8($4) # CHECK: lh $2, 8($4) # encoding: [0x3c,0x44,0x00,0x08]
lhe $4, 8($2) # CHECK: lhe $4, 8($2) # encoding: [0x60,0x82,0x6a,0x08]
lhu $4, 8($2) # CHECK: lhu $4, 8($2) # encoding: [0x34,0x82,0x00,0x08]
lhue $4, 8($2) # CHECK: lhue $4, 8($2) # encoding: [0x60,0x82,0x62,0x08]
sdardisUnsubmitted
Not Done
ReplyInline Actions

Can you sort these alphabetically into the first 100~ instructions.

sdardis: Can you sort these alphabetically into the first 100~ instructions.

test/MC/Mips/micromips64r6/invalid.s

Show First 20 Lines • Show All 126 Lines • ▼ Show 20 Lines# RUN: FileCheck %s < %t1
swm16 $5, $6, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected swm16 $5, $6, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
swm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected swm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
swm16 $16-$25, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand swm16 $16-$25, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
swm16 $16, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swm16 $16, $17, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16, $17, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lh $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhe $34, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhu $35, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhue $36, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lh $2, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhe $4, 8($33) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhu $4, 8($35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhue $4, 8($37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lh $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhe $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhu $4, 65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

test/MC/Mips/micromips64r6/valid.s

Show First 20 Lines • Show All 140 Lines • ▼ Show 20 Linesa:
sel.s $f1, $f1, $f2 # CHECK: sel.s $f1, $f1, $f2 # encoding: [0x54,0x41,0x08,0xb8] sel.s $f1, $f1, $f2 # CHECK: sel.s $f1, $f1, $f2 # encoding: [0x54,0x41,0x08,0xb8]
sel.d $f0, $f2, $f4 # CHECK: sel.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x02,0xb8] sel.d $f0, $f2, $f4 # CHECK: sel.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x02,0xb8]
seleqz.s $f1, $f2, $f3 # CHECK: seleqz.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x38] seleqz.s $f1, $f2, $f3 # CHECK: seleqz.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x38]
seleqz.d $f2, $f4, $f8 # CHECK: seleqz.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x38] seleqz.d $f2, $f4, $f8 # CHECK: seleqz.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x38]
selnez.s $f1, $f2, $f3 # CHECK: selnez.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x78] selnez.s $f1, $f2, $f3 # CHECK: selnez.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x78]
selnez.d $f2, $f4, $f8 # CHECK: selnez.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x78] selnez.d $f2, $f4, $f8 # CHECK: selnez.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x78]
class.s $f2, $f3 # CHECK: class.s $f2, $f3 # encoding: [0x54,0x62,0x00,0x60] class.s $f2, $f3 # CHECK: class.s $f2, $f3 # encoding: [0x54,0x62,0x00,0x60]
class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x54,0x82,0x02,0x60] class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x54,0x82,0x02,0x60]
lh $2, 8($4) # CHECK: lh $2, 8($4) # encoding: [0x3c,0x44,0x00,0x08]
lhe $4, 8($2) # CHECK: lhe $4, 8($2) # encoding: [0x60,0x82,0x6a,0x08]
lhu $4, 8($2) # CHECK: lhu $4, 8($2) # encoding: [0x34,0x82,0x00,0x08]
lhue $4, 8($2) # CHECK: lhue $4, 8($2) # encoding: [0x60,0x82,0x62,0x08]
1: 1:

test/MC/Mips/mips32r6/invalid.s

Show All 13 Lineslocal_label:
jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
swc2 $25,24880($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled swc2 $25,24880($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
break 1024, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction break 1024, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
break 7, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction break 7, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
break 1024, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction break 1024, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lh $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhe $34, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhu $35, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhue $36, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lh $2, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhe $4, 8($33) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhu $4, 8($35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhue $4, 8($37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lh $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhe $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhu $4, 65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
// FIXME: Following tests are temporarely disabled, until "PredicateControl not in hierarchy" problem is resolved // FIXME: Following tests are temporarely disabled, until "PredicateControl not in hierarchy" problem is resolved
bltl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bltl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bltul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bltul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
blel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled blel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bleul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bleul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bgel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bgel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bgeul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bgeul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bgtl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bgtl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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test/MC/Mips/mips64r6/invalid.s

Show All 11 Lines .set noat
align $4, $2, $3, 4 # CHECK: :[[@LINE]]:29: error: expected 2-bit unsigned immediate align $4, $2, $3, 4 # CHECK: :[[@LINE]]:29: error: expected 2-bit unsigned immediate
jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
break 1024, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction break 1024, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
break 7, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction break 7, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
break 1024, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction break 1024, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lh $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhe $34, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhu $35, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhue $36, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lh $2, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhe $4, 8($33) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhu $4, 8($35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhue $4, 8($37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lh $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhe $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhu $4, 65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
// FIXME: Following tests are temporarely disabled, until "PredicateControl not in hierarchy" problem is resolved // FIXME: Following tests are temporarely disabled, until "PredicateControl not in hierarchy" problem is resolved
bltl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bltl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bltul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bltul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
blel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled blel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bleul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bleul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bgel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bgel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bgeul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bgeul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bgtl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bgtl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
Show All 15 Lines