This is an archive of the discontinued LLVM Phabricator instance.

Differential D153843

[AMDGPU] Add more Common Feature Sets
ClosedPublic

Authored by Pierre-vh on Jun 27 2023, 1:38 AM.

Details

Reviewers
arsenm
foad
rampitec
Commits
rGb6b6c8d2d713: [AMDGPU] Add more Common Feature Sets
Summary

A small refactor to add more _Common feature sets for GFX8+.

Diff Detail

Event Timeline

Pierre-vh created this revision.Jun 27 2023, 1:38 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 27 2023, 1:38 AM
Herald added subscribers: StephenFan, kerbowa, hiraditya and 5 others. · View Herald Transcript
Pierre-vh requested review of this revision.Jun 27 2023, 1:38 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 27 2023, 1:38 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
foad accepted this revision.Jun 27 2023, 1:53 AM

LGTM assuming it's NFC.

llvm/lib/Target/AMDGPU/AMDGPU.td
1240–1255

Nit: I would either spell this gfx101x (like an -mcpu= value) or GFX 10.1.x (like an architecture name).

This revision is now accepted and ready to land.Jun 27 2023, 1:53 AM
Harbormaster completed remote builds in B241399: Diff 534870.Jun 27 2023, 2:39 AM
Pierre-vh updated this revision to Diff 534894.Jun 27 2023, 3:11 AM
Pierre-vh marked an inline comment as done.

The md5 of AMDGPUGenSubtargetInfo.inc didn't change, so this should be a NFC. Is there any other file I can verify to ensure it's not accidentally changing anything?

foad added a comment.Jun 27 2023, 3:36 AM
In D153843#4451783, @Pierre-vh wrote:

The md5 of AMDGPUGenSubtargetInfo.inc didn't change, so this should be a NFC. Is there any other file I can verify to ensure it's not accidentally changing anything?

That's good enough for me!

This revision was landed with ongoing or failed builds.Jun 27 2023, 5:24 AM
Closed by commit rGb6b6c8d2d713: [AMDGPU] Add more Common Feature Sets (authored by Pierre-vh). · Explain Why
This revision was automatically updated to reflect the committed changes.
Pierre-vh added a commit: rGb6b6c8d2d713: [AMDGPU] Add more Common Feature Sets.
Harbormaster completed remote builds in B241419: Diff 534894.Jun 27 2023, 6:08 AM

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
349 lines

Diff 534926

llvm/lib/Target/AMDGPU/AMDGPU.td

Show First 20 Lines • Show All 899 Lines • ▼ Show 20 Lines
>; >;
// Dummy feature used to disable assembler instructions. // Dummy feature used to disable assembler instructions.
def FeatureDisable : SubtargetFeature<"", def FeatureDisable : SubtargetFeature<"",
"FeatureDisable","true", "FeatureDisable","true",
"Dummy feature to disable assembler instructions" "Dummy feature to disable assembler instructions"
>; >;
//===----------------------------------------------------------------------===//
class GCNSubtargetFeatureGeneration <string Value, class GCNSubtargetFeatureGeneration <string Value,
string FeatureName, string FeatureName,
list<SubtargetFeature> Implies> : list<SubtargetFeature> Implies> :
SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>; SubtargetFeatureGeneration <Value, FeatureName, "GCNSubtarget", Implies>;
def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS", def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
"southern-islands", "southern-islands",
[FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128, [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Linesdef FeatureGFX11 : GCNSubtargetFeatureGeneration<"GFX11",
FeatureNoSdstCMPX, FeatureVscnt, FeatureNoSdstCMPX, FeatureVscnt,
FeatureVOP3Literal, FeatureDPP8, FeatureExtendedImageInsts, FeatureVOP3Literal, FeatureDPP8, FeatureExtendedImageInsts,
FeatureNoDataDepHazard, FeaturePkFmacF16Inst, FeatureNoDataDepHazard, FeaturePkFmacF16Inst,
FeatureA16, FeatureFastDenormalF32, FeatureG16, FeatureA16, FeatureFastDenormalF32, FeatureG16,
FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess
] ]
>; >;
//===----------------------------------------------------------------------===//
class FeatureSet<list<SubtargetFeature> Features_> { class FeatureSet<list<SubtargetFeature> Features_> {
list<SubtargetFeature> Features = Features_; list<SubtargetFeature> Features = Features_;
} }
def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands, def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,
FeatureFastFMAF32, FeatureFastFMAF32,
HalfRate64Ops, HalfRate64Ops,
FeatureLDSBankCount32]>; FeatureLDSBankCount32]>;
Show All 28 Lines
def FeatureISAVersion7_0_4 : FeatureSet< def FeatureISAVersion7_0_4 : FeatureSet<
[FeatureSeaIslands, [FeatureSeaIslands,
FeatureLDSBankCount32]>; FeatureLDSBankCount32]>;
def FeatureISAVersion7_0_5 : FeatureSet< def FeatureISAVersion7_0_5 : FeatureSet<
[FeatureSeaIslands, [FeatureSeaIslands,
FeatureLDSBankCount16]>; FeatureLDSBankCount16]>;
def FeatureISAVersion8_0_1 : FeatureSet< def FeatureISAVersion8_0_Common : FeatureSet<
[FeatureVolcanicIslands, [FeatureVolcanicIslands,
FeatureFastFMAF32,
HalfRate64Ops,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureSupportsXNACK,
FeatureUnpackedD16VMem]>; FeatureUnpackedD16VMem]>;
def FeatureISAVersion8_0_1 : FeatureSet<
!listconcat(FeatureISAVersion8_0_Common.Features,
[FeatureFastFMAF32,
HalfRate64Ops,
FeatureSupportsXNACK])>;
def FeatureISAVersion8_0_2 : FeatureSet< def FeatureISAVersion8_0_2 : FeatureSet<
[FeatureVolcanicIslands, !listconcat(FeatureISAVersion8_0_Common.Features,
FeatureLDSBankCount32, [FeatureSGPRInitBug])>;
FeatureSGPRInitBug,
FeatureUnpackedD16VMem]>;
def FeatureISAVersion8_0_3 : FeatureSet< def FeatureISAVersion8_0_3 : FeatureSet<
[FeatureVolcanicIslands, !listconcat(FeatureISAVersion8_0_Common.Features,
FeatureLDSBankCount32, [])>;
FeatureUnpackedD16VMem]>;
def FeatureISAVersion8_0_5 : FeatureSet< def FeatureISAVersion8_0_5 : FeatureSet<
[FeatureVolcanicIslands, !listconcat(FeatureISAVersion8_0_Common.Features,
FeatureLDSBankCount32, [FeatureSGPRInitBug])>;
FeatureSGPRInitBug,
FeatureUnpackedD16VMem]>;
def FeatureISAVersion8_1_0 : FeatureSet< def FeatureISAVersion8_1_0 : FeatureSet<
[FeatureVolcanicIslands, [FeatureVolcanicIslands,
FeatureLDSBankCount16, FeatureLDSBankCount16,
FeatureSupportsXNACK, FeatureSupportsXNACK,
FeatureImageStoreD16Bug, FeatureImageStoreD16Bug,
FeatureImageGather4D16Bug]>; FeatureImageGather4D16Bug]>;
def FeatureISAVersion9_0_0 : FeatureSet< def FeatureISAVersion9_0_Common : FeatureSet<
[FeatureGFX9, [FeatureGFX9,
FeatureMadMixInsts,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureImageInsts,
FeatureMadMacF32Insts]>;
def FeatureISAVersion9_0_MI_Common : FeatureSet<
!listconcat(FeatureISAVersion9_0_Common.Features,
[FeatureFmaMixInsts,
FeatureDLInsts,
FeatureDot1Insts,
FeatureDot2Insts,
FeatureDot3Insts,
FeatureDot4Insts,
FeatureDot5Insts,
FeatureDot6Insts,
FeatureDot7Insts,
FeatureDot10Insts,
FeatureMAIInsts,
FeaturePkFmacF16Inst,
FeatureAtomicFaddNoRtnInsts,
FeatureSupportsSRAMECC])>;
def FeatureISAVersion9_0_0 : FeatureSet<
!listconcat(FeatureISAVersion9_0_Common.Features,
[FeatureMadMixInsts,
FeatureDsSrc2Insts, FeatureDsSrc2Insts,
FeatureExtendedImageInsts, FeatureExtendedImageInsts,
FeatureImageInsts, FeatureImageGather4D16Bug])>;
FeatureMadMacF32Insts,
FeatureImageGather4D16Bug]>;
def FeatureISAVersion9_0_2 : FeatureSet< def FeatureISAVersion9_0_2 : FeatureSet<
[FeatureGFX9, !listconcat(FeatureISAVersion9_0_Common.Features,
FeatureMadMixInsts, [FeatureMadMixInsts,
FeatureLDSBankCount32,
FeatureDsSrc2Insts, FeatureDsSrc2Insts,
FeatureExtendedImageInsts, FeatureExtendedImageInsts,
FeatureImageInsts, FeatureImageGather4D16Bug])>;
FeatureMadMacF32Insts,
FeatureImageGather4D16Bug]>;
def FeatureISAVersion9_0_4 : FeatureSet< def FeatureISAVersion9_0_4 : FeatureSet<
[FeatureGFX9, !listconcat(FeatureISAVersion9_0_Common.Features,
FeatureLDSBankCount32, [FeatureDsSrc2Insts,
FeatureDsSrc2Insts,
FeatureExtendedImageInsts, FeatureExtendedImageInsts,
FeatureImageInsts,
FeatureMadMacF32Insts,
FeatureFmaMixInsts, FeatureFmaMixInsts,
FeatureImageGather4D16Bug]>; FeatureImageGather4D16Bug])>;
def FeatureISAVersion9_0_6 : FeatureSet< def FeatureISAVersion9_0_6 : FeatureSet<
[FeatureGFX9, !listconcat(FeatureISAVersion9_0_Common.Features,
HalfRate64Ops, [HalfRate64Ops,
FeatureFmaMixInsts, FeatureFmaMixInsts,
FeatureLDSBankCount32,
FeatureDsSrc2Insts, FeatureDsSrc2Insts,
FeatureExtendedImageInsts, FeatureExtendedImageInsts,
FeatureImageInsts,
FeatureMadMacF32Insts,
FeatureDLInsts, FeatureDLInsts,
FeatureDot1Insts, FeatureDot1Insts,
FeatureDot2Insts, FeatureDot2Insts,
FeatureDot7Insts, FeatureDot7Insts,
FeatureDot10Insts, FeatureDot10Insts,
FeatureSupportsSRAMECC, FeatureSupportsSRAMECC,
FeatureImageGather4D16Bug]>; FeatureImageGather4D16Bug])>;
def FeatureISAVersion9_0_8 : FeatureSet< def FeatureISAVersion9_0_8 : FeatureSet<
[FeatureGFX9, !listconcat(FeatureISAVersion9_0_MI_Common.Features,
HalfRate64Ops, [HalfRate64Ops,
FeatureFmaMixInsts,
FeatureLDSBankCount32,
FeatureDsSrc2Insts, FeatureDsSrc2Insts,
FeatureExtendedImageInsts, FeatureExtendedImageInsts,
FeatureImageInsts,
FeatureMadMacF32Insts,
FeatureDLInsts,
FeatureDot1Insts,
FeatureDot2Insts,
FeatureDot3Insts,
FeatureDot4Insts,
FeatureDot5Insts,
FeatureDot6Insts,
FeatureDot7Insts,
FeatureDot10Insts,
FeatureMAIInsts,
FeaturePkFmacF16Inst,
FeatureAtomicFaddNoRtnInsts,
FeatureAtomicBufferGlobalPkAddF16NoRtnInsts, FeatureAtomicBufferGlobalPkAddF16NoRtnInsts,
FeatureSupportsSRAMECC,
FeatureMFMAInlineLiteralBug, FeatureMFMAInlineLiteralBug,
FeatureImageGather4D16Bug]>; FeatureImageGather4D16Bug])>;
def FeatureISAVersion9_0_9 : FeatureSet< def FeatureISAVersion9_0_9 : FeatureSet<
[FeatureGFX9, !listconcat(FeatureISAVersion9_0_Common.Features,
FeatureMadMixInsts, [FeatureMadMixInsts,
FeatureLDSBankCount32,
FeatureDsSrc2Insts, FeatureDsSrc2Insts,
FeatureExtendedImageInsts, FeatureExtendedImageInsts,
FeatureImageInsts, FeatureImageInsts,
FeatureMadMacF32Insts, FeatureImageGather4D16Bug])>;
FeatureImageGather4D16Bug]>;
def FeatureISAVersion9_0_A : FeatureSet< def FeatureISAVersion9_0_A : FeatureSet<
[FeatureGFX9, !listconcat(FeatureISAVersion9_0_MI_Common.Features,
FeatureGFX90AInsts, [FeatureGFX90AInsts,
FeatureFmaMixInsts,
FeatureLDSBankCount32,
FeatureDLInsts,
FeatureFmacF64Inst, FeatureFmacF64Inst,
FeatureDot1Insts,
FeatureDot2Insts,
FeatureDot3Insts,
FeatureDot4Insts,
FeatureDot5Insts,
FeatureDot6Insts,
FeatureDot7Insts,
FeatureDot10Insts,
Feature64BitDPP, Feature64BitDPP,
FeaturePackedFP32Ops, FeaturePackedFP32Ops,
FeatureMAIInsts,
FeaturePkFmacF16Inst,
FeatureAtomicFaddRtnInsts, FeatureAtomicFaddRtnInsts,
FeatureAtomicFaddNoRtnInsts,
FeatureAtomicBufferGlobalPkAddF16Insts, FeatureAtomicBufferGlobalPkAddF16Insts,
FeatureImageInsts,
FeatureMadMacF32Insts,
FeatureSupportsSRAMECC,
FeaturePackedTID, FeaturePackedTID,
FullRate64Ops, FullRate64Ops,
FeatureBackOffBarrier]>; FeatureBackOffBarrier])>;
def FeatureISAVersion9_0_C : FeatureSet< def FeatureISAVersion9_0_C : FeatureSet<
[FeatureGFX9, !listconcat(FeatureISAVersion9_0_Common.Features,
FeatureMadMixInsts, [FeatureMadMixInsts,
FeatureLDSBankCount32,
FeatureDsSrc2Insts, FeatureDsSrc2Insts,
FeatureExtendedImageInsts, FeatureExtendedImageInsts,
FeatureImageInsts, FeatureImageGather4D16Bug])>;
FeatureMadMacF32Insts,
FeatureImageGather4D16Bug]>;
def FeatureISAVersion9_4_Common : FeatureSet< def FeatureISAVersion9_4_Common : FeatureSet<
[FeatureGFX9, [FeatureGFX9,
FeatureGFX90AInsts, FeatureGFX90AInsts,
FeatureGFX940Insts, FeatureGFX940Insts,
FeatureFmaMixInsts, FeatureFmaMixInsts,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureDLInsts, FeatureDLInsts,
Show All 31 Lines
def FeatureISAVersion9_4_1 : FeatureSet< def FeatureISAVersion9_4_1 : FeatureSet<
!listconcat(FeatureISAVersion9_4_Common.Features, !listconcat(FeatureISAVersion9_4_Common.Features,
[FeatureForceStoreSC0SC1])>; [FeatureForceStoreSC0SC1])>;
def FeatureISAVersion9_4_2 : FeatureSet< def FeatureISAVersion9_4_2 : FeatureSet<
!listconcat(FeatureISAVersion9_4_Common.Features, !listconcat(FeatureISAVersion9_4_Common.Features,
[])>; [])>;
// TODO: Organize more features into groups. def FeatureISAVersion10_Common : FeatureSet<
def FeatureGroup {
// Bugs present on gfx10.1.
list<SubtargetFeature> GFX10_1_Bugs = [
FeatureVcmpxPermlaneHazard,
FeatureVMEMtoScalarWriteHazard,
FeatureSMEMtoVectorWriteHazard,
FeatureInstFwdPrefetchBug,
FeatureVcmpxExecWARHazard,
FeatureLdsBranchVmemWARHazard,
FeatureNSAtoVMEMBug,
FeatureNSAClauseBug,
FeatureOffset3fBug,
FeatureFlatSegmentOffsetBug,
FeatureNegativeUnalignedScratchOffsetBug
];
}
def FeatureISAVersion10_1_0 : FeatureSet<
!listconcat(FeatureGroup.GFX10_1_Bugs,
[FeatureGFX10, [FeatureGFX10,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureDLInsts, FeatureDLInsts,
FeatureNSAEncoding, FeatureNSAEncoding,
FeatureWavefrontSize32, FeatureWavefrontSize32,
FeatureScalarStores, FeatureBackOffBarrier]>;
def FeatureISAVersion10_1_Common : FeatureSet<
!listconcat(FeatureISAVersion10_Common.Features,
[FeatureScalarStores,
FeatureScalarAtomics, FeatureScalarAtomics,
FeatureScalarFlatScratchInsts, FeatureScalarFlatScratchInsts,
FeatureGetWaveIdInst, FeatureGetWaveIdInst,
FeatureMadMacF32Insts, FeatureMadMacF32Insts,
FeatureDsSrc2Insts, FeatureDsSrc2Insts,
FeatureLdsMisalignedBug, FeatureLdsMisalignedBug,
FeatureSupportsXNACK, FeatureSupportsXNACK,
FeatureBackOffBarrier])>; // gfx101x bugs
FeatureVcmpxPermlaneHazard,
FeatureVMEMtoScalarWriteHazard,
FeatureSMEMtoVectorWriteHazard,
FeatureInstFwdPrefetchBug,
FeatureVcmpxExecWARHazard,
FeatureLdsBranchVmemWARHazard,
FeatureNSAtoVMEMBug,
FeatureNSAClauseBug,
FeatureOffset3fBug,
FeatureFlatSegmentOffsetBug,
FeatureNegativeUnalignedScratchOffsetBug])>;
def FeatureISAVersion10_1_0 : FeatureSet<
!listconcat(FeatureISAVersion10_1_Common.Features,
[])>;
foadUnsubmitted
Done
ReplyInline Actions

Nit: I would either spell this gfx101x (like an -mcpu= value) or GFX 10.1.x (like an architecture name).

foad: Nit: I would either spell this gfx101x (like an -mcpu= value) or GFX 10.1.x (like an…
def FeatureISAVersion10_1_1 : FeatureSet< def FeatureISAVersion10_1_1 : FeatureSet<
!listconcat(FeatureGroup.GFX10_1_Bugs, !listconcat(FeatureISAVersion10_1_Common.Features,
[FeatureGFX10, [FeatureDot1Insts,
FeatureLDSBankCount32,
FeatureDLInsts,
FeatureDot1Insts,
FeatureDot2Insts, FeatureDot2Insts,
FeatureDot5Insts, FeatureDot5Insts,
FeatureDot6Insts, FeatureDot6Insts,
FeatureDot7Insts, FeatureDot7Insts,
FeatureDot10Insts, FeatureDot10Insts])>;
FeatureNSAEncoding,
FeatureWavefrontSize32,
FeatureScalarStores,
FeatureScalarAtomics,
FeatureScalarFlatScratchInsts,
FeatureGetWaveIdInst,
FeatureMadMacF32Insts,
FeatureDsSrc2Insts,
FeatureLdsMisalignedBug,
FeatureSupportsXNACK,
FeatureBackOffBarrier])>;
def FeatureISAVersion10_1_2 : FeatureSet< def FeatureISAVersion10_1_2 : FeatureSet<
!listconcat(FeatureGroup.GFX10_1_Bugs, !listconcat(FeatureISAVersion10_1_Common.Features,
[FeatureGFX10, [FeatureDot1Insts,
FeatureLDSBankCount32,
FeatureDLInsts,
FeatureDot1Insts,
FeatureDot2Insts, FeatureDot2Insts,
FeatureDot5Insts, FeatureDot5Insts,
FeatureDot6Insts, FeatureDot6Insts,
FeatureDot7Insts, FeatureDot7Insts,
FeatureDot10Insts, FeatureDot10Insts])>;
FeatureNSAEncoding,
FeatureWavefrontSize32,
FeatureScalarStores,
FeatureScalarAtomics,
FeatureScalarFlatScratchInsts,
FeatureGetWaveIdInst,
FeatureMadMacF32Insts,
FeatureDsSrc2Insts,
FeatureLdsMisalignedBug,
FeatureSupportsXNACK,
FeatureBackOffBarrier])>;
def FeatureISAVersion10_1_3 : FeatureSet< def FeatureISAVersion10_1_3 : FeatureSet<
!listconcat(FeatureGroup.GFX10_1_Bugs, !listconcat(FeatureISAVersion10_1_Common.Features,
[FeatureGFX10, [FeatureGFX10_AEncoding])>;
FeatureGFX10_AEncoding,
FeatureLDSBankCount32,
FeatureDLInsts,
FeatureNSAEncoding,
FeatureWavefrontSize32,
FeatureScalarStores,
FeatureScalarAtomics,
FeatureScalarFlatScratchInsts,
FeatureGetWaveIdInst,
FeatureMadMacF32Insts,
FeatureDsSrc2Insts,
FeatureLdsMisalignedBug,
FeatureSupportsXNACK,
FeatureBackOffBarrier])>;
def FeatureISAVersion10_3_0 : FeatureSet< def FeatureISAVersion10_3_0 : FeatureSet<
[FeatureGFX10, !listconcat(FeatureISAVersion10_Common.Features,
FeatureGFX10_AEncoding, [FeatureGFX10_AEncoding,
FeatureGFX10_BEncoding, FeatureGFX10_BEncoding,
FeatureGFX10_3Insts, FeatureGFX10_3Insts,
FeatureLDSBankCount32,
FeatureDLInsts,
FeatureDot1Insts, FeatureDot1Insts,
FeatureDot2Insts, FeatureDot2Insts,
FeatureDot5Insts, FeatureDot5Insts,
FeatureDot6Insts, FeatureDot6Insts,
FeatureDot7Insts, FeatureDot7Insts,
FeatureDot10Insts, FeatureDot10Insts,
FeatureNSAEncoding, FeatureShaderCyclesRegister])>;
FeatureWavefrontSize32,
FeatureShaderCyclesRegister,
FeatureBackOffBarrier]>;
def FeatureISAVersion11_Common : FeatureSet< def FeatureISAVersion11_Common : FeatureSet<
[FeatureGFX11, [FeatureGFX11,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureDLInsts, FeatureDLInsts,
FeatureDot5Insts, FeatureDot5Insts,
FeatureDot7Insts, FeatureDot7Insts,
FeatureDot8Insts, FeatureDot8Insts,
▲ Show 20 Lines • Show All 539 Lines • Show Last 20 Lines