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Differential D153793

[RISCV] Fix encoding for Zcb instruction c.sh.
ClosedPublic

Authored by craig.topper on Jun 26 2023, 11:03 AM.

Details

Reviewers
asb
VincentWu
jrtc27
Commits
rGa32499fba959: [RISCV] Fix encoding for Zcb instruction c.sh.
Summary

Bit 6 should be 0.

Diff Detail

Event Timeline

craig.topper created this revision.Jun 26 2023, 11:03 AM
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craig.topper requested review of this revision.Jun 26 2023, 11:03 AM
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Harbormaster completed remote builds in B241248: Diff 534657.Jun 26 2023, 1:01 PM
asb accepted this revision.Jun 27 2023, 5:49 AM

LGTM, good catch. I stepped through the other Zcb instructions (PDF vs tblgen field bits<16> Inst = { ... } and didn't see other errors FWIW.

This revision is now accepted and ready to land.Jun 27 2023, 5:49 AM
This revision was landed with ongoing or failed builds.Jun 27 2023, 9:45 AM
Closed by commit rGa32499fba959: [RISCV] Fix encoding for Zcb instruction c.sh. (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rGa32499fba959: [RISCV] Fix encoding for Zcb instruction c.sh..

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
2 lines
test/
MC/
RISCV/
6 lines

Diff 535029

llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

Show First 20 Lines • Show All 168 Lines • ▼ Show 20 Linesdef C_LBU : CLoadB_ri<0b100000, "c.lbu">,
Sched<[WriteLDB, ReadMemBase]>; Sched<[WriteLDB, ReadMemBase]>;
def C_LHU : CLoadH_ri<0b100001, 0b0, "c.lhu">, def C_LHU : CLoadH_ri<0b100001, 0b0, "c.lhu">,
Sched<[WriteLDH, ReadMemBase]>; Sched<[WriteLDH, ReadMemBase]>;
def C_LH : CLoadH_ri<0b100001, 0b1, "c.lh">, def C_LH : CLoadH_ri<0b100001, 0b1, "c.lh">,
Sched<[WriteLDH, ReadMemBase]>; Sched<[WriteLDH, ReadMemBase]>;
def C_SB : CStoreB_rri<0b100010, "c.sb">, def C_SB : CStoreB_rri<0b100010, "c.sb">,
Sched<[WriteSTB, ReadStoreData, ReadMemBase]>; Sched<[WriteSTB, ReadStoreData, ReadMemBase]>;
def C_SH : CStoreH_rri<0b100011, 0b1, "c.sh">, def C_SH : CStoreH_rri<0b100011, 0b0, "c.sh">,
Sched<[WriteSTH, ReadStoreData, ReadMemBase]>; Sched<[WriteSTH, ReadStoreData, ReadMemBase]>;
} }
// Zcmp // Zcmp
let DecoderNamespace = "RVZcmp", Predicates = [HasStdExtZcmp], let DecoderNamespace = "RVZcmp", Predicates = [HasStdExtZcmp],
Defs = [X10, X11], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { Defs = [X10, X11], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
def CM_MVA01S : RVInst16CA<0b101011, 0b11, 0b10, (outs), def CM_MVA01S : RVInst16CA<0b101011, 0b11, 0b10, (outs),
(ins SR07:$rs1, SR07:$rs2), "cm.mva01s", "$rs1, $rs2">; (ins SR07:$rs1, SR07:$rs2), "cm.mva01s", "$rs1, $rs2">;
▲ Show 20 Lines • Show All 134 Lines • Show Last 20 Lines

llvm/test/MC/RISCV/rv32zcb-valid.s

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
c.lh a5, 2(a4) c.lh a5, 2(a4)
# CHECK-ASM-AND-OBJ: c.sb a5, 2(a4) # CHECK-ASM-AND-OBJ: c.sb a5, 2(a4)
# CHECK-ASM: encoding: [0x3c,0x8b] # CHECK-ASM: encoding: [0x3c,0x8b]
# CHECK-NO-EXT: error: instruction requires the following: 'Zcb' (Compressed basic bit manipulation instructions){{$}} # CHECK-NO-EXT: error: instruction requires the following: 'Zcb' (Compressed basic bit manipulation instructions){{$}}
c.sb a5, 2(a4) c.sb a5, 2(a4)
# CHECK-ASM-AND-OBJ: c.sh a5, 2(a4) # CHECK-ASM-AND-OBJ: c.sh a5, 2(a4)
# CHECK-ASM: encoding: [0x7c,0x8f] # CHECK-ASM: encoding: [0x3c,0x8f]
# CHECK-NO-EXT: error: instruction requires the following: 'Zcb' (Compressed basic bit manipulation instructions){{$}} # CHECK-NO-EXT: error: instruction requires the following: 'Zcb' (Compressed basic bit manipulation instructions){{$}}
c.sh a5, 2(a4) c.sh a5, 2(a4)
# CHECK-ASM-AND-OBJ: c.mul s0, s1 # CHECK-ASM-AND-OBJ: c.mul s0, s1
# CHECK-ASM: encoding: [0x45,0x9c] # CHECK-ASM: encoding: [0x45,0x9c]
mul s0, s1, s0 mul s0, s1, s0
# CHECK-ASM-AND-OBJ: c.mul s0, s1 # CHECK-ASM-AND-OBJ: c.mul s0, s1
Show All 32 Lines
# CHECK-ASM: encoding: [0x3c,0x87] # CHECK-ASM: encoding: [0x3c,0x87]
lhu a5, 2(a4) lhu a5, 2(a4)
# CHECK-ASM-AND-OBJ: c.sb a5, 2(a4) # CHECK-ASM-AND-OBJ: c.sb a5, 2(a4)
# CHECK-ASM: encoding: [0x3c,0x8b] # CHECK-ASM: encoding: [0x3c,0x8b]
sb a5, 2(a4) sb a5, 2(a4)
# CHECK-ASM-AND-OBJ: c.sh a5, 2(a4) # CHECK-ASM-AND-OBJ: c.sh a5, 2(a4)
# CHECK-ASM: encoding: [0x7c,0x8f] # CHECK-ASM: encoding: [0x3c,0x8f]
sh a5, 2(a4) sh a5, 2(a4)
# CHECK-ASM-AND-OBJ: c.lbu s0, 0(s1) # CHECK-ASM-AND-OBJ: c.lbu s0, 0(s1)
# CHECK-ASM: encoding: [0x80,0x80] # CHECK-ASM: encoding: [0x80,0x80]
c.lbu s0, (s1) c.lbu s0, (s1)
# CHECK-ASM-AND-OBJ: c.lhu s0, 0(s1) # CHECK-ASM-AND-OBJ: c.lhu s0, 0(s1)
# CHECK-ASM: encoding: [0x80,0x84] # CHECK-ASM: encoding: [0x80,0x84]
c.lhu s0, (s1) c.lhu s0, (s1)
# CHECK-ASM-AND-OBJ: c.lh s0, 0(s1) # CHECK-ASM-AND-OBJ: c.lh s0, 0(s1)
# CHECK-ASM: encoding: [0xc0,0x84] # CHECK-ASM: encoding: [0xc0,0x84]
c.lh s0, (s1) c.lh s0, (s1)
# CHECK-ASM-AND-OBJ: c.sb s0, 0(s1) # CHECK-ASM-AND-OBJ: c.sb s0, 0(s1)
# CHECK-ASM: encoding: [0x80,0x88] # CHECK-ASM: encoding: [0x80,0x88]
c.sb s0, (s1) c.sb s0, (s1)
# CHECK-ASM-AND-OBJ: c.sh s0, 0(s1) # CHECK-ASM-AND-OBJ: c.sh s0, 0(s1)
# CHECK-ASM: encoding: [0xc0,0x8c] # CHECK-ASM: encoding: [0x80,0x8c]
c.sh s0, (s1) c.sh s0, (s1)