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Differential D153537

[AMDGPU] Do not wait for vscnt on function entry and return
ClosedPublic

Authored by foad on Jun 22 2023, 5:31 AM.

Details

Reviewers
nhaehnle
mareko
rampitec
kerbowa
stepthomas
arsenm
Group Reviewers
Restricted Project
Commits
rGf2c164c81505: [AMDGPU] Do not wait for vscnt on function entry and return
Summary

SIInsertWaitcnts inserts waitcnt instructions to resolve data
dependencies. The GFX10+ vscnt (VMEM store count) counter is never used
in this way. It is only used to resolve memory dependencies, and that is
handled by SIMemoryLegalizer. Hence there is no need to conservatively
wait for vscnt to be 0 on function entry and before returns.

Diff Detail

Unit TestsFailed

TimeTest
3,800 msx64 debian > AddressSanitizer-x86_64-linux.TestCases/Linux::auto_memory_profile_test.cpp

Event Timeline

foad created this revision.Jun 22 2023, 5:31 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 22 2023, 5:31 AM
Herald added subscribers: bzcheeseman, StephenFan, wenlei and 7 others. · View Herald Transcript
foad requested review of this revision.Jun 22 2023, 5:31 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 22 2023, 5:31 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
foad added inline comments.Jun 22 2023, 5:33 AM
llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
1231

@kerbowa unlike the rest of SIInsertWaitcnts, I assume this part does want to wait for vscnt==0 since it is handling memory dependencies?

Harbormaster completed remote builds in B240481: Diff 533569.Jun 22 2023, 6:50 AM
arsenm added inline comments.Jun 22 2023, 7:24 AM
llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
70

These were super annoying

kerbowa added inline comments.Jun 25 2023, 4:42 PM
llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
1231

Technically it should not matter on HW with VScnt since they all can back off barriers, so this 'if' should never be true on Navi. There is an exception currently with gfx11 because of the memory model description bug with cumode, but that should be temporary.

foad added a comment.Jul 3 2023, 7:29 AM

Ping!

This does not change the ABI. It just removes a bunch of wait instructions that were never required in the first place.

arsenm added a comment.Jul 3 2023, 7:56 AM

It is only used to resolve memory dependencies, and that is handled by SIMemoryLegalizer.

The idea was the stores on the caller side don't need to wait to finish because the prolog wait will take care of it after the latency of the jump. Is the memory legalizer not taking advantage of this?

foad added a comment.Jul 3 2023, 8:02 AM

It is only used to resolve memory dependencies, and that is handled by SIMemoryLegalizer.

The idea was the stores on the caller side don't need to wait to finish because the prolog wait will take care of it after the latency of the jump. Is the memory legalizer not taking advantage of this?

I don't see how it can be taking advantage of that, because it only considers each load or store in isolation.

arsenm added a comment.Jul 3 2023, 8:14 AM
In D153537#4468557, @foad wrote:

It is only used to resolve memory dependencies, and that is handled by SIMemoryLegalizer.

The idea was the stores on the caller side don't need to wait to finish because the prolog wait will take care of it after the latency of the jump. Is the memory legalizer not taking advantage of this?

I don't see how it can be taking advantage of that, because it only considers each load or store in isolation.

Would that just be an implementation deficiency? With something like https://godbolt.org/z/55YEn473W where does the wait happen?

foad added a comment.Jul 3 2023, 8:20 AM

With something like https://godbolt.org/z/55YEn473W where does the wait happen?

No wait is required. The store and the load stay in order. SIMemoryLegalizer does not insert one, irrespective of whether the store and load are in the same function or not.

arsenm accepted this revision.Jul 3 2023, 9:18 AM

LGTM I guess wait would only be needed in the atomic case anyway?

This revision is now accepted and ready to land.Jul 3 2023, 9:18 AM
foad updated this revision to Diff 537051.Jul 4 2023, 4:25 AM

Rebase.

This revision was landed with ongoing or failed builds.Jul 4 2023, 4:26 AM
Closed by commit rGf2c164c81505: [AMDGPU] Do not wait for vscnt on function entry and return (authored by foad). · Explain Why
This revision was automatically updated to reflect the committed changes.
foad added a commit: rGf2c164c81505: [AMDGPU] Do not wait for vscnt on function entry and return.
Harbormaster completed remote builds in B243009: Diff 537051.Jul 4 2023, 5:40 AM

Large Diff

This large diff affects 205 files. Files without inline comments have been collapsed. Expand All Files

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Diff 537051

llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp

Show First 20 Lines • Show All 413 Lines • ▼ Show 20 Linespublic:
bool isForceEmitWaitcnt() const { bool isForceEmitWaitcnt() const {
for (auto T : inst_counter_types()) for (auto T : inst_counter_types())
if (ForceEmitWaitcnt[T]) if (ForceEmitWaitcnt[T])
return true; return true;
return false; return false;
} }
AMDGPU::Waitcnt allZeroWaitcnt() const {
return AMDGPU::Waitcnt::allZero(ST->hasVscnt());
}
void setForceEmitWaitcnt() { void setForceEmitWaitcnt() {
// For non-debug builds, ForceEmitWaitcnt has been initialized to false; // For non-debug builds, ForceEmitWaitcnt has been initialized to false;
// For debug builds, get the debug counter info and adjust if need be // For debug builds, get the debug counter info and adjust if need be
#ifndef NDEBUG #ifndef NDEBUG
if (DebugCounter::isCounterSet(ForceExpCounter) && if (DebugCounter::isCounterSet(ForceExpCounter) &&
DebugCounter::shouldExecute(ForceExpCounter)) { DebugCounter::shouldExecute(ForceExpCounter)) {
ForceEmitWaitcnt[EXP_CNT] = true; ForceEmitWaitcnt[EXP_CNT] = true;
} else { } else {
▲ Show 20 Lines • Show All 597 Lines • ▼ Show 20 Linesbool SIInsertWaitcnts::generateWaitcntInstBefore(MachineInstr &MI,
// All waits must be resolved at call return. // All waits must be resolved at call return.
// NOTE: this could be improved with knowledge of all call sites or // NOTE: this could be improved with knowledge of all call sites or
// with knowledge of the called routines. // with knowledge of the called routines.
if (MI.getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG || if (MI.getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG ||
MI.getOpcode() == AMDGPU::SI_RETURN || MI.getOpcode() == AMDGPU::SI_RETURN ||
MI.getOpcode() == AMDGPU::S_SETPC_B64_return || MI.getOpcode() == AMDGPU::S_SETPC_B64_return ||
(MI.isReturn() && MI.isCall() && !callWaitsOnFunctionEntry(MI))) { (MI.isReturn() && MI.isCall() && !callWaitsOnFunctionEntry(MI))) {
Wait = Wait.combined(allZeroWaitcnt()); Wait = Wait.combined(AMDGPU::Waitcnt::allZeroExceptVsCnt());
} }
// Identify S_ENDPGM instructions which may have to wait for outstanding VMEM // Identify S_ENDPGM instructions which may have to wait for outstanding VMEM
// stores. In this case it can be useful to send a message to explicitly // stores. In this case it can be useful to send a message to explicitly
// release all VGPRs before the stores have completed, but it is only safe to // release all VGPRs before the stores have completed, but it is only safe to
// do this if there are no outstanding scratch stores. // do this if there are no outstanding scratch stores.
else if (MI.getOpcode() == AMDGPU::S_ENDPGM || else if (MI.getOpcode() == AMDGPU::S_ENDPGM ||
MI.getOpcode() == AMDGPU::S_ENDPGM_SAVED) { MI.getOpcode() == AMDGPU::S_ENDPGM_SAVED) {
if (ST->getGeneration() >= AMDGPUSubtarget::GFX11 && if (ST->getGeneration() >= AMDGPUSubtarget::GFX11 &&
▲ Show 20 Lines • Show All 179 Lines • ▼ Show 20 Lines#endif
} }
// The subtarget may have an implicit S_WAITCNT 0 before barriers. If it does // The subtarget may have an implicit S_WAITCNT 0 before barriers. If it does
// not, we need to ensure the subtarget is capable of backing off barrier // not, we need to ensure the subtarget is capable of backing off barrier
// instructions in case there are any outstanding memory operations that may // instructions in case there are any outstanding memory operations that may
// cause an exception. Otherwise, insert an explicit S_WAITCNT 0 here. // cause an exception. Otherwise, insert an explicit S_WAITCNT 0 here.
if (MI.getOpcode() == AMDGPU::S_BARRIER && if (MI.getOpcode() == AMDGPU::S_BARRIER &&
!ST->hasAutoWaitcntBeforeBarrier() && !ST->supportsBackOffBarrier()) { !ST->hasAutoWaitcntBeforeBarrier() && !ST->supportsBackOffBarrier()) {
Wait = Wait.combined(allZeroWaitcnt()); Wait = Wait.combined(AMDGPU::Waitcnt::allZero(ST->hasVscnt()));
foadAuthorUnsubmitted
Done
ReplyInline Actions

@kerbowa unlike the rest of SIInsertWaitcnts, I assume this part does want to wait for vscnt==0 since it is handling memory dependencies?

foad: @kerbowa unlike the rest of SIInsertWaitcnts, I assume this part does want to wait for vscnt==0…
kerbowaUnsubmitted
Not Done
ReplyInline Actions

Technically it should not matter on HW with VScnt since they all can back off barriers, so this 'if' should never be true on Navi. There is an exception currently with gfx11 because of the memory model description bug with cumode, but that should be temporary.

kerbowa: Technically it should not matter on HW with VScnt since they all can back off barriers, so this…
} }
// TODO: Remove this work-around, enable the assert for Bug 457939 // TODO: Remove this work-around, enable the assert for Bug 457939
// after fixing the scheduler. Also, the Shader Compiler code is // after fixing the scheduler. Also, the Shader Compiler code is
// independent of target. // independent of target.
if (readsVCCZ(MI) && ST->hasReadVCCZBug()) { if (readsVCCZ(MI) && ST->hasReadVCCZBug()) {
if (ScoreBrackets.hasPendingEvent(SMEM_ACCESS)) { if (ScoreBrackets.hasPendingEvent(SMEM_ACCESS)) {
Wait.LgkmCnt = 0; Wait.LgkmCnt = 0;
} }
} }
// Verify that the wait is actually needed. // Verify that the wait is actually needed.
ScoreBrackets.simplifyWaitcnt(Wait); ScoreBrackets.simplifyWaitcnt(Wait);
if (ForceEmitZeroWaitcnts) if (ForceEmitZeroWaitcnts)
Wait = allZeroWaitcnt(); Wait = AMDGPU::Waitcnt::allZeroExceptVsCnt();
if (ForceEmitWaitcnt[VM_CNT]) if (ForceEmitWaitcnt[VM_CNT])
Wait.VmCnt = 0; Wait.VmCnt = 0;
if (ForceEmitWaitcnt[EXP_CNT]) if (ForceEmitWaitcnt[EXP_CNT])
Wait.ExpCnt = 0; Wait.ExpCnt = 0;
if (ForceEmitWaitcnt[LGKM_CNT]) if (ForceEmitWaitcnt[LGKM_CNT])
Wait.LgkmCnt = 0; Wait.LgkmCnt = 0;
if (ForceEmitWaitcnt[VS_CNT])
Wait.VsCnt = 0;
if (FlushVmCnt) { if (FlushVmCnt) {
if (ScoreBrackets.hasPendingEvent(VM_CNT)) if (ScoreBrackets.hasPendingEvent(VM_CNT))
Wait.VmCnt = 0; Wait.VmCnt = 0;
} }
return generateWaitcnt(Wait, MI.getIterator(), *MI.getParent(), ScoreBrackets, return generateWaitcnt(Wait, MI.getIterator(), *MI.getParent(), ScoreBrackets,
OldWaitcntInstr); OldWaitcntInstr);
▲ Show 20 Lines • Show All 206 Lines • ▼ Show 20 Lines if (ST->vmemWriteNeedsExpWaitcnt() &&
(Inst.mayStore() || SIInstrInfo::isAtomicRet(Inst))) { (Inst.mayStore() || SIInstrInfo::isAtomicRet(Inst))) {
ScoreBrackets->updateByEvent(TII, TRI, MRI, VMW_GPR_LOCK, Inst); ScoreBrackets->updateByEvent(TII, TRI, MRI, VMW_GPR_LOCK, Inst);
} }
} else if (TII->isSMRD(Inst)) { } else if (TII->isSMRD(Inst)) {
ScoreBrackets->updateByEvent(TII, TRI, MRI, SMEM_ACCESS, Inst); ScoreBrackets->updateByEvent(TII, TRI, MRI, SMEM_ACCESS, Inst);
} else if (Inst.isCall()) { } else if (Inst.isCall()) {
if (callWaitsOnFunctionReturn(Inst)) { if (callWaitsOnFunctionReturn(Inst)) {
// Act as a wait on everything // Act as a wait on everything
ScoreBrackets->applyWaitcnt(allZeroWaitcnt()); ScoreBrackets->applyWaitcnt(AMDGPU::Waitcnt::allZeroExceptVsCnt());
} else { } else {
// May need to way wait for anything. // May need to way wait for anything.
ScoreBrackets->applyWaitcnt(AMDGPU::Waitcnt()); ScoreBrackets->applyWaitcnt(AMDGPU::Waitcnt());
} }
} else if (SIInstrInfo::isLDSDIR(Inst)) { } else if (SIInstrInfo::isLDSDIR(Inst)) {
ScoreBrackets->updateByEvent(TII, TRI, MRI, EXP_LDS_ACCESS, Inst); ScoreBrackets->updateByEvent(TII, TRI, MRI, EXP_LDS_ACCESS, Inst);
} else if (TII->isVINTERP(Inst)) { } else if (TII->isVINTERP(Inst)) {
int64_t Imm = TII->getNamedOperand(Inst, AMDGPU::OpName::waitexp)->getImm(); int64_t Imm = TII->getNamedOperand(Inst, AMDGPU::OpName::waitexp)->getImm();
▲ Show 20 Lines • Show All 365 Lines • ▼ Show 20 Lines if (!MFI->isEntryFunction()) {
// TODO: Could insert earlier and schedule more liberally with operations // TODO: Could insert earlier and schedule more liberally with operations
// that only use caller preserved registers. // that only use caller preserved registers.
MachineBasicBlock &EntryBB = MF.front(); MachineBasicBlock &EntryBB = MF.front();
MachineBasicBlock::iterator I = EntryBB.begin(); MachineBasicBlock::iterator I = EntryBB.begin();
for (MachineBasicBlock::iterator E = EntryBB.end(); for (MachineBasicBlock::iterator E = EntryBB.end();
I != E && (I->isPHI() || I->isMetaInstruction()); ++I) I != E && (I->isPHI() || I->isMetaInstruction()); ++I)
; ;
BuildMI(EntryBB, I, DebugLoc(), TII->get(AMDGPU::S_WAITCNT)).addImm(0); BuildMI(EntryBB, I, DebugLoc(), TII->get(AMDGPU::S_WAITCNT)).addImm(0);
if (ST->hasVscnt())
BuildMI(EntryBB, I, DebugLoc(), TII->get(AMDGPU::S_WAITCNT_VSCNT))
.addReg(AMDGPU::SGPR_NULL, RegState::Undef)
.addImm(0);
Modified = true; Modified = true;
} }
// Keep iterating over the blocks in reverse post order, inserting and // Keep iterating over the blocks in reverse post order, inserting and
// updating s_waitcnt where needed, until a fix point is reached. // updating s_waitcnt where needed, until a fix point is reached.
for (auto *MBB : ReversePostOrderTraversal<MachineFunction *>(&MF)) for (auto *MBB : ReversePostOrderTraversal<MachineFunction *>(&MF))
BlockInfos.insert({MBB, BlockInfo()}); BlockInfos.insert({MBB, BlockInfo()});
▲ Show 20 Lines • Show All 111 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-asserts.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/br-constant-invalid-sgpr-copy.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 0x10203 ; GFX9-NEXT: s_mov_b32 s4, 0x10203
; GFX9-NEXT: v_perm_b32 v0, 0, v0, s4 ; GFX9-NEXT: v_perm_b32 v0, 0, v0, s4
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_bswap_i32: ; GFX10-LABEL: v_bswap_i32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
arsenmUnsubmitted
Not Done
ReplyInline Actions

These were super annoying

arsenm: These were super annoying
; GFX10-NEXT: v_perm_b32 v0, 0, v0, 0x10203 ; GFX10-NEXT: v_perm_b32 v0, 0, v0, 0x10203
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%bswap = call i32 @llvm.bswap.i32(i32 %src) %bswap = call i32 @llvm.bswap.i32(i32 %src)
ret i32 %bswap ret i32 %bswap
} }
define amdgpu_ps <2 x i32> @s_bswap_v2i32(<2 x i32> inreg %src) { define amdgpu_ps <2 x i32> @s_bswap_v2i32(<2 x i32> inreg %src) {
; GFX7-LABEL: s_bswap_v2i32: ; GFX7-LABEL: s_bswap_v2i32:
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines
; GFX9-NEXT: s_mov_b32 s4, 0x10203 ; GFX9-NEXT: s_mov_b32 s4, 0x10203
; GFX9-NEXT: v_perm_b32 v0, 0, v0, s4 ; GFX9-NEXT: v_perm_b32 v0, 0, v0, s4
; GFX9-NEXT: v_perm_b32 v1, 0, v1, s4 ; GFX9-NEXT: v_perm_b32 v1, 0, v1, s4
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_bswap_v2i32: ; GFX10-LABEL: v_bswap_v2i32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_perm_b32 v0, 0, v0, 0x10203 ; GFX10-NEXT: v_perm_b32 v0, 0, v0, 0x10203
; GFX10-NEXT: v_perm_b32 v1, 0, v1, 0x10203 ; GFX10-NEXT: v_perm_b32 v1, 0, v1, 0x10203
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%bswap = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %src) %bswap = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %src)
ret <2 x i32> %bswap ret <2 x i32> %bswap
} }
define amdgpu_ps i64 @s_bswap_i64(i64 inreg %src) { define amdgpu_ps i64 @s_bswap_i64(i64 inreg %src) {
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_perm_b32 v2, 0, v1, s4 ; GFX9-NEXT: v_perm_b32 v2, 0, v1, s4
; GFX9-NEXT: v_perm_b32 v1, 0, v0, s4 ; GFX9-NEXT: v_perm_b32 v1, 0, v0, s4
; GFX9-NEXT: v_mov_b32_e32 v0, v2 ; GFX9-NEXT: v_mov_b32_e32 v0, v2
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_bswap_i64: ; GFX10-LABEL: v_bswap_i64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_perm_b32 v2, 0, v1, 0x10203 ; GFX10-NEXT: v_perm_b32 v2, 0, v1, 0x10203
; GFX10-NEXT: v_perm_b32 v1, 0, v0, 0x10203 ; GFX10-NEXT: v_perm_b32 v1, 0, v0, 0x10203
; GFX10-NEXT: v_mov_b32_e32 v0, v2 ; GFX10-NEXT: v_mov_b32_e32 v0, v2
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%bswap = call i64 @llvm.bswap.i64(i64 %src) %bswap = call i64 @llvm.bswap.i64(i64 %src)
ret i64 %bswap ret i64 %bswap
} }
▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_perm_b32 v3, 0, v2, s4 ; GFX9-NEXT: v_perm_b32 v3, 0, v2, s4
; GFX9-NEXT: v_mov_b32_e32 v0, v4 ; GFX9-NEXT: v_mov_b32_e32 v0, v4
; GFX9-NEXT: v_mov_b32_e32 v2, v5 ; GFX9-NEXT: v_mov_b32_e32 v2, v5
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_bswap_v2i64: ; GFX10-LABEL: v_bswap_v2i64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_perm_b32 v4, 0, v1, 0x10203 ; GFX10-NEXT: v_perm_b32 v4, 0, v1, 0x10203
; GFX10-NEXT: v_perm_b32 v5, 0, v3, 0x10203 ; GFX10-NEXT: v_perm_b32 v5, 0, v3, 0x10203
; GFX10-NEXT: v_perm_b32 v1, 0, v0, 0x10203 ; GFX10-NEXT: v_perm_b32 v1, 0, v0, 0x10203
; GFX10-NEXT: v_perm_b32 v3, 0, v2, 0x10203 ; GFX10-NEXT: v_perm_b32 v3, 0, v2, 0x10203
; GFX10-NEXT: v_mov_b32_e32 v0, v4 ; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: v_mov_b32_e32 v2, v5 ; GFX10-NEXT: v_mov_b32_e32 v2, v5
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%bswap = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %src) %bswap = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %src)
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0001 ; GFX9-NEXT: s_mov_b32 s4, 0xc0c0001
; GFX9-NEXT: v_perm_b32 v0, 0, v0, s4 ; GFX9-NEXT: v_perm_b32 v0, 0, v0, s4
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_bswap_i16: ; GFX10-LABEL: v_bswap_i16:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001 ; GFX10-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%bswap = call i16 @llvm.bswap.i16(i16 %src) %bswap = call i16 @llvm.bswap.i16(i16 %src)
ret i16 %bswap ret i16 %bswap
} }
define amdgpu_ps i32 @s_bswap_v2i16(<2 x i16> inreg %src) { define amdgpu_ps i32 @s_bswap_v2i16(<2 x i16> inreg %src) {
; GFX7-LABEL: s_bswap_v2i16: ; GFX7-LABEL: s_bswap_v2i16:
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0001 ; GFX9-NEXT: s_mov_b32 s4, 0xc0c0001
; GFX9-NEXT: v_perm_b32 v0, 0, v0, s4 ; GFX9-NEXT: v_perm_b32 v0, 0, v0, s4
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_bswap_i16_zext_to_i32: ; GFX10-LABEL: v_bswap_i16_zext_to_i32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001 ; GFX10-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%bswap = call i16 @llvm.bswap.i16(i16 %src) %bswap = call i16 @llvm.bswap.i16(i16 %src)
%zext = zext i16 %bswap to i32 %zext = zext i16 %bswap to i32
ret i32 %zext ret i32 %zext
} }
define i32 @v_bswap_i16_sext_to_i32(i16 %src) { define i32 @v_bswap_i16_sext_to_i32(i16 %src) {
Show All 20 Lines
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0001 ; GFX9-NEXT: s_mov_b32 s4, 0xc0c0001
; GFX9-NEXT: v_perm_b32 v0, 0, v0, s4 ; GFX9-NEXT: v_perm_b32 v0, 0, v0, s4
; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 16 ; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_bswap_i16_sext_to_i32: ; GFX10-LABEL: v_bswap_i16_sext_to_i32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001 ; GFX10-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001
; GFX10-NEXT: v_bfe_i32 v0, v0, 0, 16 ; GFX10-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%bswap = call i16 @llvm.bswap.i16(i16 %src) %bswap = call i16 @llvm.bswap.i16(i16 %src)
%zext = sext i16 %bswap to i32 %zext = sext i16 %bswap to i32
ret i32 %zext ret i32 %zext
} }
Show All 21 Lines
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 0x2030001 ; GFX9-NEXT: s_mov_b32 s4, 0x2030001
; GFX9-NEXT: v_perm_b32 v0, 0, v0, s4 ; GFX9-NEXT: v_perm_b32 v0, 0, v0, s4
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_bswap_v2i16: ; GFX10-LABEL: v_bswap_v2i16:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_perm_b32 v0, 0, v0, 0x2030001 ; GFX10-NEXT: v_perm_b32 v0, 0, v0, 0x2030001
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%bswap = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> %src) %bswap = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> %src)
ret <2 x i16> %bswap ret <2 x i16> %bswap
} }
define <3 x i16> @v_bswap_v3i16(<3 x i16> %src) { define <3 x i16> @v_bswap_v3i16(<3 x i16> %src) {
; GFX7-LABEL: v_bswap_v3i16: ; GFX7-LABEL: v_bswap_v3i16:
Show All 26 Lines
; GFX9-NEXT: s_mov_b32 s4, 0x2030001 ; GFX9-NEXT: s_mov_b32 s4, 0x2030001
; GFX9-NEXT: v_perm_b32 v0, 0, v0, s4 ; GFX9-NEXT: v_perm_b32 v0, 0, v0, s4
; GFX9-NEXT: v_perm_b32 v1, 0, v1, s4 ; GFX9-NEXT: v_perm_b32 v1, 0, v1, s4
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_bswap_v3i16: ; GFX10-LABEL: v_bswap_v3i16:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_perm_b32 v0, 0, v0, 0x2030001 ; GFX10-NEXT: v_perm_b32 v0, 0, v0, 0x2030001
; GFX10-NEXT: v_perm_b32 v1, 0, v1, 0x2030001 ; GFX10-NEXT: v_perm_b32 v1, 0, v1, 0x2030001
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%bswap = call <3 x i16> @llvm.bswap.v3i16(<3 x i16> %src) %bswap = call <3 x i16> @llvm.bswap.v3i16(<3 x i16> %src)
ret <3 x i16> %bswap ret <3 x i16> %bswap
} }
define i64 @v_bswap_i48(i64 %src) { define i64 @v_bswap_i48(i64 %src) {
Show All 26 Lines
; GFX9-NEXT: v_perm_b32 v1, 0, v1, s4 ; GFX9-NEXT: v_perm_b32 v1, 0, v1, s4
; GFX9-NEXT: v_perm_b32 v2, 0, v0, s4 ; GFX9-NEXT: v_perm_b32 v2, 0, v0, s4
; GFX9-NEXT: v_lshrrev_b64 v[0:1], 16, v[1:2] ; GFX9-NEXT: v_lshrrev_b64 v[0:1], 16, v[1:2]
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_bswap_i48: ; GFX10-LABEL: v_bswap_i48:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_perm_b32 v1, 0, v1, 0x10203 ; GFX10-NEXT: v_perm_b32 v1, 0, v1, 0x10203
; GFX10-NEXT: v_perm_b32 v2, 0, v0, 0x10203 ; GFX10-NEXT: v_perm_b32 v2, 0, v0, 0x10203
; GFX10-NEXT: v_lshrrev_b64 v[0:1], 16, v[1:2] ; GFX10-NEXT: v_lshrrev_b64 v[0:1], 16, v[1:2]
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%trunc = trunc i64 %src to i48 %trunc = trunc i64 %src to i48
%bswap = call i48 @llvm.bswap.i48(i48 %trunc) %bswap = call i48 @llvm.bswap.i48(i48 %trunc)
%zext = zext i48 %bswap to i64 %zext = zext i48 %bswap to i64
ret i64 %zext ret i64 %zext
Show All 13 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/bug-legalization-artifact-combiner-dead-def.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/image-waterfall-loop-O0.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.fadd.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.fmin.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fdot2.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.setreg.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot2.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot8.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sudot4.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sudot8.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot2.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot8.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.96.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/mul.v2i16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/sbfx.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/shlN_add.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/ubfx.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/umed3.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/v_bfe_i32.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll

llvm/test/CodeGen/AMDGPU/amd.endpgm.ll

llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll

llvm/test/CodeGen/AMDGPU/back-off-barrier-subtarget-feature.ll

llvm/test/CodeGen/AMDGPU/bf16.ll

llvm/test/CodeGen/AMDGPU/bfi_int.ll

llvm/test/CodeGen/AMDGPU/bitreverse.ll

llvm/test/CodeGen/AMDGPU/bswap.ll

llvm/test/CodeGen/AMDGPU/bug-sdag-emitcopyfromreg.ll

llvm/test/CodeGen/AMDGPU/call-argument-types.ll

llvm/test/CodeGen/AMDGPU/calling-conventions.ll

llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll

llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll

llvm/test/CodeGen/AMDGPU/clamp-modifier.ll

llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll

llvm/test/CodeGen/AMDGPU/cse-convergent.ll

llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll

llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll

llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll

llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll

llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll

llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll

llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll

llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll

llvm/test/CodeGen/AMDGPU/fcanonicalize.ll

llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll

llvm/test/CodeGen/AMDGPU/fcopysign.f32.ll

llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll

llvm/test/CodeGen/AMDGPU/flat-scratch.ll

llvm/test/CodeGen/AMDGPU/fma.f16.ll

llvm/test/CodeGen/AMDGPU/fmad-formation-fmul-distribute-denormal-mode.ll

llvm/test/CodeGen/AMDGPU/fmax3.ll

llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll

llvm/test/CodeGen/AMDGPU/fmin3.ll

llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll

llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll

llvm/test/CodeGen/AMDGPU/fneg-fold-legalize-dag-increase-insts.ll

llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll

llvm/test/CodeGen/AMDGPU/fneg.ll

llvm/test/CodeGen/AMDGPU/fold-fabs.ll

llvm/test/CodeGen/AMDGPU/fp-min-max-flat-atomics.ll

llvm/test/CodeGen/AMDGPU/fpext-free.ll

llvm/test/CodeGen/AMDGPU/fpow.ll

llvm/test/CodeGen/AMDGPU/fract-match.ll

llvm/test/CodeGen/AMDGPU/fshr.ll

llvm/test/CodeGen/AMDGPU/function-args.ll

llvm/test/CodeGen/AMDGPU/function-returns.ll

llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll

llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll

llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll

llvm/test/CodeGen/AMDGPU/imm16.ll

llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll

llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll

llvm/test/CodeGen/AMDGPU/known-never-nan.ll

llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sudot4.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sudot8.ll

llvm/test/CodeGen/AMDGPU/llvm.frexp.ll

llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll

llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll

llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll

llvm/test/CodeGen/AMDGPU/llvm.log.ll

llvm/test/CodeGen/AMDGPU/llvm.log10.ll

llvm/test/CodeGen/AMDGPU/llvm.log2.ll

llvm/test/CodeGen/AMDGPU/llvm.mulo.ll

llvm/test/CodeGen/AMDGPU/llvm.powi.ll

llvm/test/CodeGen/AMDGPU/lo16-hi16-physreg-copy.mir

llvm/test/CodeGen/AMDGPU/load-local.128.ll

llvm/test/CodeGen/AMDGPU/load-local.96.ll

llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll

llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll

llvm/test/CodeGen/AMDGPU/mad-mix.ll

llvm/test/CodeGen/AMDGPU/mad.u16.ll

llvm/test/CodeGen/AMDGPU/mad_64_32.ll

llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll

llvm/test/CodeGen/AMDGPU/memory_clause.ll

llvm/test/CodeGen/AMDGPU/minmax.ll

llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll

llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll

llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll

llvm/test/CodeGen/AMDGPU/offset-split-flat.ll

llvm/test/CodeGen/AMDGPU/offset-split-global.ll

llvm/test/CodeGen/AMDGPU/permute_i8.ll

llvm/test/CodeGen/AMDGPU/preserve-hi16.ll

llvm/test/CodeGen/AMDGPU/ptrmask.ll

llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll

llvm/test/CodeGen/AMDGPU/roundeven.ll

llvm/test/CodeGen/AMDGPU/saddsat.ll

llvm/test/CodeGen/AMDGPU/select-constant-xor.ll

llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.f16.ll

llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll

llvm/test/CodeGen/AMDGPU/setcc-multiple-use.ll

llvm/test/CodeGen/AMDGPU/skip-if-dead.ll

llvm/test/CodeGen/AMDGPU/ssubsat.ll

llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll

llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll

llvm/test/CodeGen/AMDGPU/strict_fadd.f32.ll

llvm/test/CodeGen/AMDGPU/strict_fadd.f64.ll

llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll

llvm/test/CodeGen/AMDGPU/strict_fma.f32.ll

llvm/test/CodeGen/AMDGPU/strict_fma.f64.ll

llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll

llvm/test/CodeGen/AMDGPU/strict_fmul.f32.ll

llvm/test/CodeGen/AMDGPU/strict_fmul.f64.ll

llvm/test/CodeGen/AMDGPU/strict_fpext.ll

llvm/test/CodeGen/AMDGPU/strict_fptrunc.ll

llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll

llvm/test/CodeGen/AMDGPU/strict_fsub.f32.ll

llvm/test/CodeGen/AMDGPU/strict_fsub.f64.ll

llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll

llvm/test/CodeGen/AMDGPU/strict_ldexp.f32.ll

llvm/test/CodeGen/AMDGPU/strict_ldexp.f64.ll

llvm/test/CodeGen/AMDGPU/uaddsat.ll

llvm/test/CodeGen/AMDGPU/udiv.ll

llvm/test/CodeGen/AMDGPU/usubsat.ll

llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll

llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll

llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll

llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll

llvm/test/CodeGen/AMDGPU/waitcnt-bvh.mir

llvm/test/CodeGen/AMDGPU/waitcnt-overflow.mir

llvm/test/CodeGen/AMDGPU/waitcnt-preexisting-vscnt.mir

llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll

llvm/test/CodeGen/AMDGPU/wave32.ll

llvm/test/CodeGen/AMDGPU/wqm.ll