AMDGPU: Partially fix not respecting dynamic denormal mode

[arsenm]

Summary

The most notable issue was producing v_mad_f32 in functions with the
dynamic mode, since it just ignores the mode. fdiv lowering is still
somewhat broken because it involves a mode switch and we need to query
the original mode.

[arsenm]

ping

[rampitec]

Can you please explain why does it need reversal of the HasFP32Denormals? This creates a lot turmoil.

[arsenm]

In D153084#4474883, @rampitec wrote:

Can you please explain why does it need reversal of the HasFP32Denormals? This creates a lot turmoil.

It's conceptually backwards. The default logic has to be treat like IEEE. It needs to be the positive condition that we definitely have flushing on

[rampitec]

In D153084#4475195, @arsenm wrote:

In D153084#4474883, @rampitec wrote:

Can you please explain why does it need reversal of the HasFP32Denormals? This creates a lot turmoil.

It's conceptually backwards. The default logic has to be treat like IEEE. It needs to be the positive condition that we definitely have flushing on

It should be possible to logically separate it into 2 patches then: one reversing the flag but not changing the behavior, and then the fix itself?

[arsenm]

In D153084#4475241, @rampitec wrote:

It should be possible to logically separate it into 2 patches then: one reversing the flag but not changing the behavior, and then the fix itself?

Yes, but it's kind of the same thing. I'd have to go spend the time to re-invert all the logic here and doesn't seem worth the effort

[rampitec]

In D153084#4475290, @arsenm wrote:

In D153084#4475241, @rampitec wrote:

It should be possible to logically separate it into 2 patches then: one reversing the flag but not changing the behavior, and then the fix itself?

Yes, but it's kind of the same thing. I'd have to go spend the time to re-invert all the logic here and doesn't seem worth the effort

Most of the patch is the logic inversion, I believe I have scanned it 3 times already. Could you please highlight the actual fix, or why does the inversion itself fixes it?

[arsenm]

In D153084#4475463, @rampitec wrote:

In D153084#4475290, @arsenm wrote:

In D153084#4475241, @rampitec wrote:

It should be possible to logically separate it into 2 patches then: one reversing the flag but not changing the behavior, and then the fix itself?

Yes, but it's kind of the same thing. I'd have to go spend the time to re-invert all the logic here and doesn't seem worth the effort

Most of the patch is the logic inversion, I believe I have scanned it 3 times already. Could you please highlight the actual fix, or why does the inversion itself fixes it?

Because there's a 3rd option now, dynamic. It could be either mode. !IEEE doesn't imply denormals can be flushed, it has to be ==PreserveSign. This fixes illegally forming v_mad_f32 (see v_mac_f32_dynamic_ftz, this would be wrong if the function was called from an IEEE context if it used v_mad_f32)

[rampitec]

In D153084#4480984, @arsenm wrote:

In D153084#4475463, @rampitec wrote:

In D153084#4475290, @arsenm wrote:

In D153084#4475241, @rampitec wrote:

It should be possible to logically separate it into 2 patches then: one reversing the flag but not changing the behavior, and then the fix itself?

Yes, but it's kind of the same thing. I'd have to go spend the time to re-invert all the logic here and doesn't seem worth the effort

Most of the patch is the logic inversion, I believe I have scanned it 3 times already. Could you please highlight the actual fix, or why does the inversion itself fixes it?

Because there's a 3rd option now, dynamic. It could be either mode. !IEEE doesn't imply denormals can be flushed, it has to be ==PreserveSign. This fixes illegally forming v_mad_f32 (see v_mac_f32_dynamic_ftz, this would be wrong if the function was called from an IEEE context if it used v_mad_f32)

OK, thanks.

[arsenm]

fbe4ff8149a2b656a66cc0c64a38a5302c051c6e

llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp

public:
   const GCNSubtarget *ST = nullptr;
   const TargetLibraryInfo *TLInfo = nullptr;
   AssumptionCache *AC = nullptr;
   DominatorTree *DT = nullptr;
   UniformityInfo *UA = nullptr;
   Module *Mod = nullptr;
   const DataLayout *DL = nullptr;
   bool HasUnsafeFPMath = false;
-  bool HasFP32Denormals = false;
+  bool HasFP32DenormalFlush = false;
   bool FlowChanged = false;
 
   DenseMap<const PHINode *, bool> BreakPhiNodesCache;
 
   bool canBreakPHINode(const PHINode &I);
 
   /// Copies exact/nsw/nuw flags (if any) from binary operation \p I to
   /// binary operation \p V.

 // optimize with fdiv.fast:
 //
 // a/b -> fdiv.fast(a, b) when !fpmath >= 2.5ulp with denormals flushed.
 //
 // 1/x -> fdiv.fast(1,x)  when !fpmath >= 2.5ulp.
 //
 // NOTE: optimizeWithRcp should be tried first because rcp is the preference.
 static Value *optimizeWithFDivFast(Value *Num, Value *Den, float ReqdAccuracy,
-                                   bool HasDenormals, IRBuilder<> &Builder,
-                                   Module *Mod) {
+                                   bool HasFP32DenormalFlush,
+                                   IRBuilder<> &Builder, Module *Mod) {
   // fdiv.fast can achieve 2.5 ULP accuracy.
   if (ReqdAccuracy < 2.5f)
     return nullptr;
 
   // Only have fdiv.fast for f32.
   Type *Ty = Den->getType();
   if (!Ty->isFloatTy())
     return nullptr;
 
   bool NumIsOne = false;
   if (const ConstantFP *CNum = dyn_cast<ConstantFP>(Num)) {
     if (CNum->isExactlyValue(+1.0) || CNum->isExactlyValue(-1.0))
       NumIsOne = true;
   }
 
   // fdiv does not support denormals. But 1.0/x is always fine to use it.
-  if (HasDenormals && !NumIsOne)
+  if (!HasFP32DenormalFlush && !NumIsOne)
     return nullptr;
 
   Function *Decl = Intrinsic::getDeclaration(Mod, Intrinsic::amdgcn_fdiv_fast);
   return Builder.CreateCall(Decl, { Num, Den });
 }
 
 // Optimizations is performed based on fpmath, fast math flags as well as
 // denormals to optimize fdiv with either rcp or fdiv.fast.
bool AMDGPUCodeGenPrepareImpl::visitFDiv(BinaryOperator &FDiv) {
 
   // Inaccurate rcp is allowed with unsafe-fp-math or afn.
   FastMathFlags FMF = FPOp->getFastMathFlags();
   const bool AllowInaccurateRcp = HasUnsafeFPMath || FMF.approxFunc();
 
   // rcp_f16 is accurate for !fpmath >= 1.0ulp.
   // rcp_f32 is accurate for !fpmath >= 1.0ulp and denormals are flushed.
   // rcp_f64 is never accurate.
-  const bool RcpIsAccurate = (Ty->isHalfTy() && ReqdAccuracy >= 1.0f) ||
-            (Ty->isFloatTy() && !HasFP32Denormals && ReqdAccuracy >= 1.0f);
+  const bool RcpIsAccurate =
+      (Ty->isHalfTy() && ReqdAccuracy >= 1.0f) ||
+      (Ty->isFloatTy() && HasFP32DenormalFlush && ReqdAccuracy >= 1.0f);
 
   IRBuilder<> Builder(FDiv.getParent(), std::next(FDiv.getIterator()));
   Builder.setFastMathFlags(FMF);
   Builder.SetCurrentDebugLocation(FDiv.getDebugLoc());
 
   Value *Num = FDiv.getOperand(0);
   Value *Den = FDiv.getOperand(1);
 
   Value *NewFDiv = nullptr;
   if (auto *VT = dyn_cast<FixedVectorType>(FDiv.getType())) {
     NewFDiv = PoisonValue::get(VT);
 
     // FIXME: Doesn't do the right thing for cases where the vector is partially
     // constant. This works when the scalarizer pass is run first.
     for (unsigned I = 0, E = VT->getNumElements(); I != E; ++I) {
       Value *NumEltI = Builder.CreateExtractElement(Num, I);
       Value *DenEltI = Builder.CreateExtractElement(Den, I);
       // Try rcp first.
       Value *NewElt = optimizeWithRcp(NumEltI, DenEltI, AllowInaccurateRcp,
                                       RcpIsAccurate, Builder, Mod);
       if (!NewElt) // Try fdiv.fast.
          NewElt = optimizeWithFDivFast(NumEltI, DenEltI, ReqdAccuracy,
-                                      HasFP32Denormals, Builder, Mod);
+                                       HasFP32DenormalFlush, Builder, Mod);
       if (!NewElt) // Keep the original.
         NewElt = Builder.CreateFDiv(NumEltI, DenEltI);
 
       NewFDiv = Builder.CreateInsertElement(NewFDiv, NewElt, I);
     }
   } else { // Scalar FDiv.
     // Try rcp first.
     NewFDiv = optimizeWithRcp(Num, Den, AllowInaccurateRcp, RcpIsAccurate,
                               Builder, Mod);
     if (!NewFDiv) { // Try fdiv.fast.
-      NewFDiv = optimizeWithFDivFast(Num, Den, ReqdAccuracy, HasFP32Denormals,
-                                     Builder, Mod);
+      NewFDiv = optimizeWithFDivFast(Num, Den, ReqdAccuracy,
+                                     HasFP32DenormalFlush, Builder, Mod);
     }
   }
 
   if (NewFDiv) {
     FDiv.replaceAllUsesWith(NewFDiv);
     NewFDiv->takeName(&FDiv);
     FDiv.eraseFromParent();
   }
bool AMDGPUCodeGenPrepare::runOnFunction(Function &F) {
   Impl.TLInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI(F);
   Impl.ST = &TM.getSubtarget<GCNSubtarget>(F);
   Impl.AC = &getAnalysis<AssumptionCacheTracker>().getAssumptionCache(F);
   Impl.UA = &getAnalysis<UniformityInfoWrapperPass>().getUniformityInfo();
   auto *DTWP = getAnalysisIfAvailable<DominatorTreeWrapperPass>();
   Impl.DT = DTWP ? &DTWP->getDomTree() : nullptr;
   Impl.HasUnsafeFPMath = hasUnsafeFPMath(F);
   SIModeRegisterDefaults Mode(F);
-  Impl.HasFP32Denormals = Mode.allFP32Denormals();
+  Impl.HasFP32DenormalFlush =
+      Mode.FP32Denormals == DenormalMode::getPreserveSign();
   return Impl.run(F);
 }
 
 PreservedAnalyses AMDGPUCodeGenPreparePass::run(Function &F,
                                                 FunctionAnalysisManager &FAM) {
   AMDGPUCodeGenPrepareImpl Impl;
   Impl.Mod = F.getParent();
   Impl.DL = &Impl.Mod->getDataLayout();
   Impl.TLInfo = &FAM.getResult<TargetLibraryAnalysis>(F);
   Impl.ST = &TM.getSubtarget<GCNSubtarget>(F);
   Impl.AC = &FAM.getResult<AssumptionAnalysis>(F);
   Impl.UA = &FAM.getResult<UniformityInfoAnalysis>(F);
   Impl.DT = FAM.getCachedResult<DominatorTreeAnalysis>(F);
   Impl.HasUnsafeFPMath = hasUnsafeFPMath(F);
   SIModeRegisterDefaults Mode(F);
-  Impl.HasFP32Denormals = Mode.allFP32Denormals();
+  Impl.HasFP32DenormalFlush =
+      Mode.FP32Denormals == DenormalMode::getPreserveSign();
   PreservedAnalyses PA = PreservedAnalyses::none();
   if (!Impl.FlowChanged)
     PA.preserveSet<CFGAnalyses>();
   return Impl.run(F) ? PA : PreservedAnalyses::all();
 }
 
 INITIALIZE_PASS_BEGIN(AMDGPUCodeGenPrepare, DEBUG_TYPE,
                       "AMDGPU IR optimizations", false, false)

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG,
   // float fqneg = -fq;
   SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
 
   MachineFunction &MF = DAG.getMachineFunction();
 
   bool UseFmadFtz = false;
   if (Subtarget->isGCN()) {
     const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
-    UseFmadFtz = MFI->getMode().allFP32Denormals();
+    UseFmadFtz =
+        MFI->getMode().FP32Denormals != DenormalMode::getPreserveSign();
   }
 
   // float fr = mad(fqneg, fb, fa);
   unsigned OpCode = !Subtarget->hasMadMacF32Insts() ? (unsigned)ISD::FMA
                     : UseFmadFtz ? (unsigned)AMDGPUISD::FMAD_FTZ
                                  : (unsigned)ISD::FMAD;
   SDValue fr = DAG.getNode(OpCode, DL, FltVT, fqneg, fb, fa);
 
void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
   if (isTypeLegal(MVT::i64)) {
     // The algorithm here is based on ideas from "Software Integer Division",
     // Tom Rodeheffer, August 2008.
 
     MachineFunction &MF = DAG.getMachineFunction();
     const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 
     // Compute denominator reciprocal.
-    unsigned FMAD = !Subtarget->hasMadMacF32Insts() ?
-                    (unsigned)ISD::FMA :
-                    !MFI->getMode().allFP32Denormals() ?
-                    (unsigned)ISD::FMAD :
-                    (unsigned)AMDGPUISD::FMAD_FTZ;
+    unsigned FMAD =
+        !Subtarget->hasMadMacF32Insts() ? (unsigned)ISD::FMA
+        : MFI->getMode().FP32Denormals == DenormalMode::getPreserveSign()
+            ? (unsigned)ISD::FMAD
+            : (unsigned)AMDGPUISD::FMAD_FTZ;
 
     SDValue Cvt_Lo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Lo);
     SDValue Cvt_Hi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Hi);
     SDValue Mad1 = DAG.getNode(FMAD, DL, MVT::f32, Cvt_Hi,
       DAG.getConstantFP(APInt(32, 0x4f800000).bitsToFloat(), DL, MVT::f32),
       Cvt_Lo);
     SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, DL, MVT::f32, Mad1);
     SDValue Mul1 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Rcp,

llvm/lib/Target/AMDGPU/AMDGPUInstructions.td

 
 class AMDGPUPat<dag pattern, dag result> : Pat<pattern, result>,
       PredicateControl, GISelFlags;
 
 let GIIgnoreCopies = 1 in
 class AMDGPUPatIgnoreCopies<dag pattern, dag result> : AMDGPUPat<pattern, result>;
 
 let RecomputePerFunction = 1 in {
-def FP16Denormals : Predicate<"MF->getInfo<SIMachineFunctionInfo>()->getMode().allFP64FP16Denormals()">;
-def FP32Denormals : Predicate<"MF->getInfo<SIMachineFunctionInfo>()->getMode().allFP32Denormals()">;
-def FP64Denormals : Predicate<"MF->getInfo<SIMachineFunctionInfo>()->getMode().allFP64FP16Denormals()">;
-def NoFP16Denormals : Predicate<"!MF->getInfo<SIMachineFunctionInfo>()->getMode().allFP64FP16Denormals()">;
-def NoFP32Denormals : Predicate<"!MF->getInfo<SIMachineFunctionInfo>()->getMode().allFP32Denormals()">;
-def NoFP64Denormals : Predicate<"!MF->getInfo<SIMachineFunctionInfo>()->getMode().allFP64FP16Denormals()">;
+def FP16Denormals : Predicate<"MF->getInfo<SIMachineFunctionInfo>()->getMode().FP64FP16Denormals != DenormalMode::getPreserveSign()">;
+def FP32Denormals : Predicate<"MF->getInfo<SIMachineFunctionInfo>()->getMode().FP32Denormals != DenormalMode::getPreserveSign()">;
+def FP64Denormals : Predicate<"MF->getInfo<SIMachineFunctionInfo>()->getMode().FP64FP16Denormals != DenormalMode::getPreserveSign()">;
+def NoFP16Denormals : Predicate<"MF->getInfo<SIMachineFunctionInfo>()->getMode().FP64FP16Denormals == DenormalMode::getPreserveSign()">;
+def NoFP32Denormals : Predicate<"MF->getInfo<SIMachineFunctionInfo>()->getMode().FP32Denormals == DenormalMode::getPreserveSign()">;
+def NoFP64Denormals : Predicate<"MF->getInfo<SIMachineFunctionInfo>()->getMode().FP64FP16Denormals == DenormalMode::getPreserveSign()">;
 def UnsafeFPMath : Predicate<"TM.Options.UnsafeFPMath">;
 }
 
 def FMA : Predicate<"Subtarget->hasFMA()">;
 
 def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
 
 class CustomOperandClass<string name, bit optional, string parserMethod,

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

bool AMDGPULegalizerInfo::legalizeFMad(
   LLT Ty = MRI.getType(MI.getOperand(0).getReg());
   assert(Ty.isScalar());
 
   MachineFunction &MF = B.getMF();
   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 
   // TODO: Always legal with future ftz flag.
   // FIXME: Do we need just output?
-  if (Ty == LLT::scalar(32) && !MFI->getMode().allFP32Denormals())
+  if (Ty == LLT::scalar(32) &&
+      MFI->getMode().FP32Denormals == DenormalMode::getPreserveSign())
     return true;
-  if (Ty == LLT::scalar(16) && !MFI->getMode().allFP64FP16Denormals())
+  if (Ty == LLT::scalar(16) &&
+      MFI->getMode().FP64FP16Denormals == DenormalMode::getPreserveSign())
     return true;
 
   MachineIRBuilder HelperBuilder(MI);
   GISelObserverWrapper DummyObserver;
   LegalizerHelper Helper(MF, DummyObserver, HelperBuilder);
   return Helper.lowerFMad(MI) == LegalizerHelper::Legalized;
 }
 
bool AMDGPULegalizerInfo::legalizeFDIV32(MachineInstr &MI,
 
   auto ApproxRcp = B.buildIntrinsic(Intrinsic::amdgcn_rcp, {S32}, false)
     .addUse(DenominatorScaled.getReg(0))
     .setMIFlags(Flags);
   auto NegDivScale0 = B.buildFNeg(S32, DenominatorScaled, Flags);
 
   // FIXME: Doesn't correctly model the FP mode switch, and the FP operations
   // aren't modeled as reading it.
-  if (!Mode.allFP32Denormals())
+  if (Mode.FP32Denormals != DenormalMode::getIEEE())
     toggleSPDenormMode(true, B, ST, Mode);
 
   auto Fma0 = B.buildFMA(S32, NegDivScale0, ApproxRcp, One, Flags);
   auto Fma1 = B.buildFMA(S32, Fma0, ApproxRcp, ApproxRcp, Flags);
   auto Mul = B.buildFMul(S32, NumeratorScaled, Fma1, Flags);
   auto Fma2 = B.buildFMA(S32, NegDivScale0, Mul, NumeratorScaled, Flags);
   auto Fma3 = B.buildFMA(S32, Fma2, Fma1, Mul, Flags);
   auto Fma4 = B.buildFMA(S32, NegDivScale0, Fma3, NumeratorScaled, Flags);
 
-  if (!Mode.allFP32Denormals())
+  // FIXME: This mishandles dynamic denormal mode. We need to query the
+  // current mode and restore the original.
+  if (Mode.FP32Denormals != DenormalMode::getIEEE())
     toggleSPDenormMode(false, B, ST, Mode);
 
   auto Fmas = B.buildIntrinsic(Intrinsic::amdgcn_div_fmas, {S32}, false)
     .addUse(Fma4.getReg(0))
     .addUse(Fma1.getReg(0))
     .addUse(Fma3.getReg(0))
     .addUse(NumeratorScaled.getReg(1))
     .setMIFlags(Flags);

llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp

const FeatureBitset GCNTTIImpl::InlineFeatureIgnoreList = {
     AMDGPU::FeatureFastFMAF32, AMDGPU::HalfRate64Ops};
 
 GCNTTIImpl::GCNTTIImpl(const AMDGPUTargetMachine *TM, const Function &F)
     : BaseT(TM, F.getParent()->getDataLayout()),
       ST(static_cast<const GCNSubtarget *>(TM->getSubtargetImpl(F))),
       TLI(ST->getTargetLowering()), CommonTTI(TM, F),
       IsGraphics(AMDGPU::isGraphics(F.getCallingConv())) {
   SIModeRegisterDefaults Mode(F);
-  HasFP32Denormals = Mode.allFP32Denormals();
-  HasFP64FP16Denormals = Mode.allFP64FP16Denormals();
+  HasFP32Denormals = Mode.FP32Denormals != DenormalMode::getPreserveSign();
+  HasFP64FP16Denormals =
+      Mode.FP64FP16Denormals != DenormalMode::getPreserveSign();
 }
 
 unsigned GCNTTIImpl::getNumberOfRegisters(unsigned RCID) const {
   // NB: RCID is not an RCID. In fact it is 0 or 1 for scalar or vector
   // registers. See getRegisterClassForType for the implementation.
   // In this case vector registers are not vector in terms of
   // VGPRs, but those which can hold multiple values.
 

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

static cl::opt<bool> DisableLoopAlignment(
   cl::init(false));
 
 static cl::opt<bool> UseDivergentRegisterIndexing(
   "amdgpu-use-divergent-register-indexing",
   cl::Hidden,
   cl::desc("Use indirect register addressing for divergent indexes"),
   cl::init(false));
 
-static bool hasFP32Denormals(const MachineFunction &MF) {
+static bool denormalModeIsFlushAllF32(const MachineFunction &MF) {
   const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
-  return Info->getMode().allFP32Denormals();
+  return Info->getMode().FP32Denormals == DenormalMode::getPreserveSign();
 }
 
-static bool hasFP64FP16Denormals(const MachineFunction &MF) {
+static bool denormalModeIsFlushAllF64F16(const MachineFunction &MF) {
   const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
-  return Info->getMode().allFP64FP16Denormals();
+  return Info->getMode().FP64FP16Denormals == DenormalMode::getPreserveSign();
 }
 
 static unsigned findFirstFreeSGPR(CCState &CCInfo) {
   unsigned NumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
   for (unsigned Reg = 0; Reg < NumSGPRs; ++Reg) {
     if (!CCInfo.isAllocated(AMDGPU::SGPR0 + Reg)) {
       return AMDGPU::SGPR0 + Reg;
     }

 // v_mad_mix* support a conversion from f16 to f32.
 //
 // There is only one special case when denormals are enabled we don't currently,
 // where this is OK to use.
 bool SITargetLowering::isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode,
                                        EVT DestVT, EVT SrcVT) const {
   return ((Opcode == ISD::FMAD && Subtarget->hasMadMixInsts()) ||
           (Opcode == ISD::FMA && Subtarget->hasFmaMixInsts())) &&
          DestVT.getScalarType() == MVT::f32 &&
          SrcVT.getScalarType() == MVT::f16 &&
          // TODO: This probably only requires no input flushing?
-    !hasFP32Denormals(DAG.getMachineFunction());
+         denormalModeIsFlushAllF32(DAG.getMachineFunction());
 }
 
 bool SITargetLowering::isFPExtFoldable(const MachineInstr &MI, unsigned Opcode,
                                        LLT DestTy, LLT SrcTy) const {
   return ((Opcode == TargetOpcode::G_FMAD && Subtarget->hasMadMixInsts()) ||
           (Opcode == TargetOpcode::G_FMA && Subtarget->hasFmaMixInsts())) &&
          DestTy.getScalarSizeInBits() == 32 &&
          SrcTy.getScalarSizeInBits() == 16 &&
          // TODO: This probably only requires no input flushing?
-         !hasFP32Denormals(*MI.getMF());
+         denormalModeIsFlushAllF32(*MI.getMF());
 }
 
 bool SITargetLowering::isShuffleMaskLegal(ArrayRef<int>, EVT) const {
   // SI has some legal vector types, but no legal vector operations. Say no
   // shuffles are legal in order to prefer scalarizing some vector operations.
   return false;
 }
 
bool SITargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
   case MVT::f32: {
     // If mad is not available this depends only on if f32 fma is full rate.
     if (!Subtarget->hasMadMacF32Insts())
       return Subtarget->hasFastFMAF32();
 
     // Otherwise f32 mad is always full rate and returns the same result as
     // the separate operations so should be preferred over fma.
     // However does not support denormals.
-    if (hasFP32Denormals(MF))
+    if (!denormalModeIsFlushAllF32(MF))
       return Subtarget->hasFastFMAF32() || Subtarget->hasDLInsts();
 
     // If the subtarget has v_fmac_f32, that's just as good as v_mac_f32.
     return Subtarget->hasFastFMAF32() && Subtarget->hasDLInsts();
   }
   case MVT::f64:
     return true;
   case MVT::f16:
-    return Subtarget->has16BitInsts() && hasFP64FP16Denormals(MF);
+    return Subtarget->has16BitInsts() && !denormalModeIsFlushAllF64F16(MF);
   default:
     break;
   }
 
   return false;
 }
 
 bool SITargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
bool SITargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
   return false;
 }
 
 bool SITargetLowering::isFMADLegal(const MachineInstr &MI, LLT Ty) const {
   if (!Ty.isScalar())
     return false;
 
   if (Ty.getScalarSizeInBits() == 16)
-    return Subtarget->hasMadF16() && !hasFP64FP16Denormals(*MI.getMF());
+    return Subtarget->hasMadF16() && denormalModeIsFlushAllF64F16(*MI.getMF());
   if (Ty.getScalarSizeInBits() == 32)
-    return Subtarget->hasMadMacF32Insts() && !hasFP32Denormals(*MI.getMF());
+    return Subtarget->hasMadMacF32Insts() &&
+           denormalModeIsFlushAllF32(*MI.getMF());
 
   return false;
 }
 
 bool SITargetLowering::isFMADLegal(const SelectionDAG &DAG,
                                    const SDNode *N) const {
   // TODO: Check future ftz flag
   // v_mad_f32/v_mac_f32 do not support denormals.
   EVT VT = N->getValueType(0);
   if (VT == MVT::f32)
     return Subtarget->hasMadMacF32Insts() &&
-           !hasFP32Denormals(DAG.getMachineFunction());
+           denormalModeIsFlushAllF32(DAG.getMachineFunction());
   if (VT == MVT::f16) {
     return Subtarget->hasMadF16() &&
-           !hasFP64FP16Denormals(DAG.getMachineFunction());
+           denormalModeIsFlushAllF64F16(DAG.getMachineFunction());
   }
 
   return false;
 }
 
 //===----------------------------------------------------------------------===//
 // Custom DAG Lowering Operations
 //===----------------------------------------------------------------------===//
SDValue SITargetLowering::lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const {
 
   SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0);
 
   return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul);
 }
 
 // Returns immediate value for setting the F32 denorm mode when using the
 // S_DENORM_MODE instruction.
-static SDValue getSPDenormModeValue(int SPDenormMode, SelectionDAG &DAG,
-                                    const SDLoc &SL, const GCNSubtarget *ST) {
+static SDValue getSPDenormModeValue(uint32_t SPDenormMode, SelectionDAG &DAG,
+                                    const SIMachineFunctionInfo *Info,
+                                    const GCNSubtarget *ST) {
   assert(ST->hasDenormModeInst() && "Requires S_DENORM_MODE");
-  int DPDenormModeDefault = hasFP64FP16Denormals(DAG.getMachineFunction())
-                                ? FP_DENORM_FLUSH_NONE
-                                : FP_DENORM_FLUSH_IN_FLUSH_OUT;
-
-  int Mode = SPDenormMode | (DPDenormModeDefault << 2);
-  return DAG.getTargetConstant(Mode, SL, MVT::i32);
+  uint32_t DPDenormModeDefault = Info->getMode().fpDenormModeDPValue();
+  uint32_t Mode = SPDenormMode | (DPDenormModeDefault << 2);
+  return DAG.getTargetConstant(Mode, SDLoc(), MVT::i32);
 }
 
 SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {
   if (SDValue FastLowered = lowerFastUnsafeFDIV(Op, DAG))
     return FastLowered;
 
   // The selection matcher assumes anything with a chain selecting to a
   // mayRaiseFPException machine instruction. Since we're introducing a chain
SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {
   SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f32,
                                      DenominatorScaled, Flags);
 
   const unsigned Denorm32Reg = AMDGPU::Hwreg::ID_MODE |
                                (4 << AMDGPU::Hwreg::OFFSET_SHIFT_) |
                                (1 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_);
   const SDValue BitField = DAG.getTargetConstant(Denorm32Reg, SL, MVT::i32);
 
-  const bool HasFP32Denormals = hasFP32Denormals(DAG.getMachineFunction());
+  const MachineFunction &MF = DAG.getMachineFunction();
+  const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
+  const DenormalMode DenormMode = Info->getMode().FP32Denormals;
+
+  const bool HasFP32Denormals = DenormMode == DenormalMode::getIEEE();
 
   if (!HasFP32Denormals) {
     // Note we can't use the STRICT_FMA/STRICT_FMUL for the non-strict FDIV
     // lowering. The chain dependence is insufficient, and we need glue. We do
     // not need the glue variants in a strictfp function.
 
     SDVTList BindParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
 
     SDNode *EnableDenorm;
     if (Subtarget->hasDenormModeInst()) {
       const SDValue EnableDenormValue =
-          getSPDenormModeValue(FP_DENORM_FLUSH_NONE, DAG, SL, Subtarget);
+          getSPDenormModeValue(FP_DENORM_FLUSH_NONE, DAG, Info, Subtarget);
 
       EnableDenorm = DAG.getNode(AMDGPUISD::DENORM_MODE, SL, BindParamVTs,
                                  DAG.getEntryNode(), EnableDenormValue).getNode();
     } else {
       const SDValue EnableDenormValue = DAG.getConstant(FP_DENORM_FLUSH_NONE,
                                                         SL, MVT::i32);
       EnableDenorm =
           DAG.getMachineNode(AMDGPU::S_SETREG_B32, SL, BindParamVTs,
SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {
 
   SDValue Fma3 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32,
                              Fma2, Fma1, Mul, Fma2, Flags);
 
   SDValue Fma4 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, Fma3,
                              NumeratorScaled, Fma3, Flags);
 
   if (!HasFP32Denormals) {
+    // FIXME: This mishandles dynamic denormal mode. We need to query the
+    // current mode and restore the original.
+
     SDNode *DisableDenorm;
     if (Subtarget->hasDenormModeInst()) {
-      const SDValue DisableDenormValue =
-          getSPDenormModeValue(FP_DENORM_FLUSH_IN_FLUSH_OUT, DAG, SL, Subtarget);
+      const SDValue DisableDenormValue = getSPDenormModeValue(
+          FP_DENORM_FLUSH_IN_FLUSH_OUT, DAG, Info, Subtarget);
 
       DisableDenorm = DAG.getNode(AMDGPUISD::DENORM_MODE, SL, MVT::Other,
                                   Fma4.getValue(1), DisableDenormValue,
                                   Fma4.getValue(2)).getNode();
     } else {
       const SDValue DisableDenormValue =
           DAG.getConstant(FP_DENORM_FLUSH_IN_FLUSH_OUT, SL, MVT::i32);
 

 
 unsigned SITargetLowering::getFusedOpcode(const SelectionDAG &DAG,
                                           const SDNode *N0,
                                           const SDNode *N1) const {
   EVT VT = N0->getValueType(0);
 
   // Only do this if we are not trying to support denormals. v_mad_f32 does not
   // support denormals ever.
-  if (((VT == MVT::f32 && !hasFP32Denormals(DAG.getMachineFunction())) ||
-       (VT == MVT::f16 && !hasFP64FP16Denormals(DAG.getMachineFunction()) &&
-        getSubtarget()->hasMadF16())) &&
-       isOperationLegal(ISD::FMAD, VT))
+  if (((VT == MVT::f32 &&
+        denormalModeIsFlushAllF32(DAG.getMachineFunction())) ||
+       (VT == MVT::f16 && Subtarget->hasMadF16() &&
+        denormalModeIsFlushAllF64F16(DAG.getMachineFunction()))) &&
     return ISD::FMAD;
 
   const TargetOptions &Options = DAG.getTarget().Options;
   if ((Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath ||
        (N0->getFlags().hasAllowContract() &&
         N1->getFlags().hasAllowContract())) &&
       isFMAFasterThanFMulAndFAdd(DAG.getMachineFunction(), VT)) {
     return ISD::FMA;
default:
     return false;
   }
 }
 
 bool SITargetLowering::denormalsEnabledForType(const SelectionDAG &DAG,
                                                EVT VT) const {
   switch (VT.getScalarType().getSimpleVT().SimpleTy) {
   case MVT::f32:
-    return hasFP32Denormals(DAG.getMachineFunction());
+    return !denormalModeIsFlushAllF32(DAG.getMachineFunction());
   case MVT::f64:
   case MVT::f16:
-    return hasFP64FP16Denormals(DAG.getMachineFunction());
+    return !denormalModeIsFlushAllF64F16(DAG.getMachineFunction());
   default:
     return false;
   }
 }
 
 bool SITargetLowering::denormalsEnabledForType(LLT Ty,
                                                MachineFunction &MF) const {
   switch (Ty.getScalarSizeInBits()) {
   case 32:
-    return hasFP32Denormals(MF);
+    return !denormalModeIsFlushAllF32(MF);
   case 64:
   case 16:
-    return hasFP64FP16Denormals(MF);
+    return !denormalModeIsFlushAllF64F16(MF);
   default:
     return false;
   }
 }
 
 bool SITargetLowering::isKnownNeverNaNForTargetNode(SDValue Op,
                                                     const SelectionDAG &DAG,
                                                     bool SNaN,

llvm/lib/Target/AMDGPU/SIModeRegisterDefaults.h

struct SIModeRegisterDefaults {
   }
 
   bool operator==(const SIModeRegisterDefaults Other) const {
     return IEEE == Other.IEEE && DX10Clamp == Other.DX10Clamp &&
            FP32Denormals == Other.FP32Denormals &&
            FP64FP16Denormals == Other.FP64FP16Denormals;
   }
 
-  bool allFP32Denormals() const {
-    return FP32Denormals == DenormalMode::getIEEE();
-  }
-
-  bool allFP64FP16Denormals() const {
-    return FP64FP16Denormals == DenormalMode::getIEEE();
-  }
-
   /// Get the encoding value for the FP_DENORM bits of the mode register for the
   /// FP32 denormal mode.
   uint32_t fpDenormModeSPValue() const {
     if (FP32Denormals == DenormalMode::getPreserveSign())
       return FP_DENORM_FLUSH_IN_FLUSH_OUT;
     if (FP32Denormals.Output == DenormalMode::PreserveSign)
       return FP_DENORM_FLUSH_OUT;
     if (FP32Denormals.Input == DenormalMode::PreserveSign)

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-unmerge-values.mir

bb.1:
     $vgpr0 = COPY %7(s32)
 ...
 
 ---
 name: test_f32_add_mul_rhs
 machineFunctionInfo:
   mode:
     fp32-input-denormals: false
+    fp32-output-denormals: false
 body: |
   bb.1:
     liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3
 
     ; GFX10-LABEL: name: test_f32_add_mul_rhs
     ; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3
     ; GFX10-NEXT: {{  $}}
     ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
bb.1:
     $vgpr0 = COPY %7(s32)
 ...
 
 ---
 name: test_f16_f32_add_ext_mul
 machineFunctionInfo:
   mode:
     fp32-input-denormals: false
+    fp32-output-denormals: false
 body: |
   bb.1:
     liveins: $sgpr0, $sgpr1, $vgpr0_vgpr1
 
     ; GFX10-LABEL: name: test_f16_f32_add_ext_mul
     ; GFX10: liveins: $sgpr0, $sgpr1, $vgpr0_vgpr1
     ; GFX10-NEXT: {{  $}}
     ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
bb.1:
     $vgpr0 = COPY %10(s32)
 ...
 
 ---
 name: test_f16_f32_add_ext_mul_rhs
 machineFunctionInfo:
   mode:
     fp32-input-denormals: false
+    fp32-output-denormals: false
 body: |
   bb.1:
     liveins: $sgpr0, $sgpr1, $vgpr0_vgpr1
 
     ; GFX10-LABEL: name: test_f16_f32_add_ext_mul_rhs
     ; GFX10: liveins: $sgpr0, $sgpr1, $vgpr0_vgpr1
     ; GFX10-NEXT: {{  $}}
     ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
bb.1:
     $vgpr0 = COPY %10(s32)
 ...
 
 ---
 name: test_f16_f32_add_fma_ext_mul
 machineFunctionInfo:
   mode:
     fp32-input-denormals: false
+    fp32-output-denormals: false
 body: |
   bb.1:
     liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4, $vgpr5
 
     ; GFX10-LABEL: name: test_f16_f32_add_fma_ext_mul
     ; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4, $vgpr5
     ; GFX10-NEXT: {{  $}}
     ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
bb.1:
     $vgpr0 = COPY %13(s32)
 ...
 
 ---
 name: test_f16_f32_add_ext_fma_mul
 machineFunctionInfo:
   mode:
     fp32-input-denormals: false
+    fp32-output-denormals: false
 body: |
   bb.1:
     liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4, $vgpr5
 
     ; GFX10-LABEL: name: test_f16_f32_add_ext_fma_mul
     ; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4, $vgpr5
     ; GFX10-NEXT: {{  $}}
     ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
bb.1:
     $vgpr0 = COPY %16(s32)
 ...
 
 ---
 name: test_f16_f32_add_fma_ext_mul_rhs
 machineFunctionInfo:
   mode:
     fp32-input-denormals: false
+    fp32-output-denormals: false
 body: |
   bb.1:
     liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
 
     ; GFX10-LABEL: name: test_f16_f32_add_fma_ext_mul_rhs
     ; GFX10: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
     ; GFX10-NEXT: {{  $}}
     ; GFX10-NEXT: %ptr:_(p1) = COPY $vgpr0_vgpr1
bb.1:
     $vgpr0 = COPY %13(s32)
 ...
 
 ---
 name: test_f16_f32_add_ext_fma_mul_rhs
 machineFunctionInfo:
   mode:
     fp32-input-denormals: false
+    fp32-output-denormals: false
 body: |
   bb.1:
     liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
 
     ; GFX10-LABEL: name: test_f16_f32_add_ext_fma_mul_rhs
     ; GFX10: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
     ; GFX10-NEXT: {{  $}}
     ; GFX10-NEXT: %ptr:_(p1) = COPY $vgpr0_vgpr1
bb.1:
     $vgpr0 = COPY %16(s32)
 ...
 
 ---
 name: test_f32_sub_mul
 machineFunctionInfo:
   mode:
     fp32-input-denormals: false
+    fp32-output-denormals: false
 body: |
   bb.1:
     liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3
 
     ; GFX10-LABEL: name: test_f32_sub_mul
     ; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3
     ; GFX10-NEXT: {{  $}}
     ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
bb.1:
     $vgpr0 = COPY %7(s32)
 ...
 
 ---
 name: test_f32_sub_mul_rhs
 machineFunctionInfo:
   mode:
     fp32-input-denormals: false
+    fp32-output-denormals: false
 body: |
   bb.1:
     liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3
 
     ; GFX10-LABEL: name: test_f32_sub_mul_rhs
     ; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3
     ; GFX10-NEXT: {{  $}}
     ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0

llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll

 ; RUN: opt -S -mtriple=amdgcn-- -amdgpu-codegenprepare %s | FileCheck %s
 ; RUN: opt -S -amdgpu-codegenprepare %s | FileCheck -check-prefix=NOOP %s
 ; Make sure this doesn't crash with no triple
 
 ; NOOP-LABEL: @noop_fdiv_fpmath(
 ; NOOP: %md.25ulp = fdiv float %a, %b, !fpmath !0
-define amdgpu_kernel void @noop_fdiv_fpmath(ptr addrspace(1) %out, float %a, float %b) #3 {
+define amdgpu_kernel void @noop_fdiv_fpmath(ptr addrspace(1) %out, float %a, float %b) {
   %md.25ulp = fdiv float %a, %b, !fpmath !0
   store volatile float %md.25ulp, ptr addrspace(1) %out
   ret void
 }
 
 ; CHECK-LABEL: @fdiv_fpmath(
 ; CHECK: %no.md = fdiv float %a, %b{{$}}
 ; CHECK: %md.half.ulp = fdiv float %a, %b
define amdgpu_kernel void @fdiv_fpmath_f32_denormals(ptr addrspace(1) %out, float %a, float %b) #2 {
   store volatile float %fast.md.25ulp, ptr addrspace(1) %out
 
   %afn.md.25ulp = fdiv afn float %a, %b, !fpmath !0
   store volatile float %afn.md.25ulp, ptr addrspace(1) %out
 
   ret void
 }
 
+; CHECK-LABEL: @rcp_fpmath_dynamic_denorm(
+; CHECK: %md.25ulp = fdiv float 1.000000e+00, %x, !fpmath !2
+define float @rcp_fpmath_dynamic_denorm(float %x) #3 {
+  %md.25ulp = fdiv float 1.0, %x, !fpmath !2
+  ret float %md.25ulp
+}
+
+; CHECK-LABEL: @rcp_dynamic_denorm(
+; CHECK: %md.25ulp = fdiv float 1.000000e+00, %x
+define float @rcp_dynamic_denorm(float %x) #3 {
+  %md.25ulp = fdiv float 1.0, %x
+  ret float %md.25ulp
+}
+
 attributes #0 = { nounwind optnone noinline }
 attributes #1 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
 attributes #2 = { nounwind "denormal-fp-math-f32"="ieee,ieee" }
+attributes #3 = { nounwind "denormal-fp-math-f32"="dynamic,dynamic" }
 
 !0 = !{float 2.500000e+00}
 !1 = !{float 5.000000e-01}
 !2 = !{float 1.000000e+00}
 !3 = !{float 3.000000e+00}

llvm/test/CodeGen/AMDGPU/fdiv.ll

 ; GCN: v_div_fixup_f32 v{{[0-9]+}}, [[FMAS]],
 define amdgpu_kernel void @fdiv_f32_denorms_correctly_rounded_divide_sqrt(ptr addrspace(1) %out, float %a) #2 {
 entry:
   %fdiv = fdiv float 1.000000e+00, %a
   store float %fdiv, ptr addrspace(1) %out
   ret void
 }
 
+; FUNC-LABEL: {{^}}v_fdiv_f32_dynamic_denorm:
+; PREGFX10: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX10: s_denorm_mode 15
+
+; PREGFX10: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX10: s_denorm_mode 12
+define float @v_fdiv_f32_dynamic_denorm(float %a, float %b) #3 {
+  %fdiv = fdiv float %a, %b
+  ret float %fdiv
+}
+
 attributes #0 = { nounwind "enable-unsafe-fp-math"="false" "denormal-fp-math-f32"="preserve-sign,preserve-sign" "target-features"="-flat-for-global" }
 attributes #1 = { nounwind "enable-unsafe-fp-math"="true" "denormal-fp-math-f32"="preserve-sign,preserve-sign" "target-features"="-flat-for-global" }
 attributes #2 = { nounwind "enable-unsafe-fp-math"="false" "denormal-fp-math-f32"="ieee,ieee" "target-features"="-flat-for-global" }
+attributes #3 = { nounwind "denormal-fp-math-f32"="dynamic,dynamic" "target-features"="-flat-for-global" }
 
 !0 = !{float 2.500000e+00}

llvm/test/CodeGen/AMDGPU/llvm.exp.ll

 define float @v_exp_f32_afn_dynamic(float %in) #1 {
 ; VI-SDAG-LABEL: v_exp_f32_afn_dynamic:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-SDAG-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-SDAG-NEXT:    v_sub_f32_e32 v4, v0, v1
 ; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3fb8a000, v1
 ; VI-SDAG-NEXT:    v_mul_f32_e32 v5, 0x39a3b295, v4
-; VI-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8a000
-; VI-SDAG-NEXT:    v_rndne_f32_e32 v2, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v5, 0x3fb8a000, v4
-; VI-SDAG-NEXT:    v_mad_f32 v3, v1, s4, -v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v5, 0x39a3b295, v1
-; VI-SDAG-NEXT:    v_add_f32_e32 v1, v3, v5
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-SDAG-NEXT:    v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT:    v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-SDAG-NEXT:    v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v2, v1
 ; VI-SDAG-NEXT:    v_exp_f32_e32 v1, v1
-; VI-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v2
+; VI-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v3
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
 ; VI-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v0
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0x42b17218
 ; VI-SDAG-NEXT:    v_ldexp_f32 v1, v1, v2
 ; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; VI-SDAG-NEXT:    v_cmp_nlt_f32_e32 vcc, s4, v0
 ; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
 ; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-GISEL-LABEL: v_exp_f32_afn_dynamic:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-GISEL-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-GISEL-NEXT:    v_sub_f32_e32 v2, v0, v1
-; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3fb8a000, v1
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v4, 0x39a3b295, v2
-; VI-GISEL-NEXT:    s_mov_b32 s4, 0x3fb8a000
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x3fb8a000, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
 ; VI-GISEL-NEXT:    v_rndne_f32_e32 v2, v3
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x39a3b295, v1
-; VI-GISEL-NEXT:    v_mad_f32 v1, v1, s4, -v2
-; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v4
+; VI-GISEL-NEXT:    v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v3, v1
 ; VI-GISEL-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; VI-GISEL-NEXT:    v_exp_f32_e32 v1, v1
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x7f800000
 ; VI-GISEL-NEXT:    v_ldexp_f32 v1, v1, v2
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0xc2ce8ed0
 ; VI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x42b17218
 ; VI-GISEL-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc
 ; VI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v2
 ; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v1, v3, vcc
 ; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-SDAG-LABEL: v_exp_f32_afn_dynamic:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
-; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
-; GFX900-SDAG-NEXT:    s_mov_b32 s5, 0x32a5705f
-; GFX900-SDAG-NEXT:    v_rndne_f32_e32 v1, v1
-; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
-; GFX900-SDAG-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; GFX900-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
-; GFX900-SDAG-NEXT:    v_exp_f32_e32 v2, v2
-; GFX900-SDAG-NEXT:    v_cvt_i32_f32_e32 v1, v1
+; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
+; GFX900-SDAG-NEXT:    v_rndne_f32_e32 v2, v1
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v3, v1, v2
+; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x32a5705f
+; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
+; GFX900-SDAG-NEXT:    v_add_f32_e32 v1, v3, v1
+; GFX900-SDAG-NEXT:    v_exp_f32_e32 v1, v1
+; GFX900-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
 ; GFX900-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v0
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x42b17218
-; GFX900-SDAG-NEXT:    v_ldexp_f32 v1, v2, v1
+; GFX900-SDAG-NEXT:    v_ldexp_f32 v1, v1, v2
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; GFX900-SDAG-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; GFX900-SDAG-NEXT:    v_cmp_nlt_f32_e32 vcc, s4, v0
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
 ; GFX900-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-GISEL-LABEL: v_exp_f32_afn_dynamic:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-GISEL-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
 ; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x32a5705f
-; GFX900-GISEL-NEXT:    v_rndne_f32_e32 v1, v1
 ; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, v3, v2
-; GFX900-GISEL-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; GFX900-GISEL-NEXT:    v_add_f32_e32 v2, v3, v2
-; GFX900-GISEL-NEXT:    v_cvt_i32_f32_e32 v1, v1
-; GFX900-GISEL-NEXT:    v_exp_f32_e32 v2, v2
+; GFX900-GISEL-NEXT:    v_rndne_f32_e32 v3, v1
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v1, v1, v3
+; GFX900-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
+; GFX900-GISEL-NEXT:    v_cvt_i32_f32_e32 v2, v3
+; GFX900-GISEL-NEXT:    v_exp_f32_e32 v1, v1
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x7f800000
-; GFX900-GISEL-NEXT:    v_ldexp_f32 v1, v2, v1
+; GFX900-GISEL-NEXT:    v_ldexp_f32 v1, v1, v2
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0xc2ce8ed0
 ; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x42b17218
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc
 ; GFX900-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v2
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, v1, v3, vcc
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-SDAG-LABEL: v_exp_f32_afn_dynamic:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
-; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
-; SI-SDAG-NEXT:    s_mov_b32 s5, 0x32a5705f
-; SI-SDAG-NEXT:    v_rndne_f32_e32 v1, v1
-; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
-; SI-SDAG-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; SI-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
-; SI-SDAG-NEXT:    v_exp_f32_e32 v2, v2
-; SI-SDAG-NEXT:    v_cvt_i32_f32_e32 v1, v1
+; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
+; SI-SDAG-NEXT:    v_rndne_f32_e32 v2, v1
+; SI-SDAG-NEXT:    v_sub_f32_e32 v3, v1, v2
+; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; SI-SDAG-NEXT:    s_mov_b32 s4, 0x32a5705f
+; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
+; SI-SDAG-NEXT:    v_add_f32_e32 v1, v3, v1
+; SI-SDAG-NEXT:    v_exp_f32_e32 v1, v1
+; SI-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
 ; SI-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v0
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x42b17218
-; SI-SDAG-NEXT:    v_ldexp_f32_e32 v1, v2, v1
+; SI-SDAG-NEXT:    v_ldexp_f32_e32 v1, v1, v2
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; SI-SDAG-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; SI-SDAG-NEXT:    v_cmp_nlt_f32_e32 vcc, s4, v0
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_exp_f32_afn_dynamic:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
 ; SI-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x32a5705f
-; SI-GISEL-NEXT:    v_rndne_f32_e32 v1, v1
 ; SI-GISEL-NEXT:    v_fma_f32 v2, v0, v3, v2
-; SI-GISEL-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; SI-GISEL-NEXT:    v_add_f32_e32 v2, v3, v2
-; SI-GISEL-NEXT:    v_cvt_i32_f32_e32 v1, v1
-; SI-GISEL-NEXT:    v_exp_f32_e32 v2, v2
+; SI-GISEL-NEXT:    v_rndne_f32_e32 v3, v1
+; SI-GISEL-NEXT:    v_sub_f32_e32 v1, v1, v3
+; SI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
+; SI-GISEL-NEXT:    v_cvt_i32_f32_e32 v2, v3
+; SI-GISEL-NEXT:    v_exp_f32_e32 v1, v1
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x7f800000
-; SI-GISEL-NEXT:    v_ldexp_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT:    v_ldexp_f32_e32 v1, v1, v2
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0xc2ce8ed0
 ; SI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x42b17218
 ; SI-GISEL-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc
 ; SI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v2
 ; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v1, v3, vcc
 ; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;

 define float @v_exp_f32_daz(float %in) #0 {
 ; VI-SDAG-LABEL: v_exp_f32_daz:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-SDAG-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-SDAG-NEXT:    v_sub_f32_e32 v4, v0, v1
 ; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3fb8a000, v1
 ; VI-SDAG-NEXT:    v_mul_f32_e32 v5, 0x39a3b295, v4
-; VI-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8a000
-; VI-SDAG-NEXT:    v_rndne_f32_e32 v2, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v5, 0x3fb8a000, v4
-; VI-SDAG-NEXT:    v_mad_f32 v3, v1, s4, -v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v5, 0x39a3b295, v1
-; VI-SDAG-NEXT:    v_add_f32_e32 v1, v3, v5
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-SDAG-NEXT:    v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT:    v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-SDAG-NEXT:    v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v2, v1
 ; VI-SDAG-NEXT:    v_exp_f32_e32 v1, v1
-; VI-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v2
+; VI-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v3
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
 ; VI-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v0
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0x42b17218
 ; VI-SDAG-NEXT:    v_ldexp_f32 v1, v1, v2
 ; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; VI-SDAG-NEXT:    v_cmp_nlt_f32_e32 vcc, s4, v0
 ; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
 ; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-GISEL-LABEL: v_exp_f32_daz:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-GISEL-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-GISEL-NEXT:    v_sub_f32_e32 v2, v0, v1
-; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3fb8a000, v1
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v4, 0x39a3b295, v2
-; VI-GISEL-NEXT:    s_mov_b32 s4, 0x3fb8a000
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x3fb8a000, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
 ; VI-GISEL-NEXT:    v_rndne_f32_e32 v2, v3
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x39a3b295, v1
-; VI-GISEL-NEXT:    v_mad_f32 v1, v1, s4, -v2
-; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v4
+; VI-GISEL-NEXT:    v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v3, v1
 ; VI-GISEL-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; VI-GISEL-NEXT:    v_exp_f32_e32 v1, v1
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x7f800000
 ; VI-GISEL-NEXT:    v_ldexp_f32 v1, v1, v2
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0xc2ce8ed0
 ; VI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x42b17218
 ; VI-GISEL-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc
 ; VI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v2
 ; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v1, v3, vcc
 ; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-SDAG-LABEL: v_exp_f32_daz:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
-; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
-; GFX900-SDAG-NEXT:    s_mov_b32 s5, 0x32a5705f
-; GFX900-SDAG-NEXT:    v_rndne_f32_e32 v1, v1
-; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
-; GFX900-SDAG-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; GFX900-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
-; GFX900-SDAG-NEXT:    v_exp_f32_e32 v2, v2
-; GFX900-SDAG-NEXT:    v_cvt_i32_f32_e32 v1, v1
+; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
+; GFX900-SDAG-NEXT:    v_rndne_f32_e32 v2, v1
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v3, v1, v2
+; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x32a5705f
+; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
+; GFX900-SDAG-NEXT:    v_add_f32_e32 v1, v3, v1
+; GFX900-SDAG-NEXT:    v_exp_f32_e32 v1, v1
+; GFX900-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
 ; GFX900-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v0
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x42b17218
-; GFX900-SDAG-NEXT:    v_ldexp_f32 v1, v2, v1
+; GFX900-SDAG-NEXT:    v_ldexp_f32 v1, v1, v2
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; GFX900-SDAG-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; GFX900-SDAG-NEXT:    v_cmp_nlt_f32_e32 vcc, s4, v0
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
 ; GFX900-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-GISEL-LABEL: v_exp_f32_daz:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-GISEL-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
 ; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x32a5705f
-; GFX900-GISEL-NEXT:    v_rndne_f32_e32 v1, v1
 ; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, v3, v2
-; GFX900-GISEL-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; GFX900-GISEL-NEXT:    v_add_f32_e32 v2, v3, v2
-; GFX900-GISEL-NEXT:    v_cvt_i32_f32_e32 v1, v1
-; GFX900-GISEL-NEXT:    v_exp_f32_e32 v2, v2
+; GFX900-GISEL-NEXT:    v_rndne_f32_e32 v3, v1
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v1, v1, v3
+; GFX900-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
+; GFX900-GISEL-NEXT:    v_cvt_i32_f32_e32 v2, v3
+; GFX900-GISEL-NEXT:    v_exp_f32_e32 v1, v1
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x7f800000
-; GFX900-GISEL-NEXT:    v_ldexp_f32 v1, v2, v1
+; GFX900-GISEL-NEXT:    v_ldexp_f32 v1, v1, v2
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0xc2ce8ed0
 ; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x42b17218
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc
 ; GFX900-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v2
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, v1, v3, vcc
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-SDAG-LABEL: v_exp_f32_daz:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
-; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
-; SI-SDAG-NEXT:    s_mov_b32 s5, 0x32a5705f
-; SI-SDAG-NEXT:    v_rndne_f32_e32 v1, v1
-; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
-; SI-SDAG-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; SI-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
-; SI-SDAG-NEXT:    v_exp_f32_e32 v2, v2
-; SI-SDAG-NEXT:    v_cvt_i32_f32_e32 v1, v1
+; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
+; SI-SDAG-NEXT:    v_rndne_f32_e32 v2, v1
+; SI-SDAG-NEXT:    v_sub_f32_e32 v3, v1, v2
+; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; SI-SDAG-NEXT:    s_mov_b32 s4, 0x32a5705f
+; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
+; SI-SDAG-NEXT:    v_add_f32_e32 v1, v3, v1
+; SI-SDAG-NEXT:    v_exp_f32_e32 v1, v1
+; SI-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
 ; SI-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v0
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x42b17218
-; SI-SDAG-NEXT:    v_ldexp_f32_e32 v1, v2, v1
+; SI-SDAG-NEXT:    v_ldexp_f32_e32 v1, v1, v2
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; SI-SDAG-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; SI-SDAG-NEXT:    v_cmp_nlt_f32_e32 vcc, s4, v0
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_exp_f32_daz:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
 ; SI-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x32a5705f
-; SI-GISEL-NEXT:    v_rndne_f32_e32 v1, v1
 ; SI-GISEL-NEXT:    v_fma_f32 v2, v0, v3, v2
-; SI-GISEL-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; SI-GISEL-NEXT:    v_add_f32_e32 v2, v3, v2
-; SI-GISEL-NEXT:    v_cvt_i32_f32_e32 v1, v1
-; SI-GISEL-NEXT:    v_exp_f32_e32 v2, v2
+; SI-GISEL-NEXT:    v_rndne_f32_e32 v3, v1
+; SI-GISEL-NEXT:    v_sub_f32_e32 v1, v1, v3
+; SI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
+; SI-GISEL-NEXT:    v_cvt_i32_f32_e32 v2, v3
+; SI-GISEL-NEXT:    v_exp_f32_e32 v1, v1
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x7f800000
-; SI-GISEL-NEXT:    v_ldexp_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT:    v_ldexp_f32_e32 v1, v1, v2
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0xc2ce8ed0
 ; SI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x42b17218
 ; SI-GISEL-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc
 ; SI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v2
 ; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v1, v3, vcc
 ; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;

 define float @v_exp_f32_nnan_daz(float %in) #0 {
 ; VI-SDAG-LABEL: v_exp_f32_nnan_daz:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-SDAG-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-SDAG-NEXT:    v_sub_f32_e32 v4, v0, v1
 ; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3fb8a000, v1
 ; VI-SDAG-NEXT:    v_mul_f32_e32 v5, 0x39a3b295, v4
-; VI-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8a000
-; VI-SDAG-NEXT:    v_rndne_f32_e32 v2, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v5, 0x3fb8a000, v4
-; VI-SDAG-NEXT:    v_mad_f32 v3, v1, s4, -v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v5, 0x39a3b295, v1
-; VI-SDAG-NEXT:    v_add_f32_e32 v1, v3, v5
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-SDAG-NEXT:    v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT:    v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-SDAG-NEXT:    v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v2, v1
 ; VI-SDAG-NEXT:    v_exp_f32_e32 v1, v1
-; VI-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v2
+; VI-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v3
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
 ; VI-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v0
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0x42b17218
 ; VI-SDAG-NEXT:    v_ldexp_f32 v1, v1, v2
 ; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; VI-SDAG-NEXT:    v_cmp_nlt_f32_e32 vcc, s4, v0
 ; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
 ; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-GISEL-LABEL: v_exp_f32_nnan_daz:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-GISEL-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-GISEL-NEXT:    v_sub_f32_e32 v2, v0, v1
-; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3fb8a000, v1
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v4, 0x39a3b295, v2
-; VI-GISEL-NEXT:    s_mov_b32 s4, 0x3fb8a000
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x3fb8a000, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
 ; VI-GISEL-NEXT:    v_rndne_f32_e32 v2, v3
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x39a3b295, v1
-; VI-GISEL-NEXT:    v_mad_f32 v1, v1, s4, -v2
-; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v4
+; VI-GISEL-NEXT:    v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v3, v1
 ; VI-GISEL-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; VI-GISEL-NEXT:    v_exp_f32_e32 v1, v1
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x7f800000
 ; VI-GISEL-NEXT:    v_ldexp_f32 v1, v1, v2
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0xc2ce8ed0
 ; VI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x42b17218
 ; VI-GISEL-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc
 ; VI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v2
 ; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v1, v3, vcc
 ; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-SDAG-LABEL: v_exp_f32_nnan_daz:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
-; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
-; GFX900-SDAG-NEXT:    s_mov_b32 s5, 0x32a5705f
-; GFX900-SDAG-NEXT:    v_rndne_f32_e32 v1, v1
-; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
-; GFX900-SDAG-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; GFX900-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
-; GFX900-SDAG-NEXT:    v_exp_f32_e32 v2, v2
-; GFX900-SDAG-NEXT:    v_cvt_i32_f32_e32 v1, v1
+; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
+; GFX900-SDAG-NEXT:    v_rndne_f32_e32 v2, v1
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v3, v1, v2
+; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x32a5705f
+; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
+; GFX900-SDAG-NEXT:    v_add_f32_e32 v1, v3, v1
+; GFX900-SDAG-NEXT:    v_exp_f32_e32 v1, v1
+; GFX900-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
 ; GFX900-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v0
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x42b17218
-; GFX900-SDAG-NEXT:    v_ldexp_f32 v1, v2, v1
+; GFX900-SDAG-NEXT:    v_ldexp_f32 v1, v1, v2
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; GFX900-SDAG-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; GFX900-SDAG-NEXT:    v_cmp_nlt_f32_e32 vcc, s4, v0
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
 ; GFX900-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-GISEL-LABEL: v_exp_f32_nnan_daz:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-GISEL-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
 ; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x32a5705f
-; GFX900-GISEL-NEXT:    v_rndne_f32_e32 v1, v1
 ; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, v3, v2
-; GFX900-GISEL-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; GFX900-GISEL-NEXT:    v_add_f32_e32 v2, v3, v2
-; GFX900-GISEL-NEXT:    v_cvt_i32_f32_e32 v1, v1
-; GFX900-GISEL-NEXT:    v_exp_f32_e32 v2, v2
+; GFX900-GISEL-NEXT:    v_rndne_f32_e32 v3, v1
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v1, v1, v3
+; GFX900-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
+; GFX900-GISEL-NEXT:    v_cvt_i32_f32_e32 v2, v3
+; GFX900-GISEL-NEXT:    v_exp_f32_e32 v1, v1
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x7f800000
-; GFX900-GISEL-NEXT:    v_ldexp_f32 v1, v2, v1
+; GFX900-GISEL-NEXT:    v_ldexp_f32 v1, v1, v2
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0xc2ce8ed0
 ; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x42b17218
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc
 ; GFX900-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v2
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, v1, v3, vcc
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-SDAG-LABEL: v_exp_f32_nnan_daz:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
-; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
-; SI-SDAG-NEXT:    s_mov_b32 s5, 0x32a5705f
-; SI-SDAG-NEXT:    v_rndne_f32_e32 v1, v1
-; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
-; SI-SDAG-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; SI-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
-; SI-SDAG-NEXT:    v_exp_f32_e32 v2, v2
-; SI-SDAG-NEXT:    v_cvt_i32_f32_e32 v1, v1
+; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
+; SI-SDAG-NEXT:    v_rndne_f32_e32 v2, v1
+; SI-SDAG-NEXT:    v_sub_f32_e32 v3, v1, v2
+; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; SI-SDAG-NEXT:    s_mov_b32 s4, 0x32a5705f
+; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
+; SI-SDAG-NEXT:    v_add_f32_e32 v1, v3, v1
+; SI-SDAG-NEXT:    v_exp_f32_e32 v1, v1
+; SI-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
 ; SI-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v0
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x42b17218
-; SI-SDAG-NEXT:    v_ldexp_f32_e32 v1, v2, v1
+; SI-SDAG-NEXT:    v_ldexp_f32_e32 v1, v1, v2
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; SI-SDAG-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; SI-SDAG-NEXT:    v_cmp_nlt_f32_e32 vcc, s4, v0
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_exp_f32_nnan_daz:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
 ; SI-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x32a5705f
-; SI-GISEL-NEXT:    v_rndne_f32_e32 v1, v1
 ; SI-GISEL-NEXT:    v_fma_f32 v2, v0, v3, v2
-; SI-GISEL-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; SI-GISEL-NEXT:    v_add_f32_e32 v2, v3, v2
-; SI-GISEL-NEXT:    v_cvt_i32_f32_e32 v1, v1
-; SI-GISEL-NEXT:    v_exp_f32_e32 v2, v2
+; SI-GISEL-NEXT:    v_rndne_f32_e32 v3, v1
+; SI-GISEL-NEXT:    v_sub_f32_e32 v1, v1, v3
+; SI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
+; SI-GISEL-NEXT:    v_cvt_i32_f32_e32 v2, v3
+; SI-GISEL-NEXT:    v_exp_f32_e32 v1, v1
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x7f800000
-; SI-GISEL-NEXT:    v_ldexp_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT:    v_ldexp_f32_e32 v1, v1, v2
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0xc2ce8ed0
 ; SI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x42b17218
 ; SI-GISEL-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc
 ; SI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v2
 ; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v1, v3, vcc
 ; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;

 define float @v_exp_f32_nnan_dynamic(float %in) #1 {
 ; VI-SDAG-LABEL: v_exp_f32_nnan_dynamic:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-SDAG-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-SDAG-NEXT:    v_sub_f32_e32 v4, v0, v1
 ; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3fb8a000, v1
 ; VI-SDAG-NEXT:    v_mul_f32_e32 v5, 0x39a3b295, v4
-; VI-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8a000
-; VI-SDAG-NEXT:    v_rndne_f32_e32 v2, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v5, 0x3fb8a000, v4
-; VI-SDAG-NEXT:    v_mad_f32 v3, v1, s4, -v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v5, 0x39a3b295, v1
-; VI-SDAG-NEXT:    v_add_f32_e32 v1, v3, v5
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-SDAG-NEXT:    v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT:    v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-SDAG-NEXT:    v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v2, v1
 ; VI-SDAG-NEXT:    v_exp_f32_e32 v1, v1
-; VI-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v2
+; VI-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v3
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
 ; VI-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v0
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0x42b17218
 ; VI-SDAG-NEXT:    v_ldexp_f32 v1, v1, v2
 ; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; VI-SDAG-NEXT:    v_cmp_nlt_f32_e32 vcc, s4, v0
 ; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
 ; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-GISEL-LABEL: v_exp_f32_nnan_dynamic:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-GISEL-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-GISEL-NEXT:    v_sub_f32_e32 v2, v0, v1
-; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3fb8a000, v1
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v4, 0x39a3b295, v2
-; VI-GISEL-NEXT:    s_mov_b32 s4, 0x3fb8a000
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x3fb8a000, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
 ; VI-GISEL-NEXT:    v_rndne_f32_e32 v2, v3
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x39a3b295, v1
-; VI-GISEL-NEXT:    v_mad_f32 v1, v1, s4, -v2
-; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v4
+; VI-GISEL-NEXT:    v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v3, v1
 ; VI-GISEL-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; VI-GISEL-NEXT:    v_exp_f32_e32 v1, v1
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x7f800000
 ; VI-GISEL-NEXT:    v_ldexp_f32 v1, v1, v2
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0xc2ce8ed0
 ; VI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x42b17218
 ; VI-GISEL-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc
 ; VI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v2
 ; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v1, v3, vcc
 ; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-SDAG-LABEL: v_exp_f32_nnan_dynamic:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
-; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
-; GFX900-SDAG-NEXT:    s_mov_b32 s5, 0x32a5705f
-; GFX900-SDAG-NEXT:    v_rndne_f32_e32 v1, v1
-; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
-; GFX900-SDAG-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; GFX900-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
-; GFX900-SDAG-NEXT:    v_exp_f32_e32 v2, v2
-; GFX900-SDAG-NEXT:    v_cvt_i32_f32_e32 v1, v1
+; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
+; GFX900-SDAG-NEXT:    v_rndne_f32_e32 v2, v1
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v3, v1, v2
+; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x32a5705f
+; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
+; GFX900-SDAG-NEXT:    v_add_f32_e32 v1, v3, v1
+; GFX900-SDAG-NEXT:    v_exp_f32_e32 v1, v1
+; GFX900-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
 ; GFX900-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v0
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x42b17218
-; GFX900-SDAG-NEXT:    v_ldexp_f32 v1, v2, v1
+; GFX900-SDAG-NEXT:    v_ldexp_f32 v1, v1, v2
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; GFX900-SDAG-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; GFX900-SDAG-NEXT:    v_cmp_nlt_f32_e32 vcc, s4, v0
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
 ; GFX900-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-GISEL-LABEL: v_exp_f32_nnan_dynamic:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-GISEL-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
 ; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x32a5705f
-; GFX900-GISEL-NEXT:    v_rndne_f32_e32 v1, v1
 ; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, v3, v2
-; GFX900-GISEL-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; GFX900-GISEL-NEXT:    v_add_f32_e32 v2, v3, v2
-; GFX900-GISEL-NEXT:    v_cvt_i32_f32_e32 v1, v1
-; GFX900-GISEL-NEXT:    v_exp_f32_e32 v2, v2
+; GFX900-GISEL-NEXT:    v_rndne_f32_e32 v3, v1
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v1, v1, v3
+; GFX900-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
+; GFX900-GISEL-NEXT:    v_cvt_i32_f32_e32 v2, v3
+; GFX900-GISEL-NEXT:    v_exp_f32_e32 v1, v1
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x7f800000
-; GFX900-GISEL-NEXT:    v_ldexp_f32 v1, v2, v1
+; GFX900-GISEL-NEXT:    v_ldexp_f32 v1, v1, v2
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0xc2ce8ed0
 ; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x42b17218
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc
 ; GFX900-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v2
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, v1, v3, vcc
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-SDAG-LABEL: v_exp_f32_nnan_dynamic:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
-; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
-; SI-SDAG-NEXT:    s_mov_b32 s5, 0x32a5705f
-; SI-SDAG-NEXT:    v_rndne_f32_e32 v1, v1
-; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
-; SI-SDAG-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; SI-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
-; SI-SDAG-NEXT:    v_exp_f32_e32 v2, v2
-; SI-SDAG-NEXT:    v_cvt_i32_f32_e32 v1, v1
+; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
+; SI-SDAG-NEXT:    v_rndne_f32_e32 v2, v1
+; SI-SDAG-NEXT:    v_sub_f32_e32 v3, v1, v2
+; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; SI-SDAG-NEXT:    s_mov_b32 s4, 0x32a5705f
+; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
+; SI-SDAG-NEXT:    v_add_f32_e32 v1, v3, v1
+; SI-SDAG-NEXT:    v_exp_f32_e32 v1, v1
+; SI-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
 ; SI-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v0
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x42b17218
-; SI-SDAG-NEXT:    v_ldexp_f32_e32 v1, v2, v1
+; SI-SDAG-NEXT:    v_ldexp_f32_e32 v1, v1, v2
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; SI-SDAG-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; SI-SDAG-NEXT:    v_cmp_nlt_f32_e32 vcc, s4, v0
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_exp_f32_nnan_dynamic:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
 ; SI-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x32a5705f
-; SI-GISEL-NEXT:    v_rndne_f32_e32 v1, v1
 ; SI-GISEL-NEXT:    v_fma_f32 v2, v0, v3, v2
-; SI-GISEL-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; SI-GISEL-NEXT:    v_add_f32_e32 v2, v3, v2
-; SI-GISEL-NEXT:    v_cvt_i32_f32_e32 v1, v1
-; SI-GISEL-NEXT:    v_exp_f32_e32 v2, v2
+; SI-GISEL-NEXT:    v_rndne_f32_e32 v3, v1
+; SI-GISEL-NEXT:    v_sub_f32_e32 v1, v1, v3
+; SI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
+; SI-GISEL-NEXT:    v_cvt_i32_f32_e32 v2, v3
+; SI-GISEL-NEXT:    v_exp_f32_e32 v1, v1
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x7f800000
-; SI-GISEL-NEXT:    v_ldexp_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT:    v_ldexp_f32_e32 v1, v1, v2
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0xc2ce8ed0
 ; SI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x42b17218
 ; SI-GISEL-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc
 ; SI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v2
 ; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v1, v3, vcc
 ; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;

 define float @v_exp_f32_ninf_daz(float %in) #0 {
 ; VI-SDAG-LABEL: v_exp_f32_ninf_daz:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-SDAG-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-SDAG-NEXT:    v_sub_f32_e32 v4, v0, v1
 ; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3fb8a000, v1
 ; VI-SDAG-NEXT:    v_mul_f32_e32 v5, 0x39a3b295, v4
-; VI-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8a000
-; VI-SDAG-NEXT:    v_rndne_f32_e32 v2, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v5, 0x3fb8a000, v4
-; VI-SDAG-NEXT:    v_mad_f32 v3, v1, s4, -v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v5, 0x39a3b295, v1
-; VI-SDAG-NEXT:    v_add_f32_e32 v1, v3, v5
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-SDAG-NEXT:    v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT:    v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-SDAG-NEXT:    v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v2, v1
 ; VI-SDAG-NEXT:    v_exp_f32_e32 v1, v1
-; VI-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v2
+; VI-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v3
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
 ; VI-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v0
 ; VI-SDAG-NEXT:    v_ldexp_f32 v1, v1, v2
 ; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
 ; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-GISEL-LABEL: v_exp_f32_ninf_daz:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-GISEL-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-GISEL-NEXT:    v_sub_f32_e32 v2, v0, v1
-; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3fb8a000, v1
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v4, 0x39a3b295, v2
-; VI-GISEL-NEXT:    s_mov_b32 s4, 0x3fb8a000
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x3fb8a000, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
 ; VI-GISEL-NEXT:    v_rndne_f32_e32 v2, v3
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x39a3b295, v1
-; VI-GISEL-NEXT:    v_mad_f32 v1, v1, s4, -v2
-; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v4
+; VI-GISEL-NEXT:    v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v3, v1
 ; VI-GISEL-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; VI-GISEL-NEXT:    v_exp_f32_e32 v1, v1
 ; VI-GISEL-NEXT:    v_ldexp_f32 v1, v1, v2
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0xc2ce8ed0
 ; VI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; VI-GISEL-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc
 ; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-SDAG-LABEL: v_exp_f32_ninf_daz:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
-; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
-; GFX900-SDAG-NEXT:    s_mov_b32 s5, 0x32a5705f
-; GFX900-SDAG-NEXT:    v_rndne_f32_e32 v1, v1
-; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
-; GFX900-SDAG-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; GFX900-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
-; GFX900-SDAG-NEXT:    v_exp_f32_e32 v2, v2
-; GFX900-SDAG-NEXT:    v_cvt_i32_f32_e32 v1, v1
+; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
+; GFX900-SDAG-NEXT:    v_rndne_f32_e32 v2, v1
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v3, v1, v2
+; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x32a5705f
+; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
+; GFX900-SDAG-NEXT:    v_add_f32_e32 v1, v3, v1
+; GFX900-SDAG-NEXT:    v_exp_f32_e32 v1, v1
+; GFX900-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
 ; GFX900-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v0
-; GFX900-SDAG-NEXT:    v_ldexp_f32 v1, v2, v1
+; GFX900-SDAG-NEXT:    v_ldexp_f32 v1, v1, v2
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
 ; GFX900-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-GISEL-LABEL: v_exp_f32_ninf_daz:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-GISEL-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
 ; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x32a5705f
-; GFX900-GISEL-NEXT:    v_rndne_f32_e32 v1, v1
 ; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, v3, v2
-; GFX900-GISEL-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; GFX900-GISEL-NEXT:    v_add_f32_e32 v2, v3, v2
-; GFX900-GISEL-NEXT:    v_cvt_i32_f32_e32 v1, v1
-; GFX900-GISEL-NEXT:    v_exp_f32_e32 v2, v2
-; GFX900-GISEL-NEXT:    v_ldexp_f32 v1, v2, v1
+; GFX900-GISEL-NEXT:    v_rndne_f32_e32 v3, v1
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v1, v1, v3
+; GFX900-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
+; GFX900-GISEL-NEXT:    v_cvt_i32_f32_e32 v2, v3
+; GFX900-GISEL-NEXT:    v_exp_f32_e32 v1, v1
+; GFX900-GISEL-NEXT:    v_ldexp_f32 v1, v1, v2
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0xc2ce8ed0
 ; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-SDAG-LABEL: v_exp_f32_ninf_daz:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
-; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
-; SI-SDAG-NEXT:    s_mov_b32 s5, 0x32a5705f
-; SI-SDAG-NEXT:    v_rndne_f32_e32 v1, v1
-; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
-; SI-SDAG-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; SI-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
-; SI-SDAG-NEXT:    v_exp_f32_e32 v2, v2
-; SI-SDAG-NEXT:    v_cvt_i32_f32_e32 v1, v1
+; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
+; SI-SDAG-NEXT:    v_rndne_f32_e32 v2, v1
+; SI-SDAG-NEXT:    v_sub_f32_e32 v3, v1, v2
+; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; SI-SDAG-NEXT:    s_mov_b32 s4, 0x32a5705f
+; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
+; SI-SDAG-NEXT:    v_add_f32_e32 v1, v3, v1
+; SI-SDAG-NEXT:    v_exp_f32_e32 v1, v1
+; SI-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
 ; SI-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v0
-; SI-SDAG-NEXT:    v_ldexp_f32_e32 v1, v2, v1
+; SI-SDAG-NEXT:    v_ldexp_f32_e32 v1, v1, v2
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_exp_f32_ninf_daz:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
 ; SI-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x32a5705f
-; SI-GISEL-NEXT:    v_rndne_f32_e32 v1, v1
 ; SI-GISEL-NEXT:    v_fma_f32 v2, v0, v3, v2
-; SI-GISEL-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; SI-GISEL-NEXT:    v_add_f32_e32 v2, v3, v2
-; SI-GISEL-NEXT:    v_cvt_i32_f32_e32 v1, v1
-; SI-GISEL-NEXT:    v_exp_f32_e32 v2, v2
-; SI-GISEL-NEXT:    v_ldexp_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT:    v_rndne_f32_e32 v3, v1
+; SI-GISEL-NEXT:    v_sub_f32_e32 v1, v1, v3
+; SI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
+; SI-GISEL-NEXT:    v_cvt_i32_f32_e32 v2, v3
+; SI-GISEL-NEXT:    v_exp_f32_e32 v1, v1
+; SI-GISEL-NEXT:    v_ldexp_f32_e32 v1, v1, v2
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0xc2ce8ed0
 ; SI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; SI-GISEL-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc
 ; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_exp_f32_ninf_daz:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END

 define float @v_exp_f32_ninf_dynamic(float %in) #1 {
 ; VI-SDAG-LABEL: v_exp_f32_ninf_dynamic:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-SDAG-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-SDAG-NEXT:    v_sub_f32_e32 v4, v0, v1
 ; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3fb8a000, v1
 ; VI-SDAG-NEXT:    v_mul_f32_e32 v5, 0x39a3b295, v4
-; VI-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8a000
-; VI-SDAG-NEXT:    v_rndne_f32_e32 v2, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v5, 0x3fb8a000, v4
-; VI-SDAG-NEXT:    v_mad_f32 v3, v1, s4, -v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v5, 0x39a3b295, v1
-; VI-SDAG-NEXT:    v_add_f32_e32 v1, v3, v5
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-SDAG-NEXT:    v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT:    v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-SDAG-NEXT:    v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v2, v1
 ; VI-SDAG-NEXT:    v_exp_f32_e32 v1, v1
-; VI-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v2
+; VI-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v3
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
 ; VI-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v0
 ; VI-SDAG-NEXT:    v_ldexp_f32 v1, v1, v2
 ; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
 ; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-GISEL-LABEL: v_exp_f32_ninf_dynamic:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-GISEL-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-GISEL-NEXT:    v_sub_f32_e32 v2, v0, v1
-; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3fb8a000, v1
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v4, 0x39a3b295, v2
-; VI-GISEL-NEXT:    s_mov_b32 s4, 0x3fb8a000
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x3fb8a000, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
 ; VI-GISEL-NEXT:    v_rndne_f32_e32 v2, v3
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x39a3b295, v1
-; VI-GISEL-NEXT:    v_mad_f32 v1, v1, s4, -v2
-; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v4
+; VI-GISEL-NEXT:    v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v3, v1
 ; VI-GISEL-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; VI-GISEL-NEXT:    v_exp_f32_e32 v1, v1
 ; VI-GISEL-NEXT:    v_ldexp_f32 v1, v1, v2
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0xc2ce8ed0
 ; VI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; VI-GISEL-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc
 ; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-SDAG-LABEL: v_exp_f32_ninf_dynamic:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
-; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
-; GFX900-SDAG-NEXT:    s_mov_b32 s5, 0x32a5705f
-; GFX900-SDAG-NEXT:    v_rndne_f32_e32 v1, v1
-; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
-; GFX900-SDAG-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; GFX900-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
-; GFX900-SDAG-NEXT:    v_exp_f32_e32 v2, v2
-; GFX900-SDAG-NEXT:    v_cvt_i32_f32_e32 v1, v1
+; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
+; GFX900-SDAG-NEXT:    v_rndne_f32_e32 v2, v1
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v3, v1, v2
+; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x32a5705f
+; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
+; GFX900-SDAG-NEXT:    v_add_f32_e32 v1, v3, v1
+; GFX900-SDAG-NEXT:    v_exp_f32_e32 v1, v1
+; GFX900-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
 ; GFX900-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v0
-; GFX900-SDAG-NEXT:    v_ldexp_f32 v1, v2, v1
+; GFX900-SDAG-NEXT:    v_ldexp_f32 v1, v1, v2
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
 ; GFX900-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-GISEL-LABEL: v_exp_f32_ninf_dynamic:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-GISEL-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
 ; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x32a5705f
-; GFX900-GISEL-NEXT:    v_rndne_f32_e32 v1, v1
 ; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, v3, v2
-; GFX900-GISEL-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; GFX900-GISEL-NEXT:    v_add_f32_e32 v2, v3, v2
-; GFX900-GISEL-NEXT:    v_cvt_i32_f32_e32 v1, v1
-; GFX900-GISEL-NEXT:    v_exp_f32_e32 v2, v2
-; GFX900-GISEL-NEXT:    v_ldexp_f32 v1, v2, v1
+; GFX900-GISEL-NEXT:    v_rndne_f32_e32 v3, v1
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v1, v1, v3
+; GFX900-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
+; GFX900-GISEL-NEXT:    v_cvt_i32_f32_e32 v2, v3
+; GFX900-GISEL-NEXT:    v_exp_f32_e32 v1, v1
+; GFX900-GISEL-NEXT:    v_ldexp_f32 v1, v1, v2
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0xc2ce8ed0
 ; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-SDAG-LABEL: v_exp_f32_ninf_dynamic:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
-; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
-; SI-SDAG-NEXT:    s_mov_b32 s5, 0x32a5705f
-; SI-SDAG-NEXT:    v_rndne_f32_e32 v1, v1
-; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
-; SI-SDAG-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; SI-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
-; SI-SDAG-NEXT:    v_exp_f32_e32 v2, v2
-; SI-SDAG-NEXT:    v_cvt_i32_f32_e32 v1, v1
+; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
+; SI-SDAG-NEXT:    v_rndne_f32_e32 v2, v1
+; SI-SDAG-NEXT:    v_sub_f32_e32 v3, v1, v2
+; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; SI-SDAG-NEXT:    s_mov_b32 s4, 0x32a5705f
+; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
+; SI-SDAG-NEXT:    v_add_f32_e32 v1, v3, v1
+; SI-SDAG-NEXT:    v_exp_f32_e32 v1, v1
+; SI-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
 ; SI-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v0
-; SI-SDAG-NEXT:    v_ldexp_f32_e32 v1, v2, v1
+; SI-SDAG-NEXT:    v_ldexp_f32_e32 v1, v1, v2
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_exp_f32_ninf_dynamic:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
 ; SI-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x32a5705f
-; SI-GISEL-NEXT:    v_rndne_f32_e32 v1, v1
 ; SI-GISEL-NEXT:    v_fma_f32 v2, v0, v3, v2
-; SI-GISEL-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; SI-GISEL-NEXT:    v_add_f32_e32 v2, v3, v2
-; SI-GISEL-NEXT:    v_cvt_i32_f32_e32 v1, v1
-; SI-GISEL-NEXT:    v_exp_f32_e32 v2, v2
-; SI-GISEL-NEXT:    v_ldexp_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT:    v_rndne_f32_e32 v3, v1
+; SI-GISEL-NEXT:    v_sub_f32_e32 v1, v1, v3
+; SI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
+; SI-GISEL-NEXT:    v_cvt_i32_f32_e32 v2, v3
+; SI-GISEL-NEXT:    v_exp_f32_e32 v1, v1
+; SI-GISEL-NEXT:    v_ldexp_f32_e32 v1, v1, v2
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0xc2ce8ed0
 ; SI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; SI-GISEL-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc
 ; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_exp_f32_ninf_dynamic:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END

 define float @v_exp_f32_nnan_ninf_daz(float %in) #0 {
 ; VI-SDAG-LABEL: v_exp_f32_nnan_ninf_daz:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-SDAG-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-SDAG-NEXT:    v_sub_f32_e32 v4, v0, v1
 ; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3fb8a000, v1
 ; VI-SDAG-NEXT:    v_mul_f32_e32 v5, 0x39a3b295, v4
-; VI-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8a000
-; VI-SDAG-NEXT:    v_rndne_f32_e32 v2, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v5, 0x3fb8a000, v4
-; VI-SDAG-NEXT:    v_mad_f32 v3, v1, s4, -v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v5, 0x39a3b295, v1
-; VI-SDAG-NEXT:    v_add_f32_e32 v1, v3, v5
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-SDAG-NEXT:    v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT:    v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-SDAG-NEXT:    v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v2, v1
 ; VI-SDAG-NEXT:    v_exp_f32_e32 v1, v1
-; VI-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v2
+; VI-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v3
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
 ; VI-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v0
 ; VI-SDAG-NEXT:    v_ldexp_f32 v1, v1, v2
 ; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
 ; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-GISEL-LABEL: v_exp_f32_nnan_ninf_daz:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-GISEL-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-GISEL-NEXT:    v_sub_f32_e32 v2, v0, v1
-; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3fb8a000, v1
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v4, 0x39a3b295, v2
-; VI-GISEL-NEXT:    s_mov_b32 s4, 0x3fb8a000
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x3fb8a000, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
 ; VI-GISEL-NEXT:    v_rndne_f32_e32 v2, v3
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x39a3b295, v1
-; VI-GISEL-NEXT:    v_mad_f32 v1, v1, s4, -v2
-; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v4
+; VI-GISEL-NEXT:    v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v3, v1
 ; VI-GISEL-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; VI-GISEL-NEXT:    v_exp_f32_e32 v1, v1
 ; VI-GISEL-NEXT:    v_ldexp_f32 v1, v1, v2
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0xc2ce8ed0
 ; VI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; VI-GISEL-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc
 ; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-SDAG-LABEL: v_exp_f32_nnan_ninf_daz:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
-; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
-; GFX900-SDAG-NEXT:    s_mov_b32 s5, 0x32a5705f
-; GFX900-SDAG-NEXT:    v_rndne_f32_e32 v1, v1
-; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
-; GFX900-SDAG-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; GFX900-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
-; GFX900-SDAG-NEXT:    v_exp_f32_e32 v2, v2
-; GFX900-SDAG-NEXT:    v_cvt_i32_f32_e32 v1, v1
+; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
+; GFX900-SDAG-NEXT:    v_rndne_f32_e32 v2, v1
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v3, v1, v2
+; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x32a5705f
+; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
+; GFX900-SDAG-NEXT:    v_add_f32_e32 v1, v3, v1
+; GFX900-SDAG-NEXT:    v_exp_f32_e32 v1, v1
+; GFX900-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
 ; GFX900-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v0
-; GFX900-SDAG-NEXT:    v_ldexp_f32 v1, v2, v1
+; GFX900-SDAG-NEXT:    v_ldexp_f32 v1, v1, v2
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
 ; GFX900-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-GISEL-LABEL: v_exp_f32_nnan_ninf_daz:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-GISEL-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
 ; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x32a5705f
-; GFX900-GISEL-NEXT:    v_rndne_f32_e32 v1, v1
 ; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, v3, v2
-; GFX900-GISEL-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; GFX900-GISEL-NEXT:    v_add_f32_e32 v2, v3, v2
-; GFX900-GISEL-NEXT:    v_cvt_i32_f32_e32 v1, v1
-; GFX900-GISEL-NEXT:    v_exp_f32_e32 v2, v2
-; GFX900-GISEL-NEXT:    v_ldexp_f32 v1, v2, v1
+; GFX900-GISEL-NEXT:    v_rndne_f32_e32 v3, v1
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v1, v1, v3
+; GFX900-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
+; GFX900-GISEL-NEXT:    v_cvt_i32_f32_e32 v2, v3
+; GFX900-GISEL-NEXT:    v_exp_f32_e32 v1, v1
+; GFX900-GISEL-NEXT:    v_ldexp_f32 v1, v1, v2
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0xc2ce8ed0
 ; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-SDAG-LABEL: v_exp_f32_nnan_ninf_daz:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
-; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
-; SI-SDAG-NEXT:    s_mov_b32 s5, 0x32a5705f
-; SI-SDAG-NEXT:    v_rndne_f32_e32 v1, v1
-; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
-; SI-SDAG-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; SI-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
-; SI-SDAG-NEXT:    v_exp_f32_e32 v2, v2
-; SI-SDAG-NEXT:    v_cvt_i32_f32_e32 v1, v1
+; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
+; SI-SDAG-NEXT:    v_rndne_f32_e32 v2, v1
+; SI-SDAG-NEXT:    v_sub_f32_e32 v3, v1, v2
+; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; SI-SDAG-NEXT:    s_mov_b32 s4, 0x32a5705f
+; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
+; SI-SDAG-NEXT:    v_add_f32_e32 v1, v3, v1
+; SI-SDAG-NEXT:    v_exp_f32_e32 v1, v1
+; SI-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
 ; SI-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v0
-; SI-SDAG-NEXT:    v_ldexp_f32_e32 v1, v2, v1
+; SI-SDAG-NEXT:    v_ldexp_f32_e32 v1, v1, v2
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_exp_f32_nnan_ninf_daz:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
 ; SI-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x32a5705f
-; SI-GISEL-NEXT:    v_rndne_f32_e32 v1, v1
 ; SI-GISEL-NEXT:    v_fma_f32 v2, v0, v3, v2
-; SI-GISEL-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; SI-GISEL-NEXT:    v_add_f32_e32 v2, v3, v2
-; SI-GISEL-NEXT:    v_cvt_i32_f32_e32 v1, v1
-; SI-GISEL-NEXT:    v_exp_f32_e32 v2, v2
-; SI-GISEL-NEXT:    v_ldexp_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT:    v_rndne_f32_e32 v3, v1
+; SI-GISEL-NEXT:    v_sub_f32_e32 v1, v1, v3
+; SI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
+; SI-GISEL-NEXT:    v_cvt_i32_f32_e32 v2, v3
+; SI-GISEL-NEXT:    v_exp_f32_e32 v1, v1
+; SI-GISEL-NEXT:    v_ldexp_f32_e32 v1, v1, v2
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0xc2ce8ed0
 ; SI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; SI-GISEL-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc
 ; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_exp_f32_nnan_ninf_daz:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END

 define float @v_exp_f32_nnan_ninf_dynamic(float %in) #1 {
 ; VI-SDAG-LABEL: v_exp_f32_nnan_ninf_dynamic:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-SDAG-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-SDAG-NEXT:    v_sub_f32_e32 v4, v0, v1
 ; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3fb8a000, v1
 ; VI-SDAG-NEXT:    v_mul_f32_e32 v5, 0x39a3b295, v4
-; VI-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8a000
-; VI-SDAG-NEXT:    v_rndne_f32_e32 v2, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v5, 0x3fb8a000, v4
-; VI-SDAG-NEXT:    v_mad_f32 v3, v1, s4, -v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v5, 0x39a3b295, v1
-; VI-SDAG-NEXT:    v_add_f32_e32 v1, v3, v5
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-SDAG-NEXT:    v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT:    v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-SDAG-NEXT:    v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v2, v1
 ; VI-SDAG-NEXT:    v_exp_f32_e32 v1, v1
-; VI-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v2
+; VI-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v3
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
 ; VI-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v0
 ; VI-SDAG-NEXT:    v_ldexp_f32 v1, v1, v2
 ; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
 ; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-GISEL-LABEL: v_exp_f32_nnan_ninf_dynamic:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-GISEL-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-GISEL-NEXT:    v_sub_f32_e32 v2, v0, v1
-; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3fb8a000, v1
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v4, 0x39a3b295, v2
-; VI-GISEL-NEXT:    s_mov_b32 s4, 0x3fb8a000
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x3fb8a000, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
 ; VI-GISEL-NEXT:    v_rndne_f32_e32 v2, v3
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x39a3b295, v1
-; VI-GISEL-NEXT:    v_mad_f32 v1, v1, s4, -v2
-; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v4
+; VI-GISEL-NEXT:    v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v3, v1
 ; VI-GISEL-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; VI-GISEL-NEXT:    v_exp_f32_e32 v1, v1
 ; VI-GISEL-NEXT:    v_ldexp_f32 v1, v1, v2
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0xc2ce8ed0
 ; VI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; VI-GISEL-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc
 ; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-SDAG-LABEL: v_exp_f32_nnan_ninf_dynamic:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
-; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
-; GFX900-SDAG-NEXT:    s_mov_b32 s5, 0x32a5705f
-; GFX900-SDAG-NEXT:    v_rndne_f32_e32 v1, v1
-; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
-; GFX900-SDAG-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; GFX900-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
-; GFX900-SDAG-NEXT:    v_exp_f32_e32 v2, v2
-; GFX900-SDAG-NEXT:    v_cvt_i32_f32_e32 v1, v1
+; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
+; GFX900-SDAG-NEXT:    v_rndne_f32_e32 v2, v1
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v3, v1, v2
+; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x32a5705f
+; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
+; GFX900-SDAG-NEXT:    v_add_f32_e32 v1, v3, v1
+; GFX900-SDAG-NEXT:    v_exp_f32_e32 v1, v1
+; GFX900-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
 ; GFX900-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v0
-; GFX900-SDAG-NEXT:    v_ldexp_f32 v1, v2, v1
+; GFX900-SDAG-NEXT:    v_ldexp_f32 v1, v1, v2
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
 ; GFX900-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-GISEL-LABEL: v_exp_f32_nnan_ninf_dynamic:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-GISEL-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
 ; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x32a5705f
-; GFX900-GISEL-NEXT:    v_rndne_f32_e32 v1, v1
 ; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, v3, v2
-; GFX900-GISEL-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; GFX900-GISEL-NEXT:    v_add_f32_e32 v2, v3, v2
-; GFX900-GISEL-NEXT:    v_cvt_i32_f32_e32 v1, v1
-; GFX900-GISEL-NEXT:    v_exp_f32_e32 v2, v2
-; GFX900-GISEL-NEXT:    v_ldexp_f32 v1, v2, v1
+; GFX900-GISEL-NEXT:    v_rndne_f32_e32 v3, v1
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v1, v1, v3
+; GFX900-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
+; GFX900-GISEL-NEXT:    v_cvt_i32_f32_e32 v2, v3
+; GFX900-GISEL-NEXT:    v_exp_f32_e32 v1, v1
+; GFX900-GISEL-NEXT:    v_ldexp_f32 v1, v1, v2
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0xc2ce8ed0
 ; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-SDAG-LABEL: v_exp_f32_nnan_ninf_dynamic:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
-; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
-; SI-SDAG-NEXT:    s_mov_b32 s5, 0x32a5705f
-; SI-SDAG-NEXT:    v_rndne_f32_e32 v1, v1
-; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
-; SI-SDAG-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; SI-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
-; SI-SDAG-NEXT:    v_exp_f32_e32 v2, v2
-; SI-SDAG-NEXT:    v_cvt_i32_f32_e32 v1, v1
+; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
+; SI-SDAG-NEXT:    v_rndne_f32_e32 v2, v1
+; SI-SDAG-NEXT:    v_sub_f32_e32 v3, v1, v2
+; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; SI-SDAG-NEXT:    s_mov_b32 s4, 0x32a5705f
+; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
+; SI-SDAG-NEXT:    v_add_f32_e32 v1, v3, v1
+; SI-SDAG-NEXT:    v_exp_f32_e32 v1, v1
+; SI-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
 ; SI-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v0
-; SI-SDAG-NEXT:    v_ldexp_f32_e32 v1, v2, v1
+; SI-SDAG-NEXT:    v_ldexp_f32_e32 v1, v1, v2
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_exp_f32_nnan_ninf_dynamic:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
 ; SI-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x32a5705f
-; SI-GISEL-NEXT:    v_rndne_f32_e32 v1, v1
 ; SI-GISEL-NEXT:    v_fma_f32 v2, v0, v3, v2
-; SI-GISEL-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; SI-GISEL-NEXT:    v_add_f32_e32 v2, v3, v2
-; SI-GISEL-NEXT:    v_cvt_i32_f32_e32 v1, v1
-; SI-GISEL-NEXT:    v_exp_f32_e32 v2, v2
-; SI-GISEL-NEXT:    v_ldexp_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT:    v_rndne_f32_e32 v3, v1
+; SI-GISEL-NEXT:    v_sub_f32_e32 v1, v1, v3
+; SI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
+; SI-GISEL-NEXT:    v_cvt_i32_f32_e32 v2, v3
+; SI-GISEL-NEXT:    v_exp_f32_e32 v1, v1
+; SI-GISEL-NEXT:    v_ldexp_f32_e32 v1, v1, v2
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0xc2ce8ed0
 ; SI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; SI-GISEL-NEXT:    v_cndmask_b32_e64 v0, v1, 0, vcc
 ; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_exp_f32_nnan_ninf_dynamic:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END

 define float @v_exp_f32_dynamic_mode(float %in) #1 {
 ; VI-SDAG-LABEL: v_exp_f32_dynamic_mode:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-SDAG-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-SDAG-NEXT:    v_sub_f32_e32 v4, v0, v1
 ; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3fb8a000, v1
 ; VI-SDAG-NEXT:    v_mul_f32_e32 v5, 0x39a3b295, v4
-; VI-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8a000
-; VI-SDAG-NEXT:    v_rndne_f32_e32 v2, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v5, 0x3fb8a000, v4
-; VI-SDAG-NEXT:    v_mad_f32 v3, v1, s4, -v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v5, 0x39a3b295, v1
-; VI-SDAG-NEXT:    v_add_f32_e32 v1, v3, v5
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, 0x3fb8a000, v4
+; VI-SDAG-NEXT:    v_rndne_f32_e32 v3, v2
+; VI-SDAG-NEXT:    v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-SDAG-NEXT:    v_sub_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v2, v1
 ; VI-SDAG-NEXT:    v_exp_f32_e32 v1, v1
-; VI-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v2
+; VI-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v3
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
 ; VI-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v0
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0x42b17218
 ; VI-SDAG-NEXT:    v_ldexp_f32 v1, v1, v2
 ; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; VI-SDAG-NEXT:    v_cmp_nlt_f32_e32 vcc, s4, v0
 ; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
 ; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-GISEL-LABEL: v_exp_f32_dynamic_mode:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-GISEL-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-GISEL-NEXT:    v_sub_f32_e32 v2, v0, v1
-; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3fb8a000, v1
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v4, 0x39a3b295, v2
-; VI-GISEL-NEXT:    s_mov_b32 s4, 0x3fb8a000
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x3fb8a000, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
 ; VI-GISEL-NEXT:    v_rndne_f32_e32 v2, v3
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x39a3b295, v1
-; VI-GISEL-NEXT:    v_mad_f32 v1, v1, s4, -v2
-; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v4
+; VI-GISEL-NEXT:    v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v3, v1
 ; VI-GISEL-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; VI-GISEL-NEXT:    v_exp_f32_e32 v1, v1
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x7f800000
 ; VI-GISEL-NEXT:    v_ldexp_f32 v1, v1, v2
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0xc2ce8ed0
 ; VI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x42b17218
 ; VI-GISEL-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc
 ; VI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v2
 ; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v1, v3, vcc
 ; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-SDAG-LABEL: v_exp_f32_dynamic_mode:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
-; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
-; GFX900-SDAG-NEXT:    s_mov_b32 s5, 0x32a5705f
-; GFX900-SDAG-NEXT:    v_rndne_f32_e32 v1, v1
-; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
-; GFX900-SDAG-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; GFX900-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
-; GFX900-SDAG-NEXT:    v_exp_f32_e32 v2, v2
-; GFX900-SDAG-NEXT:    v_cvt_i32_f32_e32 v1, v1
+; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
+; GFX900-SDAG-NEXT:    v_rndne_f32_e32 v2, v1
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v3, v1, v2
+; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x32a5705f
+; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
+; GFX900-SDAG-NEXT:    v_add_f32_e32 v1, v3, v1
+; GFX900-SDAG-NEXT:    v_exp_f32_e32 v1, v1
+; GFX900-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
 ; GFX900-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v0
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x42b17218
-; GFX900-SDAG-NEXT:    v_ldexp_f32 v1, v2, v1
+; GFX900-SDAG-NEXT:    v_ldexp_f32 v1, v1, v2
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; GFX900-SDAG-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; GFX900-SDAG-NEXT:    v_cmp_nlt_f32_e32 vcc, s4, v0
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
 ; GFX900-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-GISEL-LABEL: v_exp_f32_dynamic_mode:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-GISEL-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
 ; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x32a5705f
-; GFX900-GISEL-NEXT:    v_rndne_f32_e32 v1, v1
 ; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, v3, v2
-; GFX900-GISEL-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; GFX900-GISEL-NEXT:    v_add_f32_e32 v2, v3, v2
-; GFX900-GISEL-NEXT:    v_cvt_i32_f32_e32 v1, v1
-; GFX900-GISEL-NEXT:    v_exp_f32_e32 v2, v2
+; GFX900-GISEL-NEXT:    v_rndne_f32_e32 v3, v1
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v1, v1, v3
+; GFX900-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
+; GFX900-GISEL-NEXT:    v_cvt_i32_f32_e32 v2, v3
+; GFX900-GISEL-NEXT:    v_exp_f32_e32 v1, v1
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x7f800000
-; GFX900-GISEL-NEXT:    v_ldexp_f32 v1, v2, v1
+; GFX900-GISEL-NEXT:    v_ldexp_f32 v1, v1, v2
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0xc2ce8ed0
 ; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x42b17218
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc
 ; GFX900-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v2
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, v1, v3, vcc
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-SDAG-LABEL: v_exp_f32_dynamic_mode:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
-; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
-; SI-SDAG-NEXT:    s_mov_b32 s5, 0x32a5705f
-; SI-SDAG-NEXT:    v_rndne_f32_e32 v1, v1
-; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
-; SI-SDAG-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; SI-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
-; SI-SDAG-NEXT:    v_exp_f32_e32 v2, v2
-; SI-SDAG-NEXT:    v_cvt_i32_f32_e32 v1, v1
+; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
+; SI-SDAG-NEXT:    v_rndne_f32_e32 v2, v1
+; SI-SDAG-NEXT:    v_sub_f32_e32 v3, v1, v2
+; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; SI-SDAG-NEXT:    s_mov_b32 s4, 0x32a5705f
+; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
+; SI-SDAG-NEXT:    v_add_f32_e32 v1, v3, v1
+; SI-SDAG-NEXT:    v_exp_f32_e32 v1, v1
+; SI-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
 ; SI-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v0
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x42b17218
-; SI-SDAG-NEXT:    v_ldexp_f32_e32 v1, v2, v1
+; SI-SDAG-NEXT:    v_ldexp_f32_e32 v1, v1, v2
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; SI-SDAG-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; SI-SDAG-NEXT:    v_cmp_nlt_f32_e32 vcc, s4, v0
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_exp_f32_dynamic_mode:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
 ; SI-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x32a5705f
-; SI-GISEL-NEXT:    v_rndne_f32_e32 v1, v1
 ; SI-GISEL-NEXT:    v_fma_f32 v2, v0, v3, v2
-; SI-GISEL-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; SI-GISEL-NEXT:    v_add_f32_e32 v2, v3, v2
-; SI-GISEL-NEXT:    v_cvt_i32_f32_e32 v1, v1
-; SI-GISEL-NEXT:    v_exp_f32_e32 v2, v2
+; SI-GISEL-NEXT:    v_rndne_f32_e32 v3, v1
+; SI-GISEL-NEXT:    v_sub_f32_e32 v1, v1, v3
+; SI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
+; SI-GISEL-NEXT:    v_cvt_i32_f32_e32 v2, v3
+; SI-GISEL-NEXT:    v_exp_f32_e32 v1, v1
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x7f800000
-; SI-GISEL-NEXT:    v_ldexp_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT:    v_ldexp_f32_e32 v1, v1, v2
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0xc2ce8ed0
 ; SI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x42b17218
 ; SI-GISEL-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc
 ; SI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v2
 ; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v1, v3, vcc
 ; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;

 }
 
 define float @v_exp_f32_from_fpext_math_f16_daz(i16 %src0.i, i16 %src1.i) #0 {
 ; VI-SDAG-LABEL: v_exp_f32_from_fpext_math_f16_daz:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-SDAG-NEXT:    v_add_f16_e32 v0, v0, v1
 ; VI-SDAG-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; VI-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8a000
+; VI-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
 ; VI-SDAG-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-SDAG-NEXT:    v_sub_f32_e32 v2, v0, v1
-; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3fb8a000, v1
 ; VI-SDAG-NEXT:    v_mul_f32_e32 v4, 0x39a3b295, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v4, 0x3fb8a000, v2
-; VI-SDAG-NEXT:    v_rndne_f32_e32 v2, v3
-; VI-SDAG-NEXT:    v_mac_f32_e32 v4, 0x39a3b295, v1
-; VI-SDAG-NEXT:    v_mad_f32 v1, v1, s4, -v2
-; VI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v4
-; VI-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v2
+; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x39a3b295, v1
+; VI-SDAG-NEXT:    v_add_f32_e32 v2, v2, v4
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3fb8a000, v1
+; VI-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT:    v_rndne_f32_e32 v3, v1
+; VI-SDAG-NEXT:    v_sub_f32_e32 v1, v1, v3
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; VI-SDAG-NEXT:    v_exp_f32_e32 v1, v1
-; VI-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
+; VI-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v3
 ; VI-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v0
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0x42b17218
 ; VI-SDAG-NEXT:    v_ldexp_f32 v1, v1, v2
 ; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; VI-SDAG-NEXT:    v_cmp_nlt_f32_e32 vcc, s4, v0
 ; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
 ; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-GISEL-LABEL: v_exp_f32_from_fpext_math_f16_daz:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-GISEL-NEXT:    v_add_f16_e32 v0, v0, v1
 ; VI-GISEL-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; VI-GISEL-NEXT:    s_mov_b32 s4, 0x3fb8a000
 ; VI-GISEL-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-GISEL-NEXT:    v_sub_f32_e32 v2, v0, v1
-; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3fb8a000, v1
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v4, 0x39a3b295, v2
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x3fb8a000, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3fb8a000, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3fb8a000, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v2, v2, v4
+; VI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x39a3b295, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
 ; VI-GISEL-NEXT:    v_rndne_f32_e32 v2, v3
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x39a3b295, v1
-; VI-GISEL-NEXT:    v_mad_f32 v1, v1, s4, -v2
-; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v4
+; VI-GISEL-NEXT:    v_sub_f32_e32 v3, v3, v2
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v3, v1
 ; VI-GISEL-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; VI-GISEL-NEXT:    v_exp_f32_e32 v1, v1
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x7f800000
 ; VI-GISEL-NEXT:    v_ldexp_f32 v1, v1, v2
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0xc2ce8ed0
 ; VI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x42b17218
 ; VI-GISEL-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc
 ; VI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v2
 ; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v1, v3, vcc
 ; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-SDAG-LABEL: v_exp_f32_from_fpext_math_f16_daz:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-SDAG-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX900-SDAG-NEXT:    v_cvt_f32_f16_e32 v1, v0
+; GFX900-SDAG-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
 ; GFX900-SDAG-NEXT:    s_mov_b32 s5, 0x32a5705f
-; GFX900-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3fb8aa3b, v1
-; GFX900-SDAG-NEXT:    v_fma_f32 v3, v1, s4, -v2
-; GFX900-SDAG-NEXT:    v_rndne_f32_e32 v2, v2
-; GFX900-SDAG-NEXT:    v_fma_f32 v3, v1, s5, v3
-; GFX900-SDAG-NEXT:    v_mad_mix_f32 v0, v0, s4, -v2 op_sel_hi:[1,0,0]
-; GFX900-SDAG-NEXT:    v_add_f32_e32 v0, v0, v3
-; GFX900-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v2
-; GFX900-SDAG-NEXT:    v_exp_f32_e32 v0, v0
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
+; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT:    v_rndne_f32_e32 v3, v1
+; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v1, v1, v3
+; GFX900-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v3
+; GFX900-SDAG-NEXT:    v_exp_f32_e32 v1, v1
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
-; GFX900-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v1
+; GFX900-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v0
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x42b17218
-; GFX900-SDAG-NEXT:    v_ldexp_f32 v0, v0, v2
-; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
+; GFX900-SDAG-NEXT:    v_ldexp_f32 v1, v1, v2
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; GFX900-SDAG-NEXT:    v_mov_b32_e32 v2, 0x7f800000
-; GFX900-SDAG-NEXT:    v_cmp_nlt_f32_e32 vcc, s4, v1
-; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX900-SDAG-NEXT:    v_cmp_nlt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
 ; GFX900-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-GISEL-LABEL: v_exp_f32_from_fpext_math_f16_daz:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-GISEL-NEXT:    v_add_f16_e32 v0, v0, v1
-; GFX900-GISEL-NEXT:    v_cvt_f32_f16_e32 v1, v0
+; GFX900-GISEL-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; GFX900-GISEL-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
-; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x32a5705f
-; GFX900-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3fb8aa3b, v1
-; GFX900-GISEL-NEXT:    v_fma_f32 v4, v1, s4, -v3
-; GFX900-GISEL-NEXT:    v_rndne_f32_e32 v3, v3
-; GFX900-GISEL-NEXT:    v_fma_f32 v2, v1, v2, v4
-; GFX900-GISEL-NEXT:    v_mad_mix_f32 v0, v0, s4, -v3 op_sel_hi:[1,0,0]
-; GFX900-GISEL-NEXT:    v_add_f32_e32 v0, v0, v2
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x32a5705f
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3fb8aa3b, v0
+; GFX900-GISEL-NEXT:    v_fma_f32 v3, v0, s4, -v2
+; GFX900-GISEL-NEXT:    v_fma_f32 v1, v0, v1, v3
+; GFX900-GISEL-NEXT:    v_rndne_f32_e32 v3, v2
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v2, v2, v3
+; GFX900-GISEL-NEXT:    v_add_f32_e32 v1, v2, v1
 ; GFX900-GISEL-NEXT:    v_cvt_i32_f32_e32 v2, v3
-; GFX900-GISEL-NEXT:    v_exp_f32_e32 v0, v0
+; GFX900-GISEL-NEXT:    v_exp_f32_e32 v1, v1
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x7f800000
-; GFX900-GISEL-NEXT:    v_ldexp_f32 v0, v0, v2
+; GFX900-GISEL-NEXT:    v_ldexp_f32 v1, v1, v2
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0xc2ce8ed0
-; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v1, v2
+; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x42b17218
-; GFX900-GISEL-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc
-; GFX900-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v2
-; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc
+; GFX900-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v2
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, v1, v3, vcc
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-SDAG-LABEL: v_exp_f32_from_fpext_math_f16_daz:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; SI-SDAG-NEXT:    v_cvt_f32_f16_e32 v1, v1
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
-; SI-SDAG-NEXT:    s_mov_b32 s5, 0x32a5705f
 ; SI-SDAG-NEXT:    v_add_f32_e32 v0, v0, v1
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3fb8aa3b, v0
 ; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
-; SI-SDAG-NEXT:    v_rndne_f32_e32 v1, v1
-; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
-; SI-SDAG-NEXT:    v_mad_f32 v3, v0, s4, -v1
-; SI-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
-; SI-SDAG-NEXT:    v_exp_f32_e32 v2, v2
-; SI-SDAG-NEXT:    v_cvt_i32_f32_e32 v1, v1
+; SI-SDAG-NEXT:    s_mov_b32 s4, 0x32a5705f
+; SI-SDAG-NEXT:    v_rndne_f32_e32 v3, v1
+; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, v2
+; SI-SDAG-NEXT:    v_sub_f32_e32 v1, v1, v3
+; SI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT:    v_exp_f32_e32 v1, v1
+; SI-SDAG-NEXT:    v_cvt_i32_f32_e32 v2, v3
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0xc2ce8ed0
 ; SI-SDAG-NEXT:    v_cmp_ngt_f32_e32 vcc, s4, v0
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x42b17218
-; SI-SDAG-NEXT:    v_ldexp_f32_e32 v1, v2, v1
+; SI-SDAG-NEXT:    v_ldexp_f32_e32 v1, v1, v2
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; SI-SDAG-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; SI-SDAG-NEXT:    v_cmp_nlt_f32_e32 vcc, s4, v0
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_exp_f32_from_fpext_math_f16_daz:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; SI-GISEL-NEXT:    v_cvt_f32_f16_e32 v1, v1
 ; SI-GISEL-NEXT:    s_mov_b32 s4, 0x3fb8aa3b
-; SI-GISEL-NEXT:    v_mov_b32_e32 v4, 0x42b17218
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v5, 0x7f800000
 ; SI-GISEL-NEXT:    v_add_f32_e32 v0, v0, v1
 ; SI-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x32a5705f
 ; SI-GISEL-NEXT:    v_cvt_f32_f16_e32 v0, v0
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3fb8aa3b, v0
 ; SI-GISEL-NEXT:    v_fma_f32 v3, v0, s4, -v2
-; SI-GISEL-NEXT:    v_rndne_f32_e32 v2, v2
+; SI-GISEL-NEXT:    v_rndne_f32_e32 v4, v2
 ; SI-GISEL-NEXT:    v_fma_f32 v1, v0, v1, v3
-; SI-GISEL-NEXT:    v_mad_f32 v3, v0, s4, -v2
-; SI-GISEL-NEXT:    v_add_f32_e32 v1, v3, v1
-; SI-GISEL-NEXT:    v_cvt_i32_f32_e32 v2, v2
+; SI-GISEL-NEXT:    v_sub_f32_e32 v2, v2, v4
+; SI-GISEL-NEXT:    v_add_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT:    v_cvt_i32_f32_e32 v3, v4
 ; SI-GISEL-NEXT:    v_exp_f32_e32 v1, v1
-; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0xc2ce8ed0
-; SI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v3
-; SI-GISEL-NEXT:    v_ldexp_f32_e32 v1, v1, v2
+; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0xc2ce8ed0
+; SI-GISEL-NEXT:    v_mov_b32_e32 v4, 0x42b17218
+; SI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v2
+; SI-GISEL-NEXT:    v_ldexp_f32_e32 v1, v1, v3
 ; SI-GISEL-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc
 ; SI-GISEL-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v4
 ; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v1, v5, vcc
 ; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; R600-LABEL: v_exp_f32_from_fpext_math_f16_daz:
 ; R600:       ; %bb.0:
 ; R600-NEXT:    CF_END

llvm/test/CodeGen/AMDGPU/llvm.log.ll

 ; SI-SDAG-LABEL: v_log_f32_daz:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3f317217
 ; SI-SDAG-NEXT:    s_mov_b32 s5, 0x3377d1cf
 ; SI-SDAG-NEXT:    s_mov_b32 s6, 0x7f800000
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
-; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
-; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s5, v1
-; SI-SDAG-NEXT:    v_mac_f32_e32 v1, 0x3f317217, v0
+; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
+; SI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; SI-SDAG-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s6
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_log_f32_daz:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; SI-GISEL-NEXT:    s_mov_b32 s4, 0x3f317217
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x3377d1cf
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3f317217, v0
-; SI-GISEL-NEXT:    v_fma_f32 v3, v0, s4, -v3
-; SI-GISEL-NEXT:    v_fma_f32 v1, v0, v1, v3
-; SI-GISEL-NEXT:    v_mac_f32_e32 v1, 0x3f317217, v0
+; SI-GISEL-NEXT:    v_fma_f32 v4, v0, s4, -v3
+; SI-GISEL-NEXT:    v_fma_f32 v1, v0, v1, v4
+; SI-GISEL-NEXT:    v_add_f32_e32 v1, v3, v1
 ; SI-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
 ; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-SDAG-LABEL: v_log_f32_daz:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0x7f800000
 ; VI-SDAG-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
-; VI-SDAG-NEXT:    v_sub_f32_e32 v2, v0, v1
-; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3805fdf4, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x3805fdf4, v1
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x3f317000, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x3f317000, v1
+; VI-SDAG-NEXT:    v_sub_f32_e32 v3, v0, v1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3805fdf4, v1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, 0x3805fdf4, v3
+; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3f317000, v3
+; VI-SDAG-NEXT:    v_add_f32_e32 v2, v2, v4
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; VI-SDAG-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s4
-; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-GISEL-LABEL: v_log_f32_daz:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-GISEL-NEXT:    v_log_f32_e32 v0, v0
-; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x7f800000
-; VI-GISEL-NEXT:    v_and_b32_e32 v2, 0xfffff000, v0
-; VI-GISEL-NEXT:    v_sub_f32_e32 v3, v0, v2
-; VI-GISEL-NEXT:    v_mul_f32_e32 v4, 0x3805fdf4, v3
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x3805fdf4, v2
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x3f317000, v3
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x3f317000, v2
-; VI-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v1
-; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
+; VI-GISEL-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT:    v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3805fdf4, v1
+; VI-GISEL-NEXT:    v_mul_f32_e32 v4, 0x3805fdf4, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3f317000, v2
+; VI-GISEL-NEXT:    v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-SDAG-LABEL: v_log_f32_daz:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3f317217
 ; GFX900-SDAG-NEXT:    s_mov_b32 s5, 0x3377d1cf
 ; GFX900-SDAG-NEXT:    s_mov_b32 s6, 0x7f800000
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
-; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s5, v1
-; GFX900-SDAG-NEXT:    v_mac_f32_e32 v1, 0x3f317217, v0
+; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
+; GFX900-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s6
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; GFX900-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-GISEL-LABEL: v_log_f32_daz:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-GISEL-NEXT:    s_mov_b32 s4, 0x3f317217
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x3377d1cf
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3f317217, v0
-; GFX900-GISEL-NEXT:    v_fma_f32 v3, v0, s4, -v3
-; GFX900-GISEL-NEXT:    v_fma_f32 v1, v0, v1, v3
-; GFX900-GISEL-NEXT:    v_mac_f32_e32 v1, 0x3f317217, v0
+; GFX900-GISEL-NEXT:    v_fma_f32 v4, v0, s4, -v3
+; GFX900-GISEL-NEXT:    v_fma_f32 v1, v0, v1, v4
+; GFX900-GISEL-NEXT:    v_add_f32_e32 v1, v3, v1
 ; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX1100-SDAG-LABEL: v_log_f32_daz:
 ; GFX1100-SDAG:       ; %bb.0:
 ; GFX1100-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX1100-SDAG-NEXT:    s_waitcnt_vscnt null, 0x0

 ; SI-SDAG-LABEL: v_log_f32_nnan_daz:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3f317217
 ; SI-SDAG-NEXT:    s_mov_b32 s5, 0x3377d1cf
 ; SI-SDAG-NEXT:    s_mov_b32 s6, 0x7f800000
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
-; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
-; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s5, v1
-; SI-SDAG-NEXT:    v_mac_f32_e32 v1, 0x3f317217, v0
+; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
+; SI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; SI-SDAG-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s6
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_log_f32_nnan_daz:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; SI-GISEL-NEXT:    s_mov_b32 s4, 0x3f317217
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x3377d1cf
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3f317217, v0
-; SI-GISEL-NEXT:    v_fma_f32 v3, v0, s4, -v3
-; SI-GISEL-NEXT:    v_fma_f32 v1, v0, v1, v3
-; SI-GISEL-NEXT:    v_mac_f32_e32 v1, 0x3f317217, v0
+; SI-GISEL-NEXT:    v_fma_f32 v4, v0, s4, -v3
+; SI-GISEL-NEXT:    v_fma_f32 v1, v0, v1, v4
+; SI-GISEL-NEXT:    v_add_f32_e32 v1, v3, v1
 ; SI-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
 ; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-SDAG-LABEL: v_log_f32_nnan_daz:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0x7f800000
 ; VI-SDAG-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
-; VI-SDAG-NEXT:    v_sub_f32_e32 v2, v0, v1
-; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3805fdf4, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x3805fdf4, v1
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x3f317000, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x3f317000, v1
+; VI-SDAG-NEXT:    v_sub_f32_e32 v3, v0, v1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3805fdf4, v1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, 0x3805fdf4, v3
+; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3f317000, v3
+; VI-SDAG-NEXT:    v_add_f32_e32 v2, v2, v4
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; VI-SDAG-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s4
-; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-GISEL-LABEL: v_log_f32_nnan_daz:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-GISEL-NEXT:    v_log_f32_e32 v0, v0
-; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x7f800000
-; VI-GISEL-NEXT:    v_and_b32_e32 v2, 0xfffff000, v0
-; VI-GISEL-NEXT:    v_sub_f32_e32 v3, v0, v2
-; VI-GISEL-NEXT:    v_mul_f32_e32 v4, 0x3805fdf4, v3
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x3805fdf4, v2
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x3f317000, v3
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x3f317000, v2
-; VI-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v1
-; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
+; VI-GISEL-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT:    v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3805fdf4, v1
+; VI-GISEL-NEXT:    v_mul_f32_e32 v4, 0x3805fdf4, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3f317000, v2
+; VI-GISEL-NEXT:    v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-SDAG-LABEL: v_log_f32_nnan_daz:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3f317217
 ; GFX900-SDAG-NEXT:    s_mov_b32 s5, 0x3377d1cf
 ; GFX900-SDAG-NEXT:    s_mov_b32 s6, 0x7f800000
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
-; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s5, v1
-; GFX900-SDAG-NEXT:    v_mac_f32_e32 v1, 0x3f317217, v0
+; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
+; GFX900-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s6
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; GFX900-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-GISEL-LABEL: v_log_f32_nnan_daz:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-GISEL-NEXT:    s_mov_b32 s4, 0x3f317217
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x3377d1cf
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3f317217, v0
-; GFX900-GISEL-NEXT:    v_fma_f32 v3, v0, s4, -v3
-; GFX900-GISEL-NEXT:    v_fma_f32 v1, v0, v1, v3
-; GFX900-GISEL-NEXT:    v_mac_f32_e32 v1, 0x3f317217, v0
+; GFX900-GISEL-NEXT:    v_fma_f32 v4, v0, s4, -v3
+; GFX900-GISEL-NEXT:    v_fma_f32 v1, v0, v1, v4
+; GFX900-GISEL-NEXT:    v_add_f32_e32 v1, v3, v1
 ; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX1100-SDAG-LABEL: v_log_f32_nnan_daz:
 ; GFX1100-SDAG:       ; %bb.0:
 ; GFX1100-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX1100-SDAG-NEXT:    s_waitcnt_vscnt null, 0x0

 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x800000
 ; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; SI-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; SI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3f317217
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
-; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3377d1cf
-; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
+; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, v2
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x7f800000
-; SI-SDAG-NEXT:    v_mac_f32_e32 v1, 0x3f317217, v0
+; SI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; SI-SDAG-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, s4
 ; SI-SDAG-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x41b17218
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; SI-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_log_f32_nnan_dynamic:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; SI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
 ; SI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; SI-GISEL-NEXT:    s_mov_b32 s4, 0x3f317217
-; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x3377d1cf
+; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x3377d1cf
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
-; SI-GISEL-NEXT:    v_fma_f32 v1, v0, s4, -v1
-; SI-GISEL-NEXT:    v_fma_f32 v1, v0, v2, v1
+; SI-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; SI-GISEL-NEXT:    v_fma_f32 v2, v0, v3, v2
+; SI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
-; SI-GISEL-NEXT:    v_mac_f32_e32 v1, 0x3f317217, v0
 ; SI-GISEL-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, v2
 ; SI-GISEL-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x41b17218
 ; SI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; SI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-SDAG-LABEL: v_log_f32_nnan_dynamic:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0x800000
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; VI-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
 ; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
 ; VI-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; VI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0x7f800000
 ; VI-SDAG-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-SDAG-NEXT:    v_sub_f32_e32 v2, v0, v1
-; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3805fdf4, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x3805fdf4, v1
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x3f317000, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x3f317000, v1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3f317000, v2
+; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3805fdf4, v2
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, 0x3805fdf4, v1
+; VI-SDAG-NEXT:    v_add_f32_e32 v2, v4, v2
+; VI-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; VI-SDAG-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; VI-SDAG-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x41b17218
-; VI-SDAG-NEXT:    v_cndmask_b32_e64 v0, v0, v3, s[4:5]
 ; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; VI-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-GISEL-LABEL: v_log_f32_nnan_dynamic:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; VI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
 ; VI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; VI-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; VI-GISEL-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-GISEL-NEXT:    v_sub_f32_e32 v2, v0, v1
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3805fdf4, v2
-; VI-GISEL-NEXT:    v_mac_f32_e32 v3, 0x3805fdf4, v1
-; VI-GISEL-NEXT:    v_mac_f32_e32 v3, 0x3f317000, v2
-; VI-GISEL-NEXT:    v_mac_f32_e32 v3, 0x3f317000, v1
-; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x7f800000
-; VI-GISEL-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, v1
+; VI-GISEL-NEXT:    v_mul_f32_e32 v4, 0x3805fdf4, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v3, v4, v3
+; VI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3f317000, v2
+; VI-GISEL-NEXT:    v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; VI-GISEL-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x41b17218
-; VI-GISEL-NEXT:    v_cndmask_b32_e64 v0, v0, v3, s[4:5]
 ; VI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; VI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-SDAG-LABEL: v_log_f32_nnan_dynamic:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x800000
 ; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; GFX900-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; GFX900-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3f317217
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3377d1cf
-; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
+; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, v2
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x7f800000
-; GFX900-SDAG-NEXT:    v_mac_f32_e32 v1, 0x3f317217, v0
+; GFX900-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, s4
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x41b17218
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; GFX900-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GFX900-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-GISEL-LABEL: v_log_f32_nnan_dynamic:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-GISEL-NEXT:    s_mov_b32 s4, 0x3f317217
-; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x3377d1cf
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x3377d1cf
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX900-GISEL-NEXT:    v_fma_f32 v1, v0, s4, -v1
-; GFX900-GISEL-NEXT:    v_fma_f32 v1, v0, v2, v1
+; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, v3, v2
+; GFX900-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
-; GFX900-GISEL-NEXT:    v_mac_f32_e32 v1, 0x3f317217, v0
 ; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, v2
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x41b17218
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; GFX900-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX1100-SDAG-LABEL: v_log_f32_nnan_dynamic:

 ; SI-SDAG-LABEL: v_log_f32_ninf_daz:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3f317217
 ; SI-SDAG-NEXT:    s_mov_b32 s5, 0x3377d1cf
 ; SI-SDAG-NEXT:    s_mov_b32 s6, 0x7f800000
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
-; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
-; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s5, v1
-; SI-SDAG-NEXT:    v_mac_f32_e32 v1, 0x3f317217, v0
+; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
+; SI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; SI-SDAG-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s6
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_log_f32_ninf_daz:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; SI-GISEL-NEXT:    s_mov_b32 s4, 0x3f317217
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x3377d1cf
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3f317217, v0
-; SI-GISEL-NEXT:    v_fma_f32 v3, v0, s4, -v3
-; SI-GISEL-NEXT:    v_fma_f32 v1, v0, v1, v3
-; SI-GISEL-NEXT:    v_mac_f32_e32 v1, 0x3f317217, v0
+; SI-GISEL-NEXT:    v_fma_f32 v4, v0, s4, -v3
+; SI-GISEL-NEXT:    v_fma_f32 v1, v0, v1, v4
+; SI-GISEL-NEXT:    v_add_f32_e32 v1, v3, v1
 ; SI-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
 ; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-SDAG-LABEL: v_log_f32_ninf_daz:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0x7f800000
 ; VI-SDAG-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
-; VI-SDAG-NEXT:    v_sub_f32_e32 v2, v0, v1
-; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3805fdf4, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x3805fdf4, v1
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x3f317000, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x3f317000, v1
+; VI-SDAG-NEXT:    v_sub_f32_e32 v3, v0, v1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3805fdf4, v1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, 0x3805fdf4, v3
+; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3f317000, v3
+; VI-SDAG-NEXT:    v_add_f32_e32 v2, v2, v4
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; VI-SDAG-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s4
-; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-GISEL-LABEL: v_log_f32_ninf_daz:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-GISEL-NEXT:    v_log_f32_e32 v0, v0
-; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x7f800000
-; VI-GISEL-NEXT:    v_and_b32_e32 v2, 0xfffff000, v0
-; VI-GISEL-NEXT:    v_sub_f32_e32 v3, v0, v2
-; VI-GISEL-NEXT:    v_mul_f32_e32 v4, 0x3805fdf4, v3
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x3805fdf4, v2
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x3f317000, v3
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x3f317000, v2
-; VI-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v1
-; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
+; VI-GISEL-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT:    v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3805fdf4, v1
+; VI-GISEL-NEXT:    v_mul_f32_e32 v4, 0x3805fdf4, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3f317000, v2
+; VI-GISEL-NEXT:    v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-SDAG-LABEL: v_log_f32_ninf_daz:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3f317217
 ; GFX900-SDAG-NEXT:    s_mov_b32 s5, 0x3377d1cf
 ; GFX900-SDAG-NEXT:    s_mov_b32 s6, 0x7f800000
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
-; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s5, v1
-; GFX900-SDAG-NEXT:    v_mac_f32_e32 v1, 0x3f317217, v0
+; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
+; GFX900-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s6
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; GFX900-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-GISEL-LABEL: v_log_f32_ninf_daz:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-GISEL-NEXT:    s_mov_b32 s4, 0x3f317217
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x3377d1cf
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3f317217, v0
-; GFX900-GISEL-NEXT:    v_fma_f32 v3, v0, s4, -v3
-; GFX900-GISEL-NEXT:    v_fma_f32 v1, v0, v1, v3
-; GFX900-GISEL-NEXT:    v_mac_f32_e32 v1, 0x3f317217, v0
+; GFX900-GISEL-NEXT:    v_fma_f32 v4, v0, s4, -v3
+; GFX900-GISEL-NEXT:    v_fma_f32 v1, v0, v1, v4
+; GFX900-GISEL-NEXT:    v_add_f32_e32 v1, v3, v1
 ; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX1100-SDAG-LABEL: v_log_f32_ninf_daz:
 ; GFX1100-SDAG:       ; %bb.0:
 ; GFX1100-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX1100-SDAG-NEXT:    s_waitcnt_vscnt null, 0x0

 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x800000
 ; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; SI-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; SI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3f317217
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
-; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3377d1cf
-; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
+; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, v2
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x7f800000
-; SI-SDAG-NEXT:    v_mac_f32_e32 v1, 0x3f317217, v0
+; SI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; SI-SDAG-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, s4
 ; SI-SDAG-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x41b17218
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; SI-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_log_f32_ninf_dynamic:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; SI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
 ; SI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; SI-GISEL-NEXT:    s_mov_b32 s4, 0x3f317217
-; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x3377d1cf
+; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x3377d1cf
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
-; SI-GISEL-NEXT:    v_fma_f32 v1, v0, s4, -v1
-; SI-GISEL-NEXT:    v_fma_f32 v1, v0, v2, v1
+; SI-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; SI-GISEL-NEXT:    v_fma_f32 v2, v0, v3, v2
+; SI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
-; SI-GISEL-NEXT:    v_mac_f32_e32 v1, 0x3f317217, v0
 ; SI-GISEL-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, v2
 ; SI-GISEL-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x41b17218
 ; SI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; SI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-SDAG-LABEL: v_log_f32_ninf_dynamic:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0x800000
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; VI-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
 ; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
 ; VI-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; VI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0x7f800000
 ; VI-SDAG-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-SDAG-NEXT:    v_sub_f32_e32 v2, v0, v1
-; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3805fdf4, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x3805fdf4, v1
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x3f317000, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x3f317000, v1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3f317000, v2
+; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3805fdf4, v2
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, 0x3805fdf4, v1
+; VI-SDAG-NEXT:    v_add_f32_e32 v2, v4, v2
+; VI-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; VI-SDAG-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; VI-SDAG-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x41b17218
-; VI-SDAG-NEXT:    v_cndmask_b32_e64 v0, v0, v3, s[4:5]
 ; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; VI-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-GISEL-LABEL: v_log_f32_ninf_dynamic:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; VI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
 ; VI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; VI-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; VI-GISEL-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-GISEL-NEXT:    v_sub_f32_e32 v2, v0, v1
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3805fdf4, v2
-; VI-GISEL-NEXT:    v_mac_f32_e32 v3, 0x3805fdf4, v1
-; VI-GISEL-NEXT:    v_mac_f32_e32 v3, 0x3f317000, v2
-; VI-GISEL-NEXT:    v_mac_f32_e32 v3, 0x3f317000, v1
-; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x7f800000
-; VI-GISEL-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, v1
+; VI-GISEL-NEXT:    v_mul_f32_e32 v4, 0x3805fdf4, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v3, v4, v3
+; VI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3f317000, v2
+; VI-GISEL-NEXT:    v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; VI-GISEL-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x41b17218
-; VI-GISEL-NEXT:    v_cndmask_b32_e64 v0, v0, v3, s[4:5]
 ; VI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; VI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-SDAG-LABEL: v_log_f32_ninf_dynamic:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x800000
 ; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; GFX900-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; GFX900-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3f317217
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3377d1cf
-; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
+; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, v2
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x7f800000
-; GFX900-SDAG-NEXT:    v_mac_f32_e32 v1, 0x3f317217, v0
+; GFX900-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, s4
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x41b17218
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; GFX900-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GFX900-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-GISEL-LABEL: v_log_f32_ninf_dynamic:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-GISEL-NEXT:    s_mov_b32 s4, 0x3f317217
-; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x3377d1cf
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x3377d1cf
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX900-GISEL-NEXT:    v_fma_f32 v1, v0, s4, -v1
-; GFX900-GISEL-NEXT:    v_fma_f32 v1, v0, v2, v1
+; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, v3, v2
+; GFX900-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
-; GFX900-GISEL-NEXT:    v_mac_f32_e32 v1, 0x3f317217, v0
 ; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, v2
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x41b17218
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; GFX900-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX1100-SDAG-LABEL: v_log_f32_ninf_dynamic:
; CM-NEXT:    PAD
   %result = call nnan ninf float @llvm.log.f32(float %in)
   ret float %result
 }
 
 define float @v_log_f32_nnan_ninf_daz(float %in) #0 {
 ; SI-SDAG-LABEL: v_log_f32_nnan_ninf_daz:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SDAG-NEXT:    v_log_f32_e32 v1, v0
+; SI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3f317217
-; SI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317217, v1
-; SI-SDAG-NEXT:    v_fma_f32 v0, v1, s4, -v0
+; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
+; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3377d1cf
-; SI-SDAG-NEXT:    v_fma_f32 v0, v1, s4, v0
-; SI-SDAG-NEXT:    v_mac_f32_e32 v0, 0x3f317217, v1
+; SI-SDAG-NEXT:    v_fma_f32 v0, v0, s4, v2
+; SI-SDAG-NEXT:    v_add_f32_e32 v0, v1, v0
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_log_f32_nnan_ninf_daz:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-GISEL-NEXT:    v_log_f32_e32 v1, v0
+; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; SI-GISEL-NEXT:    s_mov_b32 s4, 0x3f317217
-; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x3377d1cf
-; SI-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317217, v1
-; SI-GISEL-NEXT:    v_fma_f32 v0, v1, s4, -v0
-; SI-GISEL-NEXT:    v_fma_f32 v0, v1, v2, v0
-; SI-GISEL-NEXT:    v_mac_f32_e32 v0, 0x3f317217, v1
+; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x3377d1cf
+; SI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
+; SI-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; SI-GISEL-NEXT:    v_fma_f32 v0, v0, v3, v2
+; SI-GISEL-NEXT:    v_add_f32_e32 v0, v1, v0
 ; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-LABEL: v_log_f32_nnan_ninf_daz:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_log_f32_e32 v0, v0
 ; VI-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT:    v_sub_f32_e32 v2, v0, v1
-; VI-NEXT:    v_mul_f32_e32 v0, 0x3805fdf4, v2
-; VI-NEXT:    v_mac_f32_e32 v0, 0x3805fdf4, v1
-; VI-NEXT:    v_mac_f32_e32 v0, 0x3f317000, v2
-; VI-NEXT:    v_mac_f32_e32 v0, 0x3f317000, v1
+; VI-NEXT:    v_sub_f32_e32 v0, v0, v1
+; VI-NEXT:    v_mul_f32_e32 v2, 0x3805fdf4, v1
+; VI-NEXT:    v_mul_f32_e32 v3, 0x3805fdf4, v0
+; VI-NEXT:    v_mul_f32_e32 v0, 0x3f317000, v0
+; VI-NEXT:    v_add_f32_e32 v2, v2, v3
+; VI-NEXT:    v_add_f32_e32 v0, v0, v2
+; VI-NEXT:    v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-NEXT:    v_add_f32_e32 v0, v1, v0
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-SDAG-LABEL: v_log_f32_nnan_ninf_daz:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v1, v0
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3f317217
-; GFX900-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3f317217, v1
-; GFX900-SDAG-NEXT:    v_fma_f32 v0, v1, s4, -v0
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3377d1cf
-; GFX900-SDAG-NEXT:    v_fma_f32 v0, v1, s4, v0
-; GFX900-SDAG-NEXT:    v_mac_f32_e32 v0, 0x3f317217, v1
+; GFX900-SDAG-NEXT:    v_fma_f32 v0, v0, s4, v2
+; GFX900-SDAG-NEXT:    v_add_f32_e32 v0, v1, v0
 ; GFX900-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-GISEL-LABEL: v_log_f32_nnan_ninf_daz:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v1, v0
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-GISEL-NEXT:    s_mov_b32 s4, 0x3f317217
-; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x3377d1cf
-; GFX900-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317217, v1
-; GFX900-GISEL-NEXT:    v_fma_f32 v0, v1, s4, -v0
-; GFX900-GISEL-NEXT:    v_fma_f32 v0, v1, v2, v0
-; GFX900-GISEL-NEXT:    v_mac_f32_e32 v0, 0x3f317217, v1
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x3377d1cf
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; GFX900-GISEL-NEXT:    v_fma_f32 v0, v0, v3, v2
+; GFX900-GISEL-NEXT:    v_add_f32_e32 v0, v1, v0
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX1100-SDAG-LABEL: v_log_f32_nnan_ninf_daz:
 ; GFX1100-SDAG:       ; %bb.0:
 ; GFX1100-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX1100-SDAG-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX1100-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; GFX1100-SDAG-NEXT:    s_waitcnt_depctr 0xfff

 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x800000
 ; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; SI-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; SI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3f317217
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
-; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3377d1cf
-; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
-; SI-SDAG-NEXT:    v_mac_f32_e32 v1, 0x3f317217, v0
-; SI-SDAG-NEXT:    v_mov_b32_e32 v0, 0x41b17218
-; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; SI-SDAG-NEXT:    v_sub_f32_e32 v0, v1, v0
+; SI-SDAG-NEXT:    v_fma_f32 v0, v0, s4, v2
+; SI-SDAG-NEXT:    v_add_f32_e32 v0, v1, v0
+; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x41b17218
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_log_f32_nnan_ninf_dynamic:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; SI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
 ; SI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; SI-GISEL-NEXT:    s_mov_b32 s4, 0x3f317217
-; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x3377d1cf
+; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x3377d1cf
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
-; SI-GISEL-NEXT:    v_fma_f32 v1, v0, s4, -v1
-; SI-GISEL-NEXT:    v_fma_f32 v1, v0, v2, v1
-; SI-GISEL-NEXT:    v_mac_f32_e32 v1, 0x3f317217, v0
-; SI-GISEL-NEXT:    v_mov_b32_e32 v0, 0x41b17218
-; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; SI-GISEL-NEXT:    v_sub_f32_e32 v0, v1, v0
+; SI-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; SI-GISEL-NEXT:    v_fma_f32 v0, v0, v3, v2
+; SI-GISEL-NEXT:    v_add_f32_e32 v0, v1, v0
+; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x41b17218
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-SDAG-LABEL: v_log_f32_nnan_ninf_dynamic:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0x800000
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; VI-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
 ; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
 ; VI-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; VI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; VI-SDAG-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
-; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3805fdf4, v0
-; VI-SDAG-NEXT:    v_mac_f32_e32 v2, 0x3805fdf4, v1
-; VI-SDAG-NEXT:    v_mac_f32_e32 v2, 0x3f317000, v0
-; VI-SDAG-NEXT:    v_mov_b32_e32 v0, 0x41b17218
-; VI-SDAG-NEXT:    v_mac_f32_e32 v2, 0x3f317000, v1
-; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; VI-SDAG-NEXT:    v_sub_f32_e32 v0, v2, v0
+; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3f317000, v0
+; VI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3805fdf4, v0
+; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3805fdf4, v1
+; VI-SDAG-NEXT:    v_add_f32_e32 v0, v3, v0
+; VI-SDAG-NEXT:    v_add_f32_e32 v0, v2, v0
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-SDAG-NEXT:    v_add_f32_e32 v0, v1, v0
+; VI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x41b17218
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-GISEL-LABEL: v_log_f32_nnan_ninf_dynamic:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; VI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
 ; VI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; VI-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; VI-GISEL-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3805fdf4, v0
-; VI-GISEL-NEXT:    v_mac_f32_e32 v2, 0x3805fdf4, v1
-; VI-GISEL-NEXT:    v_mac_f32_e32 v2, 0x3f317000, v0
-; VI-GISEL-NEXT:    v_mov_b32_e32 v0, 0x41b17218
-; VI-GISEL-NEXT:    v_mac_f32_e32 v2, 0x3f317000, v1
-; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; VI-GISEL-NEXT:    v_sub_f32_e32 v0, v2, v0
+; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3805fdf4, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v2, v3, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3f317000, v0
+; VI-GISEL-NEXT:    v_add_f32_e32 v0, v0, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v0, v1, v0
+; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x41b17218
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-SDAG-LABEL: v_log_f32_nnan_ninf_dynamic:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x800000
 ; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; GFX900-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; GFX900-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3f317217
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3377d1cf
-; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
-; GFX900-SDAG-NEXT:    v_mac_f32_e32 v1, 0x3f317217, v0
-; GFX900-SDAG-NEXT:    v_mov_b32_e32 v0, 0x41b17218
-; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; GFX900-SDAG-NEXT:    v_sub_f32_e32 v0, v1, v0
+; GFX900-SDAG-NEXT:    v_fma_f32 v0, v0, s4, v2
+; GFX900-SDAG-NEXT:    v_add_f32_e32 v0, v1, v0
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x41b17218
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GFX900-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-GISEL-LABEL: v_log_f32_nnan_ninf_dynamic:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-GISEL-NEXT:    s_mov_b32 s4, 0x3f317217
-; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x3377d1cf
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x3377d1cf
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX900-GISEL-NEXT:    v_fma_f32 v1, v0, s4, -v1
-; GFX900-GISEL-NEXT:    v_fma_f32 v1, v0, v2, v1
-; GFX900-GISEL-NEXT:    v_mac_f32_e32 v1, 0x3f317217, v0
-; GFX900-GISEL-NEXT:    v_mov_b32_e32 v0, 0x41b17218
-; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; GFX900-GISEL-NEXT:    v_sub_f32_e32 v0, v1, v0
+; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; GFX900-GISEL-NEXT:    v_fma_f32 v0, v0, v3, v2
+; GFX900-GISEL-NEXT:    v_add_f32_e32 v0, v1, v0
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x41b17218
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX1100-SDAG-LABEL: v_log_f32_nnan_ninf_dynamic:
 ; GFX1100-SDAG:       ; %bb.0:
 ; GFX1100-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX1100-SDAG-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX1100-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
 ; GFX1100-SDAG-NEXT:    v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo

 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x800000
 ; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; SI-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; SI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3f317217
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
-; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3377d1cf
-; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
+; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, v2
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x7f800000
-; SI-SDAG-NEXT:    v_mac_f32_e32 v1, 0x3f317217, v0
+; SI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; SI-SDAG-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, s4
 ; SI-SDAG-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x41b17218
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; SI-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_log_f32_dynamic_mode:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; SI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
 ; SI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; SI-GISEL-NEXT:    s_mov_b32 s4, 0x3f317217
-; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x3377d1cf
+; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x3377d1cf
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
-; SI-GISEL-NEXT:    v_fma_f32 v1, v0, s4, -v1
-; SI-GISEL-NEXT:    v_fma_f32 v1, v0, v2, v1
+; SI-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; SI-GISEL-NEXT:    v_fma_f32 v2, v0, v3, v2
+; SI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
-; SI-GISEL-NEXT:    v_mac_f32_e32 v1, 0x3f317217, v0
 ; SI-GISEL-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, v2
 ; SI-GISEL-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x41b17218
 ; SI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; SI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-SDAG-LABEL: v_log_f32_dynamic_mode:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0x800000
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; VI-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
 ; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
 ; VI-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; VI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0x7f800000
 ; VI-SDAG-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-SDAG-NEXT:    v_sub_f32_e32 v2, v0, v1
-; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3805fdf4, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x3805fdf4, v1
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x3f317000, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x3f317000, v1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3f317000, v2
+; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3805fdf4, v2
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, 0x3805fdf4, v1
+; VI-SDAG-NEXT:    v_add_f32_e32 v2, v4, v2
+; VI-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; VI-SDAG-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; VI-SDAG-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x41b17218
-; VI-SDAG-NEXT:    v_cndmask_b32_e64 v0, v0, v3, s[4:5]
 ; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; VI-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-GISEL-LABEL: v_log_f32_dynamic_mode:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; VI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
 ; VI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; VI-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; VI-GISEL-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-GISEL-NEXT:    v_sub_f32_e32 v2, v0, v1
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3805fdf4, v2
-; VI-GISEL-NEXT:    v_mac_f32_e32 v3, 0x3805fdf4, v1
-; VI-GISEL-NEXT:    v_mac_f32_e32 v3, 0x3f317000, v2
-; VI-GISEL-NEXT:    v_mac_f32_e32 v3, 0x3f317000, v1
-; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x7f800000
-; VI-GISEL-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, v1
+; VI-GISEL-NEXT:    v_mul_f32_e32 v4, 0x3805fdf4, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v3, v4, v3
+; VI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3f317000, v2
+; VI-GISEL-NEXT:    v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; VI-GISEL-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x41b17218
-; VI-GISEL-NEXT:    v_cndmask_b32_e64 v0, v0, v3, s[4:5]
 ; VI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; VI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-SDAG-LABEL: v_log_f32_dynamic_mode:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x800000
 ; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; GFX900-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; GFX900-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3f317217
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3377d1cf
-; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
+; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, v2
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x7f800000
-; GFX900-SDAG-NEXT:    v_mac_f32_e32 v1, 0x3f317217, v0
+; GFX900-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, s4
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x41b17218
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; GFX900-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GFX900-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-GISEL-LABEL: v_log_f32_dynamic_mode:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-GISEL-NEXT:    s_mov_b32 s4, 0x3f317217
-; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x3377d1cf
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x3377d1cf
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX900-GISEL-NEXT:    v_fma_f32 v1, v0, s4, -v1
-; GFX900-GISEL-NEXT:    v_fma_f32 v1, v0, v2, v1
+; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, v3, v2
+; GFX900-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
-; GFX900-GISEL-NEXT:    v_mac_f32_e32 v1, 0x3f317217, v0
 ; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, v2
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x41b17218
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; GFX900-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX1100-SDAG-LABEL: v_log_f32_dynamic_mode:

llvm/test/CodeGen/AMDGPU/llvm.log10.ll

 ; SI-SDAG-LABEL: v_log10_f32_daz:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3e9a209a
 ; SI-SDAG-NEXT:    s_mov_b32 s5, 0x3284fbcf
 ; SI-SDAG-NEXT:    s_mov_b32 s6, 0x7f800000
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
-; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
-; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s5, v1
-; SI-SDAG-NEXT:    v_mac_f32_e32 v1, 0x3e9a209a, v0
+; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
+; SI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; SI-SDAG-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s6
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_log10_f32_daz:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; SI-GISEL-NEXT:    s_mov_b32 s4, 0x3e9a209a
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x3284fbcf
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3e9a209a, v0
-; SI-GISEL-NEXT:    v_fma_f32 v3, v0, s4, -v3
-; SI-GISEL-NEXT:    v_fma_f32 v1, v0, v1, v3
-; SI-GISEL-NEXT:    v_mac_f32_e32 v1, 0x3e9a209a, v0
+; SI-GISEL-NEXT:    v_fma_f32 v4, v0, s4, -v3
+; SI-GISEL-NEXT:    v_fma_f32 v1, v0, v1, v4
+; SI-GISEL-NEXT:    v_add_f32_e32 v1, v3, v1
 ; SI-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
 ; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-SDAG-LABEL: v_log10_f32_daz:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0x7f800000
 ; VI-SDAG-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
-; VI-SDAG-NEXT:    v_sub_f32_e32 v2, v0, v1
-; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x369a84fb, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x369a84fb, v1
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x3e9a2000, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x3e9a2000, v1
+; VI-SDAG-NEXT:    v_sub_f32_e32 v3, v0, v1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x369a84fb, v1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, 0x369a84fb, v3
+; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3e9a2000, v3
+; VI-SDAG-NEXT:    v_add_f32_e32 v2, v2, v4
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; VI-SDAG-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s4
-; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-GISEL-LABEL: v_log10_f32_daz:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-GISEL-NEXT:    v_log_f32_e32 v0, v0
-; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x7f800000
-; VI-GISEL-NEXT:    v_and_b32_e32 v2, 0xfffff000, v0
-; VI-GISEL-NEXT:    v_sub_f32_e32 v3, v0, v2
-; VI-GISEL-NEXT:    v_mul_f32_e32 v4, 0x369a84fb, v3
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x369a84fb, v2
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x3e9a2000, v3
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x3e9a2000, v2
-; VI-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v1
-; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
+; VI-GISEL-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT:    v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x369a84fb, v1
+; VI-GISEL-NEXT:    v_mul_f32_e32 v4, 0x369a84fb, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3e9a2000, v2
+; VI-GISEL-NEXT:    v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-SDAG-LABEL: v_log10_f32_daz:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3e9a209a
 ; GFX900-SDAG-NEXT:    s_mov_b32 s5, 0x3284fbcf
 ; GFX900-SDAG-NEXT:    s_mov_b32 s6, 0x7f800000
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
-; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s5, v1
-; GFX900-SDAG-NEXT:    v_mac_f32_e32 v1, 0x3e9a209a, v0
+; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
+; GFX900-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s6
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; GFX900-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-GISEL-LABEL: v_log10_f32_daz:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-GISEL-NEXT:    s_mov_b32 s4, 0x3e9a209a
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x3284fbcf
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3e9a209a, v0
-; GFX900-GISEL-NEXT:    v_fma_f32 v3, v0, s4, -v3
-; GFX900-GISEL-NEXT:    v_fma_f32 v1, v0, v1, v3
-; GFX900-GISEL-NEXT:    v_mac_f32_e32 v1, 0x3e9a209a, v0
+; GFX900-GISEL-NEXT:    v_fma_f32 v4, v0, s4, -v3
+; GFX900-GISEL-NEXT:    v_fma_f32 v1, v0, v1, v4
+; GFX900-GISEL-NEXT:    v_add_f32_e32 v1, v3, v1
 ; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX1100-SDAG-LABEL: v_log10_f32_daz:
 ; GFX1100-SDAG:       ; %bb.0:
 ; GFX1100-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX1100-SDAG-NEXT:    s_waitcnt_vscnt null, 0x0

 ; SI-SDAG-LABEL: v_log10_f32_nnan_daz:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3e9a209a
 ; SI-SDAG-NEXT:    s_mov_b32 s5, 0x3284fbcf
 ; SI-SDAG-NEXT:    s_mov_b32 s6, 0x7f800000
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
-; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
-; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s5, v1
-; SI-SDAG-NEXT:    v_mac_f32_e32 v1, 0x3e9a209a, v0
+; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
+; SI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; SI-SDAG-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s6
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_log10_f32_nnan_daz:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; SI-GISEL-NEXT:    s_mov_b32 s4, 0x3e9a209a
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x3284fbcf
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3e9a209a, v0
-; SI-GISEL-NEXT:    v_fma_f32 v3, v0, s4, -v3
-; SI-GISEL-NEXT:    v_fma_f32 v1, v0, v1, v3
-; SI-GISEL-NEXT:    v_mac_f32_e32 v1, 0x3e9a209a, v0
+; SI-GISEL-NEXT:    v_fma_f32 v4, v0, s4, -v3
+; SI-GISEL-NEXT:    v_fma_f32 v1, v0, v1, v4
+; SI-GISEL-NEXT:    v_add_f32_e32 v1, v3, v1
 ; SI-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
 ; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-SDAG-LABEL: v_log10_f32_nnan_daz:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0x7f800000
 ; VI-SDAG-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
-; VI-SDAG-NEXT:    v_sub_f32_e32 v2, v0, v1
-; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x369a84fb, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x369a84fb, v1
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x3e9a2000, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x3e9a2000, v1
+; VI-SDAG-NEXT:    v_sub_f32_e32 v3, v0, v1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x369a84fb, v1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, 0x369a84fb, v3
+; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3e9a2000, v3
+; VI-SDAG-NEXT:    v_add_f32_e32 v2, v2, v4
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; VI-SDAG-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s4
-; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-GISEL-LABEL: v_log10_f32_nnan_daz:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-GISEL-NEXT:    v_log_f32_e32 v0, v0
-; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x7f800000
-; VI-GISEL-NEXT:    v_and_b32_e32 v2, 0xfffff000, v0
-; VI-GISEL-NEXT:    v_sub_f32_e32 v3, v0, v2
-; VI-GISEL-NEXT:    v_mul_f32_e32 v4, 0x369a84fb, v3
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x369a84fb, v2
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x3e9a2000, v3
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x3e9a2000, v2
-; VI-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v1
-; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
+; VI-GISEL-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT:    v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x369a84fb, v1
+; VI-GISEL-NEXT:    v_mul_f32_e32 v4, 0x369a84fb, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3e9a2000, v2
+; VI-GISEL-NEXT:    v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-SDAG-LABEL: v_log10_f32_nnan_daz:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3e9a209a
 ; GFX900-SDAG-NEXT:    s_mov_b32 s5, 0x3284fbcf
 ; GFX900-SDAG-NEXT:    s_mov_b32 s6, 0x7f800000
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
-; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s5, v1
-; GFX900-SDAG-NEXT:    v_mac_f32_e32 v1, 0x3e9a209a, v0
+; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
+; GFX900-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s6
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; GFX900-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-GISEL-LABEL: v_log10_f32_nnan_daz:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-GISEL-NEXT:    s_mov_b32 s4, 0x3e9a209a
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x3284fbcf
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3e9a209a, v0
-; GFX900-GISEL-NEXT:    v_fma_f32 v3, v0, s4, -v3
-; GFX900-GISEL-NEXT:    v_fma_f32 v1, v0, v1, v3
-; GFX900-GISEL-NEXT:    v_mac_f32_e32 v1, 0x3e9a209a, v0
+; GFX900-GISEL-NEXT:    v_fma_f32 v4, v0, s4, -v3
+; GFX900-GISEL-NEXT:    v_fma_f32 v1, v0, v1, v4
+; GFX900-GISEL-NEXT:    v_add_f32_e32 v1, v3, v1
 ; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX1100-SDAG-LABEL: v_log10_f32_nnan_daz:
 ; GFX1100-SDAG:       ; %bb.0:
 ; GFX1100-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX1100-SDAG-NEXT:    s_waitcnt_vscnt null, 0x0

 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x800000
 ; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; SI-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; SI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3e9a209a
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
-; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3284fbcf
-; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
+; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, v2
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x7f800000
-; SI-SDAG-NEXT:    v_mac_f32_e32 v1, 0x3e9a209a, v0
+; SI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; SI-SDAG-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, s4
 ; SI-SDAG-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x411a209b
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; SI-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_log10_f32_nnan_dynamic:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; SI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
 ; SI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; SI-GISEL-NEXT:    s_mov_b32 s4, 0x3e9a209a
-; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x3284fbcf
+; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x3284fbcf
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
-; SI-GISEL-NEXT:    v_fma_f32 v1, v0, s4, -v1
-; SI-GISEL-NEXT:    v_fma_f32 v1, v0, v2, v1
+; SI-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; SI-GISEL-NEXT:    v_fma_f32 v2, v0, v3, v2
+; SI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
-; SI-GISEL-NEXT:    v_mac_f32_e32 v1, 0x3e9a209a, v0
 ; SI-GISEL-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, v2
 ; SI-GISEL-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x411a209b
 ; SI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; SI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-SDAG-LABEL: v_log10_f32_nnan_dynamic:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0x800000
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; VI-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
 ; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
 ; VI-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; VI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0x7f800000
 ; VI-SDAG-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-SDAG-NEXT:    v_sub_f32_e32 v2, v0, v1
-; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x369a84fb, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x369a84fb, v1
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x3e9a2000, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x3e9a2000, v1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3e9a2000, v2
+; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x369a84fb, v2
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, 0x369a84fb, v1
+; VI-SDAG-NEXT:    v_add_f32_e32 v2, v4, v2
+; VI-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; VI-SDAG-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; VI-SDAG-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x411a209b
-; VI-SDAG-NEXT:    v_cndmask_b32_e64 v0, v0, v3, s[4:5]
 ; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; VI-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-GISEL-LABEL: v_log10_f32_nnan_dynamic:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; VI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
 ; VI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; VI-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; VI-GISEL-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-GISEL-NEXT:    v_sub_f32_e32 v2, v0, v1
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x369a84fb, v2
-; VI-GISEL-NEXT:    v_mac_f32_e32 v3, 0x369a84fb, v1
-; VI-GISEL-NEXT:    v_mac_f32_e32 v3, 0x3e9a2000, v2
-; VI-GISEL-NEXT:    v_mac_f32_e32 v3, 0x3e9a2000, v1
-; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x7f800000
-; VI-GISEL-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, v1
+; VI-GISEL-NEXT:    v_mul_f32_e32 v4, 0x369a84fb, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v3, v4, v3
+; VI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3e9a2000, v2
+; VI-GISEL-NEXT:    v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; VI-GISEL-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x411a209b
-; VI-GISEL-NEXT:    v_cndmask_b32_e64 v0, v0, v3, s[4:5]
 ; VI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; VI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-SDAG-LABEL: v_log10_f32_nnan_dynamic:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x800000
 ; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; GFX900-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; GFX900-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3e9a209a
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3284fbcf
-; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
+; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, v2
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x7f800000
-; GFX900-SDAG-NEXT:    v_mac_f32_e32 v1, 0x3e9a209a, v0
+; GFX900-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, s4
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x411a209b
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; GFX900-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GFX900-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-GISEL-LABEL: v_log10_f32_nnan_dynamic:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-GISEL-NEXT:    s_mov_b32 s4, 0x3e9a209a
-; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x3284fbcf
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x3284fbcf
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX900-GISEL-NEXT:    v_fma_f32 v1, v0, s4, -v1
-; GFX900-GISEL-NEXT:    v_fma_f32 v1, v0, v2, v1
+; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, v3, v2
+; GFX900-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
-; GFX900-GISEL-NEXT:    v_mac_f32_e32 v1, 0x3e9a209a, v0
 ; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, v2
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x411a209b
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; GFX900-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX1100-SDAG-LABEL: v_log10_f32_nnan_dynamic:

 ; SI-SDAG-LABEL: v_log10_f32_ninf_daz:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3e9a209a
 ; SI-SDAG-NEXT:    s_mov_b32 s5, 0x3284fbcf
 ; SI-SDAG-NEXT:    s_mov_b32 s6, 0x7f800000
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
-; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
-; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s5, v1
-; SI-SDAG-NEXT:    v_mac_f32_e32 v1, 0x3e9a209a, v0
+; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
+; SI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; SI-SDAG-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s6
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_log10_f32_ninf_daz:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; SI-GISEL-NEXT:    s_mov_b32 s4, 0x3e9a209a
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x3284fbcf
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3e9a209a, v0
-; SI-GISEL-NEXT:    v_fma_f32 v3, v0, s4, -v3
-; SI-GISEL-NEXT:    v_fma_f32 v1, v0, v1, v3
-; SI-GISEL-NEXT:    v_mac_f32_e32 v1, 0x3e9a209a, v0
+; SI-GISEL-NEXT:    v_fma_f32 v4, v0, s4, -v3
+; SI-GISEL-NEXT:    v_fma_f32 v1, v0, v1, v4
+; SI-GISEL-NEXT:    v_add_f32_e32 v1, v3, v1
 ; SI-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
 ; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-SDAG-LABEL: v_log10_f32_ninf_daz:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0x7f800000
 ; VI-SDAG-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
-; VI-SDAG-NEXT:    v_sub_f32_e32 v2, v0, v1
-; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x369a84fb, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x369a84fb, v1
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x3e9a2000, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x3e9a2000, v1
+; VI-SDAG-NEXT:    v_sub_f32_e32 v3, v0, v1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x369a84fb, v1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, 0x369a84fb, v3
+; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3e9a2000, v3
+; VI-SDAG-NEXT:    v_add_f32_e32 v2, v2, v4
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; VI-SDAG-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s4
-; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-GISEL-LABEL: v_log10_f32_ninf_daz:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-GISEL-NEXT:    v_log_f32_e32 v0, v0
-; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x7f800000
-; VI-GISEL-NEXT:    v_and_b32_e32 v2, 0xfffff000, v0
-; VI-GISEL-NEXT:    v_sub_f32_e32 v3, v0, v2
-; VI-GISEL-NEXT:    v_mul_f32_e32 v4, 0x369a84fb, v3
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x369a84fb, v2
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x3e9a2000, v3
-; VI-GISEL-NEXT:    v_mac_f32_e32 v4, 0x3e9a2000, v2
-; VI-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v1
-; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
+; VI-GISEL-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
+; VI-GISEL-NEXT:    v_sub_f32_e32 v2, v0, v1
+; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x369a84fb, v1
+; VI-GISEL-NEXT:    v_mul_f32_e32 v4, 0x369a84fb, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3e9a2000, v2
+; VI-GISEL-NEXT:    v_add_f32_e32 v3, v3, v4
+; VI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-SDAG-LABEL: v_log10_f32_ninf_daz:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3e9a209a
 ; GFX900-SDAG-NEXT:    s_mov_b32 s5, 0x3284fbcf
 ; GFX900-SDAG-NEXT:    s_mov_b32 s6, 0x7f800000
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
-; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s5, v1
-; GFX900-SDAG-NEXT:    v_mac_f32_e32 v1, 0x3e9a209a, v0
+; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s5, v2
+; GFX900-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, s6
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; GFX900-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-GISEL-LABEL: v_log10_f32_ninf_daz:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-GISEL-NEXT:    s_mov_b32 s4, 0x3e9a209a
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x3284fbcf
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v3, 0x3e9a209a, v0
-; GFX900-GISEL-NEXT:    v_fma_f32 v3, v0, s4, -v3
-; GFX900-GISEL-NEXT:    v_fma_f32 v1, v0, v1, v3
-; GFX900-GISEL-NEXT:    v_mac_f32_e32 v1, 0x3e9a209a, v0
+; GFX900-GISEL-NEXT:    v_fma_f32 v4, v0, s4, -v3
+; GFX900-GISEL-NEXT:    v_fma_f32 v1, v0, v1, v4
+; GFX900-GISEL-NEXT:    v_add_f32_e32 v1, v3, v1
 ; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e64 vcc, |v0|, v2
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX1100-SDAG-LABEL: v_log10_f32_ninf_daz:
 ; GFX1100-SDAG:       ; %bb.0:
 ; GFX1100-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX1100-SDAG-NEXT:    s_waitcnt_vscnt null, 0x0

 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x800000
 ; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; SI-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; SI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3e9a209a
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
-; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3284fbcf
-; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
+; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, v2
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x7f800000
-; SI-SDAG-NEXT:    v_mac_f32_e32 v1, 0x3e9a209a, v0
+; SI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; SI-SDAG-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, s4
 ; SI-SDAG-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x411a209b
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; SI-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_log10_f32_ninf_dynamic:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; SI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
 ; SI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; SI-GISEL-NEXT:    s_mov_b32 s4, 0x3e9a209a
-; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x3284fbcf
+; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x3284fbcf
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
-; SI-GISEL-NEXT:    v_fma_f32 v1, v0, s4, -v1
-; SI-GISEL-NEXT:    v_fma_f32 v1, v0, v2, v1
+; SI-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; SI-GISEL-NEXT:    v_fma_f32 v2, v0, v3, v2
+; SI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
-; SI-GISEL-NEXT:    v_mac_f32_e32 v1, 0x3e9a209a, v0
 ; SI-GISEL-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, v2
 ; SI-GISEL-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x411a209b
 ; SI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; SI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-SDAG-LABEL: v_log10_f32_ninf_dynamic:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0x800000
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; VI-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
 ; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
 ; VI-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; VI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0x7f800000
 ; VI-SDAG-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-SDAG-NEXT:    v_sub_f32_e32 v2, v0, v1
-; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x369a84fb, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x369a84fb, v1
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x3e9a2000, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x3e9a2000, v1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3e9a2000, v2
+; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x369a84fb, v2
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, 0x369a84fb, v1
+; VI-SDAG-NEXT:    v_add_f32_e32 v2, v4, v2
+; VI-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; VI-SDAG-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; VI-SDAG-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x411a209b
-; VI-SDAG-NEXT:    v_cndmask_b32_e64 v0, v0, v3, s[4:5]
 ; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; VI-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-GISEL-LABEL: v_log10_f32_ninf_dynamic:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; VI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
 ; VI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; VI-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; VI-GISEL-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-GISEL-NEXT:    v_sub_f32_e32 v2, v0, v1
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x369a84fb, v2
-; VI-GISEL-NEXT:    v_mac_f32_e32 v3, 0x369a84fb, v1
-; VI-GISEL-NEXT:    v_mac_f32_e32 v3, 0x3e9a2000, v2
-; VI-GISEL-NEXT:    v_mac_f32_e32 v3, 0x3e9a2000, v1
-; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x7f800000
-; VI-GISEL-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, v1
+; VI-GISEL-NEXT:    v_mul_f32_e32 v4, 0x369a84fb, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v3, v4, v3
+; VI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3e9a2000, v2
+; VI-GISEL-NEXT:    v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; VI-GISEL-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x411a209b
-; VI-GISEL-NEXT:    v_cndmask_b32_e64 v0, v0, v3, s[4:5]
 ; VI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; VI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-SDAG-LABEL: v_log10_f32_ninf_dynamic:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x800000
 ; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; GFX900-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; GFX900-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3e9a209a
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3284fbcf
-; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
+; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, v2
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x7f800000
-; GFX900-SDAG-NEXT:    v_mac_f32_e32 v1, 0x3e9a209a, v0
+; GFX900-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, s4
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x411a209b
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; GFX900-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GFX900-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-GISEL-LABEL: v_log10_f32_ninf_dynamic:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-GISEL-NEXT:    s_mov_b32 s4, 0x3e9a209a
-; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x3284fbcf
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x3284fbcf
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX900-GISEL-NEXT:    v_fma_f32 v1, v0, s4, -v1
-; GFX900-GISEL-NEXT:    v_fma_f32 v1, v0, v2, v1
+; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, v3, v2
+; GFX900-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
-; GFX900-GISEL-NEXT:    v_mac_f32_e32 v1, 0x3e9a209a, v0
 ; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, v2
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x411a209b
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; GFX900-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX1100-SDAG-LABEL: v_log10_f32_ninf_dynamic:
; CM-NEXT:    PAD
   %result = call nnan ninf float @llvm.log10.f32(float %in)
   ret float %result
 }
 
 define float @v_log10_f32_nnan_ninf_daz(float %in) #0 {
 ; SI-SDAG-LABEL: v_log10_f32_nnan_ninf_daz:
 ; SI-SDAG:       ; %bb.0:
 ; SI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SDAG-NEXT:    v_log_f32_e32 v1, v0
+; SI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3e9a209a
-; SI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209a, v1
-; SI-SDAG-NEXT:    v_fma_f32 v0, v1, s4, -v0
+; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
+; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3284fbcf
-; SI-SDAG-NEXT:    v_fma_f32 v0, v1, s4, v0
-; SI-SDAG-NEXT:    v_mac_f32_e32 v0, 0x3e9a209a, v1
+; SI-SDAG-NEXT:    v_fma_f32 v0, v0, s4, v2
+; SI-SDAG-NEXT:    v_add_f32_e32 v0, v1, v0
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_log10_f32_nnan_ninf_daz:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-GISEL-NEXT:    v_log_f32_e32 v1, v0
+; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; SI-GISEL-NEXT:    s_mov_b32 s4, 0x3e9a209a
-; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x3284fbcf
-; SI-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a209a, v1
-; SI-GISEL-NEXT:    v_fma_f32 v0, v1, s4, -v0
-; SI-GISEL-NEXT:    v_fma_f32 v0, v1, v2, v0
-; SI-GISEL-NEXT:    v_mac_f32_e32 v0, 0x3e9a209a, v1
+; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x3284fbcf
+; SI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
+; SI-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; SI-GISEL-NEXT:    v_fma_f32 v0, v0, v3, v2
+; SI-GISEL-NEXT:    v_add_f32_e32 v0, v1, v0
 ; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-LABEL: v_log10_f32_nnan_ninf_daz:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-NEXT:    v_log_f32_e32 v0, v0
 ; VI-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT:    v_sub_f32_e32 v2, v0, v1
-; VI-NEXT:    v_mul_f32_e32 v0, 0x369a84fb, v2
-; VI-NEXT:    v_mac_f32_e32 v0, 0x369a84fb, v1
-; VI-NEXT:    v_mac_f32_e32 v0, 0x3e9a2000, v2
-; VI-NEXT:    v_mac_f32_e32 v0, 0x3e9a2000, v1
+; VI-NEXT:    v_sub_f32_e32 v0, v0, v1
+; VI-NEXT:    v_mul_f32_e32 v2, 0x369a84fb, v1
+; VI-NEXT:    v_mul_f32_e32 v3, 0x369a84fb, v0
+; VI-NEXT:    v_mul_f32_e32 v0, 0x3e9a2000, v0
+; VI-NEXT:    v_add_f32_e32 v2, v2, v3
+; VI-NEXT:    v_add_f32_e32 v0, v0, v2
+; VI-NEXT:    v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-NEXT:    v_add_f32_e32 v0, v1, v0
 ; VI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-SDAG-LABEL: v_log10_f32_nnan_ninf_daz:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-SDAG-NEXT:    v_log_f32_e32 v1, v0
+; GFX900-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3e9a209a
-; GFX900-SDAG-NEXT:    v_mul_f32_e32 v0, 0x3e9a209a, v1
-; GFX900-SDAG-NEXT:    v_fma_f32 v0, v1, s4, -v0
+; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3284fbcf
-; GFX900-SDAG-NEXT:    v_fma_f32 v0, v1, s4, v0
-; GFX900-SDAG-NEXT:    v_mac_f32_e32 v0, 0x3e9a209a, v1
+; GFX900-SDAG-NEXT:    v_fma_f32 v0, v0, s4, v2
+; GFX900-SDAG-NEXT:    v_add_f32_e32 v0, v1, v0
 ; GFX900-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-GISEL-LABEL: v_log10_f32_nnan_ninf_daz:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-GISEL-NEXT:    v_log_f32_e32 v1, v0
+; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-GISEL-NEXT:    s_mov_b32 s4, 0x3e9a209a
-; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x3284fbcf
-; GFX900-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a209a, v1
-; GFX900-GISEL-NEXT:    v_fma_f32 v0, v1, s4, -v0
-; GFX900-GISEL-NEXT:    v_fma_f32 v0, v1, v2, v0
-; GFX900-GISEL-NEXT:    v_mac_f32_e32 v0, 0x3e9a209a, v1
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x3284fbcf
+; GFX900-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; GFX900-GISEL-NEXT:    v_fma_f32 v0, v0, v3, v2
+; GFX900-GISEL-NEXT:    v_add_f32_e32 v0, v1, v0
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX1100-SDAG-LABEL: v_log10_f32_nnan_ninf_daz:
 ; GFX1100-SDAG:       ; %bb.0:
 ; GFX1100-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX1100-SDAG-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX1100-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; GFX1100-SDAG-NEXT:    s_waitcnt_depctr 0xfff

 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x800000
 ; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; SI-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; SI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3e9a209a
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
-; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3284fbcf
-; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
-; SI-SDAG-NEXT:    v_mac_f32_e32 v1, 0x3e9a209a, v0
-; SI-SDAG-NEXT:    v_mov_b32_e32 v0, 0x411a209b
-; SI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; SI-SDAG-NEXT:    v_sub_f32_e32 v0, v1, v0
+; SI-SDAG-NEXT:    v_fma_f32 v0, v0, s4, v2
+; SI-SDAG-NEXT:    v_add_f32_e32 v0, v1, v0
+; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x411a209b
+; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_log10_f32_nnan_ninf_dynamic:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; SI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
 ; SI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; SI-GISEL-NEXT:    s_mov_b32 s4, 0x3e9a209a
-; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x3284fbcf
+; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x3284fbcf
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
-; SI-GISEL-NEXT:    v_fma_f32 v1, v0, s4, -v1
-; SI-GISEL-NEXT:    v_fma_f32 v1, v0, v2, v1
-; SI-GISEL-NEXT:    v_mac_f32_e32 v1, 0x3e9a209a, v0
-; SI-GISEL-NEXT:    v_mov_b32_e32 v0, 0x411a209b
-; SI-GISEL-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; SI-GISEL-NEXT:    v_sub_f32_e32 v0, v1, v0
+; SI-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; SI-GISEL-NEXT:    v_fma_f32 v0, v0, v3, v2
+; SI-GISEL-NEXT:    v_add_f32_e32 v0, v1, v0
+; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x411a209b
+; SI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-SDAG-LABEL: v_log10_f32_nnan_ninf_dynamic:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0x800000
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; VI-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
 ; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
 ; VI-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; VI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; VI-SDAG-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
-; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x369a84fb, v0
-; VI-SDAG-NEXT:    v_mac_f32_e32 v2, 0x369a84fb, v1
-; VI-SDAG-NEXT:    v_mac_f32_e32 v2, 0x3e9a2000, v0
-; VI-SDAG-NEXT:    v_mov_b32_e32 v0, 0x411a209b
-; VI-SDAG-NEXT:    v_mac_f32_e32 v2, 0x3e9a2000, v1
-; VI-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; VI-SDAG-NEXT:    v_sub_f32_e32 v0, v2, v0
+; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x3e9a2000, v0
+; VI-SDAG-NEXT:    v_mul_f32_e32 v0, 0x369a84fb, v0
+; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x369a84fb, v1
+; VI-SDAG-NEXT:    v_add_f32_e32 v0, v3, v0
+; VI-SDAG-NEXT:    v_add_f32_e32 v0, v2, v0
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-SDAG-NEXT:    v_add_f32_e32 v0, v1, v0
+; VI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x411a209b
+; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-GISEL-LABEL: v_log10_f32_nnan_ninf_dynamic:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; VI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
 ; VI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; VI-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; VI-GISEL-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x369a84fb, v0
-; VI-GISEL-NEXT:    v_mac_f32_e32 v2, 0x369a84fb, v1
-; VI-GISEL-NEXT:    v_mac_f32_e32 v2, 0x3e9a2000, v0
-; VI-GISEL-NEXT:    v_mov_b32_e32 v0, 0x411a209b
-; VI-GISEL-NEXT:    v_mac_f32_e32 v2, 0x3e9a2000, v1
-; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; VI-GISEL-NEXT:    v_sub_f32_e32 v0, v2, v0
+; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x369a84fb, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v2, v3, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v0, 0x3e9a2000, v0
+; VI-GISEL-NEXT:    v_add_f32_e32 v0, v0, v2
+; VI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v0, v1, v0
+; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x411a209b
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-SDAG-LABEL: v_log10_f32_nnan_ninf_dynamic:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x800000
 ; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; GFX900-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; GFX900-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3e9a209a
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3284fbcf
-; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
-; GFX900-SDAG-NEXT:    v_mac_f32_e32 v1, 0x3e9a209a, v0
-; GFX900-SDAG-NEXT:    v_mov_b32_e32 v0, 0x411a209b
-; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; GFX900-SDAG-NEXT:    v_sub_f32_e32 v0, v1, v0
+; GFX900-SDAG-NEXT:    v_fma_f32 v0, v0, s4, v2
+; GFX900-SDAG-NEXT:    v_add_f32_e32 v0, v1, v0
+; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x411a209b
+; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GFX900-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-GISEL-LABEL: v_log10_f32_nnan_ninf_dynamic:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-GISEL-NEXT:    s_mov_b32 s4, 0x3e9a209a
-; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x3284fbcf
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x3284fbcf
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX900-GISEL-NEXT:    v_fma_f32 v1, v0, s4, -v1
-; GFX900-GISEL-NEXT:    v_fma_f32 v1, v0, v2, v1
-; GFX900-GISEL-NEXT:    v_mac_f32_e32 v1, 0x3e9a209a, v0
-; GFX900-GISEL-NEXT:    v_mov_b32_e32 v0, 0x411a209b
-; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; GFX900-GISEL-NEXT:    v_sub_f32_e32 v0, v1, v0
+; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; GFX900-GISEL-NEXT:    v_fma_f32 v0, v0, v3, v2
+; GFX900-GISEL-NEXT:    v_add_f32_e32 v0, v1, v0
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x411a209b
+; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX1100-SDAG-LABEL: v_log10_f32_nnan_ninf_dynamic:
 ; GFX1100-SDAG:       ; %bb.0:
 ; GFX1100-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX1100-SDAG-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX1100-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
 ; GFX1100-SDAG-NEXT:    v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo

 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x800000
 ; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; SI-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; SI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3e9a209a
 ; SI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
-; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x3284fbcf
-; SI-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
+; SI-SDAG-NEXT:    v_fma_f32 v2, v0, s4, v2
 ; SI-SDAG-NEXT:    s_mov_b32 s4, 0x7f800000
-; SI-SDAG-NEXT:    v_mac_f32_e32 v1, 0x3e9a209a, v0
+; SI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; SI-SDAG-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, s4
 ; SI-SDAG-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; SI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x411a209b
 ; SI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; SI-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; SI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; SI-GISEL-LABEL: v_log10_f32_dynamic_mode:
 ; SI-GISEL:       ; %bb.0:
 ; SI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; SI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
 ; SI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; SI-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; SI-GISEL-NEXT:    s_mov_b32 s4, 0x3e9a209a
-; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x3284fbcf
+; SI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x3284fbcf
 ; SI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
-; SI-GISEL-NEXT:    v_fma_f32 v1, v0, s4, -v1
-; SI-GISEL-NEXT:    v_fma_f32 v1, v0, v2, v1
+; SI-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; SI-GISEL-NEXT:    v_fma_f32 v2, v0, v3, v2
+; SI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
-; SI-GISEL-NEXT:    v_mac_f32_e32 v1, 0x3e9a209a, v0
 ; SI-GISEL-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, v2
 ; SI-GISEL-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; SI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x411a209b
 ; SI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; SI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; SI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-SDAG-LABEL: v_log10_f32_dynamic_mode:
 ; VI-SDAG:       ; %bb.0:
 ; VI-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0x800000
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; VI-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
 ; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
 ; VI-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; VI-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; VI-SDAG-NEXT:    s_mov_b32 s4, 0x7f800000
 ; VI-SDAG-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-SDAG-NEXT:    v_sub_f32_e32 v2, v0, v1
-; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x369a84fb, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x369a84fb, v1
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x3e9a2000, v2
-; VI-SDAG-NEXT:    v_mac_f32_e32 v3, 0x3e9a2000, v1
+; VI-SDAG-NEXT:    v_mul_f32_e32 v3, 0x3e9a2000, v2
+; VI-SDAG-NEXT:    v_mul_f32_e32 v2, 0x369a84fb, v2
+; VI-SDAG-NEXT:    v_mul_f32_e32 v4, 0x369a84fb, v1
+; VI-SDAG-NEXT:    v_add_f32_e32 v2, v4, v2
+; VI-SDAG-NEXT:    v_add_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; VI-SDAG-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; VI-SDAG-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; VI-SDAG-NEXT:    v_mov_b32_e32 v1, 0x411a209b
-; VI-SDAG-NEXT:    v_cndmask_b32_e64 v0, v0, v3, s[4:5]
 ; VI-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; VI-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; VI-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; VI-GISEL-LABEL: v_log10_f32_dynamic_mode:
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; VI-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
 ; VI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; VI-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; VI-GISEL-NEXT:    v_and_b32_e32 v1, 0xfffff000, v0
 ; VI-GISEL-NEXT:    v_sub_f32_e32 v2, v0, v1
 ; VI-GISEL-NEXT:    v_mul_f32_e32 v3, 0x369a84fb, v2
-; VI-GISEL-NEXT:    v_mac_f32_e32 v3, 0x369a84fb, v1
-; VI-GISEL-NEXT:    v_mac_f32_e32 v3, 0x3e9a2000, v2
-; VI-GISEL-NEXT:    v_mac_f32_e32 v3, 0x3e9a2000, v1
-; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x7f800000
-; VI-GISEL-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, v1
+; VI-GISEL-NEXT:    v_mul_f32_e32 v4, 0x369a84fb, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v3, v4, v3
+; VI-GISEL-NEXT:    v_mul_f32_e32 v2, 0x3e9a2000, v2
+; VI-GISEL-NEXT:    v_add_f32_e32 v2, v2, v3
+; VI-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
+; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
+; VI-GISEL-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; VI-GISEL-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; VI-GISEL-NEXT:    v_mov_b32_e32 v1, 0x411a209b
-; VI-GISEL-NEXT:    v_cndmask_b32_e64 v0, v0, v3, s[4:5]
 ; VI-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; VI-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-SDAG-LABEL: v_log10_f32_dynamic_mode:
 ; GFX900-SDAG:       ; %bb.0:
 ; GFX900-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x800000
 ; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; GFX900-SDAG-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 1.0, v1, vcc
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; GFX900-SDAG-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3e9a209a
 ; GFX900-SDAG-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, -v1
+; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, -v1
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x3284fbcf
-; GFX900-SDAG-NEXT:    v_fma_f32 v1, v0, s4, v1
+; GFX900-SDAG-NEXT:    v_fma_f32 v2, v0, s4, v2
 ; GFX900-SDAG-NEXT:    s_mov_b32 s4, 0x7f800000
-; GFX900-SDAG-NEXT:    v_mac_f32_e32 v1, 0x3e9a209a, v0
+; GFX900-SDAG-NEXT:    v_add_f32_e32 v1, v1, v2
 ; GFX900-SDAG-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, s4
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; GFX900-SDAG-NEXT:    v_mov_b32_e32 v1, 0x411a209b
 ; GFX900-SDAG-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; GFX900-SDAG-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GFX900-SDAG-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX900-GISEL-LABEL: v_log10_f32_dynamic_mode:
 ; GFX900-GISEL:       ; %bb.0:
 ; GFX900-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x800000
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x4f800000
 ; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e32 vcc, v0, v1
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v1, 1.0, v2, vcc
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v0, v0, v1
 ; GFX900-GISEL-NEXT:    v_log_f32_e32 v0, v0
 ; GFX900-GISEL-NEXT:    s_mov_b32 s4, 0x3e9a209a
-; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x3284fbcf
+; GFX900-GISEL-NEXT:    v_mov_b32_e32 v3, 0x3284fbcf
 ; GFX900-GISEL-NEXT:    v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX900-GISEL-NEXT:    v_fma_f32 v1, v0, s4, -v1
-; GFX900-GISEL-NEXT:    v_fma_f32 v1, v0, v2, v1
+; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, s4, -v1
+; GFX900-GISEL-NEXT:    v_fma_f32 v2, v0, v3, v2
+; GFX900-GISEL-NEXT:    v_add_f32_e32 v1, v1, v2
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f800000
-; GFX900-GISEL-NEXT:    v_mac_f32_e32 v1, 0x3e9a209a, v0
 ; GFX900-GISEL-NEXT:    v_cmp_lt_f32_e64 s[4:5], |v0|, v2
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e64 v0, v0, v1, s[4:5]
 ; GFX900-GISEL-NEXT:    v_mov_b32_e32 v1, 0x411a209b
 ; GFX900-GISEL-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; GFX900-GISEL-NEXT:    v_sub_f32_e32 v0, v0, v1
 ; GFX900-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX1100-SDAG-LABEL: v_log10_f32_dynamic_mode:

llvm/test/CodeGen/AMDGPU/v_mac.ll

bb:
   %tmp7 = fmul half %tmp6, %tmp
   %tmp8 = fsub half 1.0, %tmp7
   %tmp9 = fmul half %tmp8, 8.0
   %tmp10 = fadd half %tmp5, %tmp9
   store half %tmp10, ptr addrspace(1) %gep.out
   ret void
 }
 
+; Need to assume denormal handling is needed for dynamic denormal mode
+; GCN-LABEL: {{^}}v_mac_f32_dynamic:
+; GCN: v_mul_f32
+; GCN: v_add_f32
+define float @v_mac_f32_dynamic(float %a, float %b, float %c) "denormal-fp-math-f32"="dynamic,dynamic" {
+  %mul = fmul float %a, %b
+  %mad = fadd float %mul, %c
+  ret float %mad
+}
+
+; GCN-LABEL: {{^}}v_mac_f32_dynamic_daz:
+; GCN: v_mul_f32
+; GCN: v_add_f32
+define float @v_mac_f32_dynamic_daz(float %a, float %b, float %c) "denormal-fp-math-f32"="preserve-sign,dynamic" {
+  %mul = fmul float %a, %b
+  %mad = fadd float %mul, %c
+  ret float %mad
+}
+
+; GCN-LABEL: {{^}}v_mac_f32_dynamic_ftz:
+; GCN: v_mul_f32
+; GCN: v_add_f32
+define float @v_mac_f32_dynamic_ftz(float %a, float %b, float %c) "denormal-fp-math-f32"="dynamic,preserve-sign" {
+  %mul = fmul float %a, %b
+  %mad = fadd float %mul, %c
+  ret float %mad
+}
+
 declare i32 @llvm.amdgcn.workitem.id.x() #2
 
 attributes #0 = { nounwind "no-signed-zeros-fp-math"="false" }
 attributes #1 = { nounwind "no-signed-zeros-fp-math"="true" }
 attributes #2 = { nounwind readnone }
 attributes #3 = { nounwind }