[AArch64] Try to convert vector shift operation into vector add operation

[jaykang10]

Summary

It has been reported that the vector shift instructions tend to be worse than ADD/SUB on AArch64 cores.
This patch supports tablegen patterns for below simple transformation.

x << 1  ==>  x + x

[efriedma]

LGTM

I'm a little concerned this could run into issues along the lines of https://github.com/llvm/llvm-project/issues/49812 ... but I guess we currently don't try to model freeze post-isel, so it's not too likely you'll run into issues.

[efriedma]

Oh, also, please verify we have testcases to make sure these patterns don't interfere with the formation of sshll/ushll

[dmgreen]

llvm/lib/Target/AArch64/AArch64InstrInfo.td

7030

AArch64vshl can be used directly in the Pat, if it is always the same,

[jaykang10]

Thanks for kind comments. @efriedma

I'm a little concerned this could run into issues along the lines of https://github.com/llvm/llvm-project/issues/49812 ... but I guess we currently don't try to model freeze post-isel, so it's not too likely you'll run into issues.

As far as I understand, the AArch64 target uses the default SelectionDAGISel code for ISD::FREEZE so the ISD::FREEZE is mapped to the TargetOpcode::COPY. The ISD::UNDEF is mapped to TargetOpcode::IMPLICIT_DEF. The ProcessImplicitDefs pass removes the IMPLICIT_DEF and mark the add's operands with undef. The register allocator assigns same register to the add's operands because it uses same virtual register. Therefore, I think both x << 1 and x + x guarantees even number output.

Oh, also, please verify we have testcases to make sure these patterns don't interfere with the formation of sshll/ushll

Yep, let me check the test cases more.

llvm/lib/Target/AArch64/AArch64InstrInfo.td

7030

Yep, let me update it.

[jaykang10]

Added sshll/ushll test cases which should not be affected by this patch.

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 //----------------------------------------------------------------------------
 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_aarch64_neon_vcvtfp2fxs>;
 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_aarch64_neon_vcvtfp2fxu>;
 defm SCVTF: SIMDVectorRShiftToFP<0, 0b11100, "scvtf",
                                    int_aarch64_neon_vcvtfxs2fp>;
 defm RSHRN   : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn",
                           BinOpFrag<(trunc (AArch64roundingvlshr node:$LHS, node:$RHS))>>;
 defm SHL     : SIMDVectorLShiftBHSD<0, 0b01010, "shl", AArch64vshl>;
+
+// X << 1 ==> X + X
+class SHLToADDPat<ValueType ty, RegisterClass regtype>
+  : Pat<(ty (AArch64vshl (ty regtype:$Rn), (i32 1))),
+            (!cast<Instruction>("ADD"#ty) regtype:$Rn, regtype:$Rn)>;
+
+def : SHLToADDPat<v16i8, FPR128>;
+def : SHLToADDPat<v8i16, FPR128>;
+def : SHLToADDPat<v4i32, FPR128>;
+def : SHLToADDPat<v2i64, FPR128>;
+def : SHLToADDPat<v8i8,  FPR64>;
+def : SHLToADDPat<v4i16, FPR64>;
+def : SHLToADDPat<v2i32, FPR64>;
+
 defm SHRN    : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn",
                           BinOpFrag<(trunc (AArch64vashr node:$LHS, node:$RHS))>>;
 defm SLI     : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", AArch64vsli>;
 def : Pat<(v1i64 (AArch64vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
                                       (i32 vecshiftL64:$imm))),
           (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>;
 defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn",
                                          int_aarch64_neon_sqrshrn>;

llvm/test/CodeGen/AArch64/arm64-sli-sri-opt.ll

; CHECK-NEXT:    ret
   store <8 x i8> %result, ptr %dest, align 8
   ret void
 }
 
 define void @testLeftBad8x8(<8 x i8> %src1, <8 x i8> %src2, ptr %dest) nounwind {
 ; CHECK-LABEL: testLeftBad8x8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi.8b v2, #165
-; CHECK-NEXT:    shl.8b v1, v1, #1
+; CHECK-NEXT:    add.8b v1, v1, v1
 ; CHECK-NEXT:    and.8b v0, v0, v2
 ; CHECK-NEXT:    orr.8b v0, v0, v1
 ; CHECK-NEXT:    str d0, [x0]
 ; CHECK-NEXT:    ret
   %and.i = and <8 x i8> %src1, <i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165>
   %vshl_n = shl <8 x i8> %src2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   %result = or <8 x i8> %and.i, %vshl_n
   store <8 x i8> %result, ptr %dest, align 8
; CHECK-NEXT:    ret
   store <16 x i8> %result, ptr %dest, align 16
   ret void
 }
 
 define void @testLeftBad16x8(<16 x i8> %src1, <16 x i8> %src2, ptr %dest) nounwind {
 ; CHECK-LABEL: testLeftBad16x8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi.16b v2, #165
-; CHECK-NEXT:    shl.16b v1, v1, #1
+; CHECK-NEXT:    add.16b v1, v1, v1
 ; CHECK-NEXT:    and.16b v0, v0, v2
 ; CHECK-NEXT:    orr.16b v0, v0, v1
 ; CHECK-NEXT:    str q0, [x0]
 ; CHECK-NEXT:    ret
   %and.i = and <16 x i8> %src1, <i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165>
   %vshl_n = shl <16 x i8> %src2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   %result = or <16 x i8> %and.i, %vshl_n
   store <16 x i8> %result, ptr %dest, align 16

llvm/test/CodeGen/AArch64/arm64-vshift.ll

; CHECK-NEXT:    ret
   %tmp3 = call <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
   ret <4 x i32> %tmp3
 }
 
 define <8 x i16> @neon.ushl8_noext_constant_shift(ptr %A) nounwind {
 ; CHECK-LABEL: neon.ushl8_noext_constant_shift:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
-; CHECK-NEXT:    shl.8h v0, v0, #1
+; CHECK-NEXT:    add.8h v0, v0, v0
 ; CHECK-NEXT:    ret
   %tmp1 = load <8 x i16>, ptr %A
   %tmp3 = call <8 x i16> @llvm.aarch64.neon.ushl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
   ret <8 x i16> %tmp3
 }
 
 define <4 x i32> @neon.ushll4s_constant_shift(ptr %A) nounwind {
 ; CHECK-LABEL: neon.ushll4s_constant_shift:

 }
 
 ; FIXME: should be constant folded.
 define <4 x i32> @neon.ushll4s_constant_fold() nounwind {
 ; CHECK-LABEL: neon.ushll4s_constant_fold:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI160_0
 ; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI160_0]
-; CHECK-NEXT:    shl.4s v0, v0, #1
+; CHECK-NEXT:    add.4s v0, v0, v0
 ; CHECK-NEXT:    ret
   %tmp3 = call <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
   ret <4 x i32> %tmp3
 }
 
 define <2 x i64> @neon.ushll2d_constant_shift(ptr %A) nounwind {
 ; CHECK-LABEL: neon.ushll2d_constant_shift:
 ; CHECK:       // %bb.0:

 declare <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64>, <2 x i64>)
 declare <1 x i64> @llvm.aarch64.neon.sshl.v1i64(<1 x i64>, <1 x i64>)
 declare i64 @llvm.aarch64.neon.sshl.i64(i64, i64)
 
 define <16 x i8> @neon.sshl16b_constant_shift(ptr %A) nounwind {
 ; CHECK-LABEL: neon.sshl16b_constant_shift:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
-; CHECK-NEXT:    shl.16b v0, v0, #1
+; CHECK-NEXT:    add.16b v0, v0, v0
 ; CHECK-NEXT:    ret
   %tmp1 = load <16 x i8>, ptr %A
   %tmp2 = call <16 x i8> @llvm.aarch64.neon.sshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
   ret <16 x i8> %tmp2
 }
 
 define <16 x i8> @neon.sshl16b_non_splat_constant_shift(ptr %A) nounwind {
 ; CHECK-LABEL: neon.sshl16b_non_splat_constant_shift:
; CHECK-NEXT:    ret
   %tmp3 = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32> <i32 2, i32 2, i32 2, i32 2>)
   ret <4 x i32> %tmp3
 }
 
 define <4 x i32> @neon.sshl4s_no_fold(ptr %A) nounwind {
 ; CHECK-LABEL: neon.sshl4s_no_fold:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
-; CHECK-NEXT:    shl.4s v0, v0, #1
+; CHECK-NEXT:    add.4s v0, v0, v0
 ; CHECK-NEXT:    ret
   %tmp1 = load <4 x i32>, ptr %A
   %tmp3 = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
   ret <4 x i32> %tmp3
 }
 
 define <2 x i64> @neon.sshll2d_constant_shift(ptr %A) nounwind {
 ; CHECK-LABEL: neon.sshll2d_constant_shift:

 }
 
 ; FIXME: should be constant folded.
 define <2 x i64> @neon.sshl2d_constant_fold() nounwind {
 ; CHECK-LABEL: neon.sshl2d_constant_fold:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI179_0
 ; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI179_0]
-; CHECK-NEXT:    shl.2d v0, v0, #1
+; CHECK-NEXT:    add.2d v0, v0, v0
 ; CHECK-NEXT:    ret
   %tmp3 = call <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64> <i64 99, i64 1000>, <2 x i64> <i64 1, i64 1>)
   ret <2 x i64> %tmp3
 }
 
 define <2 x i64> @neon.sshl2d_no_fold(ptr %A) nounwind {
 ; CHECK-LABEL: neon.sshl2d_no_fold:
 ; CHECK:       // %bb.0:
; CHECK-NEXT:    ret
    ret <2 x i64> %tmp5
 }
 
 define <8 x i8> @shl_orr8b(ptr %A, ptr %B) nounwind {
 ; CHECK-LABEL: shl_orr8b:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
 ; CHECK-NEXT:    ldr d1, [x1]
-; CHECK-NEXT:    shl.8b v0, v0, #1
+; CHECK-NEXT:    add.8b v0, v0, v0
 ; CHECK-NEXT:    orr.8b v0, v0, v1
 ; CHECK-NEXT:    ret
   %tmp1 = load <8 x i8>, ptr %A
   %tmp4 = load <8 x i8>, ptr %B
   %tmp3 = shl <8 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   %tmp5 = or <8 x i8> %tmp3, %tmp4
   ret <8 x i8> %tmp5
 }
 
 define <4 x i16> @shl_orr4h(ptr %A, ptr %B) nounwind {
 ; CHECK-LABEL: shl_orr4h:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
 ; CHECK-NEXT:    ldr d1, [x1]
-; CHECK-NEXT:    shl.4h v0, v0, #1
+; CHECK-NEXT:    add.4h v0, v0, v0
 ; CHECK-NEXT:    orr.8b v0, v0, v1
 ; CHECK-NEXT:    ret
   %tmp1 = load <4 x i16>, ptr %A
   %tmp4 = load <4 x i16>, ptr %B
   %tmp3 = shl <4 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1>
   %tmp5 = or <4 x i16> %tmp3, %tmp4
   ret <4 x i16> %tmp5
 }
 
 define <2 x i32> @shl_orr2s(ptr %A, ptr %B) nounwind {
 ; CHECK-LABEL: shl_orr2s:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr d0, [x0]
 ; CHECK-NEXT:    ldr d1, [x1]
-; CHECK-NEXT:    shl.2s v0, v0, #1
+; CHECK-NEXT:    add.2s v0, v0, v0
 ; CHECK-NEXT:    orr.8b v0, v0, v1
 ; CHECK-NEXT:    ret
   %tmp1 = load <2 x i32>, ptr %A
   %tmp4 = load <2 x i32>, ptr %B
   %tmp3 = shl <2 x i32> %tmp1, <i32 1, i32 1>
   %tmp5 = or <2 x i32> %tmp3, %tmp4
   ret <2 x i32> %tmp5
 }
 
 define <16 x i8> @shl_orr16b(ptr %A, ptr %B) nounwind {
 ; CHECK-LABEL: shl_orr16b:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
 ; CHECK-NEXT:    ldr q1, [x1]
-; CHECK-NEXT:    shl.16b v0, v0, #1
+; CHECK-NEXT:    add.16b v0, v0, v0
 ; CHECK-NEXT:    orr.16b v0, v0, v1
 ; CHECK-NEXT:    ret
   %tmp1 = load <16 x i8>, ptr %A
   %tmp4 = load <16 x i8>, ptr %B
   %tmp3 = shl <16 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   %tmp5 = or <16 x i8> %tmp3, %tmp4
    ret <16 x i8> %tmp5
 }
 
 define <8 x i16> @shl_orr8h(ptr %A, ptr %B) nounwind {
 ; CHECK-LABEL: shl_orr8h:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
 ; CHECK-NEXT:    ldr q1, [x1]
-; CHECK-NEXT:    shl.8h v0, v0, #1
+; CHECK-NEXT:    add.8h v0, v0, v0
 ; CHECK-NEXT:    orr.16b v0, v0, v1
 ; CHECK-NEXT:    ret
   %tmp1 = load <8 x i16>, ptr %A
   %tmp4 = load <8 x i16>, ptr %B
   %tmp3 = shl <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   %tmp5 = or <8 x i16> %tmp3, %tmp4
    ret <8 x i16> %tmp5
 }
 
 define <4 x i32> @shl_orr4s(ptr %A, ptr %B) nounwind {
 ; CHECK-LABEL: shl_orr4s:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
 ; CHECK-NEXT:    ldr q1, [x1]
-; CHECK-NEXT:    shl.4s v0, v0, #1
+; CHECK-NEXT:    add.4s v0, v0, v0
 ; CHECK-NEXT:    orr.16b v0, v0, v1
 ; CHECK-NEXT:    ret
   %tmp1 = load <4 x i32>, ptr %A
   %tmp4 = load <4 x i32>, ptr %B
   %tmp3 = shl <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>
   %tmp5 = or <4 x i32> %tmp3, %tmp4
    ret <4 x i32> %tmp5
 }
 
 define <2 x i64> @shl_orr2d(ptr %A, ptr %B) nounwind {
 ; CHECK-LABEL: shl_orr2d:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
 ; CHECK-NEXT:    ldr q1, [x1]
-; CHECK-NEXT:    shl.2d v0, v0, #1
+; CHECK-NEXT:    add.2d v0, v0, v0
 ; CHECK-NEXT:    orr.16b v0, v0, v1
 ; CHECK-NEXT:    ret
   %tmp1 = load <2 x i64>, ptr %A
   %tmp4 = load <2 x i64>, ptr %B
   %tmp3 = shl <2 x i64> %tmp1, <i64 1, i64 1>
   %tmp5 = or <2 x i64> %tmp3, %tmp4
    ret <2 x i64> %tmp5
 }

llvm/test/CodeGen/AArch64/rax1.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -mtriple=aarch64-none-eabi -mattr=+sha3 < %s | FileCheck --check-prefix=SHA3 %s
 ; RUN: llc -mtriple=aarch64-none-eabi -mattr=-sha3 < %s | FileCheck --check-prefix=NOSHA3 %s
 
 define <2 x i64> @rax1(<2 x i64> %x, <2 x i64> %y) {
 ; SHA3-LABEL: rax1:
 ; SHA3:       // %bb.0:
 ; SHA3-NEXT:    rax1 v0.2d, v0.2d, v1.2d
 ; SHA3-NEXT:    ret
 ;
 ; NOSHA3-LABEL: rax1:
 ; NOSHA3:       // %bb.0:
 ; NOSHA3-NEXT:    ushr v2.2d, v1.2d, #63
-; NOSHA3-NEXT:    shl v1.2d, v1.2d, #1
+; NOSHA3-NEXT:    add v1.2d, v1.2d, v1.2d
 ; NOSHA3-NEXT:    orr v1.16b, v1.16b, v2.16b
 ; NOSHA3-NEXT:    eor v0.16b, v0.16b, v1.16b
 ; NOSHA3-NEXT:    ret
     %a = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %y, <2 x i64> %y, <2 x i64> <i64 1, i64 1>)
     %b = xor <2 x i64> %x, %a
     ret <2 x i64> %b
 }
 
 declare <2 x i64> @llvm.fshl.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)

llvm/test/CodeGen/AArch64/shl-to-add.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=aarch64-none-linux-gnu < %s -o - | FileCheck %s
+
+define <16 x i8> @shl_v16i8(<16 x i8> %a) {
+; CHECK-LABEL: shl_v16i8:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    add v0.16b, v0.16b, v0.16b
+; CHECK-NEXT:    ret
+entry:
+  %add.i = shl <16 x i8> %a, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <16 x i8> %add.i
+}
+
+define <8 x i16> @shl_v8i16(<8 x i16> %a) {
+; CHECK-LABEL: shl_v8i16:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    add v0.8h, v0.8h, v0.8h
+; CHECK-NEXT:    ret
+entry:
+  %add.i = shl <8 x i16> %a, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+  ret <8 x i16> %add.i
+}
+
+define <4 x i32> @shl_v4i32(<4 x i32> %a) {
+; CHECK-LABEL: shl_v4i32:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    add v0.4s, v0.4s, v0.4s
+; CHECK-NEXT:    ret
+entry:
+  %add.i = shl <4 x i32> %a, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %add.i
+}
+
+define <2 x i64> @shl_v2i64(<2 x i64> %a) {
+; CHECK-LABEL: shl_v2i64:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    add v0.2d, v0.2d, v0.2d
+; CHECK-NEXT:    ret
+entry:
+  %add.i = shl <2 x i64> %a, <i64 1, i64 1>
+  ret <2 x i64> %add.i
+}
+
+define <8 x i8> @shl_v8i8(<8 x i8> %a) {
+; CHECK-LABEL: shl_v8i8:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    add v0.8b, v0.8b, v0.8b
+; CHECK-NEXT:    ret
+entry:
+  %add.i = shl <8 x i8> %a, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  ret <8 x i8> %add.i
+}
+
+define <4 x i16> @shl_v4i16(<4 x i16> %a) {
+; CHECK-LABEL: shl_v4i16:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    add v0.4h, v0.4h, v0.4h
+; CHECK-NEXT:    ret
+entry:
+  %add.i = shl <4 x i16> %a, <i16 1, i16 1, i16 1, i16 1>
+  ret <4 x i16> %add.i
+}
+
+define <2 x i32> @shl_v2i32(<2 x i32> %a) {
+; CHECK-LABEL: shl_v2i32:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    add v0.2s, v0.2s, v0.2s
+; CHECK-NEXT:    ret
+entry:
+  %add.i = shl <2 x i32> %a, <i32 1, i32 1>
+  ret <2 x i32> %add.i
+}
+
+define <8 x i16> @sshll_v8i8(<8 x i8> %a) {
+; CHECK-LABEL: sshll_v8i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sshll v0.8h, v0.8b, #1
+; CHECK-NEXT:    ret
+  %1 = sext <8 x i8> %a to <8 x i16>
+  %tmp = shl <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+  ret <8 x i16> %tmp
+}
+
+define <4 x i32> @sshll_v4i16(<4 x i16> %a) {
+; CHECK-LABEL: sshll_v4i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sshll v0.4s, v0.4h, #1
+; CHECK-NEXT:    ret
+  %1 = sext <4 x i16> %a to <4 x i32>
+  %tmp = shl <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %tmp
+}
+
+define <2 x i64> @sshll_v2i32(<2 x i32> %a) {
+; CHECK-LABEL: sshll_v2i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sshll v0.2d, v0.2s, #1
+; CHECK-NEXT:    ret
+  %1 = sext <2 x i32> %a to <2 x i64>
+  %tmp = shl <2 x i64> %1, <i64 1, i64 1>
+  ret <2 x i64> %tmp
+}
+
+define <8 x i16> @ushll_v8i8(<8 x i8> %a) {
+; CHECK-LABEL: ushll_v8i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ushll v0.8h, v0.8b, #1
+; CHECK-NEXT:    ret
+  %1 = zext <8 x i8> %a to <8 x i16>
+  %tmp = shl <8 x i16> %1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+  ret <8 x i16> %tmp
+}
+
+define <4 x i32> @ushll_v4i16(<4 x i16> %a) {
+; CHECK-LABEL: ushll_v4i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ushll v0.4s, v0.4h, #1
+; CHECK-NEXT:    ret
+  %1 = zext <4 x i16> %a to <4 x i32>
+  %tmp = shl <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %tmp
+}
+
+define <2 x i64> @ushll_v2i32(<2 x i32> %a) {
+; CHECK-LABEL: ushll_v2i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ushll v0.2d, v0.2s, #1
+; CHECK-NEXT:    ret
+  %1 = zext <2 x i32> %a to <2 x i64>
+  %tmp = shl <2 x i64> %1, <i64 1, i64 1>
+  ret <2 x i64> %tmp
+}

llvm/test/CodeGen/AArch64/urem-seteq-illegal-types.ll

 ; CHECK-NEXT:    ldr d2, [x9, :lo12:.LCPI4_1]
 ; CHECK-NEXT:    adrp x8, .LCPI4_2
 ; CHECK-NEXT:    mov v0.h[2], w2
 ; CHECK-NEXT:    sub v0.4h, v0.4h, v1.4h
 ; CHECK-NEXT:    movi d1, #0x0000000000ffff
 ; CHECK-NEXT:    mul v0.4h, v0.4h, v2.4h
 ; CHECK-NEXT:    ldr d2, [x8, :lo12:.LCPI4_2]
 ; CHECK-NEXT:    adrp x8, .LCPI4_3
-; CHECK-NEXT:    shl v3.4h, v0.4h, #1
+; CHECK-NEXT:    add v3.4h, v0.4h, v0.4h
 ; CHECK-NEXT:    bic v0.4h, #248, lsl #8
 ; CHECK-NEXT:    ushl v0.4h, v0.4h, v1.4h
 ; CHECK-NEXT:    ushl v1.4h, v3.4h, v2.4h
 ; CHECK-NEXT:    ldr d2, [x8, :lo12:.LCPI4_3]
 ; CHECK-NEXT:    orr v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    bic v0.4h, #248, lsl #8
 ; CHECK-NEXT:    cmhi v0.4h, v0.4h, v2.4h
 ; CHECK-NEXT:    umov w0, v0.h[0]
 ; CHECK-NEXT:    umov w1, v0.h[1]
 ; CHECK-NEXT:    umov w2, v0.h[2]
 ; CHECK-NEXT:    ret
   %urem = urem <3 x i11> %X, <i11 6, i11 7, i11 -5>
   %cmp = icmp ne <3 x i11> %urem, <i11 0, i11 1, i11 2>
   ret <3 x i1> %cmp
 }

llvm/test/CodeGen/AArch64/vector_splat-const-shift-of-constmasked.ll

 
 ; shl
 
 define <16 x i8> @test_128_i8_x_16_7_mask_shl_1(<16 x i8> %a0) {
 ; CHECK-LABEL: test_128_i8_x_16_7_mask_shl_1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.16b, #7
 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT:    shl v0.16b, v0.16b, #1
+; CHECK-NEXT:    add v0.16b, v0.16b, v0.16b
 ; CHECK-NEXT:    ret
   %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
   %t1 = shl <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   ret <16 x i8> %t1
 }
 define <16 x i8> @test_128_i8_x_16_7_mask_shl_4(<16 x i8> %a0) {
 ; CHECK-LABEL: test_128_i8_x_16_7_mask_shl_4:
 ; CHECK:       // %bb.0:
; CHECK-NEXT:    ret
   ret <16 x i8> %t1
 }
 
 define <16 x i8> @test_128_i8_x_16_28_mask_shl_1(<16 x i8> %a0) {
 ; CHECK-LABEL: test_128_i8_x_16_28_mask_shl_1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.16b, #28
 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT:    shl v0.16b, v0.16b, #1
+; CHECK-NEXT:    add v0.16b, v0.16b, v0.16b
 ; CHECK-NEXT:    ret
   %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
   %t1 = shl <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   ret <16 x i8> %t1
 }
 define <16 x i8> @test_128_i8_x_16_28_mask_shl_2(<16 x i8> %a0) {
 ; CHECK-LABEL: test_128_i8_x_16_28_mask_shl_2:
 ; CHECK:       // %bb.0:
; CHECK-NEXT:    ret
   ret <16 x i8> %t1
 }
 
 define <16 x i8> @test_128_i8_x_16_224_mask_shl_1(<16 x i8> %a0) {
 ; CHECK-LABEL: test_128_i8_x_16_224_mask_shl_1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.16b, #224
 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT:    shl v0.16b, v0.16b, #1
+; CHECK-NEXT:    add v0.16b, v0.16b, v0.16b
 ; CHECK-NEXT:    ret
   %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
   %t1 = shl <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
   ret <16 x i8> %t1
 }
 
 ;------------------------------------------------------------------------------;
 ; 128-bit vector; 16-bit elements = 8 elements

 
 ; shl
 
 define <8 x i16> @test_128_i16_x_8_127_mask_shl_1(<8 x i16> %a0) {
 ; CHECK-LABEL: test_128_i16_x_8_127_mask_shl_1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.8h, #127
 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT:    shl v0.8h, v0.8h, #1
+; CHECK-NEXT:    add v0.8h, v0.8h, v0.8h
 ; CHECK-NEXT:    ret
   %t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
   %t1 = shl <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   ret <8 x i16> %t1
 }
 define <8 x i16> @test_128_i16_x_8_127_mask_shl_8(<8 x i16> %a0) {
 ; CHECK-LABEL: test_128_i16_x_8_127_mask_shl_8:
 ; CHECK:       // %bb.0:
; CHECK-NEXT:    ret
   ret <8 x i16> %t1
 }
 
 define <8 x i16> @test_128_i16_x_8_65024_mask_shl_1(<8 x i16> %a0) {
 ; CHECK-LABEL: test_128_i16_x_8_65024_mask_shl_1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.8h, #254, lsl #8
 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT:    shl v0.8h, v0.8h, #1
+; CHECK-NEXT:    add v0.8h, v0.8h, v0.8h
 ; CHECK-NEXT:    ret
   %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>
   %t1 = shl <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
   ret <8 x i16> %t1
 }
 
 ;------------------------------------------------------------------------------;
 ; 128-bit vector; 32-bit elements = 4 elements

 
 ; shl
 
 define <4 x i32> @test_128_i32_x_4_32767_mask_shl_1(<4 x i32> %a0) {
 ; CHECK-LABEL: test_128_i32_x_4_32767_mask_shl_1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi v1.4s, #127, msl #8
 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT:    shl v0.4s, v0.4s, #1
+; CHECK-NEXT:    add v0.4s, v0.4s, v0.4s
 ; CHECK-NEXT:    ret
   %t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>
   %t1 = shl <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>
   ret <4 x i32> %t1
 }
 define <4 x i32> @test_128_i32_x_4_32767_mask_shl_16(<4 x i32> %a0) {
 ; CHECK-LABEL: test_128_i32_x_4_32767_mask_shl_16:
 ; CHECK:       // %bb.0:
; CHECK-NEXT:    ret
   ret <4 x i32> %t1
 }
 
 define <4 x i32> @test_128_i32_x_4_4294836224_mask_shl_1(<4 x i32> %a0) {
 ; CHECK-LABEL: test_128_i32_x_4_4294836224_mask_shl_1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mvni v1.4s, #1, msl #16
 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT:    shl v0.4s, v0.4s, #1
+; CHECK-NEXT:    add v0.4s, v0.4s, v0.4s
 ; CHECK-NEXT:    ret
   %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>
   %t1 = shl <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>
   ret <4 x i32> %t1
 }
 
 ;------------------------------------------------------------------------------;
 ; 128-bit vector; 64-bit elements = 2 elements

 ; shl
 
 define <2 x i64> @test_128_i64_x_2_2147483647_mask_shl_1(<2 x i64> %a0) {
 ; CHECK-LABEL: test_128_i64_x_2_2147483647_mask_shl_1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #2147483647
 ; CHECK-NEXT:    dup v1.2d, x8
 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT:    shl v0.2d, v0.2d, #1
+; CHECK-NEXT:    add v0.2d, v0.2d, v0.2d
 ; CHECK-NEXT:    ret
   %t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647>
   %t1 = shl <2 x i64> %t0, <i64 1, i64 1>
   ret <2 x i64> %t1
 }
 define <2 x i64> @test_128_i64_x_2_2147483647_mask_shl_32(<2 x i64> %a0) {
 ; CHECK-LABEL: test_128_i64_x_2_2147483647_mask_shl_32:
 ; CHECK:       // %bb.0:

 }
 
 define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_shl_1(<2 x i64> %a0) {
 ; CHECK-LABEL: test_128_i64_x_2_18446744065119617024_mask_shl_1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #-8589934592
 ; CHECK-NEXT:    dup v1.2d, x8
 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT:    shl v0.2d, v0.2d, #1
+; CHECK-NEXT:    add v0.2d, v0.2d, v0.2d
 ; CHECK-NEXT:    ret
   %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
   %t1 = shl <2 x i64> %t0, <i64 1, i64 1>
   ret <2 x i64> %t1
 }