[AMDGPU] Fix register class for a subreg in GCNRewritePartialRegUses.

[vpykhtin]

Summary

1. Improved code that deduces register class from instruction definitions. Previously if some instruction didn't contain a reg class for an operand it was considered as no information on register class even if other instructions specified the class.

2. Added check on required size of resulting register because in some cases classes with smaller registers had been selected (for example VReg_1).

[arsenm]

llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp

100–116

This comment is a run on sentence I'm having trouble following

327–328

Why do you need the size? In the unknown case you still have a class from the vreg

[vpykhtin]

Improved function description.

[vpykhtin]

llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp

327–328

I had the following problem with that, given a test:

name: test_subregs_unknown_regclass_from_instructions_sgpr_1024_to_sgpr_64
tracksRegLiveness: true
registers:
  - { id: 0, class: sgpr_1024 }
body:             |
  bb.0:
    %1:vreg_64 = COPY undef %0.sub4_sub5

%0.sub4_sub5 doesn't have known regclass and getSubRegisterClass returns

sgpr_1024 : sub4_sub5 -> SReg_1_with_sub0_and_SReg_1_with_lo16_in_SGPR_LO16

SReg_1_with_sub0_and_SReg_1_with_lo16_in_SGPR_LO16 has the following subclasses (in tablegen generated order):

VReg_1
SGPR_64
CCR_SGPR_64
Gfx_CCR_SGPR_64

If I don't check the size it would select VReg_1 which is invalid.

I haven't followed all the consequences why tablegen generated this artificial subclass, but I know that if a class contains registers of different size tablegen puts subclass with smaller registers first, that is why VReg_1 precedes SGPR_64.

[vpykhtin]

ping.

[arsenm]

llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp

241

If you do TRI->getMatchingSuperRegClass(RC, TRI->getSubRegisterClass(RC, OldSubReg), OldSubReg) does it work?

[arsenm]

I never got around to the patch to use getSubRegisterClass so it makes sense that it's buggy

[arsenm]

llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp

241

Alternatively, getLargestLegalSuperClass

[vpykhtin]

llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp

241

getMatchingSuperRegClass(RC, TRI->getSubRegisterClass(RC, OldSubReg), OldSubReg) does different thing:

• getSubRegisterClass(RC, OldSubReg) is supposed to return the register class that can be used to allocate the register for OldSubReg subreg of a super register from class RC

• the former version is going to find a largest subclass of RC where each register has subreg OldSubReg and this subreg would have TRI->getSubRegisterClass(RC, OldSubReg) class on allocation.

getLargestLegalSuperClass doesn't seem to do the job too.

[barannikov88]

llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp

327–328

FWIW all registers in a register class must have the same (spill) size.
But VReg_1 shouldn't be a sublass of any class at all. This looks like a peculiar effect of a class containing no registers on tablegen.

[vpykhtin]

llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp

327–328

This sounds like tablegen should be fixed instead.

[arsenm]

llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp

327–328

Yes, tablegen should be fixed. Ideally VReg_1 wouldn't appear anywhere, it's a hack for the DAG only

[arsenm]

LGTM to move forward with this. I do think we should not be depending on register class size queries and I would much prefer getSubRegisterClass produce a useful result

[vpykhtin]

Rebase before landing.

llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp

private:
 
   /// Given register class RC and the set of used subregs as keys in the SubRegs
   /// map return new register class and indexes of right-shifted subregs as
   /// values in SubRegs map such that the resulting regclass would contain
   /// registers of minimal size.
   const TargetRegisterClass *getMinSizeReg(const TargetRegisterClass *RC,
                                            SubRegMap &SubRegs) const;
 
-  /// Try to find register class containing registers of minimal size for a
-  /// given register class RC and used subregs as keys in SubRegs by shifting
-  /// offsets of the subregs by RShift value to the right. If found return the
-  /// resulting regclass and new shifted subregs as values in SubRegs map.
-  /// If CoverSubregIdx isn't null it specifies covering subreg.
+  /// Given regclass RC and pairs of [OldSubReg, SubRegRC] in SubRegs try to
+  /// find new regclass such that:
+  ///   1. It has subregs obtained by shifting each OldSubReg by RShift number
+  ///      of bits to the right. Every "shifted" subreg should have the same
+  ///      SubRegRC. SubRegRC can be null, in this case it initialized using
+  ///      getSubRegisterClass. If CoverSubregIdx is not zero it's a subreg that
+  ///      "covers" all other subregs in pairs. Basically such subreg becomes a
+  ///      whole register.
+  ///   2. Resulting register class contains registers of minimal size but not
+  ///      less than RegNumBits.
+  ///
+  /// SubRegs is map of OldSubReg -> [SubRegRC, NewSubReg] and is used as in/out
+  /// parameter:
+  ///   OldSubReg - input parameter,
+  ///   SubRegRC  - in/out, should be changed for unknown regclass,
+  ///   NewSubReg - output, contains shifted subregs on return.
   const TargetRegisterClass *
   getRegClassWithShiftedSubregs(const TargetRegisterClass *RC, unsigned RShift,
-                                unsigned CoverSubregIdx,
+                                unsigned RegNumBits, unsigned CoverSubregIdx,
                                 SubRegMap &SubRegs) const;
 
   /// Update live intervals after rewriting OldReg to NewReg with SubRegs map
   /// describing OldSubReg -> NewSubReg mapping.
   void updateLiveIntervals(Register OldReg, Register NewReg,
                            SubRegMap &SubRegs) const;
 
   /// Helper methods.
for (unsigned ClassID = 0; ClassID < TRI->getNumRegClasses(); ++ClassID) {
         BV.set(ClassID);
     }
   }
   return I->second;
 }
 
 const TargetRegisterClass *
 GCNRewritePartialRegUses::getRegClassWithShiftedSubregs(
-    const TargetRegisterClass *RC, unsigned RShift, unsigned CoverSubregIdx,
-    SubRegMap &SubRegs) const {
+    const TargetRegisterClass *RC, unsigned RShift, unsigned RegNumBits,
+    unsigned CoverSubregIdx, SubRegMap &SubRegs) const {
 
   unsigned RCAlign = TRI->getRegClassAlignmentNumBits(RC);
   LLVM_DEBUG(dbgs() << "  Shift " << RShift << ", reg align " << RCAlign
                     << '\n');
 
   BitVector ClassMask(getAllocatableAndAlignedRegClassMask(RCAlign));
   for (auto &[OldSubReg, SRI] : SubRegs) {
     auto &[SubRegRC, NewSubReg] = SRI;
 
-    // Instruction operand may not specify required register class (ex. COPY).
+    // Register class may be unknown, for example:
+    //   undef %0.sub4:sgpr_1024 = S_MOV_B32 01
+    //   %0.sub5:sgpr_1024 = S_MOV_B32 02
+    //   %1:vreg_64 = COPY %0.sub4_sub5
+    // Register classes for subregs 'sub4' and 'sub5' are known from the
+    // description of destination operand of S_MOV_B32 instruction but the
+    // class for the subreg 'sub4_sub5' isn't specified by the COPY instruction.
     if (!SubRegRC)
       SubRegRC = TRI->getSubRegisterClass(RC, OldSubReg);
 
     if (!SubRegRC)
       return nullptr;
 
     LLVM_DEBUG(dbgs() << "  " << TRI->getSubRegIndexName(OldSubReg) << ':'
                       << TRI->getRegClassName(SubRegRC)
                       << (SubRegRC->isAllocatable() ? "" : " not alloc")
                       << " -> ");
 
for (auto &[OldSubReg, SRI] : SubRegs) {
     // Don't try to early exit because checking if ClassMask has set bits isn't
     // that cheap and we expect it to pass in most cases.
     LLVM_DEBUG(dbgs() << ", num regclasses " << ClassMask.count() << '\n');
   }
 
   // ClassMask is the set of all register classes such that each class is
   // allocatable, aligned, has all shifted subregs and each subreg has required
   // register class (see SubRegRC above). Now select first (that is largest)
-  // register class with registers of minimal size.
+  // register class with registers of minimal but not less than RegNumBits size.
+  // We have to check register size because we may encounter classes of smaller
+  // registers like VReg_1 in some situations.
   const TargetRegisterClass *MinRC = nullptr;
   unsigned MinNumBits = std::numeric_limits<unsigned>::max();
   for (unsigned ClassID : ClassMask.set_bits()) {
     auto *RC = TRI->getRegClass(ClassID);
     unsigned NumBits = TRI->getRegSizeInBits(*RC);
-    if (NumBits < MinNumBits) {
+    if (NumBits < MinNumBits && NumBits >= RegNumBits) {
       MinNumBits = NumBits;
       MinRC = RC;
     }
+    if (MinNumBits == RegNumBits)
+      break;
   }
 #ifndef NDEBUG
   if (MinRC) {
     assert(MinRC->isAllocatable() && TRI->isRegClassAligned(MinRC, RCAlign));
     for (auto [SubReg, SRI] : SubRegs)
+      // Check that all registers in MinRC support SRI.SubReg subregister.
       assert(MinRC == TRI->getSubClassWithSubReg(MinRC, SRI.SubReg));
   }
 #endif
   // There might be zero RShift - in this case we just trying to find smaller
   // register.
   return (MinRC != RC || RShift != 0) ? MinRC : nullptr;
 }
 
if (SubRegEnd > End) {
       CoverSubreg = AMDGPU::NoSubRegister;
     }
     if (SubRegOffset == Offset && SubRegEnd == End)
       CoverSubreg = SubReg;
   }
   // If covering subreg is found shift everything so the covering subreg would
   // be in the rightmost position.
   if (CoverSubreg != AMDGPU::NoSubRegister)
-    return getRegClassWithShiftedSubregs(RC, Offset, CoverSubreg, SubRegs);
+    return getRegClassWithShiftedSubregs(RC, Offset, End - Offset, CoverSubreg,
+                                         SubRegs);
 
   // Otherwise find subreg with maximum required alignment and shift it and all
   // other subregs to the rightmost possible position with respect to the
   // alignment.
   unsigned MaxAlign = 0;
   for (auto [SubReg, SRI] : SubRegs)
     MaxAlign = std::max(MaxAlign, TRI->getSubRegAlignmentNumBits(RC, SubReg));
 
GCNRewritePartialRegUses::getMinSizeReg(const TargetRegisterClass *RC,
 
   unsigned NewOffsetOfMaxAlignedSubReg =
       alignTo(FirstMaxAlignedSubRegOffset - Offset, MaxAlign);
 
   if (NewOffsetOfMaxAlignedSubReg > FirstMaxAlignedSubRegOffset)
     llvm_unreachable("misaligned subreg");
 
   unsigned RShift = FirstMaxAlignedSubRegOffset - NewOffsetOfMaxAlignedSubReg;
-  return getRegClassWithShiftedSubregs(RC, RShift, 0, SubRegs);
+  return getRegClassWithShiftedSubregs(RC, RShift, End - RShift, 0, SubRegs);
 }
 
 // Only the subrange's lanemasks of the original interval need to be modified.
 // Subrange for a covering subreg becomes the main range.
 void GCNRewritePartialRegUses::updateLiveIntervals(Register OldReg,
                                                    Register NewReg,
                                                    SubRegMap &SubRegs) const {
   if (!LIS->hasInterval(OldReg))
bool GCNRewritePartialRegUses::rewriteReg(Register Reg) const {
   if (Range.begin() == Range.end())
     return false;
 
   for (MachineOperand &MO : Range) {
     if (MO.getSubReg() == AMDGPU::NoSubRegister) // Whole reg used, quit.
       return false;
   }
 
+  auto *RC = MRI->getRegClass(Reg);
+  LLVM_DEBUG(dbgs() << "Try to rewrite partial reg " << printReg(Reg, TRI)
+                    << ':' << TRI->getRegClassName(RC) << '\n');
+
   // Collect used subregs and constrained reg classes infered from instruction
   // operands.
   SubRegMap SubRegs;
   for (MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
     assert(MO.getSubReg() != AMDGPU::NoSubRegister);
     auto *OpDescRC = getOperandRegClass(MO);
     const auto [I, Inserted] = SubRegs.try_emplace(MO.getSubReg(), OpDescRC);
-    if (!Inserted) {
+    if (!Inserted && OpDescRC) {
       SubRegInfo &SRI = I->second;
-      SRI.RC = TRI->getCommonSubClass(SRI.RC, OpDescRC);
+      SRI.RC = SRI.RC ? TRI->getCommonSubClass(SRI.RC, OpDescRC) : OpDescRC;
+      if (!SRI.RC) {
+        LLVM_DEBUG(dbgs() << "  Couldn't find common target regclass\n");
+        return false;
+      }
     }
   }
-  auto *RC = MRI->getRegClass(Reg);
-  LLVM_DEBUG(dbgs() << "Try to rewrite partial reg " << printReg(Reg, TRI)
-                    << ':' << TRI->getRegClassName(RC) << '\n');
 
   auto *NewRC = getMinSizeReg(RC, SubRegs);
   if (!NewRC) {
     LLVM_DEBUG(dbgs() << "  No improvement achieved\n");
     return false;
   }
 
   Register NewReg = MRI->createVirtualRegister(NewRC);

llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-gen.mir

 
 ...
 ---
 name: test_sgpr_64_w32
 tracksRegLiveness: true
 body:             |
   bb.0:
     ; CHECK-LABEL: name: test_sgpr_64_w32
-    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
+    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
-    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11
+    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
     undef %0.sub0:sgpr_64 = S_MOV_B32 00
     S_NOP 0, implicit %0.sub0
 
     undef %1.sub1:sgpr_64 = S_MOV_B32 11
     S_NOP 0, implicit %1.sub1
 
 ...
 ---
 name: test_sgpr_96_w32
 tracksRegLiveness: true
 body:             |
   bb.0:
     ; CHECK-LABEL: name: test_sgpr_96_w32
-    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
+    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
-    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11
+    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
-    ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 22
+    ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 22
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
     undef %0.sub0:sgpr_96 = S_MOV_B32 00
     S_NOP 0, implicit %0.sub0
 
     undef %1.sub1:sgpr_96 = S_MOV_B32 11
     S_NOP 0, implicit %1.sub1
 
     undef %2.sub2:sgpr_96 = S_MOV_B32 22
     S_NOP 0, implicit %2.sub2
 
 ...
 # Skip test_sgpr_96_w64: the 64-bit subreg isn't fully supported for the regclass sgpr_96
 ---
 name: test_sgpr_128_w32
 tracksRegLiveness: true
 body:             |
   bb.0:
     ; CHECK-LABEL: name: test_sgpr_128_w32
-    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
+    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
-    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11
+    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
-    ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 23
+    ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 23
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
     undef %0.sub0:sgpr_128 = S_MOV_B32 00
     S_NOP 0, implicit %0.sub0
 
     undef %1.sub1:sgpr_128 = S_MOV_B32 11
     S_NOP 0, implicit %1.sub1
 
     undef %2.sub3:sgpr_128 = S_MOV_B32 23

 ...
 # Skip test_sgpr_128_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_128
 ---
 name: test_sgpr_160_w32
 tracksRegLiveness: true
 body:             |
   bb.0:
     ; CHECK-LABEL: name: test_sgpr_160_w32
-    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
+    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
-    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11
+    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
-    ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 24
+    ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 24
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
     undef %0.sub0:sgpr_160 = S_MOV_B32 00
     S_NOP 0, implicit %0.sub0
 
     undef %1.sub1:sgpr_160 = S_MOV_B32 11
     S_NOP 0, implicit %1.sub1
 
     undef %2.sub4:sgpr_160 = S_MOV_B32 24
     S_NOP 0, implicit %2.sub4
 
 ...
 # Skip test_sgpr_160_w64: the 64-bit subreg isn't fully supported for the regclass sgpr_160
 # Skip test_sgpr_160_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_160
 # Skip test_sgpr_160_w128: the 128-bit subreg isn't fully supported for the regclass sgpr_160
 ---
 name: test_sgpr_192_w32
 tracksRegLiveness: true
 body:             |
   bb.0:
     ; CHECK-LABEL: name: test_sgpr_192_w32
-    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
+    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
-    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11
+    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
-    ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 25
+    ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 25
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
     undef %0.sub0:sgpr_192 = S_MOV_B32 00
     S_NOP 0, implicit %0.sub0
 
     undef %1.sub1:sgpr_192 = S_MOV_B32 11
     S_NOP 0, implicit %1.sub1
 
     undef %2.sub5:sgpr_192 = S_MOV_B32 25

 # Skip test_sgpr_192_w128: the 128-bit subreg isn't fully supported for the regclass sgpr_192
 # Skip test_sgpr_192_w160: the 160-bit subreg isn't fully supported for the regclass sgpr_192
 ---
 name: test_sgpr_224_w32
 tracksRegLiveness: true
 body:             |
   bb.0:
     ; CHECK-LABEL: name: test_sgpr_224_w32
-    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
+    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
-    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11
+    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
-    ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 26
+    ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 26
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
     undef %0.sub0:sgpr_224 = S_MOV_B32 00
     S_NOP 0, implicit %0.sub0
 
     undef %1.sub1:sgpr_224 = S_MOV_B32 11
     S_NOP 0, implicit %1.sub1
 
     undef %2.sub6:sgpr_224 = S_MOV_B32 26
     S_NOP 0, implicit %2.sub6
 
 ...
 # Skip test_sgpr_224_w64: the 64-bit subreg isn't fully supported for the regclass sgpr_224
 # Skip test_sgpr_224_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_224
 # Skip test_sgpr_224_w128: the 128-bit subreg isn't fully supported for the regclass sgpr_224
 # Skip test_sgpr_224_w160: the 160-bit subreg isn't fully supported for the regclass sgpr_224
 # Skip test_sgpr_224_w192: the 192-bit subreg isn't fully supported for the regclass sgpr_224
 ---
 name: test_sgpr_256_w32
 tracksRegLiveness: true
 body:             |
   bb.0:
     ; CHECK-LABEL: name: test_sgpr_256_w32
-    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
+    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
-    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11
+    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
-    ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 27
+    ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 27
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
     undef %0.sub0:sgpr_256 = S_MOV_B32 00
     S_NOP 0, implicit %0.sub0
 
     undef %1.sub1:sgpr_256 = S_MOV_B32 11
     S_NOP 0, implicit %1.sub1
 
     undef %2.sub7:sgpr_256 = S_MOV_B32 27

 # Skip test_sgpr_256_w160: the 160-bit subreg isn't fully supported for the regclass sgpr_256
 # Skip test_sgpr_256_w192: the 192-bit subreg isn't fully supported for the regclass sgpr_256
 ---
 name: test_sgpr_288_w32
 tracksRegLiveness: true
 body:             |
   bb.0:
     ; CHECK-LABEL: name: test_sgpr_288_w32
-    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
+    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
-    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11
+    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
-    ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 28
+    ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 28
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
     undef %0.sub0:sgpr_288 = S_MOV_B32 00
     S_NOP 0, implicit %0.sub0
 
     undef %1.sub1:sgpr_288 = S_MOV_B32 11
     S_NOP 0, implicit %1.sub1
 
     undef %2.sub8:sgpr_288 = S_MOV_B32 28

 # Skip test_sgpr_288_w192: the 192-bit subreg isn't fully supported for the regclass sgpr_288
 # Skip test_sgpr_288_w256: the 256-bit subreg isn't fully supported for the regclass sgpr_288
 ---
 name: test_sgpr_320_w32
 tracksRegLiveness: true
 body:             |
   bb.0:
     ; CHECK-LABEL: name: test_sgpr_320_w32
-    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
+    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
-    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11
+    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
-    ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 29
+    ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 29
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
     undef %0.sub0:sgpr_320 = S_MOV_B32 00
     S_NOP 0, implicit %0.sub0
 
     undef %1.sub1:sgpr_320 = S_MOV_B32 11
     S_NOP 0, implicit %1.sub1
 
     undef %2.sub9:sgpr_320 = S_MOV_B32 29

 ...
 # Skip test_sgpr_320_w256: the 256-bit subreg isn't fully supported for the regclass sgpr_320
 ---
 name: test_sgpr_352_w32
 tracksRegLiveness: true
 body:             |
   bb.0:
     ; CHECK-LABEL: name: test_sgpr_352_w32
-    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
+    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
-    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11
+    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
-    ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 210
+    ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 210
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
     undef %0.sub0:sgpr_352 = S_MOV_B32 00
     S_NOP 0, implicit %0.sub0
 
     undef %1.sub1:sgpr_352 = S_MOV_B32 11
     S_NOP 0, implicit %1.sub1
 
     undef %2.sub10:sgpr_352 = S_MOV_B32 210
     S_NOP 0, implicit %2.sub10
 
 ...
 # Skip test_sgpr_352_w64: the 64-bit subreg isn't fully supported for the regclass sgpr_352
 # Skip test_sgpr_352_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_352
 # Skip test_sgpr_352_w128: the 128-bit subreg isn't fully supported for the regclass sgpr_352
 # Skip test_sgpr_352_w160: the 160-bit subreg isn't fully supported for the regclass sgpr_352
 # Skip test_sgpr_352_w192: the 192-bit subreg isn't fully supported for the regclass sgpr_352
 # Skip test_sgpr_352_w256: the 256-bit subreg isn't fully supported for the regclass sgpr_352
 ---
 name: test_sgpr_384_w32
 tracksRegLiveness: true
 body:             |
   bb.0:
     ; CHECK-LABEL: name: test_sgpr_384_w32
-    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
+    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
-    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11
+    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
-    ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 211
+    ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 211
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
     undef %0.sub0:sgpr_384 = S_MOV_B32 00
     S_NOP 0, implicit %0.sub0
 
     undef %1.sub1:sgpr_384 = S_MOV_B32 11
     S_NOP 0, implicit %1.sub1
 
     undef %2.sub11:sgpr_384 = S_MOV_B32 211

 
 ...
 ---
 name: test_sgpr_512_w32
 tracksRegLiveness: true
 body:             |
   bb.0:
     ; CHECK-LABEL: name: test_sgpr_512_w32
-    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
+    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
-    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11
+    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
-    ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 215
+    ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 215
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
     undef %0.sub0:sgpr_512 = S_MOV_B32 00
     S_NOP 0, implicit %0.sub0
 
     undef %1.sub1:sgpr_512 = S_MOV_B32 11
     S_NOP 0, implicit %1.sub1
 
     undef %2.sub15:sgpr_512 = S_MOV_B32 215

 
 ...
 ---
 name: test_sgpr_1024_w32
 tracksRegLiveness: true
 body:             |
   bb.0:
     ; CHECK-LABEL: name: test_sgpr_1024_w32
-    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
+    ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
-    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 11
+    ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
-    ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 231
+    ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 231
     ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
     undef %0.sub0:sgpr_1024 = S_MOV_B32 00
     S_NOP 0, implicit %0.sub0
 
     undef %1.sub1:sgpr_1024 = S_MOV_B32 11
     S_NOP 0, implicit %1.sub1
 
     undef %2.sub31:sgpr_1024 = S_MOV_B32 231

llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir

bb.0:
     S_NOP 0, implicit %3.sub1_sub2_sub3_sub4_sub5
     S_NOP 0, implicit %3.sub2_sub3_sub4_sub5_sub6
 
     undef %4.sub1:vreg_1024 = V_MOV_B32_e32 41, implicit $exec
     %4.sub3:vreg_1024 = V_MOV_B32_e32 43, implicit $exec
     S_NOP 0, implicit %4.sub1_sub2_sub3_sub4_sub5_sub6
     S_NOP 0, implicit %4.sub3_sub4_sub5_sub6_sub7_sub8
 ...
+---
+name: test_subregs_unknown_regclass_from_instructions
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: test_subregs_unknown_regclass_from_instructions
+    ; CHECK: undef %2.sub0:sgpr_64 = S_MOV_B32 1
+    ; CHECK-NEXT: %2.sub1:sgpr_64 = S_MOV_B32 2
+    ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vreg_64 = COPY %2
+    undef %0.sub4:sgpr_1024 = S_MOV_B32 01
+    %0.sub5:sgpr_1024 = S_MOV_B32 02
+    %1:vreg_64 = COPY %0.sub4_sub5
+...
+---
+name: test_subregs_unknown_regclass_from_instructions_sgpr_1024_to_sgpr_64
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: sgpr_1024 }
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: test_subregs_unknown_regclass_from_instructions_sgpr_1024_to_sgpr_64
+    ; CHECK: dead [[COPY:%[0-9]+]]:vreg_64 = COPY undef %2:sgpr_64
+    %1:vreg_64 = COPY undef %0.sub4_sub5
+...
+---
+name: test_subregs_regclass_defined_by_dst_operand_sreg_64_xexec
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: test_subregs_regclass_defined_by_dst_operand_sreg_64_xexec
+    ; CHECK: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM undef %1:sreg_64, 0, 0
+    ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vreg_64 = COPY [[S_LOAD_DWORDX2_IMM]]
+    undef %0.sub2_sub3:sgpr_128 = S_LOAD_DWORDX2_IMM undef %1:sreg_64, 0, 0
+    %2:vreg_64 = COPY %0.sub2_sub3:sgpr_128
+...
+