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Differential D156332

[AMDGPU] Enable GCNRewritePartialRegUses pass by default.
AcceptedPublic

Authored by vpykhtin on Jul 26 2023, 7:03 AM.

Details

Reviewers
arsenm
Group Reviewers
Restricted Project
Summary

Do it once again after the fix https://reviews.llvm.org/D152832.

Diff Detail

Unit TestsFailed

TimeTest
60,040 msx64 debian > MLIR.Examples/standalone::test.toy

Event Timeline

vpykhtin created this revision.Jul 26 2023, 7:03 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 26 2023, 7:03 AM
Herald added subscribers: foad, kerbowa, asbirlea and 7 others. · View Herald Transcript
vpykhtin requested review of this revision.Jul 26 2023, 7:03 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 26 2023, 7:03 AM
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vpykhtin updated this revision to Diff 544355.Jul 26 2023, 7:10 AM

Disable pass for CodeGen/AMDGPU/dead-lane.mir test.

vpykhtin added a reviewer: Restricted Project.Jul 26 2023, 7:11 AM
arsenm accepted this revision.Jul 26 2023, 7:14 AM
This revision is now accepted and ready to land.Jul 26 2023, 7:14 AM
Harbormaster completed remote builds in B248256: Diff 544355.Jul 26 2023, 11:23 AM
vpykhtin updated this revision to Diff 544657.Jul 27 2023, 2:28 AM

Update failed expensive checks llc-pipeline.ll test.

Harbormaster completed remote builds in B248474: Diff 544657.Jul 27 2023, 3:24 AM
vpykhtin added a comment.Jul 28 2023, 7:11 AM

Got some test failure on graphics, fixing.

vpykhtin added a comment.Oct 19 2023, 9:00 AM

The reason of the failure in graphics tests is known, fix is coming soon.

Revision Contents

Diff 544657

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

Show First 20 Lines • Show All 340 Lines • ▼ Show 20 Lines
static cl::opt<bool> EnableMaxIlpSchedStrategy( static cl::opt<bool> EnableMaxIlpSchedStrategy(
"amdgpu-enable-max-ilp-scheduling-strategy", "amdgpu-enable-max-ilp-scheduling-strategy",
cl::desc("Enable scheduling strategy to maximize ILP for a single wave."), cl::desc("Enable scheduling strategy to maximize ILP for a single wave."),
cl::Hidden, cl::init(false)); cl::Hidden, cl::init(false));
static cl::opt<bool> EnableRewritePartialRegUses( static cl::opt<bool> EnableRewritePartialRegUses(
"amdgpu-enable-rewrite-partial-reg-uses", "amdgpu-enable-rewrite-partial-reg-uses",
cl::desc("Enable rewrite partial reg uses pass"), cl::init(false), cl::desc("Enable rewrite partial reg uses pass"), cl::init(true),
cl::Hidden); cl::Hidden);
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() { extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
// Register the target // Register the target
RegisterTargetMachine<R600TargetMachine> X(getTheR600Target()); RegisterTargetMachine<R600TargetMachine> X(getTheR600Target());
RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget()); RegisterTargetMachine<GCNTargetMachine> Y(getTheGCNTarget());
PassRegistry *PR = PassRegistry::getPassRegistry(); PassRegistry *PR = PassRegistry::getPassRegistry();
▲ Show 20 Lines • Show All 1,283 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -mattr=-xnack -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -mattr=-xnack -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
; Check lowering of some large extractelement that use the stack ; Check lowering of some large extractelement that use the stack
; instead of register indexing. ; instead of register indexing.
define i32 @v_extract_v64i32_varidx(ptr addrspace(1) %ptr, i32 %idx) { define i32 @v_extract_v64i32_varidx(ptr addrspace(1) %ptr, i32 %idx) {
; GCN-LABEL: v_extract_v64i32_varidx: ; GCN-LABEL: v_extract_v64i32_varidx:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s4, s33 ; GCN-NEXT: s_mov_b32 s4, s33
; GCN-NEXT: s_add_i32 s33, s32, 0x3fc0 ; GCN-NEXT: s_add_i32 s33, s32, 0x3fc0
; GCN-NEXT: s_and_b32 s33, s33, 0xffffc000 ; GCN-NEXT: s_and_b32 s33, s33, 0xffffc000
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:60 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:56 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:56 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v47, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s33 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s33 ; 4-byte Folded Spill
; GCN-NEXT: v_mov_b32_e32 v6, v2 ; GCN-NEXT: global_load_dwordx4 v[3:6], v[0:1], off
; GCN-NEXT: global_load_dwordx4 v[2:5], v[0:1], off ; GCN-NEXT: global_load_dwordx4 v[7:10], v[0:1], off offset:16
; GCN-NEXT: global_load_dwordx4 v[16:19], v[0:1], off offset:16 ; GCN-NEXT: global_load_dwordx4 v[11:14], v[0:1], off offset:32
; GCN-NEXT: global_load_dwordx4 v[56:59], v[0:1], off offset:32 ; GCN-NEXT: global_load_dwordx4 v[15:18], v[0:1], off offset:48
; GCN-NEXT: global_load_dwordx4 v[48:51], v[0:1], off offset:48 ; GCN-NEXT: global_load_dwordx4 v[19:22], v[0:1], off offset:64
; GCN-NEXT: global_load_dwordx4 v[20:23], v[0:1], off offset:64 ; GCN-NEXT: global_load_dwordx4 v[23:26], v[0:1], off offset:80
; GCN-NEXT: global_load_dwordx4 v[44:47], v[0:1], off offset:80 ; GCN-NEXT: global_load_dwordx4 v[27:30], v[0:1], off offset:96
; GCN-NEXT: global_load_dwordx4 v[40:43], v[0:1], off offset:96 ; GCN-NEXT: global_load_dwordx4 v[31:34], v[0:1], off offset:112
; GCN-NEXT: global_load_dwordx4 v[60:63], v[0:1], off offset:112 ; GCN-NEXT: global_load_dwordx4 v[35:38], v[0:1], off offset:128
; GCN-NEXT: global_load_dwordx4 v[36:39], v[0:1], off offset:128 ; GCN-NEXT: global_load_dwordx4 v[48:51], v[0:1], off offset:144
; GCN-NEXT: global_load_dwordx4 v[32:35], v[0:1], off offset:144 ; GCN-NEXT: global_load_dwordx4 v[52:55], v[0:1], off offset:160
; GCN-NEXT: global_load_dwordx4 v[28:31], v[0:1], off offset:160 ; GCN-NEXT: global_load_dwordx4 v[39:42], v[0:1], off offset:176
; GCN-NEXT: global_load_dwordx4 v[52:55], v[0:1], off offset:176 ; GCN-NEXT: global_load_dwordx4 v[43:46], v[0:1], off offset:192
; GCN-NEXT: global_load_dwordx4 v[24:27], v[0:1], off offset:192 ; GCN-NEXT: global_load_dwordx4 v[56:59], v[0:1], off offset:208
; GCN-NEXT: global_load_dwordx4 v[7:10], v[0:1], off offset:208 ; GCN-NEXT: global_load_dwordx4 v[60:63], v[0:1], off offset:224
; GCN-NEXT: s_add_i32 s32, s32, 0x10000 ; GCN-NEXT: s_add_i32 s32, s32, 0x10000
; GCN-NEXT: s_add_i32 s32, s32, 0xffff0000 ; GCN-NEXT: s_add_i32 s32, s32, 0xffff0000
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:512 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:528 ; 4-byte Folded Spill
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:516 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:532 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:520 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:536 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v6, off, s[0:3], s33 offset:524 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s33 offset:540 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v7, off, s[0:3], s33 offset:528 ; 4-byte Folded Spill ; GCN-NEXT: global_load_dwordx4 v[60:63], v[0:1], off offset:240
; GCN-NEXT: buffer_store_dword v8, off, s[0:3], s33 offset:532 ; 4-byte Folded Spill ; GCN-NEXT: v_and_b32_e32 v0, 63, v2
; GCN-NEXT: buffer_store_dword v9, off, s[0:3], s33 offset:536 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v10, off, s[0:3], s33 offset:540 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v11, off, s[0:3], s33 offset:544 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v12, off, s[0:3], s33 offset:548 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v13, off, s[0:3], s33 offset:552 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s33 offset:556 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s33 offset:560 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v16, off, s[0:3], s33 offset:564 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v17, off, s[0:3], s33 offset:568 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s33 offset:572 ; 4-byte Folded Spill
; GCN-NEXT: global_load_dwordx4 v[8:11], v[0:1], off offset:224
; GCN-NEXT: global_load_dwordx4 v[12:15], v[0:1], off offset:240
; GCN-NEXT: v_lshrrev_b32_e64 v1, 6, s33 ; GCN-NEXT: v_lshrrev_b32_e64 v1, 6, s33
; GCN-NEXT: v_add_u32_e32 v1, 0x100, v1
; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:256
; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:260
; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:264
; GCN-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:268
; GCN-NEXT: buffer_store_dword v16, off, s[0:3], s33 offset:272
; GCN-NEXT: buffer_store_dword v17, off, s[0:3], s33 offset:276
; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s33 offset:280
; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s33 offset:284
; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s33 offset:288
; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s33 offset:292
; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s33 offset:296
; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s33 offset:300
; GCN-NEXT: buffer_store_dword v48, off, s[0:3], s33 offset:304
; GCN-NEXT: buffer_store_dword v49, off, s[0:3], s33 offset:308
; GCN-NEXT: buffer_store_dword v50, off, s[0:3], s33 offset:312
; GCN-NEXT: buffer_store_dword v51, off, s[0:3], s33 offset:316
; GCN-NEXT: buffer_store_dword v20, off, s[0:3], s33 offset:320
; GCN-NEXT: buffer_store_dword v21, off, s[0:3], s33 offset:324
; GCN-NEXT: buffer_store_dword v22, off, s[0:3], s33 offset:328
; GCN-NEXT: buffer_store_dword v23, off, s[0:3], s33 offset:332
; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:336
; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:340
; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s33 offset:344
; GCN-NEXT: buffer_store_dword v47, off, s[0:3], s33 offset:348
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:352
; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:356
; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:360
; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:364
; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:368
; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:372
; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:376
; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s33 offset:380
; GCN-NEXT: buffer_store_dword v36, off, s[0:3], s33 offset:384
; GCN-NEXT: buffer_store_dword v37, off, s[0:3], s33 offset:388
; GCN-NEXT: buffer_store_dword v38, off, s[0:3], s33 offset:392
; GCN-NEXT: buffer_store_dword v39, off, s[0:3], s33 offset:396
; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s33 offset:400
; GCN-NEXT: buffer_store_dword v33, off, s[0:3], s33 offset:404
; GCN-NEXT: buffer_store_dword v34, off, s[0:3], s33 offset:408
; GCN-NEXT: buffer_store_dword v35, off, s[0:3], s33 offset:412
; GCN-NEXT: buffer_store_dword v28, off, s[0:3], s33 offset:416
; GCN-NEXT: buffer_store_dword v29, off, s[0:3], s33 offset:420
; GCN-NEXT: buffer_store_dword v30, off, s[0:3], s33 offset:424
; GCN-NEXT: buffer_store_dword v31, off, s[0:3], s33 offset:428
; GCN-NEXT: buffer_store_dword v52, off, s[0:3], s33 offset:432
; GCN-NEXT: buffer_store_dword v53, off, s[0:3], s33 offset:436
; GCN-NEXT: buffer_store_dword v54, off, s[0:3], s33 offset:440
; GCN-NEXT: buffer_store_dword v55, off, s[0:3], s33 offset:444
; GCN-NEXT: buffer_store_dword v24, off, s[0:3], s33 offset:448
; GCN-NEXT: buffer_store_dword v25, off, s[0:3], s33 offset:452
; GCN-NEXT: buffer_store_dword v26, off, s[0:3], s33 offset:456
; GCN-NEXT: buffer_store_dword v27, off, s[0:3], s33 offset:460
; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s33 offset:512 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v17, off, s[0:3], s33 offset:516 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v18, off, s[0:3], s33 offset:520 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v19, off, s[0:3], s33 offset:524 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v20, off, s[0:3], s33 offset:528 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v21, off, s[0:3], s33 offset:532 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v22, off, s[0:3], s33 offset:536 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v23, off, s[0:3], s33 offset:540 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v24, off, s[0:3], s33 offset:544 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v25, off, s[0:3], s33 offset:548 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v26, off, s[0:3], s33 offset:552 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v27, off, s[0:3], s33 offset:556 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v28, off, s[0:3], s33 offset:560 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v29, off, s[0:3], s33 offset:564 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v30, off, s[0:3], s33 offset:568 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v31, off, s[0:3], s33 offset:572 ; 4-byte Folded Reload
; GCN-NEXT: v_and_b32_e32 v0, 63, v6
; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GCN-NEXT: v_add_u32_e32 v1, 0x100, v1
; GCN-NEXT: v_add_u32_e32 v0, v1, v0 ; GCN-NEXT: v_add_u32_e32 v0, v1, v0
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v16, v20 ; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:512 ; 4-byte Folded Spill
; GCN-NEXT: v_mov_b32_e32 v17, v21 ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v18, v22 ; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:516 ; 4-byte Folded Spill
; GCN-NEXT: v_mov_b32_e32 v19, v23 ; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:520 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v16, off, s[0:3], s33 offset:464 ; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s33 offset:524 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v17, off, s[0:3], s33 offset:468 ; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:256
; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s33 offset:472 ; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:260
; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s33 offset:476 ; GCN-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:264
; GCN-NEXT: buffer_store_dword v8, off, s[0:3], s33 offset:480 ; GCN-NEXT: buffer_store_dword v6, off, s[0:3], s33 offset:268
; GCN-NEXT: buffer_store_dword v9, off, s[0:3], s33 offset:484 ; GCN-NEXT: buffer_store_dword v7, off, s[0:3], s33 offset:272
; GCN-NEXT: buffer_store_dword v10, off, s[0:3], s33 offset:488 ; GCN-NEXT: buffer_store_dword v8, off, s[0:3], s33 offset:276
; GCN-NEXT: buffer_store_dword v11, off, s[0:3], s33 offset:492 ; GCN-NEXT: buffer_store_dword v9, off, s[0:3], s33 offset:280
; GCN-NEXT: buffer_store_dword v12, off, s[0:3], s33 offset:496 ; GCN-NEXT: buffer_store_dword v10, off, s[0:3], s33 offset:284
; GCN-NEXT: buffer_store_dword v13, off, s[0:3], s33 offset:500 ; GCN-NEXT: buffer_store_dword v11, off, s[0:3], s33 offset:288
; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s33 offset:504 ; GCN-NEXT: buffer_store_dword v12, off, s[0:3], s33 offset:292
; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s33 offset:508 ; GCN-NEXT: buffer_store_dword v13, off, s[0:3], s33 offset:296
; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s33 offset:300
; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s33 offset:304
; GCN-NEXT: buffer_store_dword v16, off, s[0:3], s33 offset:308
; GCN-NEXT: buffer_store_dword v17, off, s[0:3], s33 offset:312
; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s33 offset:316
; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s33 offset:320
; GCN-NEXT: buffer_store_dword v20, off, s[0:3], s33 offset:324
; GCN-NEXT: buffer_store_dword v21, off, s[0:3], s33 offset:328
; GCN-NEXT: buffer_store_dword v22, off, s[0:3], s33 offset:332
; GCN-NEXT: buffer_store_dword v23, off, s[0:3], s33 offset:336
; GCN-NEXT: buffer_store_dword v24, off, s[0:3], s33 offset:340
; GCN-NEXT: buffer_store_dword v25, off, s[0:3], s33 offset:344
; GCN-NEXT: buffer_store_dword v26, off, s[0:3], s33 offset:348
; GCN-NEXT: buffer_store_dword v27, off, s[0:3], s33 offset:352
; GCN-NEXT: buffer_store_dword v28, off, s[0:3], s33 offset:356
; GCN-NEXT: buffer_store_dword v29, off, s[0:3], s33 offset:360
; GCN-NEXT: buffer_store_dword v30, off, s[0:3], s33 offset:364
; GCN-NEXT: buffer_store_dword v31, off, s[0:3], s33 offset:368
; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s33 offset:372
; GCN-NEXT: buffer_store_dword v33, off, s[0:3], s33 offset:376
; GCN-NEXT: buffer_store_dword v34, off, s[0:3], s33 offset:380
; GCN-NEXT: buffer_store_dword v35, off, s[0:3], s33 offset:384
; GCN-NEXT: buffer_store_dword v36, off, s[0:3], s33 offset:388
; GCN-NEXT: buffer_store_dword v37, off, s[0:3], s33 offset:392
; GCN-NEXT: buffer_store_dword v38, off, s[0:3], s33 offset:396
; GCN-NEXT: buffer_store_dword v48, off, s[0:3], s33 offset:400
; GCN-NEXT: buffer_store_dword v49, off, s[0:3], s33 offset:404
; GCN-NEXT: buffer_store_dword v50, off, s[0:3], s33 offset:408
; GCN-NEXT: buffer_store_dword v51, off, s[0:3], s33 offset:412
; GCN-NEXT: buffer_store_dword v52, off, s[0:3], s33 offset:416
; GCN-NEXT: buffer_store_dword v53, off, s[0:3], s33 offset:420
; GCN-NEXT: buffer_store_dword v54, off, s[0:3], s33 offset:424
; GCN-NEXT: buffer_store_dword v55, off, s[0:3], s33 offset:428
; GCN-NEXT: buffer_store_dword v39, off, s[0:3], s33 offset:432
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:436
; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:440
; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:444
; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:448
; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:452
; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:456
; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s33 offset:460
; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s33 offset:464
; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s33 offset:468
; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s33 offset:472
; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s33 offset:476
; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s33 offset:528 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s33 offset:532 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s33 offset:536 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s33 offset:540 ; 4-byte Folded Reload
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:480
; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:484
; GCN-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:488
; GCN-NEXT: buffer_store_dword v6, off, s[0:3], s33 offset:492
; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s33 offset:512 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s33 offset:516 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s33 offset:520 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s33 offset:524 ; 4-byte Folded Reload
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:496
; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:500
; GCN-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:504
; GCN-NEXT: buffer_store_dword v6, off, s[0:3], s33 offset:508
; GCN-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen ; GCN-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen
; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s33 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s33 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v61, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v61, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v60, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v60, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v59, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v59, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v58, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v58, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v57, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v57, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v56, off, s[0:3], s33 offset:28 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v56, off, s[0:3], s33 offset:28 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v47, off, s[0:3], s33 offset:32 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v46, off, s[0:3], s33 offset:32 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v46, off, s[0:3], s33 offset:36 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v45, off, s[0:3], s33 offset:36 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v45, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v44, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v44, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s33 offset:48 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:48 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:52 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:52 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:56 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:56 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:60 ; 4-byte Folded Reload
; GCN-NEXT: s_mov_b32 s33, s4 ; GCN-NEXT: s_mov_b32 s33, s4
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
%vec = load <64 x i32>, ptr addrspace(1) %ptr %vec = load <64 x i32>, ptr addrspace(1) %ptr
%elt = extractelement <64 x i32> %vec, i32 %idx %elt = extractelement <64 x i32> %vec, i32 %idx
ret i32 %elt ret i32 %elt
} }
define i16 @v_extract_v128i16_varidx(ptr addrspace(1) %ptr, i32 %idx) { define i16 @v_extract_v128i16_varidx(ptr addrspace(1) %ptr, i32 %idx) {
; GCN-LABEL: v_extract_v128i16_varidx: ; GCN-LABEL: v_extract_v128i16_varidx:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s4, s33 ; GCN-NEXT: s_mov_b32 s4, s33
; GCN-NEXT: s_add_i32 s33, s32, 0x3fc0 ; GCN-NEXT: s_add_i32 s33, s32, 0x3fc0
; GCN-NEXT: s_and_b32 s33, s33, 0xffffc000 ; GCN-NEXT: s_and_b32 s33, s33, 0xffffc000
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:60 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:56 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:56 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v47, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s33 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s33 ; 4-byte Folded Spill
; GCN-NEXT: v_mov_b32_e32 v6, v2 ; GCN-NEXT: global_load_dwordx4 v[3:6], v[0:1], off
; GCN-NEXT: global_load_dwordx4 v[2:5], v[0:1], off ; GCN-NEXT: global_load_dwordx4 v[7:10], v[0:1], off offset:16
; GCN-NEXT: global_load_dwordx4 v[16:19], v[0:1], off offset:16 ; GCN-NEXT: global_load_dwordx4 v[11:14], v[0:1], off offset:32
; GCN-NEXT: global_load_dwordx4 v[56:59], v[0:1], off offset:32 ; GCN-NEXT: global_load_dwordx4 v[15:18], v[0:1], off offset:48
; GCN-NEXT: global_load_dwordx4 v[48:51], v[0:1], off offset:48 ; GCN-NEXT: global_load_dwordx4 v[19:22], v[0:1], off offset:64
; GCN-NEXT: global_load_dwordx4 v[20:23], v[0:1], off offset:64 ; GCN-NEXT: global_load_dwordx4 v[23:26], v[0:1], off offset:80
; GCN-NEXT: global_load_dwordx4 v[44:47], v[0:1], off offset:80 ; GCN-NEXT: global_load_dwordx4 v[27:30], v[0:1], off offset:96
; GCN-NEXT: global_load_dwordx4 v[40:43], v[0:1], off offset:96 ; GCN-NEXT: global_load_dwordx4 v[31:34], v[0:1], off offset:112
; GCN-NEXT: global_load_dwordx4 v[60:63], v[0:1], off offset:112 ; GCN-NEXT: global_load_dwordx4 v[35:38], v[0:1], off offset:128
; GCN-NEXT: global_load_dwordx4 v[36:39], v[0:1], off offset:128 ; GCN-NEXT: global_load_dwordx4 v[48:51], v[0:1], off offset:144
; GCN-NEXT: global_load_dwordx4 v[32:35], v[0:1], off offset:144 ; GCN-NEXT: global_load_dwordx4 v[52:55], v[0:1], off offset:160
; GCN-NEXT: global_load_dwordx4 v[28:31], v[0:1], off offset:160 ; GCN-NEXT: global_load_dwordx4 v[39:42], v[0:1], off offset:176
; GCN-NEXT: global_load_dwordx4 v[52:55], v[0:1], off offset:176 ; GCN-NEXT: global_load_dwordx4 v[43:46], v[0:1], off offset:192
; GCN-NEXT: global_load_dwordx4 v[24:27], v[0:1], off offset:192 ; GCN-NEXT: global_load_dwordx4 v[56:59], v[0:1], off offset:208
; GCN-NEXT: global_load_dwordx4 v[7:10], v[0:1], off offset:208 ; GCN-NEXT: global_load_dwordx4 v[60:63], v[0:1], off offset:224
; GCN-NEXT: s_add_i32 s32, s32, 0x10000 ; GCN-NEXT: s_add_i32 s32, s32, 0x10000
; GCN-NEXT: s_add_i32 s32, s32, 0xffff0000 ; GCN-NEXT: s_add_i32 s32, s32, 0xffff0000
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:512 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:528 ; 4-byte Folded Spill
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:516 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:532 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:520 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:536 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v6, off, s[0:3], s33 offset:524 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s33 offset:540 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v7, off, s[0:3], s33 offset:528 ; 4-byte Folded Spill ; GCN-NEXT: global_load_dwordx4 v[60:63], v[0:1], off offset:240
; GCN-NEXT: buffer_store_dword v8, off, s[0:3], s33 offset:532 ; 4-byte Folded Spill ; GCN-NEXT: v_bfe_u32 v0, v2, 1, 6
; GCN-NEXT: buffer_store_dword v9, off, s[0:3], s33 offset:536 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v10, off, s[0:3], s33 offset:540 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v11, off, s[0:3], s33 offset:544 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v12, off, s[0:3], s33 offset:548 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v13, off, s[0:3], s33 offset:552 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s33 offset:556 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s33 offset:560 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v16, off, s[0:3], s33 offset:564 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v17, off, s[0:3], s33 offset:568 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s33 offset:572 ; 4-byte Folded Spill
; GCN-NEXT: global_load_dwordx4 v[8:11], v[0:1], off offset:224
; GCN-NEXT: global_load_dwordx4 v[12:15], v[0:1], off offset:240
; GCN-NEXT: v_lshrrev_b32_e64 v1, 6, s33 ; GCN-NEXT: v_lshrrev_b32_e64 v1, 6, s33
; GCN-NEXT: v_add_u32_e32 v1, 0x100, v1
; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:256
; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:260
; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:264
; GCN-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:268
; GCN-NEXT: buffer_store_dword v16, off, s[0:3], s33 offset:272
; GCN-NEXT: buffer_store_dword v17, off, s[0:3], s33 offset:276
; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s33 offset:280
; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s33 offset:284
; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s33 offset:288
; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s33 offset:292
; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s33 offset:296
; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s33 offset:300
; GCN-NEXT: buffer_store_dword v48, off, s[0:3], s33 offset:304
; GCN-NEXT: buffer_store_dword v49, off, s[0:3], s33 offset:308
; GCN-NEXT: buffer_store_dword v50, off, s[0:3], s33 offset:312
; GCN-NEXT: buffer_store_dword v51, off, s[0:3], s33 offset:316
; GCN-NEXT: buffer_store_dword v20, off, s[0:3], s33 offset:320
; GCN-NEXT: buffer_store_dword v21, off, s[0:3], s33 offset:324
; GCN-NEXT: buffer_store_dword v22, off, s[0:3], s33 offset:328
; GCN-NEXT: buffer_store_dword v23, off, s[0:3], s33 offset:332
; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:336
; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:340
; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s33 offset:344
; GCN-NEXT: buffer_store_dword v47, off, s[0:3], s33 offset:348
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:352
; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:356
; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:360
; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:364
; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:368
; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:372
; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:376
; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s33 offset:380
; GCN-NEXT: buffer_store_dword v36, off, s[0:3], s33 offset:384
; GCN-NEXT: buffer_store_dword v37, off, s[0:3], s33 offset:388
; GCN-NEXT: buffer_store_dword v38, off, s[0:3], s33 offset:392
; GCN-NEXT: buffer_store_dword v39, off, s[0:3], s33 offset:396
; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s33 offset:400
; GCN-NEXT: buffer_store_dword v33, off, s[0:3], s33 offset:404
; GCN-NEXT: buffer_store_dword v34, off, s[0:3], s33 offset:408
; GCN-NEXT: buffer_store_dword v35, off, s[0:3], s33 offset:412
; GCN-NEXT: buffer_store_dword v28, off, s[0:3], s33 offset:416
; GCN-NEXT: buffer_store_dword v29, off, s[0:3], s33 offset:420
; GCN-NEXT: buffer_store_dword v30, off, s[0:3], s33 offset:424
; GCN-NEXT: buffer_store_dword v31, off, s[0:3], s33 offset:428
; GCN-NEXT: buffer_store_dword v52, off, s[0:3], s33 offset:432
; GCN-NEXT: buffer_store_dword v53, off, s[0:3], s33 offset:436
; GCN-NEXT: buffer_store_dword v54, off, s[0:3], s33 offset:440
; GCN-NEXT: buffer_store_dword v55, off, s[0:3], s33 offset:444
; GCN-NEXT: buffer_store_dword v24, off, s[0:3], s33 offset:448
; GCN-NEXT: buffer_store_dword v25, off, s[0:3], s33 offset:452
; GCN-NEXT: buffer_store_dword v26, off, s[0:3], s33 offset:456
; GCN-NEXT: buffer_store_dword v27, off, s[0:3], s33 offset:460
; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s33 offset:512 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v17, off, s[0:3], s33 offset:516 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v18, off, s[0:3], s33 offset:520 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v19, off, s[0:3], s33 offset:524 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v20, off, s[0:3], s33 offset:528 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v21, off, s[0:3], s33 offset:532 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v22, off, s[0:3], s33 offset:536 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v23, off, s[0:3], s33 offset:540 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v24, off, s[0:3], s33 offset:544 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v25, off, s[0:3], s33 offset:548 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v26, off, s[0:3], s33 offset:552 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v27, off, s[0:3], s33 offset:556 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v28, off, s[0:3], s33 offset:560 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v29, off, s[0:3], s33 offset:564 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v30, off, s[0:3], s33 offset:568 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v31, off, s[0:3], s33 offset:572 ; 4-byte Folded Reload
; GCN-NEXT: v_bfe_u32 v0, v6, 1, 6
; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GCN-NEXT: v_add_u32_e32 v1, 0x100, v1
; GCN-NEXT: v_add_u32_e32 v0, v1, v0 ; GCN-NEXT: v_add_u32_e32 v0, v1, v0
; GCN-NEXT: v_and_b32_e32 v1, 1, v6 ; GCN-NEXT: v_and_b32_e32 v1, 1, v2
; GCN-NEXT: v_lshlrev_b32_e32 v1, 4, v1 ; GCN-NEXT: v_lshlrev_b32_e32 v1, 4, v1
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v16, v20 ; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:512 ; 4-byte Folded Spill
; GCN-NEXT: v_mov_b32_e32 v17, v21 ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v18, v22 ; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:516 ; 4-byte Folded Spill
; GCN-NEXT: v_mov_b32_e32 v19, v23 ; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:520 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v16, off, s[0:3], s33 offset:464 ; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s33 offset:524 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v17, off, s[0:3], s33 offset:468 ; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:256
; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s33 offset:472 ; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:260
; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s33 offset:476 ; GCN-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:264
; GCN-NEXT: buffer_store_dword v8, off, s[0:3], s33 offset:480 ; GCN-NEXT: buffer_store_dword v6, off, s[0:3], s33 offset:268
; GCN-NEXT: buffer_store_dword v9, off, s[0:3], s33 offset:484 ; GCN-NEXT: buffer_store_dword v7, off, s[0:3], s33 offset:272
; GCN-NEXT: buffer_store_dword v10, off, s[0:3], s33 offset:488 ; GCN-NEXT: buffer_store_dword v8, off, s[0:3], s33 offset:276
; GCN-NEXT: buffer_store_dword v11, off, s[0:3], s33 offset:492 ; GCN-NEXT: buffer_store_dword v9, off, s[0:3], s33 offset:280
; GCN-NEXT: buffer_store_dword v12, off, s[0:3], s33 offset:496 ; GCN-NEXT: buffer_store_dword v10, off, s[0:3], s33 offset:284
; GCN-NEXT: buffer_store_dword v13, off, s[0:3], s33 offset:500 ; GCN-NEXT: buffer_store_dword v11, off, s[0:3], s33 offset:288
; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s33 offset:504 ; GCN-NEXT: buffer_store_dword v12, off, s[0:3], s33 offset:292
; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s33 offset:508 ; GCN-NEXT: buffer_store_dword v13, off, s[0:3], s33 offset:296
; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s33 offset:300
; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s33 offset:304
; GCN-NEXT: buffer_store_dword v16, off, s[0:3], s33 offset:308
; GCN-NEXT: buffer_store_dword v17, off, s[0:3], s33 offset:312
; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s33 offset:316
; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s33 offset:320
; GCN-NEXT: buffer_store_dword v20, off, s[0:3], s33 offset:324
; GCN-NEXT: buffer_store_dword v21, off, s[0:3], s33 offset:328
; GCN-NEXT: buffer_store_dword v22, off, s[0:3], s33 offset:332
; GCN-NEXT: buffer_store_dword v23, off, s[0:3], s33 offset:336
; GCN-NEXT: buffer_store_dword v24, off, s[0:3], s33 offset:340
; GCN-NEXT: buffer_store_dword v25, off, s[0:3], s33 offset:344
; GCN-NEXT: buffer_store_dword v26, off, s[0:3], s33 offset:348
; GCN-NEXT: buffer_store_dword v27, off, s[0:3], s33 offset:352
; GCN-NEXT: buffer_store_dword v28, off, s[0:3], s33 offset:356
; GCN-NEXT: buffer_store_dword v29, off, s[0:3], s33 offset:360
; GCN-NEXT: buffer_store_dword v30, off, s[0:3], s33 offset:364
; GCN-NEXT: buffer_store_dword v31, off, s[0:3], s33 offset:368
; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s33 offset:372
; GCN-NEXT: buffer_store_dword v33, off, s[0:3], s33 offset:376
; GCN-NEXT: buffer_store_dword v34, off, s[0:3], s33 offset:380
; GCN-NEXT: buffer_store_dword v35, off, s[0:3], s33 offset:384
; GCN-NEXT: buffer_store_dword v36, off, s[0:3], s33 offset:388
; GCN-NEXT: buffer_store_dword v37, off, s[0:3], s33 offset:392
; GCN-NEXT: buffer_store_dword v38, off, s[0:3], s33 offset:396
; GCN-NEXT: buffer_store_dword v48, off, s[0:3], s33 offset:400
; GCN-NEXT: buffer_store_dword v49, off, s[0:3], s33 offset:404
; GCN-NEXT: buffer_store_dword v50, off, s[0:3], s33 offset:408
; GCN-NEXT: buffer_store_dword v51, off, s[0:3], s33 offset:412
; GCN-NEXT: buffer_store_dword v52, off, s[0:3], s33 offset:416
; GCN-NEXT: buffer_store_dword v53, off, s[0:3], s33 offset:420
; GCN-NEXT: buffer_store_dword v54, off, s[0:3], s33 offset:424
; GCN-NEXT: buffer_store_dword v55, off, s[0:3], s33 offset:428
; GCN-NEXT: buffer_store_dword v39, off, s[0:3], s33 offset:432
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:436
; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:440
; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:444
; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:448
; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:452
; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:456
; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s33 offset:460
; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s33 offset:464
; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s33 offset:468
; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s33 offset:472
; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s33 offset:476
; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s33 offset:528 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s33 offset:532 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s33 offset:536 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s33 offset:540 ; 4-byte Folded Reload
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:480
; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:484
; GCN-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:488
; GCN-NEXT: buffer_store_dword v6, off, s[0:3], s33 offset:492
; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s33 offset:512 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s33 offset:516 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s33 offset:520 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s33 offset:524 ; 4-byte Folded Reload
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:496
; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:500
; GCN-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:504
; GCN-NEXT: buffer_store_dword v6, off, s[0:3], s33 offset:508
; GCN-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen ; GCN-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen
; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s33 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s33 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v61, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v61, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v60, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v60, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v59, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v59, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v58, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v58, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v57, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v57, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v56, off, s[0:3], s33 offset:28 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v56, off, s[0:3], s33 offset:28 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v47, off, s[0:3], s33 offset:32 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v46, off, s[0:3], s33 offset:32 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v46, off, s[0:3], s33 offset:36 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v45, off, s[0:3], s33 offset:36 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v45, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v44, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v44, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s33 offset:48 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:48 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:52 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:52 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:56 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:56 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:60 ; 4-byte Folded Reload
; GCN-NEXT: s_mov_b32 s33, s4 ; GCN-NEXT: s_mov_b32 s33, s4
; GCN-NEXT: s_waitcnt vmcnt(16) ; GCN-NEXT: s_waitcnt vmcnt(15)
; GCN-NEXT: v_lshrrev_b32_e32 v0, v1, v0 ; GCN-NEXT: v_lshrrev_b32_e32 v0, v1, v0
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
%vec = load <128 x i16>, ptr addrspace(1) %ptr %vec = load <128 x i16>, ptr addrspace(1) %ptr
%elt = extractelement <128 x i16> %vec, i32 %idx %elt = extractelement <128 x i16> %vec, i32 %idx
ret i16 %elt ret i16 %elt
} }
define i64 @v_extract_v32i64_varidx(ptr addrspace(1) %ptr, i32 %idx) { define i64 @v_extract_v32i64_varidx(ptr addrspace(1) %ptr, i32 %idx) {
; GCN-LABEL: v_extract_v32i64_varidx: ; GCN-LABEL: v_extract_v32i64_varidx:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s4, s33 ; GCN-NEXT: s_mov_b32 s4, s33
; GCN-NEXT: s_add_i32 s33, s32, 0x3fc0 ; GCN-NEXT: s_add_i32 s33, s32, 0x3fc0
; GCN-NEXT: s_and_b32 s33, s33, 0xffffc000 ; GCN-NEXT: s_and_b32 s33, s33, 0xffffc000
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:60 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:56 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:56 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v47, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s33 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s33 ; 4-byte Folded Spill
; GCN-NEXT: v_mov_b32_e32 v6, v2 ; GCN-NEXT: global_load_dwordx4 v[3:6], v[0:1], off
; GCN-NEXT: global_load_dwordx4 v[2:5], v[0:1], off ; GCN-NEXT: global_load_dwordx4 v[7:10], v[0:1], off offset:16
; GCN-NEXT: global_load_dwordx4 v[16:19], v[0:1], off offset:16 ; GCN-NEXT: global_load_dwordx4 v[11:14], v[0:1], off offset:32
; GCN-NEXT: global_load_dwordx4 v[56:59], v[0:1], off offset:32 ; GCN-NEXT: global_load_dwordx4 v[15:18], v[0:1], off offset:48
; GCN-NEXT: global_load_dwordx4 v[48:51], v[0:1], off offset:48 ; GCN-NEXT: global_load_dwordx4 v[19:22], v[0:1], off offset:64
; GCN-NEXT: global_load_dwordx4 v[20:23], v[0:1], off offset:64 ; GCN-NEXT: global_load_dwordx4 v[23:26], v[0:1], off offset:80
; GCN-NEXT: global_load_dwordx4 v[44:47], v[0:1], off offset:80 ; GCN-NEXT: global_load_dwordx4 v[27:30], v[0:1], off offset:96
; GCN-NEXT: global_load_dwordx4 v[40:43], v[0:1], off offset:96 ; GCN-NEXT: global_load_dwordx4 v[31:34], v[0:1], off offset:112
; GCN-NEXT: global_load_dwordx4 v[60:63], v[0:1], off offset:112 ; GCN-NEXT: global_load_dwordx4 v[35:38], v[0:1], off offset:128
; GCN-NEXT: global_load_dwordx4 v[36:39], v[0:1], off offset:128 ; GCN-NEXT: global_load_dwordx4 v[48:51], v[0:1], off offset:144
; GCN-NEXT: global_load_dwordx4 v[32:35], v[0:1], off offset:144 ; GCN-NEXT: global_load_dwordx4 v[52:55], v[0:1], off offset:160
; GCN-NEXT: global_load_dwordx4 v[28:31], v[0:1], off offset:160 ; GCN-NEXT: global_load_dwordx4 v[39:42], v[0:1], off offset:176
; GCN-NEXT: global_load_dwordx4 v[52:55], v[0:1], off offset:176 ; GCN-NEXT: global_load_dwordx4 v[43:46], v[0:1], off offset:192
; GCN-NEXT: global_load_dwordx4 v[24:27], v[0:1], off offset:192 ; GCN-NEXT: global_load_dwordx4 v[56:59], v[0:1], off offset:208
; GCN-NEXT: global_load_dwordx4 v[7:10], v[0:1], off offset:208 ; GCN-NEXT: global_load_dwordx4 v[60:63], v[0:1], off offset:224
; GCN-NEXT: s_add_i32 s32, s32, 0x10000 ; GCN-NEXT: s_add_i32 s32, s32, 0x10000
; GCN-NEXT: s_add_i32 s32, s32, 0xffff0000 ; GCN-NEXT: s_add_i32 s32, s32, 0xffff0000
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:512 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:528 ; 4-byte Folded Spill
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:516 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:532 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:520 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:536 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v6, off, s[0:3], s33 offset:524 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s33 offset:540 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v7, off, s[0:3], s33 offset:528 ; 4-byte Folded Spill ; GCN-NEXT: global_load_dwordx4 v[60:63], v[0:1], off offset:240
; GCN-NEXT: buffer_store_dword v8, off, s[0:3], s33 offset:532 ; 4-byte Folded Spill ; GCN-NEXT: v_and_b32_e32 v0, 31, v2
; GCN-NEXT: buffer_store_dword v9, off, s[0:3], s33 offset:536 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v10, off, s[0:3], s33 offset:540 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v11, off, s[0:3], s33 offset:544 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v12, off, s[0:3], s33 offset:548 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v13, off, s[0:3], s33 offset:552 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s33 offset:556 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s33 offset:560 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v16, off, s[0:3], s33 offset:564 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v17, off, s[0:3], s33 offset:568 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s33 offset:572 ; 4-byte Folded Spill
; GCN-NEXT: global_load_dwordx4 v[8:11], v[0:1], off offset:224
; GCN-NEXT: global_load_dwordx4 v[12:15], v[0:1], off offset:240
; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:256
; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:260
; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:264
; GCN-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:268
; GCN-NEXT: buffer_store_dword v16, off, s[0:3], s33 offset:272
; GCN-NEXT: buffer_store_dword v17, off, s[0:3], s33 offset:276
; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s33 offset:280
; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s33 offset:284
; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s33 offset:288
; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s33 offset:292
; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s33 offset:296
; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s33 offset:300
; GCN-NEXT: buffer_store_dword v48, off, s[0:3], s33 offset:304
; GCN-NEXT: buffer_store_dword v49, off, s[0:3], s33 offset:308
; GCN-NEXT: buffer_store_dword v50, off, s[0:3], s33 offset:312
; GCN-NEXT: buffer_store_dword v51, off, s[0:3], s33 offset:316
; GCN-NEXT: buffer_store_dword v20, off, s[0:3], s33 offset:320
; GCN-NEXT: buffer_store_dword v21, off, s[0:3], s33 offset:324
; GCN-NEXT: buffer_store_dword v22, off, s[0:3], s33 offset:328
; GCN-NEXT: buffer_store_dword v23, off, s[0:3], s33 offset:332
; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:336
; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:340
; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s33 offset:344
; GCN-NEXT: buffer_store_dword v47, off, s[0:3], s33 offset:348
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:352
; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:356
; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:360
; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:364
; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:368
; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:372
; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:376
; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s33 offset:380
; GCN-NEXT: buffer_store_dword v36, off, s[0:3], s33 offset:384
; GCN-NEXT: buffer_store_dword v37, off, s[0:3], s33 offset:388
; GCN-NEXT: buffer_store_dword v38, off, s[0:3], s33 offset:392
; GCN-NEXT: buffer_store_dword v39, off, s[0:3], s33 offset:396
; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s33 offset:400
; GCN-NEXT: buffer_store_dword v33, off, s[0:3], s33 offset:404
; GCN-NEXT: buffer_store_dword v34, off, s[0:3], s33 offset:408
; GCN-NEXT: buffer_store_dword v35, off, s[0:3], s33 offset:412
; GCN-NEXT: buffer_store_dword v28, off, s[0:3], s33 offset:416
; GCN-NEXT: buffer_store_dword v29, off, s[0:3], s33 offset:420
; GCN-NEXT: buffer_store_dword v30, off, s[0:3], s33 offset:424
; GCN-NEXT: buffer_store_dword v31, off, s[0:3], s33 offset:428
; GCN-NEXT: buffer_store_dword v52, off, s[0:3], s33 offset:432
; GCN-NEXT: buffer_store_dword v53, off, s[0:3], s33 offset:436
; GCN-NEXT: buffer_store_dword v54, off, s[0:3], s33 offset:440
; GCN-NEXT: buffer_store_dword v55, off, s[0:3], s33 offset:444
; GCN-NEXT: buffer_store_dword v24, off, s[0:3], s33 offset:448
; GCN-NEXT: buffer_store_dword v25, off, s[0:3], s33 offset:452
; GCN-NEXT: buffer_store_dword v26, off, s[0:3], s33 offset:456
; GCN-NEXT: buffer_store_dword v27, off, s[0:3], s33 offset:460
; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s33 offset:512 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v17, off, s[0:3], s33 offset:516 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v18, off, s[0:3], s33 offset:520 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v19, off, s[0:3], s33 offset:524 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v20, off, s[0:3], s33 offset:528 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v21, off, s[0:3], s33 offset:532 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v22, off, s[0:3], s33 offset:536 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v23, off, s[0:3], s33 offset:540 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v24, off, s[0:3], s33 offset:544 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v25, off, s[0:3], s33 offset:548 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v26, off, s[0:3], s33 offset:552 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v27, off, s[0:3], s33 offset:556 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v28, off, s[0:3], s33 offset:560 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v29, off, s[0:3], s33 offset:564 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v30, off, s[0:3], s33 offset:568 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v31, off, s[0:3], s33 offset:572 ; 4-byte Folded Reload
; GCN-NEXT: v_and_b32_e32 v0, 31, v6
; GCN-NEXT: v_lshrrev_b32_e64 v2, 6, s33 ; GCN-NEXT: v_lshrrev_b32_e64 v2, 6, s33
; GCN-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; GCN-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GCN-NEXT: v_add_u32_e32 v2, 0x100, v2 ; GCN-NEXT: v_add_u32_e32 v2, 0x100, v2
; GCN-NEXT: v_add_u32_e32 v1, v2, v0 ; GCN-NEXT: v_add_u32_e32 v1, v2, v0
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v16, v20 ; GCN-NEXT: buffer_store_dword v60, off, s[0:3], s33 offset:512 ; 4-byte Folded Spill
; GCN-NEXT: v_mov_b32_e32 v17, v21 ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v18, v22 ; GCN-NEXT: buffer_store_dword v61, off, s[0:3], s33 offset:516 ; 4-byte Folded Spill
; GCN-NEXT: v_mov_b32_e32 v19, v23 ; GCN-NEXT: buffer_store_dword v62, off, s[0:3], s33 offset:520 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v16, off, s[0:3], s33 offset:464 ; GCN-NEXT: buffer_store_dword v63, off, s[0:3], s33 offset:524 ; 4-byte Folded Spill
; GCN-NEXT: buffer_store_dword v17, off, s[0:3], s33 offset:468 ; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:256
; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s33 offset:472 ; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:260
; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s33 offset:476 ; GCN-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:264
; GCN-NEXT: buffer_store_dword v8, off, s[0:3], s33 offset:480 ; GCN-NEXT: buffer_store_dword v6, off, s[0:3], s33 offset:268
; GCN-NEXT: buffer_store_dword v9, off, s[0:3], s33 offset:484 ; GCN-NEXT: buffer_store_dword v7, off, s[0:3], s33 offset:272
; GCN-NEXT: buffer_store_dword v10, off, s[0:3], s33 offset:488 ; GCN-NEXT: buffer_store_dword v8, off, s[0:3], s33 offset:276
; GCN-NEXT: buffer_store_dword v11, off, s[0:3], s33 offset:492 ; GCN-NEXT: buffer_store_dword v9, off, s[0:3], s33 offset:280
; GCN-NEXT: buffer_store_dword v12, off, s[0:3], s33 offset:496 ; GCN-NEXT: buffer_store_dword v10, off, s[0:3], s33 offset:284
; GCN-NEXT: buffer_store_dword v13, off, s[0:3], s33 offset:500 ; GCN-NEXT: buffer_store_dword v11, off, s[0:3], s33 offset:288
; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s33 offset:504 ; GCN-NEXT: buffer_store_dword v12, off, s[0:3], s33 offset:292
; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s33 offset:508 ; GCN-NEXT: buffer_store_dword v13, off, s[0:3], s33 offset:296
; GCN-NEXT: buffer_store_dword v14, off, s[0:3], s33 offset:300
; GCN-NEXT: buffer_store_dword v15, off, s[0:3], s33 offset:304
; GCN-NEXT: buffer_store_dword v16, off, s[0:3], s33 offset:308
; GCN-NEXT: buffer_store_dword v17, off, s[0:3], s33 offset:312
; GCN-NEXT: buffer_store_dword v18, off, s[0:3], s33 offset:316
; GCN-NEXT: buffer_store_dword v19, off, s[0:3], s33 offset:320
; GCN-NEXT: buffer_store_dword v20, off, s[0:3], s33 offset:324
; GCN-NEXT: buffer_store_dword v21, off, s[0:3], s33 offset:328
; GCN-NEXT: buffer_store_dword v22, off, s[0:3], s33 offset:332
; GCN-NEXT: buffer_store_dword v23, off, s[0:3], s33 offset:336
; GCN-NEXT: buffer_store_dword v24, off, s[0:3], s33 offset:340
; GCN-NEXT: buffer_store_dword v25, off, s[0:3], s33 offset:344
; GCN-NEXT: buffer_store_dword v26, off, s[0:3], s33 offset:348
; GCN-NEXT: buffer_store_dword v27, off, s[0:3], s33 offset:352
; GCN-NEXT: buffer_store_dword v28, off, s[0:3], s33 offset:356
; GCN-NEXT: buffer_store_dword v29, off, s[0:3], s33 offset:360
; GCN-NEXT: buffer_store_dword v30, off, s[0:3], s33 offset:364
; GCN-NEXT: buffer_store_dword v31, off, s[0:3], s33 offset:368
; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s33 offset:372
; GCN-NEXT: buffer_store_dword v33, off, s[0:3], s33 offset:376
; GCN-NEXT: buffer_store_dword v34, off, s[0:3], s33 offset:380
; GCN-NEXT: buffer_store_dword v35, off, s[0:3], s33 offset:384
; GCN-NEXT: buffer_store_dword v36, off, s[0:3], s33 offset:388
; GCN-NEXT: buffer_store_dword v37, off, s[0:3], s33 offset:392
; GCN-NEXT: buffer_store_dword v38, off, s[0:3], s33 offset:396
; GCN-NEXT: buffer_store_dword v48, off, s[0:3], s33 offset:400
; GCN-NEXT: buffer_store_dword v49, off, s[0:3], s33 offset:404
; GCN-NEXT: buffer_store_dword v50, off, s[0:3], s33 offset:408
; GCN-NEXT: buffer_store_dword v51, off, s[0:3], s33 offset:412
; GCN-NEXT: buffer_store_dword v52, off, s[0:3], s33 offset:416
; GCN-NEXT: buffer_store_dword v53, off, s[0:3], s33 offset:420
; GCN-NEXT: buffer_store_dword v54, off, s[0:3], s33 offset:424
; GCN-NEXT: buffer_store_dword v55, off, s[0:3], s33 offset:428
; GCN-NEXT: buffer_store_dword v39, off, s[0:3], s33 offset:432
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:436
; GCN-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:440
; GCN-NEXT: buffer_store_dword v42, off, s[0:3], s33 offset:444
; GCN-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:448
; GCN-NEXT: buffer_store_dword v44, off, s[0:3], s33 offset:452
; GCN-NEXT: buffer_store_dword v45, off, s[0:3], s33 offset:456
; GCN-NEXT: buffer_store_dword v46, off, s[0:3], s33 offset:460
; GCN-NEXT: buffer_store_dword v56, off, s[0:3], s33 offset:464
; GCN-NEXT: buffer_store_dword v57, off, s[0:3], s33 offset:468
; GCN-NEXT: buffer_store_dword v58, off, s[0:3], s33 offset:472
; GCN-NEXT: buffer_store_dword v59, off, s[0:3], s33 offset:476
; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s33 offset:528 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s33 offset:532 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s33 offset:536 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s33 offset:540 ; 4-byte Folded Reload
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:480
; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:484
; GCN-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:488
; GCN-NEXT: buffer_store_dword v6, off, s[0:3], s33 offset:492
; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s33 offset:512 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v4, off, s[0:3], s33 offset:516 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v5, off, s[0:3], s33 offset:520 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v6, off, s[0:3], s33 offset:524 ; 4-byte Folded Reload
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:496
; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:500
; GCN-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:504
; GCN-NEXT: buffer_store_dword v6, off, s[0:3], s33 offset:508
; GCN-NEXT: buffer_load_dword v0, v1, s[0:3], 0 offen ; GCN-NEXT: buffer_load_dword v0, v1, s[0:3], 0 offen
; GCN-NEXT: buffer_load_dword v1, v1, s[0:3], 0 offen offset:4 ; GCN-NEXT: buffer_load_dword v1, v1, s[0:3], 0 offen offset:4
; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s33 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v63, off, s[0:3], s33 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v62, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v61, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v61, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v60, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v60, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v59, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v59, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v58, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v58, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v57, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v57, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v56, off, s[0:3], s33 offset:28 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v56, off, s[0:3], s33 offset:28 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v47, off, s[0:3], s33 offset:32 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v46, off, s[0:3], s33 offset:32 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v46, off, s[0:3], s33 offset:36 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v45, off, s[0:3], s33 offset:36 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v45, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v44, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v44, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v43, off, s[0:3], s33 offset:48 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:48 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v42, off, s[0:3], s33 offset:52 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:52 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:56 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:56 ; 4-byte Folded Reload
; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:60 ; 4-byte Folded Reload
; GCN-NEXT: s_mov_b32 s33, s4 ; GCN-NEXT: s_mov_b32 s33, s4
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
%vec = load <32 x i64>, ptr addrspace(1) %ptr %vec = load <32 x i64>, ptr addrspace(1) %ptr
%elt = extractelement <32 x i64> %vec, i32 %idx %elt = extractelement <32 x i64> %vec, i32 %idx
ret i64 %elt ret i64 %elt
} }

llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; GFX9-NEXT: global_load_dwordx4 v[10:13], v[0:1], off offset:32 ; GFX9-NEXT: global_load_dwordx4 v[10:13], v[0:1], off offset:32
; GFX9-NEXT: global_load_dwordx4 v[14:17], v[0:1], off offset:48 ; GFX9-NEXT: global_load_dwordx4 v[14:17], v[0:1], off offset:48
; GFX9-NEXT: s_lshl_b32 s0, s2, 1 ; GFX9-NEXT: s_lshl_b32 s0, s2, 1
; GFX9-NEXT: s_lshl_b32 s2, s0, 1 ; GFX9-NEXT: s_lshl_b32 s2, s0, 1
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_set_gpr_idx_on s2, gpr_idx(SRC0) ; GFX9-NEXT: s_set_gpr_idx_on s2, gpr_idx(SRC0)
; GFX9-NEXT: v_mov_b32_e32 v0, v2 ; GFX9-NEXT: v_mov_b32_e32 v0, v2
; GFX9-NEXT: v_mov_b32_e32 v1, v3 ; GFX9-NEXT: v_mov_b32_e32 v1, v3
; GFX9-NEXT: v_mov_b32_e32 v18, v2
; GFX9-NEXT: s_set_gpr_idx_off ; GFX9-NEXT: s_set_gpr_idx_off
; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: s_set_gpr_idx_on s2, gpr_idx(SRC0)
; GFX9-NEXT: v_mov_b32_e32 v0, v2
; GFX9-NEXT: s_set_gpr_idx_off
; GFX9-NEXT: v_readfirstlane_b32 s1, v1 ; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: s_set_gpr_idx_on s2, gpr_idx(SRC0) ; GFX9-NEXT: s_set_gpr_idx_on s2, gpr_idx(SRC0)
; GFX9-NEXT: v_mov_b32_e32 v3, v3 ; GFX9-NEXT: v_mov_b32_e32 v1, v3
; GFX9-NEXT: s_set_gpr_idx_off ; GFX9-NEXT: s_set_gpr_idx_off
; GFX9-NEXT: v_readfirstlane_b32 s2, v18 ; GFX9-NEXT: v_readfirstlane_b32 s2, v0
; GFX9-NEXT: v_readfirstlane_b32 s3, v3 ; GFX9-NEXT: v_readfirstlane_b32 s3, v1
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: extractelement_vgpr_v4i128_sgpr_idx: ; GFX8-LABEL: extractelement_vgpr_v4i128_sgpr_idx:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: v_add_u32_e32 v6, vcc, 16, v0 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, 16, v0
; GFX8-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc ; GFX8-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc
; GFX8-NEXT: v_add_u32_e32 v10, vcc, 32, v0 ; GFX8-NEXT: v_add_u32_e32 v10, vcc, 32, v0
; GFX8-NEXT: v_addc_u32_e32 v11, vcc, 0, v1, vcc ; GFX8-NEXT: v_addc_u32_e32 v11, vcc, 0, v1, vcc
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
} }
define i128 @extractelement_vgpr_v4i128_vgpr_idx(ptr addrspace(1) %ptr, i32 %idx) { define i128 @extractelement_vgpr_v4i128_vgpr_idx(ptr addrspace(1) %ptr, i32 %idx) {
; GFX9-LABEL: extractelement_vgpr_v4i128_vgpr_idx: ; GFX9-LABEL: extractelement_vgpr_v4i128_vgpr_idx:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: global_load_dwordx4 v[3:6], v[0:1], off ; GFX9-NEXT: global_load_dwordx4 v[3:6], v[0:1], off
; GFX9-NEXT: global_load_dwordx4 v[7:10], v[0:1], off offset:16 ; GFX9-NEXT: global_load_dwordx4 v[7:10], v[0:1], off offset:16
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 1, v2 ; GFX9-NEXT: global_load_dwordx4 v[11:14], v[0:1], off offset:32
; GFX9-NEXT: v_add_u32_e32 v16, 1, v2 ; GFX9-NEXT: global_load_dwordx4 v[15:18], v[0:1], off offset:48
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v16 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v2
; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v2 ; GFX9-NEXT: v_add_u32_e32 v2, 1, v0
; GFX9-NEXT: s_waitcnt vmcnt(1) ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX9-NEXT: v_cndmask_b32_e64 v11, v3, v5, s[4:5] ; GFX9-NEXT: s_waitcnt vmcnt(3)
; GFX9-NEXT: v_cndmask_b32_e64 v12, v4, v6, s[4:5] ; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v19, v4, v6, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v5, v19, v8, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 2, v2 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 2, v2
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cndmask_b32_e32 v5, v11, v7, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v6, v12, v8, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 2, v16
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v10, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 3, v2 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 3, v2
; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 3, v16
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
; GFX9-NEXT: global_load_dwordx4 v[8:11], v[0:1], off offset:32 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 4, v0
; GFX9-NEXT: global_load_dwordx4 v[12:15], v[0:1], off offset:48
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 4, v2
; GFX9-NEXT: s_waitcnt vmcnt(1) ; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v9, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 4, v16
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 5, v2
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 5, v16 ; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v12, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v10, vcc ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 4, v2
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v11, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 6, v2 ; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v12, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 6, v16 ; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v14, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v12, vcc ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 5, v2
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v13, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v13, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 7, v2 ; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v14, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v14, vcc ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 6, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v15, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v15, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 7, v16 ; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v16, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v14, vcc ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 6, v2
; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v15, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v15, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v16, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 7, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v17, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v18, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 7, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v17, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v18, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: extractelement_vgpr_v4i128_vgpr_idx: ; GFX8-LABEL: extractelement_vgpr_v4i128_vgpr_idx:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: flat_load_dwordx4 v[3:6], v[0:1] ; GFX8-NEXT: flat_load_dwordx4 v[3:6], v[0:1]
; GFX8-NEXT: v_add_u32_e32 v7, vcc, 16, v0 ; GFX8-NEXT: v_add_u32_e32 v7, vcc, 16, v0
; GFX8-NEXT: v_addc_u32_e32 v8, vcc, 0, v1, vcc ; GFX8-NEXT: v_addc_u32_e32 v8, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dwordx4 v[7:10], v[7:8] ; GFX8-NEXT: flat_load_dwordx4 v[7:10], v[7:8]
; GFX8-NEXT: v_lshlrev_b32_e32 v16, 1, v2 ; GFX8-NEXT: v_add_u32_e32 v11, vcc, 32, v0
; GFX8-NEXT: v_add_u32_e32 v17, vcc, 1, v16 ; GFX8-NEXT: v_addc_u32_e32 v12, vcc, 0, v1, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v17 ; GFX8-NEXT: flat_load_dwordx4 v[11:14], v[11:12]
; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v16 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 48, v0
; GFX8-NEXT: s_waitcnt vmcnt(1) ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v11, v3, v5, s[4:5] ; GFX8-NEXT: flat_load_dwordx4 v[15:18], v[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v12, v4, v6, s[4:5] ; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v2
; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v5, vcc ; GFX8-NEXT: v_add_u32_e32 v2, vcc, 1, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX8-NEXT: s_waitcnt vmcnt(3)
; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v19, v4, v6, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX8-NEXT: v_add_u32_e32 v2, vcc, 32, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc ; GFX8-NEXT: s_waitcnt vmcnt(2)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v16 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: v_cndmask_b32_e32 v5, v19, v8, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v6, v11, v7, vcc ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v2
; GFX8-NEXT: v_cndmask_b32_e32 v11, v12, v8, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v17
; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v16 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0
; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v7, v11, v10, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v10, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v17 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v2
; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
; GFX8-NEXT: flat_load_dwordx4 v[8:11], v[2:3] ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v0
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 48, v0
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dwordx4 v[12:15], v[0:1]
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v16
; GFX8-NEXT: s_waitcnt vmcnt(1) ; GFX8-NEXT: s_waitcnt vmcnt(1)
; GFX8-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v9, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v17
; GFX8-NEXT: v_cndmask_b32_e32 v2, v5, v8, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v9, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v16
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v17 ; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v12, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v2
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v16 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v12, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v17 ; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v14, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v2
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v13, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v13, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v16 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v14, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v14, vcc ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v0
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v15, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v15, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v17 ; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v16, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v14, vcc ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v2
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v15, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v15, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v16, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v17, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v18, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v17, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v18, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX7-LABEL: extractelement_vgpr_v4i128_vgpr_idx: ; GFX7-LABEL: extractelement_vgpr_v4i128_vgpr_idx:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: s_mov_b32 s10, 0 ; GFX7-NEXT: s_mov_b32 s6, 0
; GFX7-NEXT: s_mov_b32 s11, 0xf000 ; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_mov_b64 s[8:9], 0 ; GFX7-NEXT: s_mov_b64 s[4:5], 0
; GFX7-NEXT: buffer_load_dwordx4 v[3:6], v[0:1], s[8:11], 0 addr64 ; GFX7-NEXT: buffer_load_dwordx4 v[3:6], v[0:1], s[4:7], 0 addr64
; GFX7-NEXT: buffer_load_dwordx4 v[7:10], v[0:1], s[8:11], 0 addr64 offset:16 ; GFX7-NEXT: buffer_load_dwordx4 v[7:10], v[0:1], s[4:7], 0 addr64 offset:16
; GFX7-NEXT: v_lshlrev_b32_e32 v2, 1, v2 ; GFX7-NEXT: buffer_load_dwordx4 v[11:14], v[0:1], s[4:7], 0 addr64 offset:32
; GFX7-NEXT: v_add_i32_e32 v16, vcc, 1, v2 ; GFX7-NEXT: buffer_load_dwordx4 v[15:18], v[0:1], s[4:7], 0 addr64 offset:48
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v16 ; GFX7-NEXT: v_lshlrev_b32_e32 v0, 1, v2
; GFX7-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v2 ; GFX7-NEXT: v_add_i32_e32 v2, vcc, 1, v0
; GFX7-NEXT: s_waitcnt vmcnt(1) ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX7-NEXT: v_cndmask_b32_e64 v11, v3, v5, s[4:5] ; GFX7-NEXT: s_waitcnt vmcnt(3)
; GFX7-NEXT: v_cndmask_b32_e64 v12, v4, v6, s[4:5] ; GFX7-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v19, v4, v6, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0
; GFX7-NEXT: s_waitcnt vmcnt(2)
; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v5, v19, v8, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 2, v2 ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 2, v2
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_cndmask_b32_e32 v5, v11, v7, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v6, v12, v8, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 2, v16
; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0
; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v5, v5, v10, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 3, v2 ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 3, v2
; GFX7-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 3, v16
; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
; GFX7-NEXT: buffer_load_dwordx4 v[8:11], v[0:1], s[8:11], 0 addr64 offset:32 ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 4, v0
; GFX7-NEXT: buffer_load_dwordx4 v[12:15], v[0:1], s[8:11], 0 addr64 offset:48
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 4, v2
; GFX7-NEXT: s_waitcnt vmcnt(1) ; GFX7-NEXT: s_waitcnt vmcnt(1)
; GFX7-NEXT: v_cndmask_b32_e32 v0, v5, v8, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v1, v6, v9, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 4, v16
; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 5, v2
; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 5, v16 ; GFX7-NEXT: v_cndmask_b32_e32 v5, v5, v12, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v10, vcc ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 4, v2
; GFX7-NEXT: v_cndmask_b32_e32 v4, v4, v11, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 6, v2 ; GFX7-NEXT: v_cndmask_b32_e32 v4, v4, v12, vcc
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0
; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v12, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 6, v16 ; GFX7-NEXT: v_cndmask_b32_e32 v5, v5, v14, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v12, vcc ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 5, v2
; GFX7-NEXT: v_cndmask_b32_e32 v4, v4, v13, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v13, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 7, v2 ; GFX7-NEXT: v_cndmask_b32_e32 v4, v4, v14, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v0, v0, v14, vcc ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 6, v0
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v15, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v15, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 7, v16 ; GFX7-NEXT: v_cndmask_b32_e32 v5, v5, v16, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v2, v3, v14, vcc ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 6, v2
; GFX7-NEXT: v_cndmask_b32_e32 v3, v4, v15, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v15, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v4, v4, v16, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 7, v0
; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v17, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v18, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 7, v2
; GFX7-NEXT: v_cndmask_b32_e32 v2, v3, v17, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v3, v4, v18, vcc
; GFX7-NEXT: s_setpc_b64 s[30:31] ; GFX7-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: extractelement_vgpr_v4i128_vgpr_idx: ; GFX10-LABEL: extractelement_vgpr_v4i128_vgpr_idx:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x3
; GFX10-NEXT: global_load_dwordx4 v[12:15], v[0:1], off ; GFX10-NEXT: global_load_dwordx4 v[3:6], v[0:1], off
; GFX10-NEXT: global_load_dwordx4 v[4:7], v[0:1], off offset:16 ; GFX10-NEXT: global_load_dwordx4 v[7:10], v[0:1], off offset:16
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 1, v2 ; GFX10-NEXT: global_load_dwordx4 v[11:14], v[0:1], off offset:32
; GFX10-NEXT: global_load_dwordx4 v[8:11], v[0:1], off offset:32 ; GFX10-NEXT: global_load_dwordx4 v[15:18], v[0:1], off offset:48
; GFX10-NEXT: v_add_nc_u32_e32 v3, 1, v2 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 1, v2
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v1, 1, v0
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 1, v3 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX10-NEXT: s_waitcnt vmcnt(2) ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 1, v1
; GFX10-NEXT: v_cndmask_b32_e32 v16, v12, v14, vcc_lo ; GFX10-NEXT: s_waitcnt vmcnt(3)
; GFX10-NEXT: v_cndmask_b32_e32 v17, v13, v15, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v18, v12, v14, s4 ; GFX10-NEXT: v_cndmask_b32_e32 v19, v4, v6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v19, v13, v15, s4 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0
; GFX10-NEXT: global_load_dwordx4 v[12:15], v[0:1], off offset:48 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v5, s4
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 2, v3
; GFX10-NEXT: s_waitcnt vmcnt(2)
; GFX10-NEXT: v_cndmask_b32_e32 v0, v16, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v17, v5, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v2
; GFX10-NEXT: v_cndmask_b32_e64 v4, v18, v4, s4
; GFX10-NEXT: v_cndmask_b32_e64 v5, v19, v5, s4
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 3, v3
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v2
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v6, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v6, s4
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v7, s4 ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 2, v1
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 4, v3 ; GFX10-NEXT: s_waitcnt vmcnt(2)
; GFX10-NEXT: s_waitcnt vmcnt(1) ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v5, v19, v8, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v2 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v7, s4
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v8, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v8, s4
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v9, s4 ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 3, v1
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 5, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v2 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v9, s4
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v10, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v10, s4
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v11, s4 ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 4, v1
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v3 ; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v11, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v12, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v12, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v11, s4
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v12, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v12, s4
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v2 ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 5, v1
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v13, s4 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v13, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 7, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v14, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v14, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v15, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v13, s4
; GFX10-NEXT: v_cndmask_b32_e64 v2, v4, v14, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v14, s4
; GFX10-NEXT: v_cndmask_b32_e64 v3, v5, v15, s4 ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v1
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v15, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v16, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v15, s4
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v16, s4
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 7, v1
; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v17, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v18, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v3, v17, s4
; GFX10-NEXT: v_cndmask_b32_e64 v3, v4, v18, s4
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: extractelement_vgpr_v4i128_vgpr_idx: ; GFX11-LABEL: extractelement_vgpr_v4i128_vgpr_idx:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_clause 0x3 ; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: global_load_b128 v[16:19], v[0:1], off ; GFX11-NEXT: global_load_b128 v[3:6], v[0:1], off
; GFX11-NEXT: global_load_b128 v[4:7], v[0:1], off offset:16 ; GFX11-NEXT: global_load_b128 v[7:10], v[0:1], off offset:16
; GFX11-NEXT: global_load_b128 v[8:11], v[0:1], off offset:32 ; GFX11-NEXT: global_load_b128 v[11:14], v[0:1], off offset:32
; GFX11-NEXT: global_load_b128 v[12:15], v[0:1], off offset:48 ; GFX11-NEXT: global_load_b128 v[15:18], v[0:1], off offset:48
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v2 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX11-NEXT: s_waitcnt vmcnt(3) ; GFX11-NEXT: s_waitcnt vmcnt(3)
; GFX11-NEXT: v_cndmask_b32_e32 v3, v17, v19, vcc_lo ; GFX11-NEXT: v_dual_cndmask_b32 v2, v3, v5 :: v_dual_add_nc_u32 v1, 1, v0
; GFX11-NEXT: v_dual_cndmask_b32 v2, v16, v18 :: v_dual_add_nc_u32 v1, 1, v0
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v1 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v1
; GFX11-NEXT: v_cndmask_b32_e32 v19, v4, v6, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v5, s0
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v6, s0
; GFX11-NEXT: s_waitcnt vmcnt(2) ; GFX11-NEXT: s_waitcnt vmcnt(2)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v3, v3, v5
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0
; GFX11-NEXT: v_cndmask_b32_e64 v16, v16, v18, s0
; GFX11-NEXT: v_cndmask_b32_e64 v17, v17, v19, s0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v1 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v1
; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v6 :: v_dual_cndmask_b32 v3, v3, v7 ; GFX11-NEXT: v_cndmask_b32_e32 v5, v19, v8, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v4, v16, v4, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v7, s0
; GFX11-NEXT: v_cndmask_b32_e64 v5, v17, v5, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v8, s0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v1 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v1
; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v9 :: v_dual_cndmask_b32 v5, v5, v10
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v9, s0
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v10, s0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 4, v1
; GFX11-NEXT: s_waitcnt vmcnt(1) ; GFX11-NEXT: s_waitcnt vmcnt(1)
; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v8 :: v_dual_cndmask_b32 v3, v3, v9 ; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v11 :: v_dual_cndmask_b32 v5, v5, v12
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v6, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v11, s0
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v7, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v12, s0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 4, v1
; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v10 :: v_dual_cndmask_b32 v3, v3, v11
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v8, s0
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v9, s0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 5, v1 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 5, v1
; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v13 :: v_dual_cndmask_b32 v5, v5, v14
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v13, s0
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v14, s0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 6, v1
; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v12 :: v_dual_cndmask_b32 v3, v3, v13 ; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v15 :: v_dual_cndmask_b32 v5, v5, v16
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v10, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v15, s0
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v11, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v16, s0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 6, v1
; GFX11-NEXT: v_cndmask_b32_e32 v0, v2, v14, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v12, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v13, s0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 7, v1 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 7, v1
; GFX11-NEXT: v_cndmask_b32_e32 v1, v3, v15, vcc_lo ; GFX11-NEXT: v_dual_cndmask_b32 v0, v2, v17 :: v_dual_cndmask_b32 v1, v5, v18
; GFX11-NEXT: v_cndmask_b32_e64 v2, v4, v14, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v2, v3, v17, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_cndmask_b32_e64 v3, v5, v15, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v3, v4, v18, s0
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
%vector = load <4 x i128>, ptr addrspace(1) %ptr %vector = load <4 x i128>, ptr addrspace(1) %ptr
%element = extractelement <4 x i128> %vector, i32 %idx %element = extractelement <4 x i128> %vector, i32 %idx
ret i128 %element ret i128 %element
} }
define amdgpu_ps i128 @extractelement_sgpr_v4i128_vgpr_idx(ptr addrspace(4) inreg %ptr, i32 %idx) { define amdgpu_ps i128 @extractelement_sgpr_v4i128_vgpr_idx(ptr addrspace(4) inreg %ptr, i32 %idx) {
; GFX9-LABEL: extractelement_sgpr_v4i128_vgpr_idx: ; GFX9-LABEL: extractelement_sgpr_v4i128_vgpr_idx:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx16 s[0:15], s[2:3], 0x0 ; GFX9-NEXT: s_load_dwordx16 s[0:15], s[2:3], 0x0
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX9-NEXT: v_add_u32_e32 v19, 1, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s0 ; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: v_mov_b32_e32 v2, s1 ; GFX9-NEXT: v_mov_b32_e32 v2, s1
; GFX9-NEXT: v_mov_b32_e32 v3, s2 ; GFX9-NEXT: v_mov_b32_e32 v3, s2
; GFX9-NEXT: v_mov_b32_e32 v4, s3 ; GFX9-NEXT: v_mov_b32_e32 v4, s3
; GFX9-NEXT: v_mov_b32_e32 v5, s4 ; GFX9-NEXT: v_mov_b32_e32 v5, s4
; GFX9-NEXT: v_mov_b32_e32 v6, s5 ; GFX9-NEXT: v_mov_b32_e32 v6, s5
; GFX9-NEXT: v_cndmask_b32_e32 v17, v1, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v17, v1, v3, vcc
Show All 14 Lines
; GFX9-NEXT: v_cndmask_b32_e32 v17, v17, v9, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v17, v17, v9, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v18, v18, v10, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v18, v18, v10, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0
; GFX9-NEXT: v_mov_b32_e32 v13, s12 ; GFX9-NEXT: v_mov_b32_e32 v13, s12
; GFX9-NEXT: v_mov_b32_e32 v14, s13 ; GFX9-NEXT: v_mov_b32_e32 v14, s13
; GFX9-NEXT: v_cndmask_b32_e32 v17, v17, v11, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v17, v17, v11, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v18, v18, v12, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v18, v18, v12, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 6, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 6, v0
; GFX9-NEXT: v_mov_b32_e32 v15, s14
; GFX9-NEXT: v_mov_b32_e32 v16, s15
; GFX9-NEXT: v_cndmask_b32_e32 v17, v17, v13, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v17, v17, v13, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v18, v18, v14, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v18, v18, v14, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v19 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 7, v0
; GFX9-NEXT: v_add_u32_e32 v0, 1, v0
; GFX9-NEXT: v_cndmask_b32_e32 v17, v17, v15, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v18, v18, v16, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v19 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0
; GFX9-NEXT: v_mov_b32_e32 v15, s14 ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX9-NEXT: v_mov_b32_e32 v16, s15 ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 7, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 3, v19 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 4, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v15, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v3, v1, v7, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e32 v1, v18, v16, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v8, s[0:1]
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 4, v19
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 5, v19 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 6, v19 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 6, v0
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v13, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v14, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v14, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 7, v19 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 7, v0
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v15, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v15, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v16, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v16, vcc
; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v17
; GFX9-NEXT: v_readfirstlane_b32 s1, v1 ; GFX9-NEXT: v_readfirstlane_b32 s1, v18
; GFX9-NEXT: v_readfirstlane_b32 s2, v2 ; GFX9-NEXT: v_readfirstlane_b32 s2, v0
; GFX9-NEXT: v_readfirstlane_b32 s3, v3 ; GFX9-NEXT: v_readfirstlane_b32 s3, v1
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: extractelement_sgpr_v4i128_vgpr_idx: ; GFX8-LABEL: extractelement_sgpr_v4i128_vgpr_idx:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx16 s[0:15], s[2:3], 0x0 ; GFX8-NEXT: s_load_dwordx16 s[0:15], s[2:3], 0x0
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v0 ; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
Show All 21 Lines
; GFX8-NEXT: v_cndmask_b32_e32 v17, v17, v9, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v17, v17, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v18, v18, v10, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v18, v18, v10, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0
; GFX8-NEXT: v_mov_b32_e32 v13, s12 ; GFX8-NEXT: v_mov_b32_e32 v13, s12
; GFX8-NEXT: v_mov_b32_e32 v14, s13 ; GFX8-NEXT: v_mov_b32_e32 v14, s13
; GFX8-NEXT: v_cndmask_b32_e32 v17, v17, v11, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v17, v17, v11, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v18, v18, v12, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v18, v18, v12, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v0
; GFX8-NEXT: v_mov_b32_e32 v15, s14
; GFX8-NEXT: v_mov_b32_e32 v16, s15
; GFX8-NEXT: v_cndmask_b32_e32 v17, v17, v13, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v17, v17, v13, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v18, v18, v14, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v18, v18, v14, vcc
; GFX8-NEXT: v_add_u32_e32 v19, vcc, 1, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v19 ; GFX8-NEXT: v_cndmask_b32_e32 v17, v17, v15, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v18, v18, v16, vcc
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 1, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v19 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0
; GFX8-NEXT: v_mov_b32_e32 v15, s14 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX8-NEXT: v_mov_b32_e32 v16, s15 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0
; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc
; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 3, v19 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v15, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v3, v1, v7, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e32 v1, v18, v16, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v8, s[0:1]
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 4, v19
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v19 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v19 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 6, v0
; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v13, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v4, v2, v14, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v14, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v19 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 7, v0
; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v15, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v15, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v16, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v16, vcc
; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: v_readfirstlane_b32 s0, v17
; GFX8-NEXT: v_readfirstlane_b32 s1, v1 ; GFX8-NEXT: v_readfirstlane_b32 s1, v18
; GFX8-NEXT: v_readfirstlane_b32 s2, v2 ; GFX8-NEXT: v_readfirstlane_b32 s2, v0
; GFX8-NEXT: v_readfirstlane_b32 s3, v3 ; GFX8-NEXT: v_readfirstlane_b32 s3, v1
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX7-LABEL: extractelement_sgpr_v4i128_vgpr_idx: ; GFX7-LABEL: extractelement_sgpr_v4i128_vgpr_idx:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_load_dwordx16 s[0:15], s[2:3], 0x0 ; GFX7-NEXT: s_load_dwordx16 s[0:15], s[2:3], 0x0
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 1, v0 ; GFX7-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
Show All 21 Lines
; GFX7-NEXT: v_cndmask_b32_e32 v17, v17, v9, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v17, v17, v9, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v18, v18, v10, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v18, v18, v10, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0 ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0
; GFX7-NEXT: v_mov_b32_e32 v13, s12 ; GFX7-NEXT: v_mov_b32_e32 v13, s12
; GFX7-NEXT: v_mov_b32_e32 v14, s13 ; GFX7-NEXT: v_mov_b32_e32 v14, s13
; GFX7-NEXT: v_cndmask_b32_e32 v17, v17, v11, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v17, v17, v11, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v18, v18, v12, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v18, v18, v12, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 6, v0 ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 6, v0
; GFX7-NEXT: v_mov_b32_e32 v15, s14
; GFX7-NEXT: v_mov_b32_e32 v16, s15
; GFX7-NEXT: v_cndmask_b32_e32 v17, v17, v13, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v17, v17, v13, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v18, v18, v14, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v18, v18, v14, vcc
; GFX7-NEXT: v_add_i32_e32 v19, vcc, 1, v0 ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 7, v0
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v19 ; GFX7-NEXT: v_cndmask_b32_e32 v17, v17, v15, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v18, v18, v16, vcc
; GFX7-NEXT: v_add_i32_e32 v0, vcc, 1, v0
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v19 ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0
; GFX7-NEXT: v_mov_b32_e32 v15, s14 ; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX7-NEXT: v_mov_b32_e32 v16, s15 ; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 7, v0 ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0
; GFX7-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1] ; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1] ; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc
; GFX7-NEXT: v_cmp_eq_u32_e64 s[0:1], 3, v19 ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 4, v0
; GFX7-NEXT: v_cndmask_b32_e32 v0, v17, v15, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v3, v1, v7, s[0:1]
; GFX7-NEXT: v_cndmask_b32_e32 v1, v18, v16, vcc
; GFX7-NEXT: v_cndmask_b32_e64 v2, v2, v8, s[0:1]
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 4, v19
; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 5, v19 ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0
; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 6, v19 ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 6, v0
; GFX7-NEXT: v_cndmask_b32_e32 v3, v3, v13, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v4, v2, v14, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v14, vcc
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 7, v19 ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 7, v0
; GFX7-NEXT: v_cndmask_b32_e32 v2, v3, v15, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v15, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v3, v4, v16, vcc ; GFX7-NEXT: v_cndmask_b32_e32 v1, v2, v16, vcc
; GFX7-NEXT: v_readfirstlane_b32 s0, v0 ; GFX7-NEXT: v_readfirstlane_b32 s0, v17
; GFX7-NEXT: v_readfirstlane_b32 s1, v1 ; GFX7-NEXT: v_readfirstlane_b32 s1, v18
; GFX7-NEXT: v_readfirstlane_b32 s2, v2 ; GFX7-NEXT: v_readfirstlane_b32 s2, v0
; GFX7-NEXT: v_readfirstlane_b32 s3, v3 ; GFX7-NEXT: v_readfirstlane_b32 s3, v1
; GFX7-NEXT: ; return to shader part epilog ; GFX7-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: extractelement_sgpr_v4i128_vgpr_idx: ; GFX10-LABEL: extractelement_sgpr_v4i128_vgpr_idx:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx16 s[4:19], s[2:3], 0x0 ; GFX10-NEXT: s_load_dwordx16 s[4:19], s[2:3], 0x0
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 1, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX10-NEXT: v_add_nc_u32_e32 v1, 1, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v1, 1, v0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
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; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s14, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s14, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s15, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s15, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 6, v1 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 6, v1
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, s16, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, s16, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, s17, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, s17, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s16, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s16, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s17, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v3, s17, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 7, v1 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 7, v1
; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, s18, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v1, v4, s18, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, s19, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v3, v5, s19, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s18, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s18, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s19, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s19, s0
; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v1
; GFX10-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: v_readfirstlane_b32 s1, v3
; GFX10-NEXT: v_readfirstlane_b32 s2, v2 ; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10-NEXT: v_readfirstlane_b32 s3, v3 ; GFX10-NEXT: v_readfirstlane_b32 s3, v0
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: extractelement_sgpr_v4i128_vgpr_idx: ; GFX11-LABEL: extractelement_sgpr_v4i128_vgpr_idx:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b512 s[4:19], s[2:3], 0x0 ; GFX11-NEXT: s_load_b512 s[4:19], s[2:3], 0x0
; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_dual_mov_b32 v3, s7 :: v_dual_lshlrev_b32 v0, 1, v0 ; GFX11-NEXT: v_dual_mov_b32 v3, s7 :: v_dual_lshlrev_b32 v0, 1, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
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; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s14, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s14, s0
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s15, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s15, s0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 6, v1 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 6, v1
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, s16, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, s16, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, s17, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, s17, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s16, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s16, s0
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s17, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v0, v3, s17, s0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 7, v1 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 7, v1
; GFX11-NEXT: v_cndmask_b32_e64 v0, v4, s18, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v1, v4, s18, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, v5, s19, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v3, v5, s19, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s18, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s18, s0
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s19, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s19, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: v_readfirstlane_b32 s0, v1
; GFX11-NEXT: v_readfirstlane_b32 s1, v1 ; GFX11-NEXT: v_readfirstlane_b32 s1, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_readfirstlane_b32 s2, v2 ; GFX11-NEXT: v_readfirstlane_b32 s2, v2
; GFX11-NEXT: v_readfirstlane_b32 s3, v3 ; GFX11-NEXT: v_readfirstlane_b32 s3, v0
; GFX11-NEXT: ; return to shader part epilog ; GFX11-NEXT: ; return to shader part epilog
%vector = load <4 x i128>, ptr addrspace(4) %ptr %vector = load <4 x i128>, ptr addrspace(4) %ptr
%element = extractelement <4 x i128> %vector, i32 %idx %element = extractelement <4 x i128> %vector, i32 %idx
ret i128 %element ret i128 %element
} }
define amdgpu_ps i128 @extractelement_sgpr_v4i128_idx0(ptr addrspace(4) inreg %ptr) { define amdgpu_ps i128 @extractelement_sgpr_v4i128_idx0(ptr addrspace(4) inreg %ptr) {
; GCN-LABEL: extractelement_sgpr_v4i128_idx0: ; GCN-LABEL: extractelement_sgpr_v4i128_idx0:
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llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll

Show First 20 Lines • Show All 286 Lines • ▼ Show 20 Linesentry:
%ext = extractelement <8 x float> %vec, i32 %sel %ext = extractelement <8 x float> %vec, i32 %sel
ret float %ext ret float %ext
} }
define i64 @dyn_extract_v8i64_const_s_v(i32 %sel) { define i64 @dyn_extract_v8i64_const_s_v(i32 %sel) {
; GCN-LABEL: dyn_extract_v8i64_const_s_v: ; GCN-LABEL: dyn_extract_v8i64_const_s_v:
; GCN: ; %bb.0: ; %entry ; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_mov_b64 s[4:5], 1 ; GCN-NEXT: s_mov_b64 s[16:17], 2
; GCN-NEXT: s_mov_b64 s[6:7], 2 ; GCN-NEXT: s_mov_b64 s[18:19], 1
; GCN-NEXT: v_mov_b32_e32 v1, s4 ; GCN-NEXT: s_mov_b64 s[14:15], 3
; GCN-NEXT: v_mov_b32_e32 v2, s5 ; GCN-NEXT: v_mov_b32_e32 v1, s18
; GCN-NEXT: v_mov_b32_e32 v3, s6 ; GCN-NEXT: v_mov_b32_e32 v2, s19
; GCN-NEXT: v_mov_b32_e32 v4, s7 ; GCN-NEXT: v_mov_b32_e32 v3, s16
; GCN-NEXT: s_mov_b64 s[8:9], 3 ; GCN-NEXT: v_mov_b32_e32 v4, s17
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GCN-NEXT: v_mov_b32_e32 v5, s8 ; GCN-NEXT: s_mov_b64 s[12:13], 4
; GCN-NEXT: v_mov_b32_e32 v6, s9 ; GCN-NEXT: v_mov_b32_e32 v5, s14
; GCN-NEXT: s_mov_b64 s[10:11], 4 ; GCN-NEXT: v_mov_b32_e32 v6, s15
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0
; GCN-NEXT: s_mov_b64 s[12:13], 5 ; GCN-NEXT: s_mov_b64 s[10:11], 5
; GCN-NEXT: v_mov_b32_e32 v7, s10 ; GCN-NEXT: v_mov_b32_e32 v7, s12
; GCN-NEXT: v_mov_b32_e32 v8, s11 ; GCN-NEXT: v_mov_b32_e32 v8, s13
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc ; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0
; GCN-NEXT: s_mov_b64 s[14:15], 6 ; GCN-NEXT: s_mov_b64 s[8:9], 6
; GCN-NEXT: v_mov_b32_e32 v9, s12 ; GCN-NEXT: v_mov_b32_e32 v9, s10
; GCN-NEXT: v_mov_b32_e32 v10, s13 ; GCN-NEXT: v_mov_b32_e32 v10, s11
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc ; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 4, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 4, v0
; GCN-NEXT: s_mov_b64 s[16:17], 7 ; GCN-NEXT: s_mov_b64 s[6:7], 7
; GCN-NEXT: v_mov_b32_e32 v11, s14 ; GCN-NEXT: v_mov_b32_e32 v11, s8
; GCN-NEXT: v_mov_b32_e32 v12, s15 ; GCN-NEXT: v_mov_b32_e32 v12, s9
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc ; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0
; GCN-NEXT: s_mov_b64 s[18:19], 8 ; GCN-NEXT: s_mov_b64 s[4:5], 8
; GCN-NEXT: v_mov_b32_e32 v13, s16 ; GCN-NEXT: v_mov_b32_e32 v13, s6
; GCN-NEXT: v_mov_b32_e32 v14, s17 ; GCN-NEXT: v_mov_b32_e32 v14, s7
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc ; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 6, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 6, v0
; GCN-NEXT: v_mov_b32_e32 v15, s18 ; GCN-NEXT: v_mov_b32_e32 v15, s4
; GCN-NEXT: v_mov_b32_e32 v16, s19 ; GCN-NEXT: v_mov_b32_e32 v16, s5
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v14, vcc ; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v14, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 7, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 7, v0
; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v15, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v15, vcc
; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v16, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v16, vcc
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: dyn_extract_v8i64_const_s_v: ; GFX10-LABEL: dyn_extract_v8i64_const_s_v:
; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_mov_b64 s[6:7], 2 ; GFX10-NEXT: s_mov_b64 s[4:5], 2
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX10-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-NEXT: v_mov_b32_e32 v1, s4
; GFX10-NEXT: v_mov_b32_e32 v2, s7 ; GFX10-NEXT: v_mov_b32_e32 v2, s5
; GFX10-NEXT: s_mov_b64 s[4:5], 1 ; GFX10-NEXT: s_mov_b64 s[6:7], 1
; GFX10-NEXT: s_mov_b64 s[8:9], 3 ; GFX10-NEXT: s_mov_b64 s[4:5], 3
; GFX10-NEXT: s_mov_b64 s[10:11], 4 ; GFX10-NEXT: v_cndmask_b32_e32 v1, s6, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, s4, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, s7, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v2, s5, v2, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0
; GFX10-NEXT: s_mov_b64 s[12:13], 5 ; GFX10-NEXT: s_mov_b64 s[6:7], 4
; GFX10-NEXT: s_mov_b64 s[14:15], 6 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo
; GFX10-NEXT: s_mov_b64 s[16:17], 7 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s5, vcc_lo
; GFX10-NEXT: s_mov_b64 s[18:19], 8
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s8, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s9, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s10, vcc_lo ; GFX10-NEXT: s_mov_b64 s[4:5], 5
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s11, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s7, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s12, vcc_lo ; GFX10-NEXT: s_mov_b64 s[6:7], 6
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s13, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s5, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s14, vcc_lo ; GFX10-NEXT: s_mov_b64 s[4:5], 7
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s15, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s7, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s16, vcc_lo ; GFX10-NEXT: s_mov_b64 s[6:7], 8
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s17, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s5, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, s18, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, s6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, s19, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, s7, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: dyn_extract_v8i64_const_s_v: ; GFX11-LABEL: dyn_extract_v8i64_const_s_v:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b64 s[2:3], 2 ; GFX11-NEXT: s_mov_b64 s[0:1], 2
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX11-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s3 ; GFX11-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s1
; GFX11-NEXT: s_mov_b64 s[0:1], 1 ; GFX11-NEXT: s_mov_b64 s[2:3], 1
; GFX11-NEXT: s_mov_b64 s[4:5], 3 ; GFX11-NEXT: s_mov_b64 s[0:1], 3
; GFX11-NEXT: s_mov_b64 s[6:7], 4 ; GFX11-NEXT: v_cndmask_b32_e32 v1, s2, v1, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e32 v1, s0, v1, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v2, s3, v2, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e32 v2, s1, v2, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0
; GFX11-NEXT: s_mov_b64 s[8:9], 5 ; GFX11-NEXT: s_mov_b64 s[2:3], 4
; GFX11-NEXT: s_mov_b64 s[10:11], 6 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s0, vcc_lo
; GFX11-NEXT: s_mov_b64 s[12:13], 7 ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s1, vcc_lo
; GFX11-NEXT: s_mov_b64 s[14:15], 8
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s5, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s6, vcc_lo ; GFX11-NEXT: s_mov_b64 s[0:1], 5
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s7, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s2, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s3, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s8, vcc_lo ; GFX11-NEXT: s_mov_b64 s[2:3], 6
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s9, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s0, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s1, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s10, vcc_lo ; GFX11-NEXT: s_mov_b64 s[0:1], 7
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s11, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s2, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s3, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s12, vcc_lo ; GFX11-NEXT: s_mov_b64 s[2:3], 8
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s13, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s0, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s1, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0
; GFX11-NEXT: v_cndmask_b32_e64 v0, v1, s14, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v0, v1, s2, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, v2, s15, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v1, v2, s3, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%ext = extractelement <8 x i64> <i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 8>, i32 %sel %ext = extractelement <8 x i64> <i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 8>, i32 %sel
ret i64 %ext ret i64 %ext
} }
define amdgpu_ps void @dyn_extract_v8i64_const_s_s(i32 inreg %sel) { define amdgpu_ps void @dyn_extract_v8i64_const_s_s(i32 inreg %sel) {
; GPRIDX-LABEL: dyn_extract_v8i64_const_s_s: ; GPRIDX-LABEL: dyn_extract_v8i64_const_s_s:
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Linesentry:
%ext = extractelement <8 x i64> <i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 8>, i32 %sel %ext = extractelement <8 x i64> <i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 8>, i32 %sel
store i64 %ext, ptr addrspace(1) undef store i64 %ext, ptr addrspace(1) undef
ret void ret void
} }
define amdgpu_ps void @dyn_extract_v8i64_s_v(<8 x i64> inreg %vec, i32 %sel) { define amdgpu_ps void @dyn_extract_v8i64_s_v(<8 x i64> inreg %vec, i32 %sel) {
; GPRIDX-LABEL: dyn_extract_v8i64_s_v: ; GPRIDX-LABEL: dyn_extract_v8i64_s_v:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_mov_b32 s0, s2 ; GPRIDX-NEXT: v_mov_b32_e32 v1, s2
; GPRIDX-NEXT: s_mov_b32 s1, s3 ; GPRIDX-NEXT: v_mov_b32_e32 v2, s3
; GPRIDX-NEXT: s_mov_b32 s2, s4 ; GPRIDX-NEXT: v_mov_b32_e32 v3, s4
; GPRIDX-NEXT: s_mov_b32 s3, s5 ; GPRIDX-NEXT: v_mov_b32_e32 v4, s5
; GPRIDX-NEXT: s_mov_b32 s4, s6
; GPRIDX-NEXT: s_mov_b32 s5, s7
; GPRIDX-NEXT: v_mov_b32_e32 v1, s0
; GPRIDX-NEXT: v_mov_b32_e32 v2, s1
; GPRIDX-NEXT: v_mov_b32_e32 v3, s2
; GPRIDX-NEXT: v_mov_b32_e32 v4, s3
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GPRIDX-NEXT: s_mov_b32 s6, s8 ; GPRIDX-NEXT: v_mov_b32_e32 v5, s6
; GPRIDX-NEXT: s_mov_b32 s7, s9 ; GPRIDX-NEXT: v_mov_b32_e32 v6, s7
; GPRIDX-NEXT: v_mov_b32_e32 v5, s4
; GPRIDX-NEXT: v_mov_b32_e32 v6, s5
; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0
; GPRIDX-NEXT: s_mov_b32 s8, s10 ; GPRIDX-NEXT: v_mov_b32_e32 v7, s8
; GPRIDX-NEXT: s_mov_b32 s9, s11 ; GPRIDX-NEXT: v_mov_b32_e32 v8, s9
; GPRIDX-NEXT: v_mov_b32_e32 v7, s6
; GPRIDX-NEXT: v_mov_b32_e32 v8, s7
; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0
; GPRIDX-NEXT: s_mov_b32 s10, s12 ; GPRIDX-NEXT: v_mov_b32_e32 v9, s10
; GPRIDX-NEXT: s_mov_b32 s11, s13 ; GPRIDX-NEXT: v_mov_b32_e32 v10, s11
; GPRIDX-NEXT: v_mov_b32_e32 v9, s8
; GPRIDX-NEXT: v_mov_b32_e32 v10, s9
; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 4, v0 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 4, v0
; GPRIDX-NEXT: v_mov_b32_e32 v11, s10 ; GPRIDX-NEXT: v_mov_b32_e32 v11, s12
; GPRIDX-NEXT: v_mov_b32_e32 v12, s11 ; GPRIDX-NEXT: v_mov_b32_e32 v12, s13
; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0
; GPRIDX-NEXT: v_mov_b32_e32 v13, s14 ; GPRIDX-NEXT: v_mov_b32_e32 v13, s14
; GPRIDX-NEXT: v_mov_b32_e32 v14, s15 ; GPRIDX-NEXT: v_mov_b32_e32 v14, s15
; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 6, v0 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 6, v0
; GPRIDX-NEXT: v_mov_b32_e32 v15, s16 ; GPRIDX-NEXT: v_mov_b32_e32 v15, s16
; GPRIDX-NEXT: v_mov_b32_e32 v16, s17 ; GPRIDX-NEXT: v_mov_b32_e32 v16, s17
; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v14, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v14, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 7, v0 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 7, v0
; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v1, v15, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v1, v15, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v2, v16, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v2, v16, vcc
; GPRIDX-NEXT: global_store_dwordx2 v[0:1], v[0:1], off ; GPRIDX-NEXT: global_store_dwordx2 v[0:1], v[0:1], off
; GPRIDX-NEXT: s_endpgm ; GPRIDX-NEXT: s_endpgm
; ;
; MOVREL-LABEL: dyn_extract_v8i64_s_v: ; MOVREL-LABEL: dyn_extract_v8i64_s_v:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s0, s2 ; MOVREL-NEXT: v_mov_b32_e32 v1, s2
; MOVREL-NEXT: s_mov_b32 s1, s3 ; MOVREL-NEXT: v_mov_b32_e32 v2, s3
; MOVREL-NEXT: s_mov_b32 s2, s4 ; MOVREL-NEXT: v_mov_b32_e32 v3, s4
; MOVREL-NEXT: s_mov_b32 s3, s5 ; MOVREL-NEXT: v_mov_b32_e32 v4, s5
; MOVREL-NEXT: s_mov_b32 s4, s6
; MOVREL-NEXT: s_mov_b32 s5, s7
; MOVREL-NEXT: v_mov_b32_e32 v1, s0
; MOVREL-NEXT: v_mov_b32_e32 v2, s1
; MOVREL-NEXT: v_mov_b32_e32 v3, s2
; MOVREL-NEXT: v_mov_b32_e32 v4, s3
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; MOVREL-NEXT: s_mov_b32 s6, s8 ; MOVREL-NEXT: v_mov_b32_e32 v5, s6
; MOVREL-NEXT: s_mov_b32 s7, s9 ; MOVREL-NEXT: v_mov_b32_e32 v6, s7
; MOVREL-NEXT: v_mov_b32_e32 v5, s4
; MOVREL-NEXT: v_mov_b32_e32 v6, s5
; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0
; MOVREL-NEXT: s_mov_b32 s8, s10 ; MOVREL-NEXT: v_mov_b32_e32 v7, s8
; MOVREL-NEXT: s_mov_b32 s9, s11 ; MOVREL-NEXT: v_mov_b32_e32 v8, s9
; MOVREL-NEXT: v_mov_b32_e32 v7, s6
; MOVREL-NEXT: v_mov_b32_e32 v8, s7
; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc ; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc ; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0
; MOVREL-NEXT: s_mov_b32 s10, s12 ; MOVREL-NEXT: v_mov_b32_e32 v9, s10
; MOVREL-NEXT: s_mov_b32 s11, s13 ; MOVREL-NEXT: v_mov_b32_e32 v10, s11
; MOVREL-NEXT: v_mov_b32_e32 v9, s8
; MOVREL-NEXT: v_mov_b32_e32 v10, s9
; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc ; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc ; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc, 4, v0 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc, 4, v0
; MOVREL-NEXT: v_mov_b32_e32 v11, s10 ; MOVREL-NEXT: v_mov_b32_e32 v11, s12
; MOVREL-NEXT: v_mov_b32_e32 v12, s11 ; MOVREL-NEXT: v_mov_b32_e32 v12, s13
; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc ; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc ; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0
; MOVREL-NEXT: v_mov_b32_e32 v13, s14 ; MOVREL-NEXT: v_mov_b32_e32 v13, s14
; MOVREL-NEXT: v_mov_b32_e32 v14, s15 ; MOVREL-NEXT: v_mov_b32_e32 v14, s15
; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc ; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc ; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc, 6, v0 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc, 6, v0
; MOVREL-NEXT: v_mov_b32_e32 v15, s16 ; MOVREL-NEXT: v_mov_b32_e32 v15, s16
; MOVREL-NEXT: v_mov_b32_e32 v16, s17 ; MOVREL-NEXT: v_mov_b32_e32 v16, s17
; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc ; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc
; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v14, vcc ; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v14, vcc
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc, 7, v0 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc, 7, v0
; MOVREL-NEXT: v_cndmask_b32_e32 v0, v1, v15, vcc ; MOVREL-NEXT: v_cndmask_b32_e32 v0, v1, v15, vcc
; MOVREL-NEXT: v_cndmask_b32_e32 v1, v2, v16, vcc ; MOVREL-NEXT: v_cndmask_b32_e32 v1, v2, v16, vcc
; MOVREL-NEXT: flat_store_dwordx2 v[0:1], v[0:1] ; MOVREL-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
; MOVREL-NEXT: s_endpgm ; MOVREL-NEXT: s_endpgm
; ;
; GFX10-LABEL: dyn_extract_v8i64_s_v: ; GFX10-LABEL: dyn_extract_v8i64_s_v:
; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s19, s5
; GFX10-NEXT: v_mov_b32_e32 v1, s2 ; GFX10-NEXT: v_mov_b32_e32 v1, s2
; GFX10-NEXT: v_mov_b32_e32 v2, s19 ; GFX10-NEXT: v_mov_b32_e32 v2, s3
; GFX10-NEXT: v_mov_b32_e32 v15, s4
; GFX10-NEXT: v_mov_b32_e32 v16, s5
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: v_mov_b32_e32 v3, s6
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: v_mov_b32_e32 v4, s7
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: v_mov_b32_e32 v5, s8
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: v_mov_b32_e32 v6, s9
; GFX10-NEXT: v_cndmask_b32_e32 v1, s0, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v15, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v2, s1, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v16, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: v_mov_b32_e32 v7, s10
; GFX10-NEXT: s_mov_b32 s8, s10 ; GFX10-NEXT: v_mov_b32_e32 v8, s11
; GFX10-NEXT: s_mov_b32 s9, s11 ; GFX10-NEXT: v_mov_b32_e32 v9, s12
; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: v_mov_b32_e32 v10, s13
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0
; GFX10-NEXT: s_mov_b32 s11, s13 ; GFX10-NEXT: v_mov_b32_e32 v11, s14
; GFX10-NEXT: s_mov_b32 s12, s14 ; GFX10-NEXT: v_mov_b32_e32 v12, s15
; GFX10-NEXT: s_mov_b32 s13, s15 ; GFX10-NEXT: v_mov_b32_e32 v13, s16
; GFX10-NEXT: s_mov_b32 s14, s16 ; GFX10-NEXT: v_mov_b32_e32 v14, s17
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s6, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s7, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0
; GFX10-NEXT: s_mov_b32 s15, s17 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s9, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s10, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s11, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s12, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s13, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, s14, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v13, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, s15, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v14, vcc_lo
; GFX10-NEXT: global_store_dwordx2 v[0:1], v[0:1], off ; GFX10-NEXT: global_store_dwordx2 v[0:1], v[0:1], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: dyn_extract_v8i64_s_v: ; GFX11-LABEL: dyn_extract_v8i64_s_v:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_mov_b32 s0, s2 ; GFX11-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s3
; GFX11-NEXT: s_mov_b32 s2, s4 ; GFX11-NEXT: v_dual_mov_b32 v15, s4 :: v_dual_mov_b32 v16, s5
; GFX11-NEXT: s_mov_b32 s19, s5
; GFX11-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s19
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX11-NEXT: s_mov_b32 s1, s3 ; GFX11-NEXT: v_dual_mov_b32 v3, s6 :: v_dual_mov_b32 v4, s7
; GFX11-NEXT: s_mov_b32 s4, s6 ; GFX11-NEXT: v_dual_mov_b32 v5, s8 :: v_dual_mov_b32 v6, s9
; GFX11-NEXT: s_mov_b32 s5, s7 ; GFX11-NEXT: v_dual_cndmask_b32 v1, v1, v15 :: v_dual_cndmask_b32 v2, v2, v16
; GFX11-NEXT: s_mov_b32 s6, s8
; GFX11-NEXT: v_cndmask_b32_e32 v1, s0, v1, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e32 v2, s1, v2, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0
; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: v_dual_mov_b32 v7, s10 :: v_dual_mov_b32 v8, s11
; GFX11-NEXT: s_mov_b32 s8, s10 ; GFX11-NEXT: v_dual_mov_b32 v9, s12 :: v_dual_mov_b32 v10, s13
; GFX11-NEXT: s_mov_b32 s9, s11 ; GFX11-NEXT: v_dual_cndmask_b32 v1, v1, v3 :: v_dual_cndmask_b32 v2, v2, v4
; GFX11-NEXT: s_mov_b32 s10, s12
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s5, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0
; GFX11-NEXT: s_mov_b32 s11, s13 ; GFX11-NEXT: v_dual_mov_b32 v11, s14 :: v_dual_mov_b32 v12, s15
; GFX11-NEXT: s_mov_b32 s12, s14 ; GFX11-NEXT: v_dual_mov_b32 v13, s16 :: v_dual_mov_b32 v14, s17
; GFX11-NEXT: s_mov_b32 s13, s15 ; GFX11-NEXT: v_dual_cndmask_b32 v1, v1, v5 :: v_dual_cndmask_b32 v2, v2, v6
; GFX11-NEXT: s_mov_b32 s14, s16
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s6, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s7, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0
; GFX11-NEXT: s_mov_b32 s15, s17 ; GFX11-NEXT: v_dual_cndmask_b32 v1, v1, v7 :: v_dual_cndmask_b32 v2, v2, v8
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s8, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s9, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s10, vcc_lo ; GFX11-NEXT: v_dual_cndmask_b32 v1, v1, v9 :: v_dual_cndmask_b32 v2, v2, v10
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s11, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s12, vcc_lo ; GFX11-NEXT: v_dual_cndmask_b32 v1, v1, v11 :: v_dual_cndmask_b32 v2, v2, v12
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s13, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0
; GFX11-NEXT: v_cndmask_b32_e64 v0, v1, s14, vcc_lo ; GFX11-NEXT: v_dual_cndmask_b32 v0, v1, v13 :: v_dual_cndmask_b32 v1, v2, v14
; GFX11-NEXT: v_cndmask_b32_e64 v1, v2, s15, vcc_lo
; GFX11-NEXT: global_store_b64 v[0:1], v[0:1], off ; GFX11-NEXT: global_store_b64 v[0:1], v[0:1], off
; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_nop 0
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-NEXT: s_endpgm ; GFX11-NEXT: s_endpgm
entry: entry:
%ext = extractelement <8 x i64> %vec, i32 %sel %ext = extractelement <8 x i64> %vec, i32 %sel
store i64 %ext, ptr addrspace(1) undef store i64 %ext, ptr addrspace(1) undef
ret void ret void
▲ Show 20 Lines • Show All 1,769 Lines • ▼ Show 20 Lines
entry: entry:
%ext = extractelement <7 x float> %vec, i32 %sel %ext = extractelement <7 x float> %vec, i32 %sel
ret float %ext ret float %ext
} }
define amdgpu_ps double @dyn_extract_v6f64_s_v(<6 x double> inreg %vec, i32 %sel) { define amdgpu_ps double @dyn_extract_v6f64_s_v(<6 x double> inreg %vec, i32 %sel) {
; GCN-LABEL: dyn_extract_v6f64_s_v: ; GCN-LABEL: dyn_extract_v6f64_s_v:
; GCN: ; %bb.0: ; %entry ; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_mov_b32 s0, s2 ; GCN-NEXT: v_mov_b32_e32 v1, s2
; GCN-NEXT: s_mov_b32 s1, s3 ; GCN-NEXT: v_mov_b32_e32 v2, s3
; GCN-NEXT: s_mov_b32 s2, s4 ; GCN-NEXT: v_mov_b32_e32 v3, s4
; GCN-NEXT: s_mov_b32 s3, s5 ; GCN-NEXT: v_mov_b32_e32 v4, s5
; GCN-NEXT: s_mov_b32 s4, s6
; GCN-NEXT: s_mov_b32 s5, s7
; GCN-NEXT: v_mov_b32_e32 v1, s0
; GCN-NEXT: v_mov_b32_e32 v2, s1
; GCN-NEXT: v_mov_b32_e32 v3, s2
; GCN-NEXT: v_mov_b32_e32 v4, s3
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GCN-NEXT: s_mov_b32 s6, s8 ; GCN-NEXT: v_mov_b32_e32 v5, s6
; GCN-NEXT: s_mov_b32 s7, s9 ; GCN-NEXT: v_mov_b32_e32 v6, s7
; GCN-NEXT: v_mov_b32_e32 v5, s4
; GCN-NEXT: v_mov_b32_e32 v6, s5
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0
; GCN-NEXT: v_mov_b32_e32 v7, s6 ; GCN-NEXT: v_mov_b32_e32 v7, s8
; GCN-NEXT: v_mov_b32_e32 v8, s7 ; GCN-NEXT: v_mov_b32_e32 v8, s9
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc ; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0
; GCN-NEXT: v_mov_b32_e32 v9, s10 ; GCN-NEXT: v_mov_b32_e32 v9, s10
; GCN-NEXT: v_mov_b32_e32 v10, s11 ; GCN-NEXT: v_mov_b32_e32 v10, s11
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc ; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 4, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 4, v0
; GCN-NEXT: v_mov_b32_e32 v11, s12 ; GCN-NEXT: v_mov_b32_e32 v11, s12
; GCN-NEXT: v_mov_b32_e32 v12, s13 ; GCN-NEXT: v_mov_b32_e32 v12, s13
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc ; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0
; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v11, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v11, vcc
; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v12, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v12, vcc
; GCN-NEXT: v_readfirstlane_b32 s0, v0 ; GCN-NEXT: v_readfirstlane_b32 s0, v0
; GCN-NEXT: v_readfirstlane_b32 s1, v1 ; GCN-NEXT: v_readfirstlane_b32 s1, v1
; GCN-NEXT: ; return to shader part epilog ; GCN-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: dyn_extract_v6f64_s_v: ; GFX10-LABEL: dyn_extract_v6f64_s_v:
; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s15, s5
; GFX10-NEXT: v_mov_b32_e32 v1, s2 ; GFX10-NEXT: v_mov_b32_e32 v1, s2
; GFX10-NEXT: v_mov_b32_e32 v2, s15 ; GFX10-NEXT: v_mov_b32_e32 v2, s3
; GFX10-NEXT: v_mov_b32_e32 v11, s4
; GFX10-NEXT: v_mov_b32_e32 v12, s5
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: v_mov_b32_e32 v3, s6
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: v_mov_b32_e32 v4, s7
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: v_mov_b32_e32 v5, s8
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: v_mov_b32_e32 v6, s9
; GFX10-NEXT: v_cndmask_b32_e32 v1, s0, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v2, s1, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: v_mov_b32_e32 v7, s10
; GFX10-NEXT: s_mov_b32 s8, s10 ; GFX10-NEXT: v_mov_b32_e32 v8, s11
; GFX10-NEXT: s_mov_b32 s9, s11 ; GFX10-NEXT: v_mov_b32_e32 v9, s12
; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: v_mov_b32_e32 v10, s13
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0
; GFX10-NEXT: s_mov_b32 s11, s13 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s6, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s7, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s9, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, s10, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v9, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, s11, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v10, vcc_lo
; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: dyn_extract_v6f64_s_v: ; GFX11-LABEL: dyn_extract_v6f64_s_v:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_mov_b32 s0, s2 ; GFX11-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s3
; GFX11-NEXT: s_mov_b32 s2, s4 ; GFX11-NEXT: v_dual_mov_b32 v11, s4 :: v_dual_mov_b32 v12, s5
; GFX11-NEXT: s_mov_b32 s15, s5
; GFX11-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s15
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX11-NEXT: s_mov_b32 s1, s3 ; GFX11-NEXT: v_dual_mov_b32 v3, s6 :: v_dual_mov_b32 v4, s7
; GFX11-NEXT: s_mov_b32 s4, s6 ; GFX11-NEXT: v_dual_mov_b32 v5, s8 :: v_dual_mov_b32 v6, s9
; GFX11-NEXT: s_mov_b32 s5, s7 ; GFX11-NEXT: v_dual_cndmask_b32 v1, v1, v11 :: v_dual_cndmask_b32 v2, v2, v12
; GFX11-NEXT: s_mov_b32 s6, s8
; GFX11-NEXT: v_cndmask_b32_e32 v1, s0, v1, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e32 v2, s1, v2, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0
; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: v_dual_mov_b32 v7, s10 :: v_dual_mov_b32 v8, s11
; GFX11-NEXT: s_mov_b32 s8, s10 ; GFX11-NEXT: v_dual_mov_b32 v9, s12 :: v_dual_mov_b32 v10, s13
; GFX11-NEXT: s_mov_b32 s9, s11 ; GFX11-NEXT: v_dual_cndmask_b32 v1, v1, v3 :: v_dual_cndmask_b32 v2, v2, v4
; GFX11-NEXT: s_mov_b32 s10, s12
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s5, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0
; GFX11-NEXT: s_mov_b32 s11, s13 ; GFX11-NEXT: v_dual_cndmask_b32 v1, v1, v5 :: v_dual_cndmask_b32 v2, v2, v6
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s6, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s7, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s8, vcc_lo ; GFX11-NEXT: v_dual_cndmask_b32 v1, v1, v7 :: v_dual_cndmask_b32 v2, v2, v8
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s9, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0
; GFX11-NEXT: v_cndmask_b32_e64 v0, v1, s10, vcc_lo ; GFX11-NEXT: v_dual_cndmask_b32 v0, v1, v9 :: v_dual_cndmask_b32 v1, v2, v10
; GFX11-NEXT: v_cndmask_b32_e64 v1, v2, s11, vcc_lo
; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: v_readfirstlane_b32 s1, v1 ; GFX11-NEXT: v_readfirstlane_b32 s1, v1
; GFX11-NEXT: ; return to shader part epilog ; GFX11-NEXT: ; return to shader part epilog
entry: entry:
%ext = extractelement <6 x double> %vec, i32 %sel %ext = extractelement <6 x double> %vec, i32 %sel
ret double %ext ret double %ext
} }
▲ Show 20 Lines • Show All 130 Lines • ▼ Show 20 Lines
entry: entry:
%ext = extractelement <6 x double> %vec, i32 %sel %ext = extractelement <6 x double> %vec, i32 %sel
ret double %ext ret double %ext
} }
define amdgpu_ps double @dyn_extract_v7f64_s_v(<7 x double> inreg %vec, i32 %sel) { define amdgpu_ps double @dyn_extract_v7f64_s_v(<7 x double> inreg %vec, i32 %sel) {
; GCN-LABEL: dyn_extract_v7f64_s_v: ; GCN-LABEL: dyn_extract_v7f64_s_v:
; GCN: ; %bb.0: ; %entry ; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_mov_b32 s0, s2 ; GCN-NEXT: v_mov_b32_e32 v1, s2
; GCN-NEXT: s_mov_b32 s1, s3 ; GCN-NEXT: v_mov_b32_e32 v2, s3
; GCN-NEXT: s_mov_b32 s2, s4 ; GCN-NEXT: v_mov_b32_e32 v3, s4
; GCN-NEXT: s_mov_b32 s3, s5 ; GCN-NEXT: v_mov_b32_e32 v4, s5
; GCN-NEXT: s_mov_b32 s4, s6
; GCN-NEXT: s_mov_b32 s5, s7
; GCN-NEXT: v_mov_b32_e32 v1, s0
; GCN-NEXT: v_mov_b32_e32 v2, s1
; GCN-NEXT: v_mov_b32_e32 v3, s2
; GCN-NEXT: v_mov_b32_e32 v4, s3
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GCN-NEXT: s_mov_b32 s6, s8 ; GCN-NEXT: v_mov_b32_e32 v5, s6
; GCN-NEXT: s_mov_b32 s7, s9 ; GCN-NEXT: v_mov_b32_e32 v6, s7
; GCN-NEXT: v_mov_b32_e32 v5, s4
; GCN-NEXT: v_mov_b32_e32 v6, s5
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc ; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0
; GCN-NEXT: s_mov_b32 s8, s10 ; GCN-NEXT: v_mov_b32_e32 v7, s8
; GCN-NEXT: s_mov_b32 s9, s11 ; GCN-NEXT: v_mov_b32_e32 v8, s9
; GCN-NEXT: v_mov_b32_e32 v7, s6
; GCN-NEXT: v_mov_b32_e32 v8, s7
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc ; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0
; GCN-NEXT: v_mov_b32_e32 v9, s8 ; GCN-NEXT: v_mov_b32_e32 v9, s10
; GCN-NEXT: v_mov_b32_e32 v10, s9 ; GCN-NEXT: v_mov_b32_e32 v10, s11
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc ; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 4, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 4, v0
; GCN-NEXT: v_mov_b32_e32 v11, s12 ; GCN-NEXT: v_mov_b32_e32 v11, s12
; GCN-NEXT: v_mov_b32_e32 v12, s13 ; GCN-NEXT: v_mov_b32_e32 v12, s13
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc ; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0
; GCN-NEXT: v_mov_b32_e32 v13, s14 ; GCN-NEXT: v_mov_b32_e32 v13, s14
; GCN-NEXT: v_mov_b32_e32 v14, s15 ; GCN-NEXT: v_mov_b32_e32 v14, s15
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc ; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v12, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 6, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 6, v0
; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v13, vcc
; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v14, vcc ; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v14, vcc
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 7, v0 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 7, v0
; GCN-NEXT: ; kill: def $vgpr15 killed $sgpr14 killed $exec ; GCN-NEXT: ; kill: def $vgpr15 killed $sgpr2 killed $exec
; GCN-NEXT: ; kill: def $vgpr16 killed $sgpr15 killed $exec ; GCN-NEXT: ; kill: def $vgpr16 killed $sgpr3 killed $exec
; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v15, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v15, vcc
; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v16, vcc ; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v16, vcc
; GCN-NEXT: v_readfirstlane_b32 s0, v0 ; GCN-NEXT: v_readfirstlane_b32 s0, v0
; GCN-NEXT: v_readfirstlane_b32 s1, v1 ; GCN-NEXT: v_readfirstlane_b32 s1, v1
; GCN-NEXT: ; return to shader part epilog ; GCN-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: dyn_extract_v7f64_s_v: ; GFX10-LABEL: dyn_extract_v7f64_s_v:
; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: v_mov_b32_e32 v2, s2
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: v_mov_b32_e32 v3, s3
; GFX10-NEXT: s_mov_b32 s19, s5 ; GFX10-NEXT: v_mov_b32_e32 v13, s4
; GFX10-NEXT: v_mov_b32_e32 v1, s2 ; GFX10-NEXT: v_mov_b32_e32 v14, s5
; GFX10-NEXT: v_mov_b32_e32 v2, s19
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: v_mov_b32_e32 v4, s6
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: v_mov_b32_e32 v5, s7
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: v_mov_b32_e32 v6, s8
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: v_mov_b32_e32 v7, s9
; GFX10-NEXT: v_cndmask_b32_e32 v1, s0, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v13, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v2, s1, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v14, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: v_mov_b32_e32 v8, s10
; GFX10-NEXT: s_mov_b32 s8, s10 ; GFX10-NEXT: v_mov_b32_e32 v9, s11
; GFX10-NEXT: s_mov_b32 s9, s11 ; GFX10-NEXT: v_mov_b32_e32 v10, s12
; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: v_mov_b32_e32 v11, s13
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0
; GFX10-NEXT: s_mov_b32 s11, s13 ; GFX10-NEXT: v_mov_b32_e32 v1, s14
; GFX10-NEXT: s_mov_b32 s12, s14 ; GFX10-NEXT: v_mov_b32_e32 v12, s15
; GFX10-NEXT: s_mov_b32 s13, s15 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s6, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s7, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s8, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s9, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s10, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s11, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s12, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s13, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v3, v12, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, s14, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, s15, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: dyn_extract_v7f64_s_v: ; GFX11-LABEL: dyn_extract_v7f64_s_v:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_mov_b32 s0, s2 ; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: s_mov_b32 s2, s4 ; GFX11-NEXT: v_dual_mov_b32 v13, s4 :: v_dual_mov_b32 v14, s5
; GFX11-NEXT: s_mov_b32 s19, s5
; GFX11-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s19
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX11-NEXT: s_mov_b32 s1, s3 ; GFX11-NEXT: v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v5, s7
; GFX11-NEXT: s_mov_b32 s4, s6 ; GFX11-NEXT: v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, s9
; GFX11-NEXT: s_mov_b32 s5, s7 ; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v13 :: v_dual_cndmask_b32 v3, v3, v14
; GFX11-NEXT: s_mov_b32 s6, s8
; GFX11-NEXT: v_cndmask_b32_e32 v1, s0, v1, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e32 v2, s1, v2, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0
; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: v_dual_mov_b32 v8, s10 :: v_dual_mov_b32 v9, s11
; GFX11-NEXT: s_mov_b32 s8, s10 ; GFX11-NEXT: v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v11, s13
; GFX11-NEXT: s_mov_b32 s9, s11 ; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v3, v3, v5
; GFX11-NEXT: s_mov_b32 s10, s12
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s5, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0
; GFX11-NEXT: s_mov_b32 s11, s13 ; GFX11-NEXT: v_dual_mov_b32 v1, s14 :: v_dual_mov_b32 v12, s15
; GFX11-NEXT: s_mov_b32 s12, s14 ; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v6 :: v_dual_cndmask_b32 v3, v3, v7
; GFX11-NEXT: s_mov_b32 s13, s15
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s6, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s7, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s8, vcc_lo ; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v8 :: v_dual_cndmask_b32 v3, v3, v9
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s9, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s10, vcc_lo ; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v10 :: v_dual_cndmask_b32 v3, v3, v11
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s11, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s12, vcc_lo ; GFX11-NEXT: v_dual_cndmask_b32 v1, v2, v1 :: v_dual_cndmask_b32 v2, v3, v12
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s13, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0
; GFX11-NEXT: v_cndmask_b32_e64 v0, v1, s14, vcc_lo ; GFX11-NEXT: v_dual_cndmask_b32 v0, v1, v3 :: v_dual_cndmask_b32 v1, v2, v4
; GFX11-NEXT: v_cndmask_b32_e64 v1, v2, s15, vcc_lo
; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: v_readfirstlane_b32 s1, v1 ; GFX11-NEXT: v_readfirstlane_b32 s1, v1
; GFX11-NEXT: ; return to shader part epilog ; GFX11-NEXT: ; return to shader part epilog
entry: entry:
%ext = extractelement <7 x double> %vec, i32 %sel %ext = extractelement <7 x double> %vec, i32 %sel
ret double %ext ret double %ext
} }
▲ Show 20 Lines • Show All 1,873 Lines • ▼ Show 20 Linesentry:
store double %ext, ptr addrspace(1) %out store double %ext, ptr addrspace(1) %out
ret void ret void
} }
define i32 @v_extract_v64i32_7(ptr addrspace(1) %ptr) { define i32 @v_extract_v64i32_7(ptr addrspace(1) %ptr) {
; GPRIDX-LABEL: v_extract_v64i32_7: ; GPRIDX-LABEL: v_extract_v64i32_7:
; GPRIDX: ; %bb.0: ; GPRIDX: ; %bb.0:
; GPRIDX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GPRIDX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GPRIDX-NEXT: global_load_dwordx4 v[4:7], v[0:1], off offset:16 ; GPRIDX-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:16
; GPRIDX-NEXT: s_waitcnt vmcnt(0) ; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: v_mov_b32_e32 v0, v7 ; GPRIDX-NEXT: v_mov_b32_e32 v0, v3
; GPRIDX-NEXT: s_setpc_b64 s[30:31] ; GPRIDX-NEXT: s_setpc_b64 s[30:31]
; ;
; MOVREL-LABEL: v_extract_v64i32_7: ; MOVREL-LABEL: v_extract_v64i32_7:
; MOVREL: ; %bb.0: ; MOVREL: ; %bb.0:
; MOVREL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; MOVREL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; MOVREL-NEXT: v_add_u32_e32 v0, vcc, 16, v0 ; MOVREL-NEXT: v_add_u32_e32 v0, vcc, 16, v0
; MOVREL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; MOVREL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; MOVREL-NEXT: flat_load_dwordx4 v[4:7], v[0:1] ; MOVREL-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; MOVREL-NEXT: s_waitcnt vmcnt(0) ; MOVREL-NEXT: s_waitcnt vmcnt(0)
; MOVREL-NEXT: v_mov_b32_e32 v0, v7 ; MOVREL-NEXT: v_mov_b32_e32 v0, v3
; MOVREL-NEXT: s_setpc_b64 s[30:31] ; MOVREL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_extract_v64i32_7: ; GFX10-LABEL: v_extract_v64i32_7:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: global_load_dwordx4 v[4:7], v[0:1], off offset:16 ; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, v7 ; GFX10-NEXT: v_mov_b32_e32 v0, v3
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_extract_v64i32_7: ; GFX11-LABEL: v_extract_v64i32_7:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: global_load_b128 v[4:7], v[0:1], off offset:16 ; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off offset:16
; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_mov_b32_e32 v0, v7 ; GFX11-NEXT: v_mov_b32_e32 v0, v3
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
%vec = load <64 x i32>, ptr addrspace(1) %ptr %vec = load <64 x i32>, ptr addrspace(1) %ptr
%elt = extractelement <64 x i32> %vec, i32 7 %elt = extractelement <64 x i32> %vec, i32 7
ret i32 %elt ret i32 %elt
} }
define i32 @v_extract_v64i32_32(ptr addrspace(1) %ptr) { define i32 @v_extract_v64i32_32(ptr addrspace(1) %ptr) {
; GPRIDX-LABEL: v_extract_v64i32_32: ; GPRIDX-LABEL: v_extract_v64i32_32:
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Lines; GFX11-NEXT: s_setpc_b64 s[30:31]
%elt = extractelement <64 x i32> %vec, i32 33 %elt = extractelement <64 x i32> %vec, i32 33
ret i32 %elt ret i32 %elt
} }
define i32 @v_extract_v64i32_37(ptr addrspace(1) %ptr) { define i32 @v_extract_v64i32_37(ptr addrspace(1) %ptr) {
; GPRIDX-LABEL: v_extract_v64i32_37: ; GPRIDX-LABEL: v_extract_v64i32_37:
; GPRIDX: ; %bb.0: ; GPRIDX: ; %bb.0:
; GPRIDX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GPRIDX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GPRIDX-NEXT: global_load_dwordx4 v[4:7], v[0:1], off offset:144 ; GPRIDX-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:144
; GPRIDX-NEXT: s_waitcnt vmcnt(0) ; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: v_mov_b32_e32 v0, v5 ; GPRIDX-NEXT: v_mov_b32_e32 v0, v1
; GPRIDX-NEXT: s_setpc_b64 s[30:31] ; GPRIDX-NEXT: s_setpc_b64 s[30:31]
; ;
; MOVREL-LABEL: v_extract_v64i32_37: ; MOVREL-LABEL: v_extract_v64i32_37:
; MOVREL: ; %bb.0: ; MOVREL: ; %bb.0:
; MOVREL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; MOVREL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; MOVREL-NEXT: v_add_u32_e32 v0, vcc, 0x90, v0 ; MOVREL-NEXT: v_add_u32_e32 v0, vcc, 0x90, v0
; MOVREL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; MOVREL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; MOVREL-NEXT: flat_load_dwordx4 v[4:7], v[0:1] ; MOVREL-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; MOVREL-NEXT: s_waitcnt vmcnt(0) ; MOVREL-NEXT: s_waitcnt vmcnt(0)
; MOVREL-NEXT: v_mov_b32_e32 v0, v5 ; MOVREL-NEXT: v_mov_b32_e32 v0, v1
; MOVREL-NEXT: s_setpc_b64 s[30:31] ; MOVREL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_extract_v64i32_37: ; GFX10-LABEL: v_extract_v64i32_37:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: global_load_dwordx4 v[4:7], v[0:1], off offset:144 ; GFX10-NEXT: global_load_dwordx4 v[0:3], v[0:1], off offset:144
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, v5 ; GFX10-NEXT: v_mov_b32_e32 v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_extract_v64i32_37: ; GFX11-LABEL: v_extract_v64i32_37:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: global_load_b128 v[4:7], v[0:1], off offset:144 ; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off offset:144
; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_mov_b32_e32 v0, v5 ; GFX11-NEXT: v_mov_b32_e32 v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
%vec = load <64 x i32>, ptr addrspace(1) %ptr %vec = load <64 x i32>, ptr addrspace(1) %ptr
%elt = extractelement <64 x i32> %vec, i32 37 %elt = extractelement <64 x i32> %vec, i32 37
ret i32 %elt ret i32 %elt
} }

llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll

Show First 20 Lines • Show All 3,255 Lines • ▼ Show 20 Lines
; GFX9-NEXT: s_not_b32 s13, s0 ; GFX9-NEXT: s_not_b32 s13, s0
; GFX9-NEXT: v_mov_b32_e32 v0, s1 ; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s12, 2 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s12, 2
; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], s12, 3 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], s12, 3
; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], s12, 4 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], s12, 4
; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], s12, 5 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], s12, 5
; GFX9-NEXT: v_cmp_eq_u32_e64 s[8:9], s12, 6 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[8:9], s12, 6
; GFX9-NEXT: v_cmp_eq_u32_e64 s[10:11], s12, 7 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[10:11], s12, 7
; GFX9-NEXT: v_mov_b32_e32 v10, 0
; GFX9-NEXT: v_mov_b32_e32 v11, 0
; GFX9-NEXT: v_mov_b32_e32 v12, 16
; GFX9-NEXT: v_mov_b32_e32 v13, 0
; GFX9-NEXT: s_waitcnt vmcnt(1) ; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[2:3] ; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[2:3]
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[4:5] ; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[6:7] ; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[6:7]
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[8:9] ; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[8:9]
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v9, s[10:11] ; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v9, s[10:11]
; GFX9-NEXT: v_and_or_b32 v10, v1, s13, v0 ; GFX9-NEXT: v_and_or_b32 v14, v1, s13, v0
; GFX9-NEXT: v_cmp_eq_u32_e64 s[12:13], s12, 0 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[12:13], s12, 0
; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, v10, s[12:13] ; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, v14, s[12:13]
; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v14, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v2, v4, v10, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v2, v4, v14, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v3, v5, v10, s[2:3] ; GFX9-NEXT: v_cndmask_b32_e64 v3, v5, v14, s[2:3]
; GFX9-NEXT: v_cndmask_b32_e64 v4, v6, v10, s[4:5] ; GFX9-NEXT: v_cndmask_b32_e64 v4, v6, v14, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v5, v7, v10, s[6:7] ; GFX9-NEXT: v_cndmask_b32_e64 v5, v7, v14, s[6:7]
; GFX9-NEXT: v_cndmask_b32_e64 v6, v8, v10, s[8:9] ; GFX9-NEXT: v_cndmask_b32_e64 v6, v8, v14, s[8:9]
; GFX9-NEXT: v_cndmask_b32_e64 v7, v9, v10, s[10:11] ; GFX9-NEXT: v_cndmask_b32_e64 v7, v9, v14, s[10:11]
; GFX9-NEXT: v_mov_b32_e32 v8, 0 ; GFX9-NEXT: global_store_dwordx4 v[10:11], v[0:3], off
; GFX9-NEXT: v_mov_b32_e32 v9, 0 ; GFX9-NEXT: global_store_dwordx4 v[12:13], v[4:7], off
; GFX9-NEXT: v_mov_b32_e32 v10, 16
; GFX9-NEXT: v_mov_b32_e32 v11, 0
; GFX9-NEXT: global_store_dwordx4 v[8:9], v[0:3], off
; GFX9-NEXT: global_store_dwordx4 v[10:11], v[4:7], off
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX8-LABEL: insertelement_v_v16i16_s_s: ; GFX8-LABEL: insertelement_v_v16i16_s_s:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: v_add_u32_e32 v4, vcc, 16, v0 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, 16, v0
; GFX8-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc ; GFX8-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1] ; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; GFX8-NEXT: flat_load_dwordx4 v[4:7], v[4:5] ; GFX8-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Lines; GFX11-NEXT: s_endpgm
store <16 x i16> %insert, ptr addrspace(1) null store <16 x i16> %insert, ptr addrspace(1) null
ret void ret void
} }
define amdgpu_ps void @insertelement_s_v16i16_v_s(ptr addrspace(4) inreg %ptr, i16 %val, i32 inreg %idx) { define amdgpu_ps void @insertelement_s_v16i16_v_s(ptr addrspace(4) inreg %ptr, i16 %val, i32 inreg %idx) {
; GFX9-LABEL: insertelement_s_v16i16_v_s: ; GFX9-LABEL: insertelement_s_v16i16_v_s:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx8 s[8:15], s[2:3], 0x0 ; GFX9-NEXT: s_load_dwordx8 s[8:15], s[2:3], 0x0
; GFX9-NEXT: s_lshr_b32 s2, s4, 1 ; GFX9-NEXT: s_lshr_b32 s0, s4, 1
; GFX9-NEXT: s_cmp_eq_u32 s2, 1 ; GFX9-NEXT: s_cmp_eq_u32 s0, 1
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s2, 0 ; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s0, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_cselect_b32 s0, s9, s8 ; GFX9-NEXT: s_cselect_b32 s1, s9, s8
; GFX9-NEXT: s_cmp_eq_u32 s2, 2 ; GFX9-NEXT: s_cmp_eq_u32 s0, 2
; GFX9-NEXT: s_cselect_b32 s0, s10, s0 ; GFX9-NEXT: s_cselect_b32 s1, s10, s1
; GFX9-NEXT: s_cmp_eq_u32 s2, 3 ; GFX9-NEXT: s_cmp_eq_u32 s0, 3
; GFX9-NEXT: s_cselect_b32 s0, s11, s0 ; GFX9-NEXT: s_cselect_b32 s1, s11, s1
; GFX9-NEXT: s_cmp_eq_u32 s2, 4 ; GFX9-NEXT: s_cmp_eq_u32 s0, 4
; GFX9-NEXT: s_cselect_b32 s0, s12, s0 ; GFX9-NEXT: s_cselect_b32 s1, s12, s1
; GFX9-NEXT: s_cmp_eq_u32 s2, 5 ; GFX9-NEXT: s_cmp_eq_u32 s0, 5
; GFX9-NEXT: s_cselect_b32 s0, s13, s0 ; GFX9-NEXT: s_cselect_b32 s1, s13, s1
; GFX9-NEXT: s_cmp_eq_u32 s2, 6 ; GFX9-NEXT: s_cmp_eq_u32 s0, 6
; GFX9-NEXT: s_cselect_b32 s0, s14, s0 ; GFX9-NEXT: s_cselect_b32 s1, s14, s1
; GFX9-NEXT: s_cmp_eq_u32 s2, 7 ; GFX9-NEXT: s_cmp_eq_u32 s0, 7
; GFX9-NEXT: s_cselect_b32 s0, s15, s0 ; GFX9-NEXT: s_cselect_b32 s1, s15, s1
; GFX9-NEXT: s_and_b32 s1, s4, 1 ; GFX9-NEXT: s_and_b32 s2, s4, 1
; GFX9-NEXT: s_lshl_b32 s1, s1, 4 ; GFX9-NEXT: s_lshl_b32 s2, s2, 4
; GFX9-NEXT: s_lshl_b32 s3, 0xffff, s1 ; GFX9-NEXT: s_lshl_b32 s3, 0xffff, s2
; GFX9-NEXT: s_andn2_b32 s0, s0, s3 ; GFX9-NEXT: s_andn2_b32 s1, s1, s3
; GFX9-NEXT: v_mov_b32_e32 v1, s0 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_lshl_or_b32 v8, v0, s1, v1 ; GFX9-NEXT: v_lshl_or_b32 v8, v0, s2, v1
; GFX9-NEXT: v_mov_b32_e32 v0, s8 ; GFX9-NEXT: v_mov_b32_e32 v0, s8
; GFX9-NEXT: v_mov_b32_e32 v1, s9 ; GFX9-NEXT: v_mov_b32_e32 v1, s9
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc
; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s2, 1 ; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s0, 1
; GFX9-NEXT: v_mov_b32_e32 v2, s10 ; GFX9-NEXT: v_mov_b32_e32 v2, s10
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc
; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s2, 2 ; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s0, 2
; GFX9-NEXT: v_mov_b32_e32 v3, s11 ; GFX9-NEXT: v_mov_b32_e32 v3, s11
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc
; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s2, 3 ; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s0, 3
; GFX9-NEXT: v_mov_b32_e32 v5, s13 ; GFX9-NEXT: v_mov_b32_e32 v4, s12
; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s2, 5 ; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s0, 4
; GFX9-NEXT: v_mov_b32_e32 v5, s13
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s0, 5
; GFX9-NEXT: v_mov_b32_e32 v6, s14 ; GFX9-NEXT: v_mov_b32_e32 v6, s14
; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s2, 6 ; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s0, 6
; GFX9-NEXT: v_mov_b32_e32 v4, s12
; GFX9-NEXT: v_mov_b32_e32 v7, s15 ; GFX9-NEXT: v_mov_b32_e32 v7, s15
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s2, 4
; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s2, 7 ; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s0, 7
; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v8, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
; GFX9-NEXT: v_mov_b32_e32 v8, 0 ; GFX9-NEXT: v_mov_b32_e32 v8, 0
; GFX9-NEXT: v_mov_b32_e32 v9, 0 ; GFX9-NEXT: v_mov_b32_e32 v9, 0
; GFX9-NEXT: v_mov_b32_e32 v10, 16 ; GFX9-NEXT: v_mov_b32_e32 v10, 16
; GFX9-NEXT: v_mov_b32_e32 v11, 0 ; GFX9-NEXT: v_mov_b32_e32 v11, 0
; GFX9-NEXT: global_store_dwordx4 v[8:9], v[0:3], off ; GFX9-NEXT: global_store_dwordx4 v[8:9], v[0:3], off
; GFX9-NEXT: global_store_dwordx4 v[10:11], v[4:7], off ; GFX9-NEXT: global_store_dwordx4 v[10:11], v[4:7], off
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
▲ Show 20 Lines • Show All 726 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_lshlrev_b32_e64 v1, v1, s0 ; GFX9-NEXT: v_lshlrev_b32_e64 v1, v1, s0
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v0 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v0
; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v0 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v0
; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 4, v0 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 4, v0
; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v0 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v0
; GFX9-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v0 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v0
; GFX9-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v0 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v0
; GFX9-NEXT: v_not_b32_e32 v1, v1 ; GFX9-NEXT: v_not_b32_e32 v1, v1
; GFX9-NEXT: v_mov_b32_e32 v11, 0
; GFX9-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v0 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v0
; GFX9-NEXT: v_mov_b32_e32 v12, 0
; GFX9-NEXT: v_mov_b32_e32 v13, 16
; GFX9-NEXT: v_mov_b32_e32 v14, 0
; GFX9-NEXT: s_waitcnt vmcnt(1) ; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_cndmask_b32_e32 v11, v3, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v15, v3, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, v5, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v15, v15, v5, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, v6, s[2:3] ; GFX9-NEXT: v_cndmask_b32_e64 v15, v15, v6, s[2:3]
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, v7, s[4:5] ; GFX9-NEXT: v_cndmask_b32_e64 v15, v15, v7, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, v8, s[6:7] ; GFX9-NEXT: v_cndmask_b32_e64 v15, v15, v8, s[6:7]
; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, v9, s[8:9] ; GFX9-NEXT: v_cndmask_b32_e64 v15, v15, v9, s[8:9]
; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, v10, s[10:11] ; GFX9-NEXT: v_cndmask_b32_e64 v15, v15, v10, s[10:11]
; GFX9-NEXT: v_and_or_b32 v11, v11, v1, v2 ; GFX9-NEXT: v_and_or_b32 v15, v15, v1, v2
; GFX9-NEXT: v_cndmask_b32_e64 v0, v3, v11, s[12:13] ; GFX9-NEXT: v_cndmask_b32_e64 v0, v3, v15, s[12:13]
; GFX9-NEXT: v_cndmask_b32_e64 v2, v5, v11, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v15, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v3, v6, v11, s[2:3] ; GFX9-NEXT: v_cndmask_b32_e64 v2, v5, v15, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v5, v8, v11, s[6:7] ; GFX9-NEXT: v_cndmask_b32_e64 v3, v6, v15, s[2:3]
; GFX9-NEXT: v_cndmask_b32_e64 v6, v9, v11, s[8:9] ; GFX9-NEXT: v_cndmask_b32_e64 v4, v7, v15, s[4:5]
; GFX9-NEXT: v_mov_b32_e32 v8, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v5, v8, v15, s[6:7]
; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v11, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v6, v9, v15, s[8:9]
; GFX9-NEXT: v_cndmask_b32_e64 v4, v7, v11, s[4:5] ; GFX9-NEXT: v_cndmask_b32_e64 v7, v10, v15, s[10:11]
; GFX9-NEXT: v_cndmask_b32_e64 v7, v10, v11, s[10:11] ; GFX9-NEXT: global_store_dwordx4 v[11:12], v[0:3], off
; GFX9-NEXT: v_mov_b32_e32 v9, 0 ; GFX9-NEXT: global_store_dwordx4 v[13:14], v[4:7], off
; GFX9-NEXT: v_mov_b32_e32 v10, 16
; GFX9-NEXT: v_mov_b32_e32 v11, 0
; GFX9-NEXT: global_store_dwordx4 v[8:9], v[0:3], off
; GFX9-NEXT: global_store_dwordx4 v[10:11], v[4:7], off
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX8-LABEL: insertelement_v_v16i16_s_v: ; GFX8-LABEL: insertelement_v_v16i16_s_v:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: flat_load_dwordx4 v[3:6], v[0:1] ; GFX8-NEXT: flat_load_dwordx4 v[3:6], v[0:1]
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 16, v0 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 16, v0
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dwordx4 v[7:10], v[0:1] ; GFX8-NEXT: flat_load_dwordx4 v[7:10], v[0:1]
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 1, v2 ; GFX8-NEXT: v_lshrrev_b32_e32 v0, 1, v2
; GFX8-NEXT: v_and_b32_e32 v1, 1, v2 ; GFX8-NEXT: v_and_b32_e32 v1, 1, v2
; GFX8-NEXT: s_mov_b32 s0, 0xffff ; GFX8-NEXT: s_mov_b32 s0, 0xffff
; GFX8-NEXT: s_and_b32 s1, s2, 0xffff ; GFX8-NEXT: s_and_b32 s1, s2, 0xffff
; GFX8-NEXT: v_lshlrev_b32_e32 v1, 4, v1 ; GFX8-NEXT: v_lshlrev_b32_e32 v1, 4, v1
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX8-NEXT: v_lshlrev_b32_e64 v2, v1, s1 ; GFX8-NEXT: v_lshlrev_b32_e64 v2, v1, s1
; GFX8-NEXT: v_lshlrev_b32_e64 v1, v1, s0 ; GFX8-NEXT: v_lshlrev_b32_e64 v1, v1, s0
; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v0 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v0
; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v0 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v0
; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 4, v0 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 4, v0
; GFX8-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v0 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v0
; GFX8-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v0 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v0
; GFX8-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v0 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v0
; GFX8-NEXT: v_not_b32_e32 v1, v1 ; GFX8-NEXT: v_not_b32_e32 v1, v1
; GFX8-NEXT: v_mov_b32_e32 v11, 0
; GFX8-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v0 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v0
; GFX8-NEXT: v_mov_b32_e32 v12, 0
; GFX8-NEXT: v_mov_b32_e32 v13, 16
; GFX8-NEXT: v_mov_b32_e32 v14, 0
; GFX8-NEXT: s_waitcnt vmcnt(1) ; GFX8-NEXT: s_waitcnt vmcnt(1)
; GFX8-NEXT: v_cndmask_b32_e32 v11, v3, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v15, v3, v4, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v5, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v15, v15, v5, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v6, s[2:3] ; GFX8-NEXT: v_cndmask_b32_e64 v15, v15, v6, s[2:3]
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v7, s[4:5] ; GFX8-NEXT: v_cndmask_b32_e64 v15, v15, v7, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v8, s[6:7] ; GFX8-NEXT: v_cndmask_b32_e64 v15, v15, v8, s[6:7]
; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v9, s[8:9] ; GFX8-NEXT: v_cndmask_b32_e64 v15, v15, v9, s[8:9]
; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v10, s[10:11] ; GFX8-NEXT: v_cndmask_b32_e64 v15, v15, v10, s[10:11]
; GFX8-NEXT: v_and_b32_e32 v1, v11, v1 ; GFX8-NEXT: v_and_b32_e32 v1, v15, v1
; GFX8-NEXT: v_or_b32_e32 v11, v1, v2 ; GFX8-NEXT: v_or_b32_e32 v15, v1, v2
; GFX8-NEXT: v_cndmask_b32_e64 v0, v3, v11, s[12:13] ; GFX8-NEXT: v_cndmask_b32_e64 v0, v3, v15, s[12:13]
; GFX8-NEXT: v_cndmask_b32_e64 v2, v5, v11, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v15, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v3, v6, v11, s[2:3] ; GFX8-NEXT: v_cndmask_b32_e64 v2, v5, v15, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v5, v8, v11, s[6:7] ; GFX8-NEXT: v_cndmask_b32_e64 v3, v6, v15, s[2:3]
; GFX8-NEXT: v_cndmask_b32_e64 v6, v9, v11, s[8:9] ; GFX8-NEXT: v_cndmask_b32_e64 v4, v7, v15, s[4:5]
; GFX8-NEXT: v_mov_b32_e32 v8, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v5, v8, v15, s[6:7]
; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v11, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v6, v9, v15, s[8:9]
; GFX8-NEXT: v_cndmask_b32_e64 v4, v7, v11, s[4:5] ; GFX8-NEXT: v_cndmask_b32_e64 v7, v10, v15, s[10:11]
; GFX8-NEXT: v_cndmask_b32_e64 v7, v10, v11, s[10:11] ; GFX8-NEXT: flat_store_dwordx4 v[11:12], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v9, 0 ; GFX8-NEXT: flat_store_dwordx4 v[13:14], v[4:7]
; GFX8-NEXT: v_mov_b32_e32 v10, 16
; GFX8-NEXT: v_mov_b32_e32 v11, 0
; GFX8-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
; GFX8-NEXT: flat_store_dwordx4 v[10:11], v[4:7]
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX7-LABEL: insertelement_v_v16i16_s_v: ; GFX7-LABEL: insertelement_v_v16i16_s_v:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_mov_b32 s18, 0 ; GFX7-NEXT: s_mov_b32 s18, 0
; GFX7-NEXT: s_mov_b32 s19, 0xf000 ; GFX7-NEXT: s_mov_b32 s19, 0xf000
; GFX7-NEXT: s_mov_b64 s[16:17], 0 ; GFX7-NEXT: s_mov_b64 s[16:17], 0
; GFX7-NEXT: buffer_load_dwordx4 v[3:6], v[0:1], s[16:19], 0 addr64 ; GFX7-NEXT: buffer_load_dwordx4 v[3:6], v[0:1], s[16:19], 0 addr64
▲ Show 20 Lines • Show All 155 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s12, 1 ; GFX9-NEXT: v_cmp_eq_u32_e64 vcc, s12, 1
; GFX9-NEXT: s_not_b32 s13, s0 ; GFX9-NEXT: s_not_b32 s13, s0
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s12, 2 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s12, 2
; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], s12, 3 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], s12, 3
; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], s12, 4 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], s12, 4
; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], s12, 5 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], s12, 5
; GFX9-NEXT: v_cmp_eq_u32_e64 s[8:9], s12, 6 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[8:9], s12, 6
; GFX9-NEXT: v_cmp_eq_u32_e64 s[10:11], s12, 7 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[10:11], s12, 7
; GFX9-NEXT: v_mov_b32_e32 v11, 0
; GFX9-NEXT: v_mov_b32_e32 v12, 0
; GFX9-NEXT: v_mov_b32_e32 v13, 16
; GFX9-NEXT: v_mov_b32_e32 v14, 0
; GFX9-NEXT: s_waitcnt vmcnt(1) ; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[2:3] ; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[2:3]
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[4:5] ; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[6:7] ; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[6:7]
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v9, s[8:9] ; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v9, s[8:9]
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v10, s[10:11] ; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v10, s[10:11]
; GFX9-NEXT: v_and_or_b32 v11, v1, s13, v0 ; GFX9-NEXT: v_and_or_b32 v15, v1, s13, v0
; GFX9-NEXT: v_cmp_eq_u32_e64 s[12:13], s12, 0 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[12:13], s12, 0
; GFX9-NEXT: v_cndmask_b32_e64 v0, v3, v11, s[12:13] ; GFX9-NEXT: v_cndmask_b32_e64 v0, v3, v15, s[12:13]
; GFX9-NEXT: v_cndmask_b32_e64 v2, v5, v11, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v15, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v3, v6, v11, s[2:3] ; GFX9-NEXT: v_cndmask_b32_e64 v2, v5, v15, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v5, v8, v11, s[6:7] ; GFX9-NEXT: v_cndmask_b32_e64 v3, v6, v15, s[2:3]
; GFX9-NEXT: v_cndmask_b32_e64 v6, v9, v11, s[8:9] ; GFX9-NEXT: v_cndmask_b32_e64 v4, v7, v15, s[4:5]
; GFX9-NEXT: v_mov_b32_e32 v8, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v5, v8, v15, s[6:7]
; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v11, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v6, v9, v15, s[8:9]
; GFX9-NEXT: v_cndmask_b32_e64 v4, v7, v11, s[4:5] ; GFX9-NEXT: v_cndmask_b32_e64 v7, v10, v15, s[10:11]
; GFX9-NEXT: v_cndmask_b32_e64 v7, v10, v11, s[10:11] ; GFX9-NEXT: global_store_dwordx4 v[11:12], v[0:3], off
; GFX9-NEXT: v_mov_b32_e32 v9, 0 ; GFX9-NEXT: global_store_dwordx4 v[13:14], v[4:7], off
; GFX9-NEXT: v_mov_b32_e32 v10, 16
; GFX9-NEXT: v_mov_b32_e32 v11, 0
; GFX9-NEXT: global_store_dwordx4 v[8:9], v[0:3], off
; GFX9-NEXT: global_store_dwordx4 v[10:11], v[4:7], off
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX8-LABEL: insertelement_v_v16i16_v_s: ; GFX8-LABEL: insertelement_v_v16i16_v_s:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: v_add_u32_e32 v7, vcc, 16, v0 ; GFX8-NEXT: v_add_u32_e32 v7, vcc, 16, v0
; GFX8-NEXT: v_addc_u32_e32 v8, vcc, 0, v1, vcc ; GFX8-NEXT: v_addc_u32_e32 v8, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dwordx4 v[3:6], v[0:1] ; GFX8-NEXT: flat_load_dwordx4 v[3:6], v[0:1]
; GFX8-NEXT: flat_load_dwordx4 v[7:10], v[7:8] ; GFX8-NEXT: flat_load_dwordx4 v[7:10], v[7:8]
▲ Show 20 Lines • Show All 112 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_lshlrev_b32_e64 v1, v1, s0 ; GFX9-NEXT: v_lshlrev_b32_e64 v1, v1, s0
; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v0 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v0
; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v0 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v0
; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 4, v0 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 4, v0
; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v0 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v0
; GFX9-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v0 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v0
; GFX9-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v0 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v0
; GFX9-NEXT: v_not_b32_e32 v1, v1 ; GFX9-NEXT: v_not_b32_e32 v1, v1
; GFX9-NEXT: v_mov_b32_e32 v12, 0
; GFX9-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v0 ; GFX9-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v0
; GFX9-NEXT: v_mov_b32_e32 v13, 0
; GFX9-NEXT: v_mov_b32_e32 v14, 16
; GFX9-NEXT: v_mov_b32_e32 v15, 0
; GFX9-NEXT: s_waitcnt vmcnt(1) ; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v7, s[2:3] ; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v7, s[2:3]
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v8, s[4:5] ; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v8, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v9, s[6:7] ; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v9, s[6:7]
; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v10, s[8:9] ; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v10, s[8:9]
; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v11, s[10:11] ; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v11, s[10:11]
; GFX9-NEXT: v_and_or_b32 v12, v3, v1, v2 ; GFX9-NEXT: v_and_or_b32 v16, v3, v1, v2
; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, v12, s[12:13] ; GFX9-NEXT: v_cndmask_b32_e64 v0, v4, v16, s[12:13]
; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v12, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v16, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v4, v8, v12, s[4:5] ; GFX9-NEXT: v_cndmask_b32_e64 v2, v6, v16, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v5, v9, v12, s[6:7] ; GFX9-NEXT: v_cndmask_b32_e64 v3, v7, v16, s[2:3]
; GFX9-NEXT: v_mov_b32_e32 v8, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v4, v8, v16, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v2, v6, v12, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v5, v9, v16, s[6:7]
; GFX9-NEXT: v_cndmask_b32_e64 v3, v7, v12, s[2:3] ; GFX9-NEXT: v_cndmask_b32_e64 v6, v10, v16, s[8:9]
; GFX9-NEXT: v_cndmask_b32_e64 v6, v10, v12, s[8:9] ; GFX9-NEXT: v_cndmask_b32_e64 v7, v11, v16, s[10:11]
; GFX9-NEXT: v_cndmask_b32_e64 v7, v11, v12, s[10:11] ; GFX9-NEXT: global_store_dwordx4 v[12:13], v[0:3], off
; GFX9-NEXT: v_mov_b32_e32 v9, 0 ; GFX9-NEXT: global_store_dwordx4 v[14:15], v[4:7], off
; GFX9-NEXT: v_mov_b32_e32 v10, 16
; GFX9-NEXT: v_mov_b32_e32 v11, 0
; GFX9-NEXT: global_store_dwordx4 v[8:9], v[0:3], off
; GFX9-NEXT: global_store_dwordx4 v[10:11], v[4:7], off
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX8-LABEL: insertelement_v_v16i16_v_v: ; GFX8-LABEL: insertelement_v_v16i16_v_v:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: flat_load_dwordx4 v[4:7], v[0:1] ; GFX8-NEXT: flat_load_dwordx4 v[4:7], v[0:1]
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 16, v0 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 16, v0
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dwordx4 v[8:11], v[0:1] ; GFX8-NEXT: flat_load_dwordx4 v[8:11], v[0:1]
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 1, v3 ; GFX8-NEXT: v_lshrrev_b32_e32 v0, 1, v3
; GFX8-NEXT: v_and_b32_e32 v1, 1, v3 ; GFX8-NEXT: v_and_b32_e32 v1, 1, v3
; GFX8-NEXT: s_mov_b32 s0, 0xffff ; GFX8-NEXT: s_mov_b32 s0, 0xffff
; GFX8-NEXT: v_lshlrev_b32_e32 v1, 4, v1 ; GFX8-NEXT: v_lshlrev_b32_e32 v1, 4, v1
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 ; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX8-NEXT: v_lshlrev_b32_e64 v1, v1, s0 ; GFX8-NEXT: v_lshlrev_b32_e64 v1, v1, s0
; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v0 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v0
; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v0 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v0
; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 4, v0 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 4, v0
; GFX8-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v0 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v0
; GFX8-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v0 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v0
; GFX8-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v0 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v0
; GFX8-NEXT: v_not_b32_e32 v1, v1 ; GFX8-NEXT: v_not_b32_e32 v1, v1
; GFX8-NEXT: v_mov_b32_e32 v12, 0
; GFX8-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v0 ; GFX8-NEXT: v_cmp_eq_u32_e64 s[12:13], 0, v0
; GFX8-NEXT: v_mov_b32_e32 v13, 0
; GFX8-NEXT: v_mov_b32_e32 v14, 16
; GFX8-NEXT: v_mov_b32_e32 v15, 0
; GFX8-NEXT: s_waitcnt vmcnt(1) ; GFX8-NEXT: s_waitcnt vmcnt(1)
; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v7, s[2:3] ; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v7, s[2:3]
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v8, s[4:5] ; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v8, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v9, s[6:7] ; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v9, s[6:7]
; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v10, s[8:9] ; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v10, s[8:9]
; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v11, s[10:11] ; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v11, s[10:11]
; GFX8-NEXT: v_and_b32_e32 v1, v3, v1 ; GFX8-NEXT: v_and_b32_e32 v1, v3, v1
; GFX8-NEXT: v_or_b32_e32 v12, v1, v2 ; GFX8-NEXT: v_or_b32_e32 v16, v1, v2
; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, v12, s[12:13] ; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, v16, s[12:13]
; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v12, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v16, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v4, v8, v12, s[4:5] ; GFX8-NEXT: v_cndmask_b32_e64 v2, v6, v16, s[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v5, v9, v12, s[6:7] ; GFX8-NEXT: v_cndmask_b32_e64 v3, v7, v16, s[2:3]
; GFX8-NEXT: v_mov_b32_e32 v8, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v4, v8, v16, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e64 v2, v6, v12, s[0:1] ; GFX8-NEXT: v_cndmask_b32_e64 v5, v9, v16, s[6:7]
; GFX8-NEXT: v_cndmask_b32_e64 v3, v7, v12, s[2:3] ; GFX8-NEXT: v_cndmask_b32_e64 v6, v10, v16, s[8:9]
; GFX8-NEXT: v_cndmask_b32_e64 v6, v10, v12, s[8:9] ; GFX8-NEXT: v_cndmask_b32_e64 v7, v11, v16, s[10:11]
; GFX8-NEXT: v_cndmask_b32_e64 v7, v11, v12, s[10:11] ; GFX8-NEXT: flat_store_dwordx4 v[12:13], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v9, 0 ; GFX8-NEXT: flat_store_dwordx4 v[14:15], v[4:7]
; GFX8-NEXT: v_mov_b32_e32 v10, 16
; GFX8-NEXT: v_mov_b32_e32 v11, 0
; GFX8-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
; GFX8-NEXT: flat_store_dwordx4 v[10:11], v[4:7]
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX7-LABEL: insertelement_v_v16i16_v_v: ; GFX7-LABEL: insertelement_v_v16i16_v_v:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_mov_b32 s18, 0 ; GFX7-NEXT: s_mov_b32 s18, 0
; GFX7-NEXT: s_mov_b32 s19, 0xf000 ; GFX7-NEXT: s_mov_b32 s19, 0xf000
; GFX7-NEXT: s_mov_b64 s[16:17], 0 ; GFX7-NEXT: s_mov_b64 s[16:17], 0
; GFX7-NEXT: buffer_load_dwordx4 v[4:7], v[0:1], s[16:19], 0 addr64 ; GFX7-NEXT: buffer_load_dwordx4 v[4:7], v[0:1], s[16:19], 0 addr64
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llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX11 %s ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX11 %s
define amdgpu_kernel void @v_insert_v64i32_37(ptr addrspace(1) %ptr.in, ptr addrspace(1) %ptr.out) #0 { define amdgpu_kernel void @v_insert_v64i32_37(ptr addrspace(1) %ptr.in, ptr addrspace(1) %ptr.out) #0 {
; GCN-LABEL: v_insert_v64i32_37: ; GCN-LABEL: v_insert_v64i32_37:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GCN-NEXT: v_lshlrev_b32_e32 v64, 8, v0 ; GCN-NEXT: v_lshlrev_b32_e32 v64, 8, v0
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: global_load_dwordx4 v[4:7], v64, s[0:1] offset:144
; GCN-NEXT: global_load_dwordx4 v[0:3], v64, s[0:1] ; GCN-NEXT: global_load_dwordx4 v[0:3], v64, s[0:1]
; GCN-NEXT: global_load_dwordx4 v[8:11], v64, s[0:1] offset:16 ; GCN-NEXT: global_load_dwordx4 v[4:7], v64, s[0:1] offset:16
; GCN-NEXT: global_load_dwordx4 v[12:15], v64, s[0:1] offset:32 ; GCN-NEXT: global_load_dwordx4 v[8:11], v64, s[0:1] offset:32
; GCN-NEXT: global_load_dwordx4 v[16:19], v64, s[0:1] offset:48 ; GCN-NEXT: global_load_dwordx4 v[12:15], v64, s[0:1] offset:48
; GCN-NEXT: global_load_dwordx4 v[20:23], v64, s[0:1] offset:64 ; GCN-NEXT: global_load_dwordx4 v[16:19], v64, s[0:1] offset:64
; GCN-NEXT: global_load_dwordx4 v[24:27], v64, s[0:1] offset:80 ; GCN-NEXT: global_load_dwordx4 v[20:23], v64, s[0:1] offset:80
; GCN-NEXT: global_load_dwordx4 v[28:31], v64, s[0:1] offset:96 ; GCN-NEXT: global_load_dwordx4 v[24:27], v64, s[0:1] offset:96
; GCN-NEXT: global_load_dwordx4 v[32:35], v64, s[0:1] offset:112 ; GCN-NEXT: global_load_dwordx4 v[28:31], v64, s[0:1] offset:112
; GCN-NEXT: global_load_dwordx4 v[36:39], v64, s[0:1] offset:128 ; GCN-NEXT: global_load_dwordx4 v[32:35], v64, s[0:1] offset:128
; GCN-NEXT: global_load_dwordx4 v[36:39], v64, s[0:1] offset:144
; GCN-NEXT: global_load_dwordx4 v[40:43], v64, s[0:1] offset:160 ; GCN-NEXT: global_load_dwordx4 v[40:43], v64, s[0:1] offset:160
; GCN-NEXT: global_load_dwordx4 v[44:47], v64, s[0:1] offset:176 ; GCN-NEXT: global_load_dwordx4 v[44:47], v64, s[0:1] offset:176
; GCN-NEXT: global_load_dwordx4 v[48:51], v64, s[0:1] offset:192 ; GCN-NEXT: global_load_dwordx4 v[48:51], v64, s[0:1] offset:192
; GCN-NEXT: global_load_dwordx4 v[52:55], v64, s[0:1] offset:208 ; GCN-NEXT: global_load_dwordx4 v[52:55], v64, s[0:1] offset:208
; GCN-NEXT: global_load_dwordx4 v[56:59], v64, s[0:1] offset:224 ; GCN-NEXT: global_load_dwordx4 v[56:59], v64, s[0:1] offset:224
; GCN-NEXT: global_load_dwordx4 v[60:63], v64, s[0:1] offset:240 ; GCN-NEXT: global_load_dwordx4 v[60:63], v64, s[0:1] offset:240
; GCN-NEXT: s_waitcnt vmcnt(15) ; GCN-NEXT: s_waitcnt vmcnt(6)
; GCN-NEXT: v_mov_b32_e32 v5, 0x3e7 ; GCN-NEXT: v_mov_b32_e32 v37, 0x3e7
; GCN-NEXT: global_store_dwordx4 v64, v[4:7], s[2:3] offset:144
; GCN-NEXT: s_waitcnt vmcnt(15)
; GCN-NEXT: global_store_dwordx4 v64, v[0:3], s[2:3] ; GCN-NEXT: global_store_dwordx4 v64, v[0:3], s[2:3]
; GCN-NEXT: s_waitcnt vmcnt(15) ; GCN-NEXT: global_store_dwordx4 v64, v[4:7], s[2:3] offset:16
; GCN-NEXT: global_store_dwordx4 v64, v[8:11], s[2:3] offset:16 ; GCN-NEXT: global_store_dwordx4 v64, v[8:11], s[2:3] offset:32
; GCN-NEXT: s_waitcnt vmcnt(15) ; GCN-NEXT: global_store_dwordx4 v64, v[12:15], s[2:3] offset:48
; GCN-NEXT: global_store_dwordx4 v64, v[12:15], s[2:3] offset:32 ; GCN-NEXT: global_store_dwordx4 v64, v[16:19], s[2:3] offset:64
; GCN-NEXT: s_waitcnt vmcnt(15) ; GCN-NEXT: global_store_dwordx4 v64, v[20:23], s[2:3] offset:80
; GCN-NEXT: global_store_dwordx4 v64, v[16:19], s[2:3] offset:48 ; GCN-NEXT: global_store_dwordx4 v64, v[24:27], s[2:3] offset:96
; GCN-NEXT: s_waitcnt vmcnt(15) ; GCN-NEXT: global_store_dwordx4 v64, v[28:31], s[2:3] offset:112
; GCN-NEXT: global_store_dwordx4 v64, v[20:23], s[2:3] offset:64 ; GCN-NEXT: global_store_dwordx4 v64, v[32:35], s[2:3] offset:128
; GCN-NEXT: s_waitcnt vmcnt(15) ; GCN-NEXT: global_store_dwordx4 v64, v[36:39], s[2:3] offset:144
; GCN-NEXT: global_store_dwordx4 v64, v[24:27], s[2:3] offset:80
; GCN-NEXT: s_waitcnt vmcnt(15)
; GCN-NEXT: global_store_dwordx4 v64, v[28:31], s[2:3] offset:96
; GCN-NEXT: s_waitcnt vmcnt(15)
; GCN-NEXT: global_store_dwordx4 v64, v[32:35], s[2:3] offset:112
; GCN-NEXT: s_waitcnt vmcnt(15)
; GCN-NEXT: global_store_dwordx4 v64, v[36:39], s[2:3] offset:128
; GCN-NEXT: s_waitcnt vmcnt(15) ; GCN-NEXT: s_waitcnt vmcnt(15)
; GCN-NEXT: global_store_dwordx4 v64, v[40:43], s[2:3] offset:160 ; GCN-NEXT: global_store_dwordx4 v64, v[40:43], s[2:3] offset:160
; GCN-NEXT: s_waitcnt vmcnt(15) ; GCN-NEXT: s_waitcnt vmcnt(15)
; GCN-NEXT: global_store_dwordx4 v64, v[44:47], s[2:3] offset:176 ; GCN-NEXT: global_store_dwordx4 v64, v[44:47], s[2:3] offset:176
; GCN-NEXT: s_waitcnt vmcnt(15) ; GCN-NEXT: s_waitcnt vmcnt(15)
; GCN-NEXT: global_store_dwordx4 v64, v[48:51], s[2:3] offset:192 ; GCN-NEXT: global_store_dwordx4 v64, v[48:51], s[2:3] offset:192
; GCN-NEXT: s_waitcnt vmcnt(15) ; GCN-NEXT: s_waitcnt vmcnt(15)
; GCN-NEXT: global_store_dwordx4 v64, v[52:55], s[2:3] offset:208 ; GCN-NEXT: global_store_dwordx4 v64, v[52:55], s[2:3] offset:208
; GCN-NEXT: s_waitcnt vmcnt(15) ; GCN-NEXT: s_waitcnt vmcnt(15)
; GCN-NEXT: global_store_dwordx4 v64, v[56:59], s[2:3] offset:224 ; GCN-NEXT: global_store_dwordx4 v64, v[56:59], s[2:3] offset:224
; GCN-NEXT: s_waitcnt vmcnt(15) ; GCN-NEXT: s_waitcnt vmcnt(15)
; GCN-NEXT: global_store_dwordx4 v64, v[60:63], s[2:3] offset:240 ; GCN-NEXT: global_store_dwordx4 v64, v[60:63], s[2:3] offset:240
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; GFX10-LABEL: v_insert_v64i32_37: ; GFX10-LABEL: v_insert_v64i32_37:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-NEXT: v_lshlrev_b32_e32 v64, 8, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v64, 8, v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0xf ; GFX10-NEXT: s_clause 0xf
; GFX10-NEXT: global_load_dwordx4 v[0:3], v64, s[0:1] ; GFX10-NEXT: global_load_dwordx4 v[0:3], v64, s[0:1]
; GFX10-NEXT: global_load_dwordx4 v[8:11], v64, s[0:1] offset:16 ; GFX10-NEXT: global_load_dwordx4 v[4:7], v64, s[0:1] offset:16
; GFX10-NEXT: global_load_dwordx4 v[12:15], v64, s[0:1] offset:32 ; GFX10-NEXT: global_load_dwordx4 v[8:11], v64, s[0:1] offset:32
; GFX10-NEXT: global_load_dwordx4 v[16:19], v64, s[0:1] offset:48 ; GFX10-NEXT: global_load_dwordx4 v[12:15], v64, s[0:1] offset:48
; GFX10-NEXT: global_load_dwordx4 v[20:23], v64, s[0:1] offset:64 ; GFX10-NEXT: global_load_dwordx4 v[16:19], v64, s[0:1] offset:64
; GFX10-NEXT: global_load_dwordx4 v[24:27], v64, s[0:1] offset:80 ; GFX10-NEXT: global_load_dwordx4 v[20:23], v64, s[0:1] offset:80
; GFX10-NEXT: global_load_dwordx4 v[28:31], v64, s[0:1] offset:96 ; GFX10-NEXT: global_load_dwordx4 v[24:27], v64, s[0:1] offset:96
; GFX10-NEXT: global_load_dwordx4 v[32:35], v64, s[0:1] offset:112 ; GFX10-NEXT: global_load_dwordx4 v[28:31], v64, s[0:1] offset:112
; GFX10-NEXT: global_load_dwordx4 v[36:39], v64, s[0:1] offset:160 ; GFX10-NEXT: global_load_dwordx4 v[32:35], v64, s[0:1] offset:128
; GFX10-NEXT: global_load_dwordx4 v[40:43], v64, s[0:1] offset:176 ; GFX10-NEXT: global_load_dwordx4 v[36:39], v64, s[0:1] offset:144
; GFX10-NEXT: global_load_dwordx4 v[44:47], v64, s[0:1] offset:192 ; GFX10-NEXT: global_load_dwordx4 v[40:43], v64, s[0:1] offset:160
; GFX10-NEXT: global_load_dwordx4 v[48:51], v64, s[0:1] offset:208 ; GFX10-NEXT: global_load_dwordx4 v[44:47], v64, s[0:1] offset:176
; GFX10-NEXT: global_load_dwordx4 v[52:55], v64, s[0:1] offset:224 ; GFX10-NEXT: global_load_dwordx4 v[48:51], v64, s[0:1] offset:192
; GFX10-NEXT: global_load_dwordx4 v[56:59], v64, s[0:1] offset:240 ; GFX10-NEXT: global_load_dwordx4 v[52:55], v64, s[0:1] offset:208
; GFX10-NEXT: global_load_dwordx4 v[60:63], v64, s[0:1] offset:128 ; GFX10-NEXT: global_load_dwordx4 v[56:59], v64, s[0:1] offset:224
; GFX10-NEXT: global_load_dwordx4 v[4:7], v64, s[0:1] offset:144 ; GFX10-NEXT: global_load_dwordx4 v[60:63], v64, s[0:1] offset:240
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(6)
; GFX10-NEXT: v_mov_b32_e32 v5, 0x3e7 ; GFX10-NEXT: v_mov_b32_e32 v37, 0x3e7
; GFX10-NEXT: global_store_dwordx4 v64, v[0:3], s[2:3] ; GFX10-NEXT: global_store_dwordx4 v64, v[0:3], s[2:3]
; GFX10-NEXT: global_store_dwordx4 v64, v[8:11], s[2:3] offset:16 ; GFX10-NEXT: global_store_dwordx4 v64, v[4:7], s[2:3] offset:16
; GFX10-NEXT: global_store_dwordx4 v64, v[12:15], s[2:3] offset:32 ; GFX10-NEXT: global_store_dwordx4 v64, v[8:11], s[2:3] offset:32
; GFX10-NEXT: global_store_dwordx4 v64, v[16:19], s[2:3] offset:48 ; GFX10-NEXT: global_store_dwordx4 v64, v[12:15], s[2:3] offset:48
; GFX10-NEXT: global_store_dwordx4 v64, v[20:23], s[2:3] offset:64 ; GFX10-NEXT: global_store_dwordx4 v64, v[16:19], s[2:3] offset:64
; GFX10-NEXT: global_store_dwordx4 v64, v[24:27], s[2:3] offset:80 ; GFX10-NEXT: global_store_dwordx4 v64, v[20:23], s[2:3] offset:80
; GFX10-NEXT: global_store_dwordx4 v64, v[28:31], s[2:3] offset:96 ; GFX10-NEXT: global_store_dwordx4 v64, v[24:27], s[2:3] offset:96
; GFX10-NEXT: global_store_dwordx4 v64, v[32:35], s[2:3] offset:112 ; GFX10-NEXT: global_store_dwordx4 v64, v[28:31], s[2:3] offset:112
; GFX10-NEXT: global_store_dwordx4 v64, v[60:63], s[2:3] offset:128 ; GFX10-NEXT: global_store_dwordx4 v64, v[32:35], s[2:3] offset:128
; GFX10-NEXT: global_store_dwordx4 v64, v[4:7], s[2:3] offset:144 ; GFX10-NEXT: global_store_dwordx4 v64, v[36:39], s[2:3] offset:144
; GFX10-NEXT: global_store_dwordx4 v64, v[36:39], s[2:3] offset:160 ; GFX10-NEXT: s_waitcnt vmcnt(5)
; GFX10-NEXT: global_store_dwordx4 v64, v[40:43], s[2:3] offset:176 ; GFX10-NEXT: global_store_dwordx4 v64, v[40:43], s[2:3] offset:160
; GFX10-NEXT: global_store_dwordx4 v64, v[44:47], s[2:3] offset:192 ; GFX10-NEXT: s_waitcnt vmcnt(4)
; GFX10-NEXT: global_store_dwordx4 v64, v[48:51], s[2:3] offset:208 ; GFX10-NEXT: global_store_dwordx4 v64, v[44:47], s[2:3] offset:176
; GFX10-NEXT: global_store_dwordx4 v64, v[52:55], s[2:3] offset:224 ; GFX10-NEXT: s_waitcnt vmcnt(3)
; GFX10-NEXT: global_store_dwordx4 v64, v[56:59], s[2:3] offset:240 ; GFX10-NEXT: global_store_dwordx4 v64, v[48:51], s[2:3] offset:192
; GFX10-NEXT: s_waitcnt vmcnt(2)
; GFX10-NEXT: global_store_dwordx4 v64, v[52:55], s[2:3] offset:208
; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: global_store_dwordx4 v64, v[56:59], s[2:3] offset:224
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dwordx4 v64, v[60:63], s[2:3] offset:240
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: v_insert_v64i32_37: ; GFX11-LABEL: v_insert_v64i32_37:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x0 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x0
; GFX11-NEXT: v_lshlrev_b32_e32 v64, 8, v0 ; GFX11-NEXT: v_lshlrev_b32_e32 v64, 8, v0
; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_clause 0xf ; GFX11-NEXT: s_clause 0xf
; GFX11-NEXT: global_load_b128 v[0:3], v64, s[0:1] ; GFX11-NEXT: global_load_b128 v[0:3], v64, s[0:1]
; GFX11-NEXT: global_load_b128 v[8:11], v64, s[0:1] offset:16 ; GFX11-NEXT: global_load_b128 v[4:7], v64, s[0:1] offset:16
; GFX11-NEXT: global_load_b128 v[12:15], v64, s[0:1] offset:32 ; GFX11-NEXT: global_load_b128 v[8:11], v64, s[0:1] offset:32
; GFX11-NEXT: global_load_b128 v[16:19], v64, s[0:1] offset:48 ; GFX11-NEXT: global_load_b128 v[12:15], v64, s[0:1] offset:48
; GFX11-NEXT: global_load_b128 v[20:23], v64, s[0:1] offset:64 ; GFX11-NEXT: global_load_b128 v[16:19], v64, s[0:1] offset:64
; GFX11-NEXT: global_load_b128 v[24:27], v64, s[0:1] offset:80 ; GFX11-NEXT: global_load_b128 v[20:23], v64, s[0:1] offset:80
; GFX11-NEXT: global_load_b128 v[28:31], v64, s[0:1] offset:96 ; GFX11-NEXT: global_load_b128 v[24:27], v64, s[0:1] offset:96
; GFX11-NEXT: global_load_b128 v[32:35], v64, s[0:1] offset:112 ; GFX11-NEXT: global_load_b128 v[28:31], v64, s[0:1] offset:112
; GFX11-NEXT: global_load_b128 v[36:39], v64, s[0:1] offset:128 ; GFX11-NEXT: global_load_b128 v[32:35], v64, s[0:1] offset:128
; GFX11-NEXT: global_load_b128 v[4:7], v64, s[0:1] offset:144 ; GFX11-NEXT: global_load_b128 v[36:39], v64, s[0:1] offset:144
; GFX11-NEXT: global_load_b128 v[40:43], v64, s[0:1] offset:160 ; GFX11-NEXT: global_load_b128 v[40:43], v64, s[0:1] offset:160
; GFX11-NEXT: global_load_b128 v[44:47], v64, s[0:1] offset:176 ; GFX11-NEXT: global_load_b128 v[44:47], v64, s[0:1] offset:176
; GFX11-NEXT: global_load_b128 v[48:51], v64, s[0:1] offset:192 ; GFX11-NEXT: global_load_b128 v[48:51], v64, s[0:1] offset:192
; GFX11-NEXT: global_load_b128 v[52:55], v64, s[0:1] offset:208 ; GFX11-NEXT: global_load_b128 v[52:55], v64, s[0:1] offset:208
; GFX11-NEXT: global_load_b128 v[56:59], v64, s[0:1] offset:224 ; GFX11-NEXT: global_load_b128 v[56:59], v64, s[0:1] offset:224
; GFX11-NEXT: global_load_b128 v[60:63], v64, s[0:1] offset:240 ; GFX11-NEXT: global_load_b128 v[60:63], v64, s[0:1] offset:240
; GFX11-NEXT: s_waitcnt vmcnt(6) ; GFX11-NEXT: s_waitcnt vmcnt(6)
; GFX11-NEXT: v_mov_b32_e32 v5, 0x3e7 ; GFX11-NEXT: v_mov_b32_e32 v37, 0x3e7
; GFX11-NEXT: s_clause 0x9 ; GFX11-NEXT: s_clause 0x9
; GFX11-NEXT: global_store_b128 v64, v[0:3], s[2:3] ; GFX11-NEXT: global_store_b128 v64, v[0:3], s[2:3]
; GFX11-NEXT: global_store_b128 v64, v[8:11], s[2:3] offset:16 ; GFX11-NEXT: global_store_b128 v64, v[4:7], s[2:3] offset:16
; GFX11-NEXT: global_store_b128 v64, v[12:15], s[2:3] offset:32 ; GFX11-NEXT: global_store_b128 v64, v[8:11], s[2:3] offset:32
; GFX11-NEXT: global_store_b128 v64, v[16:19], s[2:3] offset:48 ; GFX11-NEXT: global_store_b128 v64, v[12:15], s[2:3] offset:48
; GFX11-NEXT: global_store_b128 v64, v[20:23], s[2:3] offset:64 ; GFX11-NEXT: global_store_b128 v64, v[16:19], s[2:3] offset:64
; GFX11-NEXT: global_store_b128 v64, v[24:27], s[2:3] offset:80 ; GFX11-NEXT: global_store_b128 v64, v[20:23], s[2:3] offset:80
; GFX11-NEXT: global_store_b128 v64, v[28:31], s[2:3] offset:96 ; GFX11-NEXT: global_store_b128 v64, v[24:27], s[2:3] offset:96
; GFX11-NEXT: global_store_b128 v64, v[32:35], s[2:3] offset:112 ; GFX11-NEXT: global_store_b128 v64, v[28:31], s[2:3] offset:112
; GFX11-NEXT: global_store_b128 v64, v[36:39], s[2:3] offset:128 ; GFX11-NEXT: global_store_b128 v64, v[32:35], s[2:3] offset:128
; GFX11-NEXT: global_store_b128 v64, v[4:7], s[2:3] offset:144 ; GFX11-NEXT: global_store_b128 v64, v[36:39], s[2:3] offset:144
; GFX11-NEXT: s_waitcnt vmcnt(5) ; GFX11-NEXT: s_waitcnt vmcnt(5)
; GFX11-NEXT: global_store_b128 v64, v[40:43], s[2:3] offset:160 ; GFX11-NEXT: global_store_b128 v64, v[40:43], s[2:3] offset:160
; GFX11-NEXT: s_waitcnt vmcnt(4) ; GFX11-NEXT: s_waitcnt vmcnt(4)
; GFX11-NEXT: global_store_b128 v64, v[44:47], s[2:3] offset:176 ; GFX11-NEXT: global_store_b128 v64, v[44:47], s[2:3] offset:176
; GFX11-NEXT: s_waitcnt vmcnt(3) ; GFX11-NEXT: s_waitcnt vmcnt(3)
; GFX11-NEXT: global_store_b128 v64, v[48:51], s[2:3] offset:192 ; GFX11-NEXT: global_store_b128 v64, v[48:51], s[2:3] offset:192
; GFX11-NEXT: s_waitcnt vmcnt(2) ; GFX11-NEXT: s_waitcnt vmcnt(2)
; GFX11-NEXT: global_store_b128 v64, v[52:55], s[2:3] offset:208 ; GFX11-NEXT: global_store_b128 v64, v[52:55], s[2:3] offset:208
Show All 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll

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; GPRIDX-NEXT: v_mov_b32_e32 v11, s12 ; GPRIDX-NEXT: v_mov_b32_e32 v11, s12
; GPRIDX-NEXT: v_mov_b32_e32 v12, s13 ; GPRIDX-NEXT: v_mov_b32_e32 v12, s13
; GPRIDX-NEXT: v_mov_b32_e32 v13, s14 ; GPRIDX-NEXT: v_mov_b32_e32 v13, s14
; GPRIDX-NEXT: v_mov_b32_e32 v14, s15 ; GPRIDX-NEXT: v_mov_b32_e32 v14, s15
; GPRIDX-NEXT: v_mov_b32_e32 v15, s16 ; GPRIDX-NEXT: v_mov_b32_e32 v15, s16
; GPRIDX-NEXT: v_mov_b32_e32 v16, s17 ; GPRIDX-NEXT: v_mov_b32_e32 v16, s17
; GPRIDX-NEXT: v_mov_b32_e32 v17, s18 ; GPRIDX-NEXT: v_mov_b32_e32 v17, s18
; GPRIDX-NEXT: v_mov_b32_e32 v18, s19 ; GPRIDX-NEXT: v_mov_b32_e32 v18, s19
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[16:17], 0, v2 ; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v2
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[4:5], 2, v2 ; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[6:7], 3, v2 ; GPRIDX-NEXT: v_cndmask_b32_e64 v5, v5, v0, s[4:5]
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[8:9], 4, v2 ; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[6:7], 2, v2
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[8:9], 3, v2
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[10:11], 5, v2 ; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[10:11], 5, v2
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[12:13], 6, v2 ; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[12:13], 6, v2
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[14:15], 7, v2 ; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[14:15], 7, v2
; GPRIDX-NEXT: v_cndmask_b32_e64 v3, v3, v0, s[16:17] ; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[16:17], 4, v2
; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v4, v4, v1, s[16:17] ; GPRIDX-NEXT: v_cndmask_b32_e64 v6, v6, v1, s[4:5]
; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v1, vcc ; GPRIDX-NEXT: v_cndmask_b32_e64 v7, v7, v0, s[6:7]
; GPRIDX-NEXT: v_cndmask_b32_e64 v7, v7, v0, s[4:5] ; GPRIDX-NEXT: v_cndmask_b32_e64 v9, v9, v0, s[8:9]
; GPRIDX-NEXT: v_cndmask_b32_e64 v9, v9, v0, s[6:7] ; GPRIDX-NEXT: v_cndmask_b32_e64 v11, v11, v0, s[16:17]
; GPRIDX-NEXT: v_cndmask_b32_e64 v11, v11, v0, s[8:9]
; GPRIDX-NEXT: v_cndmask_b32_e64 v13, v13, v0, s[10:11] ; GPRIDX-NEXT: v_cndmask_b32_e64 v13, v13, v0, s[10:11]
; GPRIDX-NEXT: v_cndmask_b32_e64 v15, v15, v0, s[12:13] ; GPRIDX-NEXT: v_cndmask_b32_e64 v15, v15, v0, s[12:13]
; GPRIDX-NEXT: v_cndmask_b32_e64 v17, v17, v0, s[14:15] ; GPRIDX-NEXT: v_cndmask_b32_e64 v17, v17, v0, s[14:15]
; GPRIDX-NEXT: v_cndmask_b32_e64 v8, v8, v1, s[4:5] ; GPRIDX-NEXT: v_cndmask_b32_e64 v8, v8, v1, s[6:7]
; GPRIDX-NEXT: v_cndmask_b32_e64 v10, v10, v1, s[6:7] ; GPRIDX-NEXT: v_cndmask_b32_e64 v10, v10, v1, s[8:9]
; GPRIDX-NEXT: v_cndmask_b32_e64 v12, v12, v1, s[8:9] ; GPRIDX-NEXT: v_cndmask_b32_e64 v12, v12, v1, s[16:17]
; GPRIDX-NEXT: v_cndmask_b32_e64 v14, v14, v1, s[10:11] ; GPRIDX-NEXT: v_cndmask_b32_e64 v14, v14, v1, s[10:11]
; GPRIDX-NEXT: v_cndmask_b32_e64 v16, v16, v1, s[12:13] ; GPRIDX-NEXT: v_cndmask_b32_e64 v16, v16, v1, s[12:13]
; GPRIDX-NEXT: v_cndmask_b32_e64 v18, v18, v1, s[14:15] ; GPRIDX-NEXT: v_cndmask_b32_e64 v18, v18, v1, s[14:15]
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[3:6], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[3:6], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0) ; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[7:10], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[7:10], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0) ; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[11:14], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[11:14], off
Show All 15 Lines
; GFX10-NEXT: s_mov_b32 s13, 0x40140000 ; GFX10-NEXT: s_mov_b32 s13, 0x40140000
; GFX10-NEXT: s_mov_b32 s12, s18 ; GFX10-NEXT: s_mov_b32 s12, s18
; GFX10-NEXT: s_mov_b64 s[10:11], 4.0 ; GFX10-NEXT: s_mov_b64 s[10:11], 4.0
; GFX10-NEXT: s_mov_b32 s9, 0x40080000 ; GFX10-NEXT: s_mov_b32 s9, 0x40080000
; GFX10-NEXT: s_mov_b32 s8, s18 ; GFX10-NEXT: s_mov_b32 s8, s18
; GFX10-NEXT: s_mov_b64 s[6:7], 2.0 ; GFX10-NEXT: s_mov_b64 s[6:7], 2.0
; GFX10-NEXT: v_mov_b32_e32 v3, s4 ; GFX10-NEXT: v_mov_b32_e32 v3, s4
; GFX10-NEXT: v_mov_b32_e32 v4, s5 ; GFX10-NEXT: v_mov_b32_e32 v4, s5
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX10-NEXT: v_mov_b32_e32 v5, s6 ; GFX10-NEXT: v_mov_b32_e32 v5, s6
; GFX10-NEXT: v_mov_b32_e32 v6, s7 ; GFX10-NEXT: v_mov_b32_e32 v6, s7
; GFX10-NEXT: v_mov_b32_e32 v7, s8 ; GFX10-NEXT: v_mov_b32_e32 v7, s8
; GFX10-NEXT: v_mov_b32_e32 v8, s9 ; GFX10-NEXT: v_mov_b32_e32 v8, s9
; GFX10-NEXT: v_mov_b32_e32 v9, s10 ; GFX10-NEXT: v_mov_b32_e32 v9, s10
; GFX10-NEXT: v_mov_b32_e32 v10, s11 ; GFX10-NEXT: v_mov_b32_e32 v10, s11
; GFX10-NEXT: v_mov_b32_e32 v11, s12 ; GFX10-NEXT: v_mov_b32_e32 v11, s12
; GFX10-NEXT: v_mov_b32_e32 v12, s13 ; GFX10-NEXT: v_mov_b32_e32 v12, s13
; GFX10-NEXT: v_mov_b32_e32 v13, s14 ; GFX10-NEXT: v_mov_b32_e32 v13, s14
; GFX10-NEXT: v_mov_b32_e32 v14, s15 ; GFX10-NEXT: v_mov_b32_e32 v14, s15
; GFX10-NEXT: v_mov_b32_e32 v15, s16 ; GFX10-NEXT: v_mov_b32_e32 v15, s16
; GFX10-NEXT: v_mov_b32_e32 v16, s17 ; GFX10-NEXT: v_mov_b32_e32 v16, s17
; GFX10-NEXT: v_mov_b32_e32 v17, s18 ; GFX10-NEXT: v_mov_b32_e32 v17, s18
; GFX10-NEXT: v_mov_b32_e32 v18, s19 ; GFX10-NEXT: v_mov_b32_e32 v18, s19
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 1, v2 ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 1, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 2, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 3, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s7, 5, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s10, 4, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s8, 6, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s9, 7, v2
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v0, s4
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v2
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v0, s4
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v1, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v1, s4
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v0, s5 ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 3, v2
; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v0, s6 ; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v1, s5 ; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v1, s6 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v2
; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v0, s10 ; GFX10-NEXT: v_cndmask_b32_e64 v17, v17, v0, s5
; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, v0, s7 ; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v0, s4
; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, v1, s10 ; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v1, s4
; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, v1, s7 ; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 5, v2
; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, v0, s8 ; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v17, v17, v0, s9 ; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v16, v16, v1, s8 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v2
; GFX10-NEXT: v_cndmask_b32_e64 v18, v18, v1, s9 ; GFX10-NEXT: v_cndmask_b32_e64 v18, v18, v1, s5
; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, v0, s4
; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, v1, s4
; GFX10-NEXT: v_cndmask_b32_e32 v15, v15, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v16, v16, v1, vcc_lo
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[3:6], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[3:6], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[7:10], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[7:10], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[11:14], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[11:14], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[15:18], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[15:18], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-NEXT: v_mov_b32_e32 v7, s6 ; GFX10-NEXT: v_mov_b32_e32 v7, s6
; GFX10-NEXT: v_mov_b32_e32 v6, s5 ; GFX10-NEXT: v_mov_b32_e32 v6, s5
; GFX10-NEXT: v_mov_b32_e32 v5, s4 ; GFX10-NEXT: v_mov_b32_e32 v5, s4
; GFX10-NEXT: v_mov_b32_e32 v4, s3 ; GFX10-NEXT: v_mov_b32_e32 v4, s3
; GFX10-NEXT: v_mov_b32_e32 v3, s2 ; GFX10-NEXT: v_mov_b32_e32 v3, s2
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v0
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s18, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s18, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s19, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s19, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 2, v0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 7, v0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s18, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s18, s0
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, s19, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, s19, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 4, v0 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 3, v0
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 5, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, s18, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 6, v0 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, s19, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 7, v0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, s18, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, s18, s1
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, s19, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, s18, s0
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, s18, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, s19, s0
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, s19, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 5, v0
; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, s18, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, s18, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, s19, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, s19, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, s18, s2 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0
; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, s19, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v16, v16, s19, s1
; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, s18, s3 ; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, s18, s0
; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, s19, s3 ; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, s19, s0
; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, s18, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, s18, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v16, v16, s19, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, s19, vcc_lo
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[1:4], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[1:4], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[5:8], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[5:8], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[9:12], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[9:12], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[13:16], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[13:16], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s8, s10 ; GFX10-NEXT: s_mov_b32 s8, s10
; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: s_mov_b32 s10, s12
; GFX10-NEXT: s_mov_b32 s12, s14 ; GFX10-NEXT: s_mov_b32 s12, s14
; GFX10-NEXT: s_mov_b32 s14, s16 ; GFX10-NEXT: s_mov_b32 s14, s16
; GFX10-NEXT: v_mov_b32_e32 v18, s15 ; GFX10-NEXT: v_mov_b32_e32 v18, s15
; GFX10-NEXT: v_mov_b32_e32 v4, s1
; GFX10-NEXT: v_mov_b32_e32 v3, s0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX10-NEXT: v_mov_b32_e32 v17, s14 ; GFX10-NEXT: v_mov_b32_e32 v17, s14
; GFX10-NEXT: v_mov_b32_e32 v16, s13 ; GFX10-NEXT: v_mov_b32_e32 v16, s13
; GFX10-NEXT: v_mov_b32_e32 v15, s12 ; GFX10-NEXT: v_mov_b32_e32 v15, s12
; GFX10-NEXT: v_mov_b32_e32 v14, s11 ; GFX10-NEXT: v_mov_b32_e32 v14, s11
; GFX10-NEXT: v_mov_b32_e32 v13, s10 ; GFX10-NEXT: v_mov_b32_e32 v13, s10
; GFX10-NEXT: v_mov_b32_e32 v12, s9 ; GFX10-NEXT: v_mov_b32_e32 v12, s9
; GFX10-NEXT: v_mov_b32_e32 v11, s8 ; GFX10-NEXT: v_mov_b32_e32 v11, s8
; GFX10-NEXT: v_mov_b32_e32 v10, s7 ; GFX10-NEXT: v_mov_b32_e32 v10, s7
; GFX10-NEXT: v_mov_b32_e32 v9, s6 ; GFX10-NEXT: v_mov_b32_e32 v9, s6
; GFX10-NEXT: v_mov_b32_e32 v8, s5 ; GFX10-NEXT: v_mov_b32_e32 v8, s5
; GFX10-NEXT: v_mov_b32_e32 v7, s4 ; GFX10-NEXT: v_mov_b32_e32 v7, s4
; GFX10-NEXT: v_mov_b32_e32 v6, s3 ; GFX10-NEXT: v_mov_b32_e32 v6, s3
; GFX10-NEXT: v_mov_b32_e32 v5, s2 ; GFX10-NEXT: v_mov_b32_e32 v5, s2
; GFX10-NEXT: v_mov_b32_e32 v4, s1
; GFX10-NEXT: v_mov_b32_e32 v3, s0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v2 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 2, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v2
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v0, s0
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 7, v2
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v0, s0
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v1, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v1, s0
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v0, s6 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 3, v2
; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v0, s1 ; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v1, s6 ; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v1, s1 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v2
; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v0, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v17, v17, v0, s1
; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, v0, s3 ; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v0, s0
; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, v1, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v1, s0
; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, v1, s3 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 5, v2
; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, v0, s4 ; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v17, v17, v0, s5 ; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v16, v16, v1, s4 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v2
; GFX10-NEXT: v_cndmask_b32_e64 v18, v18, v1, s5 ; GFX10-NEXT: v_cndmask_b32_e64 v18, v18, v1, s1
; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, v0, s0
; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, v1, s0
; GFX10-NEXT: v_cndmask_b32_e32 v15, v15, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v16, v16, v1, vcc_lo
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[3:6], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[3:6], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[7:10], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[7:10], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[11:14], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[11:14], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[15:18], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[15:18], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Linesentry:
store volatile <2 x double> %vec.3, ptr addrspace(1) undef store volatile <2 x double> %vec.3, ptr addrspace(1) undef
ret void ret void
} }
define amdgpu_ps void @dyn_insertelement_v8f64_v_s_v(<8 x double> %vec, double inreg %val, i32 %idx) { define amdgpu_ps void @dyn_insertelement_v8f64_v_s_v(<8 x double> %vec, double inreg %val, i32 %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f64_v_s_v: ; GPRIDX-LABEL: dyn_insertelement_v8f64_v_s_v:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: v_mov_b32_e32 v17, s2 ; GPRIDX-NEXT: v_mov_b32_e32 v17, s2
; GPRIDX-NEXT: v_mov_b32_e32 v18, s3
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 0, v16 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 0, v16
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v16
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[14:15], 2, v16
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[4:5], 3, v16
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[6:7], 4, v16
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[8:9], 5, v16
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v16
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[12:13], 6, v16
; GPRIDX-NEXT: v_mov_b32_e32 v16, s3
; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v0, v17, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v0, v17, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v2, v2, v17, s[0:1] ; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v18, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v16, vcc ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 1, v16
; GPRIDX-NEXT: v_cndmask_b32_e64 v3, v3, v16, s[0:1] ; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v17, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v4, v4, v17, s[14:15] ; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v18, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v6, v6, v17, s[4:5] ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 2, v16
; GPRIDX-NEXT: v_cndmask_b32_e64 v8, v8, v17, s[6:7] ; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v17, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v10, v10, v17, s[8:9] ; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v18, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v12, v12, v17, s[12:13] ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 3, v16
; GPRIDX-NEXT: v_cndmask_b32_e64 v14, v14, v17, s[10:11] ; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v17, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v5, v5, v16, s[14:15] ; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v18, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v7, v7, v16, s[4:5] ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 4, v16
; GPRIDX-NEXT: v_cndmask_b32_e64 v9, v9, v16, s[6:7] ; GPRIDX-NEXT: v_cndmask_b32_e32 v8, v8, v17, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v11, v11, v16, s[8:9] ; GPRIDX-NEXT: v_cndmask_b32_e32 v9, v9, v18, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v13, v13, v16, s[12:13] ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 5, v16
; GPRIDX-NEXT: v_cndmask_b32_e64 v15, v15, v16, s[10:11] ; GPRIDX-NEXT: v_cndmask_b32_e32 v10, v10, v17, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v11, v11, v18, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 6, v16
; GPRIDX-NEXT: v_cndmask_b32_e32 v12, v12, v17, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v13, v13, v18, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 7, v16
; GPRIDX-NEXT: v_cndmask_b32_e32 v14, v14, v17, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v15, v15, v18, vcc
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0) ; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[4:7], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0) ; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[8:11], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0) ; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[12:15], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0) ; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: s_endpgm ; GPRIDX-NEXT: s_endpgm
; ;
; GFX10-LABEL: dyn_insertelement_v8f64_v_s_v: ; GFX10-LABEL: dyn_insertelement_v8f64_v_s_v:
; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v16 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v16
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v16
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 7, v16
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v16
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s3, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v16 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v16
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s2, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s3, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 3, v16
; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, s2, s1
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, s2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, s2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, s3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, s3, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v16
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, s2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, s3, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v16 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v16
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, s2, s0
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, s3, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 5, v16
; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, s3, s1
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, s2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, s2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, s3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, s3, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v16
; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, s2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, s3, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v16 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v16
; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, s2, s0
; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, s3, s0
; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, s2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, s2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, s3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, s3, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v16
; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, s2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, s3, vcc_lo
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[0:3], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[4:7], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[8:11], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[12:15], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: dyn_insertelement_v8f64_v_s_v: ; GFX11-LABEL: dyn_insertelement_v8f64_v_s_v:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v16 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v16
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v16
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 7, v16
; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v16
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s2, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s3, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v16 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v16
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s2, s0
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s3, s0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v16
; GFX11-NEXT: v_cndmask_b32_e64 v14, v14, s2, s1
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, s2, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, s2, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, s3, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, s3, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v16
; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, s2, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, s3, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v16 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v16
; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, s2, s0
; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, s3, s0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 5, v16
; GFX11-NEXT: v_cndmask_b32_e64 v15, v15, s3, s1
; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, s2, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, s2, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, s3, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, s3, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v16
; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, s2, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, s3, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v16 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v16
; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, s2, s0
; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, s3, s0
; GFX11-NEXT: v_cndmask_b32_e64 v12, v12, s2, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v12, v12, s2, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v13, v13, s3, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v13, v13, s3, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v16
; GFX11-NEXT: v_cndmask_b32_e64 v14, v14, s2, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v15, v15, s3, vcc_lo
; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off dlc ; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: global_store_b128 v[0:1], v[4:7], off dlc ; GFX11-NEXT: global_store_b128 v[0:1], v[4:7], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: global_store_b128 v[0:1], v[8:11], off dlc ; GFX11-NEXT: global_store_b128 v[0:1], v[8:11], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: global_store_b128 v[0:1], v[12:15], off dlc ; GFX11-NEXT: global_store_b128 v[0:1], v[12:15], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Linesentry:
store volatile <2 x double> %vec.3, ptr addrspace(1) undef store volatile <2 x double> %vec.3, ptr addrspace(1) undef
ret void ret void
} }
define amdgpu_ps void @dyn_insertelement_v8f64_v_v_v(<8 x double> %vec, double %val, i32 %idx) { define amdgpu_ps void @dyn_insertelement_v8f64_v_v_v(<8 x double> %vec, double %val, i32 %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f64_v_v_v: ; GPRIDX-LABEL: dyn_insertelement_v8f64_v_v_v:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 0, v18 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 0, v18
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v18
; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v2, v2, v16, s[0:1]
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[2:3], 2, v18
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[4:5], 3, v18
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[6:7], 4, v18
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[8:9], 5, v18
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v18
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[12:13], 6, v18
; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v3, v3, v17, s[0:1] ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 1, v18
; GPRIDX-NEXT: v_cndmask_b32_e64 v4, v4, v16, s[2:3] ; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v16, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v6, v6, v16, s[4:5] ; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v17, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v8, v8, v16, s[6:7] ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 2, v18
; GPRIDX-NEXT: v_cndmask_b32_e64 v10, v10, v16, s[8:9] ; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v16, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v12, v12, v16, s[12:13] ; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v17, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v14, v14, v16, s[10:11] ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 3, v18
; GPRIDX-NEXT: v_cndmask_b32_e64 v5, v5, v17, s[2:3] ; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v16, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v7, v7, v17, s[4:5] ; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v17, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v9, v9, v17, s[6:7] ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 4, v18
; GPRIDX-NEXT: v_cndmask_b32_e64 v11, v11, v17, s[8:9] ; GPRIDX-NEXT: v_cndmask_b32_e32 v8, v8, v16, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v13, v13, v17, s[12:13] ; GPRIDX-NEXT: v_cndmask_b32_e32 v9, v9, v17, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v15, v15, v17, s[10:11] ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 5, v18
; GPRIDX-NEXT: v_cndmask_b32_e32 v10, v10, v16, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v11, v11, v17, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 6, v18
; GPRIDX-NEXT: v_cndmask_b32_e32 v12, v12, v16, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v13, v13, v17, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 7, v18
; GPRIDX-NEXT: v_cndmask_b32_e32 v14, v14, v16, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v15, v15, v17, vcc
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0) ; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[4:7], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0) ; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[8:11], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0) ; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[12:15], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0) ; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: s_endpgm ; GPRIDX-NEXT: s_endpgm
; ;
; GFX10-LABEL: dyn_insertelement_v8f64_v_v_v: ; GFX10-LABEL: dyn_insertelement_v8f64_v_v_v:
; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v18 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v18
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v18 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v18
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 2, v18 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 7, v18
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 3, v18
; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 4, v18
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 5, v18
; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v18
; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 6, v18
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v16, s0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v18
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v16, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v17, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v17, s0
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v16, s1 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 3, v18
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v16, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, v16, s1
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v17, s1 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v16, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v17, s2 ; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v17, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v16, s3 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v18
; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v16, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v16, s0
; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v17, s3 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v17, s0
; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v17, s4 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 5, v18
; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, v16, s6 ; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, v17, s1
; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, v16, s5 ; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v16, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, v17, s6 ; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v17, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, v17, s5 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v18
; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v16, s0
; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v17, s0
; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v16, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v17, vcc_lo
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[0:3], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[4:7], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[8:11], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[12:15], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: dyn_insertelement_v8f64_v_v_v: ; GFX11-LABEL: dyn_insertelement_v8f64_v_v_v:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v18 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v18
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v18 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v18
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 2, v18 ; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 7, v18
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 3, v18
; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 4, v18
; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 5, v18
; GFX11-NEXT: v_cmp_eq_u32_e64 s5, 7, v18
; GFX11-NEXT: v_cmp_eq_u32_e64 s6, 6, v18
; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v16 :: v_dual_cndmask_b32 v1, v1, v17 ; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v16 :: v_dual_cndmask_b32 v1, v1, v17
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v18
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v16, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v16, s0
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v17, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v17, s0
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v16, s1 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v18
; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v16, s2 ; GFX11-NEXT: v_cndmask_b32_e64 v14, v14, v16, s1
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v17, s1 ; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v16 :: v_dual_cndmask_b32 v5, v5, v17
; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, v17, s2 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v18
; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v16, s3 ; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v16, s0
; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v16, s4 ; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, v17, s0
; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v17, s3 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 5, v18
; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, v17, s4 ; GFX11-NEXT: v_cndmask_b32_e64 v15, v15, v17, s1
; GFX11-NEXT: v_cndmask_b32_e64 v12, v12, v16, s6 ; GFX11-NEXT: v_dual_cndmask_b32 v8, v8, v16 :: v_dual_cndmask_b32 v9, v9, v17
; GFX11-NEXT: v_cndmask_b32_e64 v14, v14, v16, s5 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v18
; GFX11-NEXT: v_cndmask_b32_e64 v13, v13, v17, s6 ; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v16, s0
; GFX11-NEXT: v_cndmask_b32_e64 v15, v15, v17, s5 ; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, v17, s0
; GFX11-NEXT: v_dual_cndmask_b32 v12, v12, v16 :: v_dual_cndmask_b32 v13, v13, v17
; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off dlc ; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: global_store_b128 v[0:1], v[4:7], off dlc ; GFX11-NEXT: global_store_b128 v[0:1], v[4:7], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: global_store_b128 v[0:1], v[8:11], off dlc ; GFX11-NEXT: global_store_b128 v[0:1], v[8:11], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: global_store_b128 v[0:1], v[12:15], off dlc ; GFX11-NEXT: global_store_b128 v[0:1], v[12:15], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
▲ Show 20 Lines • Show All 622 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
define amdgpu_ps void @dyn_insertelement_v8f64_v_v_v_add_1(<8 x double> %vec, double %val, i32 %idx) { define amdgpu_ps void @dyn_insertelement_v8f64_v_v_v_add_1(<8 x double> %vec, double %val, i32 %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f64_v_v_v_add_1: ; GPRIDX-LABEL: dyn_insertelement_v8f64_v_v_v_add_1:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: v_add_u32_e32 v18, 1, v18 ; GPRIDX-NEXT: v_add_u32_e32 v18, 1, v18
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 0, v18 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 0, v18
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v18
; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v2, v2, v16, s[0:1]
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[2:3], 2, v18
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[4:5], 3, v18
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[6:7], 4, v18
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[8:9], 5, v18
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[10:11], 7, v18
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[12:13], 6, v18
; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v3, v3, v17, s[0:1] ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 1, v18
; GPRIDX-NEXT: v_cndmask_b32_e64 v4, v4, v16, s[2:3] ; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v16, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v6, v6, v16, s[4:5] ; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v17, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v8, v8, v16, s[6:7] ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 2, v18
; GPRIDX-NEXT: v_cndmask_b32_e64 v10, v10, v16, s[8:9] ; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v16, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v12, v12, v16, s[12:13] ; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v17, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v14, v14, v16, s[10:11] ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 3, v18
; GPRIDX-NEXT: v_cndmask_b32_e64 v5, v5, v17, s[2:3] ; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v16, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v7, v7, v17, s[4:5] ; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v17, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v9, v9, v17, s[6:7] ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 4, v18
; GPRIDX-NEXT: v_cndmask_b32_e64 v11, v11, v17, s[8:9] ; GPRIDX-NEXT: v_cndmask_b32_e32 v8, v8, v16, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v13, v13, v17, s[12:13] ; GPRIDX-NEXT: v_cndmask_b32_e32 v9, v9, v17, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v15, v15, v17, s[10:11] ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 5, v18
; GPRIDX-NEXT: v_cndmask_b32_e32 v10, v10, v16, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v11, v11, v17, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 6, v18
; GPRIDX-NEXT: v_cndmask_b32_e32 v12, v12, v16, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v13, v13, v17, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 7, v18
; GPRIDX-NEXT: v_cndmask_b32_e32 v14, v14, v16, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v15, v15, v17, vcc
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0) ; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[4:7], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0) ; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[8:11], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0) ; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[12:15], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0) ; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: s_endpgm ; GPRIDX-NEXT: s_endpgm
; ;
; GFX10-LABEL: dyn_insertelement_v8f64_v_v_v_add_1: ; GFX10-LABEL: dyn_insertelement_v8f64_v_v_v_add_1:
; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: v_add_nc_u32_e32 v18, 1, v18 ; GFX10-NEXT: v_add_nc_u32_e32 v18, 1, v18
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v18 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v18
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v18 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v18
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 2, v18 ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 7, v18
; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 3, v18
; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 4, v18
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 5, v18
; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v18
; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 6, v18
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v16, s0
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v18
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v16, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v17, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v17, s0
; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v16, s1 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 3, v18
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v16, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, v16, s1
; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v17, s1 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v16, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v17, s2 ; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v17, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v16, s3 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v18
; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v16, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v16, s0
; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v17, s3 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v17, s0
; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v17, s4 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 5, v18
; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, v16, s6 ; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, v17, s1
; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, v16, s5 ; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v16, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, v17, s6 ; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v17, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, v17, s5 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v18
; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v16, s0
; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v17, s0
; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v16, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v17, vcc_lo
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[0:3], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[4:7], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[8:11], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dwordx4 v[0:1], v[12:15], off ; GFX10-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: dyn_insertelement_v8f64_v_v_v_add_1: ; GFX11-LABEL: dyn_insertelement_v8f64_v_v_v_add_1:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: v_add_nc_u32_e32 v18, 1, v18 ; GFX11-NEXT: v_add_nc_u32_e32 v18, 1, v18
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v18 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v18
; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v18 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v18
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 2, v18
; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 3, v18
; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 4, v18
; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 5, v18
; GFX11-NEXT: v_cmp_eq_u32_e64 s5, 7, v18
; GFX11-NEXT: v_cmp_eq_u32_e64 s6, 6, v18
; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v18
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 7, v18
; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v16, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v16, s0
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v17, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v17, s0
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v16, s1 ; GFX11-NEXT: v_cndmask_b32_e32 v5, v5, v17, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v16, s2 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v18
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v17, s1 ; GFX11-NEXT: v_cndmask_b32_e32 v4, v4, v16, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, v17, s2 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v18
; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v16, s3 ; GFX11-NEXT: v_cndmask_b32_e64 v14, v14, v16, s1
; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v16, s4 ; GFX11-NEXT: v_cndmask_b32_e64 v15, v15, v17, s1
; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v17, s3 ; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v16, s0
; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, v17, s4 ; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, v17, s0
; GFX11-NEXT: v_cndmask_b32_e64 v12, v12, v16, s6 ; GFX11-NEXT: v_cndmask_b32_e32 v9, v9, v17, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v14, v14, v16, s5 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 5, v18
; GFX11-NEXT: v_cndmask_b32_e64 v13, v13, v17, s6 ; GFX11-NEXT: v_cndmask_b32_e32 v8, v8, v16, vcc_lo
; GFX11-NEXT: v_cndmask_b32_e64 v15, v15, v17, s5 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v18
; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v16, s0
; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, v17, s0
; GFX11-NEXT: v_dual_cndmask_b32 v13, v13, v17 :: v_dual_cndmask_b32 v12, v12, v16
; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off dlc ; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: global_store_b128 v[0:1], v[4:7], off dlc ; GFX11-NEXT: global_store_b128 v[0:1], v[4:7], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: global_store_b128 v[0:1], v[8:11], off dlc ; GFX11-NEXT: global_store_b128 v[0:1], v[8:11], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: global_store_b128 v[0:1], v[12:15], off dlc ; GFX11-NEXT: global_store_b128 v[0:1], v[12:15], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
▲ Show 20 Lines • Show All 3,126 Lines • ▼ Show 20 Lines
; GPRIDX-NEXT: s_mov_b32 s7, s9 ; GPRIDX-NEXT: s_mov_b32 s7, s9
; GPRIDX-NEXT: s_mov_b32 s8, s10 ; GPRIDX-NEXT: s_mov_b32 s8, s10
; GPRIDX-NEXT: s_mov_b32 s9, s11 ; GPRIDX-NEXT: s_mov_b32 s9, s11
; GPRIDX-NEXT: s_mov_b32 s10, s12 ; GPRIDX-NEXT: s_mov_b32 s10, s12
; GPRIDX-NEXT: s_mov_b32 s11, s13 ; GPRIDX-NEXT: s_mov_b32 s11, s13
; GPRIDX-NEXT: s_mov_b32 s12, s14 ; GPRIDX-NEXT: s_mov_b32 s12, s14
; GPRIDX-NEXT: s_mov_b32 s13, s15 ; GPRIDX-NEXT: s_mov_b32 s13, s15
; GPRIDX-NEXT: v_mov_b32_e32 v18, s15 ; GPRIDX-NEXT: v_mov_b32_e32 v18, s15
; GPRIDX-NEXT: v_mov_b32_e32 v3, s0
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GPRIDX-NEXT: v_mov_b32_e32 v4, s1
; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v17, s14 ; GPRIDX-NEXT: v_mov_b32_e32 v17, s14
; GPRIDX-NEXT: v_mov_b32_e32 v16, s13 ; GPRIDX-NEXT: v_mov_b32_e32 v16, s13
; GPRIDX-NEXT: v_mov_b32_e32 v15, s12 ; GPRIDX-NEXT: v_mov_b32_e32 v15, s12
; GPRIDX-NEXT: v_mov_b32_e32 v14, s11 ; GPRIDX-NEXT: v_mov_b32_e32 v14, s11
; GPRIDX-NEXT: v_mov_b32_e32 v13, s10 ; GPRIDX-NEXT: v_mov_b32_e32 v13, s10
; GPRIDX-NEXT: v_mov_b32_e32 v12, s9 ; GPRIDX-NEXT: v_mov_b32_e32 v12, s9
; GPRIDX-NEXT: v_mov_b32_e32 v11, s8 ; GPRIDX-NEXT: v_mov_b32_e32 v11, s8
; GPRIDX-NEXT: v_mov_b32_e32 v10, s7 ; GPRIDX-NEXT: v_mov_b32_e32 v10, s7
; GPRIDX-NEXT: v_mov_b32_e32 v9, s6 ; GPRIDX-NEXT: v_mov_b32_e32 v9, s6
; GPRIDX-NEXT: v_mov_b32_e32 v8, s5 ; GPRIDX-NEXT: v_mov_b32_e32 v8, s5
; GPRIDX-NEXT: v_mov_b32_e32 v7, s4 ; GPRIDX-NEXT: v_mov_b32_e32 v7, s4
; GPRIDX-NEXT: v_mov_b32_e32 v6, s3 ; GPRIDX-NEXT: v_mov_b32_e32 v6, s3
; GPRIDX-NEXT: v_mov_b32_e32 v5, s2 ; GPRIDX-NEXT: v_mov_b32_e32 v5, s2
; GPRIDX-NEXT: v_mov_b32_e32 v4, s1
; GPRIDX-NEXT: v_mov_b32_e32 v3, s0
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[0:1], 2, v2
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[2:3], 3, v2
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[4:5], 4, v2
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[6:7], 5, v2
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[8:9], 6, v2
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[10:11], 1, v2
; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v2, v5, v0, s[10:11]
; GPRIDX-NEXT: v_cndmask_b32_e64 v5, v7, v0, s[0:1]
; GPRIDX-NEXT: v_cndmask_b32_e64 v7, v9, v0, s[2:3]
; GPRIDX-NEXT: v_cndmask_b32_e64 v9, v11, v0, s[4:5]
; GPRIDX-NEXT: v_cndmask_b32_e64 v11, v13, v0, s[6:7]
; GPRIDX-NEXT: v_cndmask_b32_e64 v0, v15, v0, s[8:9]
; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v6, v6, v1, s[10:11]
; GPRIDX-NEXT: v_cndmask_b32_e64 v8, v8, v1, s[0:1]
; GPRIDX-NEXT: v_cndmask_b32_e64 v10, v10, v1, s[2:3]
; GPRIDX-NEXT: v_cndmask_b32_e64 v12, v12, v1, s[4:5]
; GPRIDX-NEXT: v_cndmask_b32_e64 v13, v14, v1, s[6:7]
; GPRIDX-NEXT: v_cndmask_b32_e64 v1, v16, v1, s[8:9]
; GPRIDX-NEXT: v_readfirstlane_b32 s0, v3 ; GPRIDX-NEXT: v_readfirstlane_b32 s0, v3
; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v4, v1, vcc ; GPRIDX-NEXT: v_readfirstlane_b32 s1, v4
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2 ; GPRIDX-NEXT: v_readfirstlane_b32 s2, v2
; GPRIDX-NEXT: v_readfirstlane_b32 s1, v3 ; GPRIDX-NEXT: v_readfirstlane_b32 s3, v6
; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v5, v0, vcc ; GPRIDX-NEXT: v_readfirstlane_b32 s4, v5
; GPRIDX-NEXT: v_readfirstlane_b32 s2, v3 ; GPRIDX-NEXT: v_readfirstlane_b32 s5, v8
; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v6, v1, vcc ; GPRIDX-NEXT: v_readfirstlane_b32 s6, v7
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 2, v2 ; GPRIDX-NEXT: v_readfirstlane_b32 s7, v10
; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v7, v0, vcc ; GPRIDX-NEXT: v_readfirstlane_b32 s8, v9
; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v8, v1, vcc ; GPRIDX-NEXT: v_readfirstlane_b32 s9, v12
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 3, v2 ; GPRIDX-NEXT: v_readfirstlane_b32 s10, v11
; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v9, v0, vcc ; GPRIDX-NEXT: v_readfirstlane_b32 s11, v13
; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v10, v1, vcc ; GPRIDX-NEXT: v_readfirstlane_b32 s12, v0
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 4, v2 ; GPRIDX-NEXT: v_readfirstlane_b32 s13, v1
; GPRIDX-NEXT: v_cndmask_b32_e32 v8, v11, v0, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v9, v12, v1, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 5, v2
; GPRIDX-NEXT: v_cndmask_b32_e32 v10, v13, v0, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v11, v14, v1, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 6, v2
; GPRIDX-NEXT: v_cndmask_b32_e32 v12, v15, v0, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v13, v16, v1, vcc
; GPRIDX-NEXT: v_readfirstlane_b32 s3, v3
; GPRIDX-NEXT: v_readfirstlane_b32 s4, v4
; GPRIDX-NEXT: v_readfirstlane_b32 s5, v5
; GPRIDX-NEXT: v_readfirstlane_b32 s6, v6
; GPRIDX-NEXT: v_readfirstlane_b32 s7, v7
; GPRIDX-NEXT: v_readfirstlane_b32 s8, v8
; GPRIDX-NEXT: v_readfirstlane_b32 s9, v9
; GPRIDX-NEXT: v_readfirstlane_b32 s10, v10
; GPRIDX-NEXT: v_readfirstlane_b32 s11, v11
; GPRIDX-NEXT: v_readfirstlane_b32 s12, v12
; GPRIDX-NEXT: v_readfirstlane_b32 s13, v13
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: dyn_insertelement_v7f64_s_v_v: ; GFX10-LABEL: dyn_insertelement_v7f64_s_v_v:
; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_mov_b32 s0, s2 ; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s1, s3 ; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4 ; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5 ; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s4, s6 ; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7 ; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8 ; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9 ; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: s_mov_b32 s8, s10 ; GFX10-NEXT: s_mov_b32 s8, s10
; GFX10-NEXT: s_mov_b32 s9, s11 ; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s10, s12 ; GFX10-NEXT: s_mov_b32 s10, s12
; GFX10-NEXT: s_mov_b32 s11, s13 ; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: s_mov_b32 s12, s14 ; GFX10-NEXT: s_mov_b32 s12, s14
; GFX10-NEXT: s_mov_b32 s13, s15 ; GFX10-NEXT: s_mov_b32 s13, s15
; GFX10-NEXT: v_mov_b32_e32 v18, s15 ; GFX10-NEXT: v_mov_b32_e32 v18, s15
; GFX10-NEXT: v_mov_b32_e32 v3, s0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX10-NEXT: v_mov_b32_e32 v4, s1
; GFX10-NEXT: v_mov_b32_e32 v17, s14 ; GFX10-NEXT: v_mov_b32_e32 v17, s14
; GFX10-NEXT: v_mov_b32_e32 v16, s13 ; GFX10-NEXT: v_mov_b32_e32 v16, s13
; GFX10-NEXT: v_mov_b32_e32 v15, s12 ; GFX10-NEXT: v_mov_b32_e32 v15, s12
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v14, s11 ; GFX10-NEXT: v_mov_b32_e32 v14, s11
; GFX10-NEXT: v_mov_b32_e32 v13, s10 ; GFX10-NEXT: v_mov_b32_e32 v13, s10
; GFX10-NEXT: v_mov_b32_e32 v12, s9 ; GFX10-NEXT: v_mov_b32_e32 v12, s9
; GFX10-NEXT: v_mov_b32_e32 v11, s8 ; GFX10-NEXT: v_mov_b32_e32 v11, s8
; GFX10-NEXT: v_mov_b32_e32 v10, s7 ; GFX10-NEXT: v_mov_b32_e32 v10, s7
; GFX10-NEXT: v_mov_b32_e32 v9, s6 ; GFX10-NEXT: v_mov_b32_e32 v9, s6
; GFX10-NEXT: v_mov_b32_e32 v8, s5 ; GFX10-NEXT: v_mov_b32_e32 v8, s5
; GFX10-NEXT: v_mov_b32_e32 v7, s4 ; GFX10-NEXT: v_mov_b32_e32 v7, s4
; GFX10-NEXT: v_mov_b32_e32 v6, s3 ; GFX10-NEXT: v_mov_b32_e32 v6, s3
; GFX10-NEXT: v_mov_b32_e32 v5, s2 ; GFX10-NEXT: v_mov_b32_e32 v5, s2
; GFX10-NEXT: v_readfirstlane_b32 s0, v3 ; GFX10-NEXT: v_mov_b32_e32 v4, s1
; GFX10-NEXT: v_cndmask_b32_e32 v3, v4, v1, vcc_lo ; GFX10-NEXT: v_mov_b32_e32 v3, s0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX10-NEXT: v_readfirstlane_b32 s1, v3 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v2
; GFX10-NEXT: v_cndmask_b32_e32 v3, v5, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 6, v2
; GFX10-NEXT: v_readfirstlane_b32 s2, v3 ; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v3, v6, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2
; GFX10-NEXT: v_readfirstlane_b32 s3, v3 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v0, s0
; GFX10-NEXT: v_cndmask_b32_e32 v4, v7, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v1, s0
; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v1, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 3, v2
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v2 ; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc_lo
; GFX10-NEXT: v_readfirstlane_b32 s4, v4 ; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v1, vcc_lo
; GFX10-NEXT: v_readfirstlane_b32 s5, v5
; GFX10-NEXT: v_cndmask_b32_e32 v6, v9, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v7, v10, v1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v2 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v2
; GFX10-NEXT: v_readfirstlane_b32 s6, v6 ; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v0, s0
; GFX10-NEXT: v_readfirstlane_b32 s7, v7 ; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v1, s0
; GFX10-NEXT: v_cndmask_b32_e32 v8, v11, v0, vcc_lo ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 5, v2
; GFX10-NEXT: v_cndmask_b32_e32 v9, v12, v1, vcc_lo ; GFX10-NEXT: v_readfirstlane_b32 s2, v5
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v2 ; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v0, vcc_lo
; GFX10-NEXT: v_readfirstlane_b32 s8, v8 ; GFX10-NEXT: v_cndmask_b32_e32 v2, v12, v1, vcc_lo
; GFX10-NEXT: v_readfirstlane_b32 s9, v9 ; GFX10-NEXT: v_readfirstlane_b32 s3, v6
; GFX10-NEXT: v_cndmask_b32_e32 v10, v13, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v12, v13, v0, s0
; GFX10-NEXT: v_cndmask_b32_e32 v11, v14, v1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v13, v14, v1, s0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v2 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v15, v0, s1
; GFX10-NEXT: v_readfirstlane_b32 s10, v10 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v16, v1, s1
; GFX10-NEXT: v_readfirstlane_b32 s11, v11 ; GFX10-NEXT: v_readfirstlane_b32 s0, v3
; GFX10-NEXT: v_cndmask_b32_e32 v12, v15, v0, vcc_lo ; GFX10-NEXT: v_readfirstlane_b32 s1, v4
; GFX10-NEXT: v_cndmask_b32_e32 v13, v16, v1, vcc_lo ; GFX10-NEXT: v_readfirstlane_b32 s4, v7
; GFX10-NEXT: v_readfirstlane_b32 s12, v12 ; GFX10-NEXT: v_readfirstlane_b32 s5, v8
; GFX10-NEXT: v_readfirstlane_b32 s13, v13 ; GFX10-NEXT: v_readfirstlane_b32 s6, v9
; GFX10-NEXT: v_readfirstlane_b32 s7, v10
; GFX10-NEXT: v_readfirstlane_b32 s8, v11
; GFX10-NEXT: v_readfirstlane_b32 s9, v2
; GFX10-NEXT: v_readfirstlane_b32 s10, v12
; GFX10-NEXT: v_readfirstlane_b32 s11, v13
; GFX10-NEXT: v_readfirstlane_b32 s12, v0
; GFX10-NEXT: v_readfirstlane_b32 s13, v1
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: dyn_insertelement_v7f64_s_v_v: ; GFX11-LABEL: dyn_insertelement_v7f64_s_v_v:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_mov_b32 s0, s2 ; GFX11-NEXT: s_mov_b32 s0, s2
; GFX11-NEXT: s_mov_b32 s1, s3 ; GFX11-NEXT: s_mov_b32 s1, s3
; GFX11-NEXT: s_mov_b32 s2, s4 ; GFX11-NEXT: s_mov_b32 s2, s4
; GFX11-NEXT: s_mov_b32 s3, s5 ; GFX11-NEXT: s_mov_b32 s3, s5
; GFX11-NEXT: s_mov_b32 s4, s6 ; GFX11-NEXT: s_mov_b32 s4, s6
; GFX11-NEXT: s_mov_b32 s5, s7 ; GFX11-NEXT: s_mov_b32 s5, s7
; GFX11-NEXT: s_mov_b32 s6, s8 ; GFX11-NEXT: s_mov_b32 s6, s8
; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: s_mov_b32 s7, s9
; GFX11-NEXT: s_mov_b32 s8, s10 ; GFX11-NEXT: s_mov_b32 s8, s10
; GFX11-NEXT: s_mov_b32 s9, s11 ; GFX11-NEXT: s_mov_b32 s9, s11
; GFX11-NEXT: s_mov_b32 s10, s12 ; GFX11-NEXT: s_mov_b32 s10, s12
; GFX11-NEXT: s_mov_b32 s11, s13 ; GFX11-NEXT: s_mov_b32 s11, s13
; GFX11-NEXT: s_mov_b32 s12, s14 ; GFX11-NEXT: s_mov_b32 s12, s14
; GFX11-NEXT: s_mov_b32 s13, s15 ; GFX11-NEXT: s_mov_b32 s13, s15
; GFX11-NEXT: v_dual_mov_b32 v18, s15 :: v_dual_mov_b32 v17, s14 ; GFX11-NEXT: v_dual_mov_b32 v18, s15 :: v_dual_mov_b32 v17, s14
; GFX11-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX11-NEXT: v_dual_mov_b32 v16, s13 :: v_dual_mov_b32 v15, s12 ; GFX11-NEXT: v_dual_mov_b32 v16, s13 :: v_dual_mov_b32 v15, s12
; GFX11-NEXT: v_dual_mov_b32 v14, s11 :: v_dual_mov_b32 v13, s10 ; GFX11-NEXT: v_dual_mov_b32 v14, s11 :: v_dual_mov_b32 v13, s10
; GFX11-NEXT: v_dual_mov_b32 v12, s9 :: v_dual_mov_b32 v11, s8 ; GFX11-NEXT: v_dual_mov_b32 v12, s9 :: v_dual_mov_b32 v11, s8
; GFX11-NEXT: v_dual_mov_b32 v10, s7 :: v_dual_mov_b32 v9, s6 ; GFX11-NEXT: v_dual_mov_b32 v10, s7 :: v_dual_mov_b32 v9, s6
; GFX11-NEXT: v_dual_mov_b32 v8, s5 :: v_dual_mov_b32 v7, s4 ; GFX11-NEXT: v_dual_mov_b32 v8, s5 :: v_dual_mov_b32 v7, s4
; GFX11-NEXT: v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v5, s2 ; GFX11-NEXT: v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v5, s2
; GFX11-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v2 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v2
; GFX11-NEXT: v_dual_cndmask_b32 v18, v3, v0 :: v_dual_cndmask_b32 v17, v4, v1 ; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 6, v2
; GFX11-NEXT: v_dual_cndmask_b32 v3, v3, v0 :: v_dual_cndmask_b32 v4, v4, v1
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2
; GFX11-NEXT: v_cmp_eq_u32_e64 s6, 4, v2 ; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v0, s0
; GFX11-NEXT: v_cndmask_b32_e64 v3, v5, v0, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v1, s0
; GFX11-NEXT: v_cndmask_b32_e64 v4, v6, v1, s0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v2
; GFX11-NEXT: v_cmp_eq_u32_e64 s9, 6, v2 ; GFX11-NEXT: v_dual_cndmask_b32 v7, v7, v0 :: v_dual_cndmask_b32 v8, v8, v1
; GFX11-NEXT: v_dual_cndmask_b32 v6, v7, v0 :: v_dual_cndmask_b32 v5, v8, v1 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v2
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v2 ; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v0, s0
; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, v0, s6 ; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v1, s0
; GFX11-NEXT: v_readfirstlane_b32 s0, v18 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 5, v2
; GFX11-NEXT: v_readfirstlane_b32 s1, v17 ; GFX11-NEXT: v_readfirstlane_b32 s2, v5
; GFX11-NEXT: v_readfirstlane_b32 s2, v3 ; GFX11-NEXT: v_dual_cndmask_b32 v11, v11, v0 :: v_dual_cndmask_b32 v2, v12, v1
; GFX11-NEXT: v_dual_cndmask_b32 v7, v9, v0 :: v_dual_cndmask_b32 v8, v10, v1 ; GFX11-NEXT: v_readfirstlane_b32 s3, v6
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v2 ; GFX11-NEXT: v_cndmask_b32_e64 v12, v13, v0, s0
; GFX11-NEXT: v_cndmask_b32_e64 v9, v12, v1, s6 ; GFX11-NEXT: v_cndmask_b32_e64 v13, v14, v1, s0
; GFX11-NEXT: v_cndmask_b32_e64 v12, v15, v0, s9 ; GFX11-NEXT: v_cndmask_b32_e64 v0, v15, v0, s1
; GFX11-NEXT: v_readfirstlane_b32 s3, v4 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v16, v1, s1
; GFX11-NEXT: v_readfirstlane_b32 s4, v6 ; GFX11-NEXT: v_readfirstlane_b32 s0, v3
; GFX11-NEXT: v_cndmask_b32_e32 v10, v13, v0, vcc_lo ; GFX11-NEXT: v_readfirstlane_b32 s1, v4
; GFX11-NEXT: v_cndmask_b32_e32 v14, v14, v1, vcc_lo ; GFX11-NEXT: v_readfirstlane_b32 s4, v7
; GFX11-NEXT: v_cndmask_b32_e64 v13, v16, v1, s9 ; GFX11-NEXT: v_readfirstlane_b32 s5, v8
; GFX11-NEXT: v_readfirstlane_b32 s5, v5 ; GFX11-NEXT: v_readfirstlane_b32 s6, v9
; GFX11-NEXT: v_readfirstlane_b32 s6, v7 ; GFX11-NEXT: v_readfirstlane_b32 s7, v10
; GFX11-NEXT: v_readfirstlane_b32 s7, v8
; GFX11-NEXT: v_readfirstlane_b32 s8, v11 ; GFX11-NEXT: v_readfirstlane_b32 s8, v11
; GFX11-NEXT: v_readfirstlane_b32 s9, v9 ; GFX11-NEXT: v_readfirstlane_b32 s9, v2
; GFX11-NEXT: v_readfirstlane_b32 s10, v10 ; GFX11-NEXT: v_readfirstlane_b32 s10, v12
; GFX11-NEXT: v_readfirstlane_b32 s11, v14 ; GFX11-NEXT: v_readfirstlane_b32 s11, v13
; GFX11-NEXT: v_readfirstlane_b32 s12, v12 ; GFX11-NEXT: v_readfirstlane_b32 s12, v0
; GFX11-NEXT: v_readfirstlane_b32 s13, v13 ; GFX11-NEXT: v_readfirstlane_b32 s13, v1
; GFX11-NEXT: ; return to shader part epilog ; GFX11-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <7 x double> %vec, double %val, i32 %idx %insert = insertelement <7 x double> %vec, double %val, i32 %idx
ret <7 x double> %insert ret <7 x double> %insert
} }
define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_v_v_s(<7 x double> %vec, double %val, i32 inreg %idx) { define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_v_v_s(<7 x double> %vec, double %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v7f64_v_v_s: ; GPRIDX-LABEL: dyn_insertelement_v7f64_v_v_s:
▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
; GPRIDX-NEXT: v_readfirstlane_b32 s11, v11 ; GPRIDX-NEXT: v_readfirstlane_b32 s11, v11
; GPRIDX-NEXT: v_readfirstlane_b32 s12, v12 ; GPRIDX-NEXT: v_readfirstlane_b32 s12, v12
; GPRIDX-NEXT: v_readfirstlane_b32 s13, v13 ; GPRIDX-NEXT: v_readfirstlane_b32 s13, v13
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: dyn_insertelement_v7f64_v_v_v: ; GFX10-LABEL: dyn_insertelement_v7f64_v_v_v:
; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v16 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v16
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v16
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 6, v16
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v14, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v14, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v15, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v15, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v16
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v14, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v15, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v16 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v16
; GFX10-NEXT: v_readfirstlane_b32 s2, v2 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v14, s0
; GFX10-NEXT: v_readfirstlane_b32 s3, v3 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v15, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 3, v16
; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, v14, s1
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v14, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v14, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v15, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v15, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v16 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v16
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v14, s0
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v15, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 5, v16
; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, v15, s1
; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v14, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v15, vcc_lo
; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v14, s0
; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v15, s0
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10-NEXT: v_readfirstlane_b32 s3, v3
; GFX10-NEXT: v_readfirstlane_b32 s4, v4 ; GFX10-NEXT: v_readfirstlane_b32 s4, v4
; GFX10-NEXT: v_readfirstlane_b32 s5, v5 ; GFX10-NEXT: v_readfirstlane_b32 s5, v5
; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v16
; GFX10-NEXT: v_readfirstlane_b32 s6, v6 ; GFX10-NEXT: v_readfirstlane_b32 s6, v6
; GFX10-NEXT: v_readfirstlane_b32 s7, v7 ; GFX10-NEXT: v_readfirstlane_b32 s7, v7
; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v14, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v15, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v16
; GFX10-NEXT: v_readfirstlane_b32 s8, v8 ; GFX10-NEXT: v_readfirstlane_b32 s8, v8
; GFX10-NEXT: v_readfirstlane_b32 s9, v9 ; GFX10-NEXT: v_readfirstlane_b32 s9, v9
; GFX10-NEXT: v_cndmask_b32_e32 v10, v10, v14, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v15, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v16
; GFX10-NEXT: v_readfirstlane_b32 s10, v10 ; GFX10-NEXT: v_readfirstlane_b32 s10, v10
; GFX10-NEXT: v_readfirstlane_b32 s11, v11 ; GFX10-NEXT: v_readfirstlane_b32 s11, v11
; GFX10-NEXT: v_cndmask_b32_e32 v12, v12, v14, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc_lo
; GFX10-NEXT: v_readfirstlane_b32 s12, v12 ; GFX10-NEXT: v_readfirstlane_b32 s12, v12
; GFX10-NEXT: v_readfirstlane_b32 s13, v13 ; GFX10-NEXT: v_readfirstlane_b32 s13, v13
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: dyn_insertelement_v7f64_v_v_v: ; GFX11-LABEL: dyn_insertelement_v7f64_v_v_v:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v16 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v16
; GFX11-NEXT: v_cmp_eq_u32_e64 s9, 5, v16 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v16
; GFX11-NEXT: v_cmp_eq_u32_e64 s10, 6, v16 ; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 6, v16
; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v14 :: v_dual_cndmask_b32 v1, v1, v15 ; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v14 :: v_dual_cndmask_b32 v1, v1, v15
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v16
; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v14, s9
; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, v15, s9
; GFX11-NEXT: v_cndmask_b32_e64 v12, v12, v14, s10
; GFX11-NEXT: v_cndmask_b32_e64 v13, v13, v15, s10
; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v14 :: v_dual_cndmask_b32 v3, v3, v15
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v16 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v16
; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v14, s0
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v15, s0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v16
; GFX11-NEXT: v_cndmask_b32_e64 v12, v12, v14, s1
; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v14 :: v_dual_cndmask_b32 v5, v5, v15
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v16
; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v14, s0
; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, v15, s0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 5, v16
; GFX11-NEXT: v_cndmask_b32_e64 v13, v13, v15, s1
; GFX11-NEXT: v_dual_cndmask_b32 v8, v8, v14 :: v_dual_cndmask_b32 v9, v9, v15
; GFX11-NEXT: v_readfirstlane_b32 s1, v1 ; GFX11-NEXT: v_readfirstlane_b32 s1, v1
; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v14, s0
; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, v15, s0
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: v_readfirstlane_b32 s2, v2 ; GFX11-NEXT: v_readfirstlane_b32 s2, v2
; GFX11-NEXT: v_readfirstlane_b32 s3, v3 ; GFX11-NEXT: v_readfirstlane_b32 s3, v3
; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v14 :: v_dual_cndmask_b32 v5, v5, v15
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v16
; GFX11-NEXT: v_readfirstlane_b32 s10, v10
; GFX11-NEXT: v_readfirstlane_b32 s11, v11
; GFX11-NEXT: v_readfirstlane_b32 s4, v4 ; GFX11-NEXT: v_readfirstlane_b32 s4, v4
; GFX11-NEXT: v_readfirstlane_b32 s5, v5 ; GFX11-NEXT: v_readfirstlane_b32 s5, v5
; GFX11-NEXT: v_dual_cndmask_b32 v6, v6, v14 :: v_dual_cndmask_b32 v7, v7, v15
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v16
; GFX11-NEXT: v_readfirstlane_b32 s12, v12
; GFX11-NEXT: v_readfirstlane_b32 s13, v13
; GFX11-NEXT: v_readfirstlane_b32 s6, v6 ; GFX11-NEXT: v_readfirstlane_b32 s6, v6
; GFX11-NEXT: v_readfirstlane_b32 s7, v7 ; GFX11-NEXT: v_readfirstlane_b32 s7, v7
; GFX11-NEXT: v_dual_cndmask_b32 v8, v8, v14 :: v_dual_cndmask_b32 v9, v9, v15
; GFX11-NEXT: v_readfirstlane_b32 s8, v8 ; GFX11-NEXT: v_readfirstlane_b32 s8, v8
; GFX11-NEXT: v_readfirstlane_b32 s9, v9 ; GFX11-NEXT: v_readfirstlane_b32 s9, v9
; GFX11-NEXT: v_readfirstlane_b32 s10, v10
; GFX11-NEXT: v_readfirstlane_b32 s11, v11
; GFX11-NEXT: v_readfirstlane_b32 s12, v12
; GFX11-NEXT: v_readfirstlane_b32 s13, v13
; GFX11-NEXT: ; return to shader part epilog ; GFX11-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <7 x double> %vec, double %val, i32 %idx %insert = insertelement <7 x double> %vec, double %val, i32 %idx
ret <7 x double> %insert ret <7 x double> %insert
} }
define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_s_s(<5 x double> inreg %vec, double inreg %val, i32 inreg %idx) { define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_s_s(<5 x double> inreg %vec, double inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v5f64_s_s_s: ; GPRIDX-LABEL: dyn_insertelement_v5f64_s_s_s:
▲ Show 20 Lines • Show All 317 Lines • ▼ Show 20 Linesentry:
%insert = insertelement <5 x double> %vec, double %val, i32 %idx %insert = insertelement <5 x double> %vec, double %val, i32 %idx
ret <5 x double> %insert ret <5 x double> %insert
} }
define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_v_v_s(<5 x double> %vec, double %val, i32 inreg %idx) { define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_v_v_s(<5 x double> %vec, double %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v5f64_v_v_s: ; GPRIDX-LABEL: dyn_insertelement_v5f64_v_v_s:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 0 ; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 0
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[0:1], s2, 1
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[8:9], s2, 2
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[4:5], s2, 3
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[6:7], s2, 4
; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v2, v2, v10, s[0:1]
; GPRIDX-NEXT: v_cndmask_b32_e64 v4, v4, v10, s[8:9]
; GPRIDX-NEXT: v_cndmask_b32_e64 v6, v6, v10, s[4:5]
; GPRIDX-NEXT: v_cndmask_b32_e64 v8, v8, v10, s[6:7]
; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v3, v3, v11, s[0:1] ; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 1
; GPRIDX-NEXT: v_cndmask_b32_e64 v5, v5, v11, s[8:9] ; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v7, v7, v11, s[4:5] ; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v9, v9, v11, s[6:7] ; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 2
; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 3
; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e64 vcc, s2, 4
; GPRIDX-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
; GPRIDX-NEXT: v_readfirstlane_b32 s0, v0 ; GPRIDX-NEXT: v_readfirstlane_b32 s0, v0
; GPRIDX-NEXT: v_readfirstlane_b32 s1, v1 ; GPRIDX-NEXT: v_readfirstlane_b32 s1, v1
; GPRIDX-NEXT: v_readfirstlane_b32 s2, v2 ; GPRIDX-NEXT: v_readfirstlane_b32 s2, v2
; GPRIDX-NEXT: v_readfirstlane_b32 s3, v3 ; GPRIDX-NEXT: v_readfirstlane_b32 s3, v3
; GPRIDX-NEXT: v_readfirstlane_b32 s4, v4 ; GPRIDX-NEXT: v_readfirstlane_b32 s4, v4
; GPRIDX-NEXT: v_readfirstlane_b32 s5, v5 ; GPRIDX-NEXT: v_readfirstlane_b32 s5, v5
; GPRIDX-NEXT: v_readfirstlane_b32 s6, v6 ; GPRIDX-NEXT: v_readfirstlane_b32 s6, v6
; GPRIDX-NEXT: v_readfirstlane_b32 s7, v7 ; GPRIDX-NEXT: v_readfirstlane_b32 s7, v7
; GPRIDX-NEXT: v_readfirstlane_b32 s8, v8 ; GPRIDX-NEXT: v_readfirstlane_b32 s8, v8
; GPRIDX-NEXT: v_readfirstlane_b32 s9, v9 ; GPRIDX-NEXT: v_readfirstlane_b32 s9, v9
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: dyn_insertelement_v5f64_v_v_s: ; GFX10-LABEL: dyn_insertelement_v5f64_v_v_s:
; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 0 ; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s2, 4 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s2, 1
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, s2, 4
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 1 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v10, s0
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v10, s0
; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v11, s0
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 2 ; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 2
; GFX10-NEXT: v_readfirstlane_b32 s8, v8 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v11, s0
; GFX10-NEXT: v_readfirstlane_b32 s9, v9 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s2, 3
; GFX10-NEXT: v_readfirstlane_b32 s3, v3 ; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v10, s1
; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v11, s1
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 3 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v10, s0
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v11, s0
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: v_readfirstlane_b32 s2, v2 ; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10-NEXT: v_readfirstlane_b32 s3, v3
; GFX10-NEXT: v_readfirstlane_b32 s4, v4 ; GFX10-NEXT: v_readfirstlane_b32 s4, v4
; GFX10-NEXT: v_readfirstlane_b32 s5, v5 ; GFX10-NEXT: v_readfirstlane_b32 s5, v5
; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo
; GFX10-NEXT: v_readfirstlane_b32 s6, v6 ; GFX10-NEXT: v_readfirstlane_b32 s6, v6
; GFX10-NEXT: v_readfirstlane_b32 s7, v7 ; GFX10-NEXT: v_readfirstlane_b32 s7, v7
; GFX10-NEXT: v_readfirstlane_b32 s8, v8
; GFX10-NEXT: v_readfirstlane_b32 s9, v9
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: dyn_insertelement_v5f64_v_v_s: ; GFX11-LABEL: dyn_insertelement_v5f64_v_v_s:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 0 ; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, s2, 2 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, s2, 1
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, s2, 4 ; GFX11-NEXT: v_cmp_eq_u32_e64 s1, s2, 4
; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v10 :: v_dual_cndmask_b32 v1, v1, v11 ; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v10 :: v_dual_cndmask_b32 v1, v1, v11
; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 1 ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v10, s0
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v10, s0 ; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 2
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v11, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v11, s0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, s2, 3
; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v10, s1 ; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v10, s1
; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v11, s1 ; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v11, s1
; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v10 :: v_dual_cndmask_b32 v3, v3, v11 ; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v10 :: v_dual_cndmask_b32 v5, v5, v11
; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 3 ; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v10, s0
; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, v11, s0
; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: v_readfirstlane_b32 s1, v1 ; GFX11-NEXT: v_readfirstlane_b32 s1, v1
; GFX11-NEXT: v_readfirstlane_b32 s2, v2 ; GFX11-NEXT: v_readfirstlane_b32 s2, v2
; GFX11-NEXT: v_readfirstlane_b32 s3, v3 ; GFX11-NEXT: v_readfirstlane_b32 s3, v3
; GFX11-NEXT: v_dual_cndmask_b32 v6, v6, v10 :: v_dual_cndmask_b32 v7, v7, v11
; GFX11-NEXT: v_readfirstlane_b32 s4, v4 ; GFX11-NEXT: v_readfirstlane_b32 s4, v4
; GFX11-NEXT: v_readfirstlane_b32 s5, v5 ; GFX11-NEXT: v_readfirstlane_b32 s5, v5
; GFX11-NEXT: v_readfirstlane_b32 s8, v8
; GFX11-NEXT: v_readfirstlane_b32 s6, v6 ; GFX11-NEXT: v_readfirstlane_b32 s6, v6
; GFX11-NEXT: v_readfirstlane_b32 s7, v7 ; GFX11-NEXT: v_readfirstlane_b32 s7, v7
; GFX11-NEXT: v_readfirstlane_b32 s8, v8
; GFX11-NEXT: v_readfirstlane_b32 s9, v9 ; GFX11-NEXT: v_readfirstlane_b32 s9, v9
; GFX11-NEXT: ; return to shader part epilog ; GFX11-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <5 x double> %vec, double %val, i32 %idx %insert = insertelement <5 x double> %vec, double %val, i32 %idx
ret <5 x double> %insert ret <5 x double> %insert
} }
define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_v_v_v(<5 x double> %vec, double %val, i32 %idx) { define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_v_v_v(<5 x double> %vec, double %val, i32 %idx) {
; GPRIDX-LABEL: dyn_insertelement_v5f64_v_v_v: ; GPRIDX-LABEL: dyn_insertelement_v5f64_v_v_v:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 0, v12 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 0, v12
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[0:1], 1, v12
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[2:3], 2, v12
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[4:5], 3, v12
; GPRIDX-NEXT: v_cmp_eq_u32_e64 s[6:7], 4, v12
; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v2, v2, v10, s[0:1]
; GPRIDX-NEXT: v_cndmask_b32_e64 v4, v4, v10, s[2:3]
; GPRIDX-NEXT: v_cndmask_b32_e64 v6, v6, v10, s[4:5]
; GPRIDX-NEXT: v_cndmask_b32_e64 v8, v8, v10, s[6:7]
; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v3, v3, v11, s[0:1] ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 1, v12
; GPRIDX-NEXT: v_cndmask_b32_e64 v5, v5, v11, s[2:3] ; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v7, v7, v11, s[4:5] ; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc
; GPRIDX-NEXT: v_cndmask_b32_e64 v9, v9, v11, s[6:7] ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 2, v12
; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 3, v12
; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 4, v12
; GPRIDX-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
; GPRIDX-NEXT: v_readfirstlane_b32 s0, v0 ; GPRIDX-NEXT: v_readfirstlane_b32 s0, v0
; GPRIDX-NEXT: v_readfirstlane_b32 s1, v1 ; GPRIDX-NEXT: v_readfirstlane_b32 s1, v1
; GPRIDX-NEXT: v_readfirstlane_b32 s2, v2 ; GPRIDX-NEXT: v_readfirstlane_b32 s2, v2
; GPRIDX-NEXT: v_readfirstlane_b32 s3, v3 ; GPRIDX-NEXT: v_readfirstlane_b32 s3, v3
; GPRIDX-NEXT: v_readfirstlane_b32 s4, v4 ; GPRIDX-NEXT: v_readfirstlane_b32 s4, v4
; GPRIDX-NEXT: v_readfirstlane_b32 s5, v5 ; GPRIDX-NEXT: v_readfirstlane_b32 s5, v5
; GPRIDX-NEXT: v_readfirstlane_b32 s6, v6 ; GPRIDX-NEXT: v_readfirstlane_b32 s6, v6
; GPRIDX-NEXT: v_readfirstlane_b32 s7, v7 ; GPRIDX-NEXT: v_readfirstlane_b32 s7, v7
; GPRIDX-NEXT: v_readfirstlane_b32 s8, v8 ; GPRIDX-NEXT: v_readfirstlane_b32 s8, v8
; GPRIDX-NEXT: v_readfirstlane_b32 s9, v9 ; GPRIDX-NEXT: v_readfirstlane_b32 s9, v9
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: dyn_insertelement_v5f64_v_v_v: ; GFX10-LABEL: dyn_insertelement_v5f64_v_v_v:
; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v12 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v12
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 4, v12 ; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v12
; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 4, v12
; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v10, s0
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v10, s0 ; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v12
; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v11, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v11, s0
; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 3, v12
; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v10, s1
; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v11, s1
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v10, s0
; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v11, s0
; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v12
; GFX10-NEXT: v_readfirstlane_b32 s8, v8
; GFX10-NEXT: v_readfirstlane_b32 s9, v9
; GFX10-NEXT: v_readfirstlane_b32 s2, v2 ; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10-NEXT: v_readfirstlane_b32 s3, v3 ; GFX10-NEXT: v_readfirstlane_b32 s3, v3
; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v12
; GFX10-NEXT: v_readfirstlane_b32 s4, v4 ; GFX10-NEXT: v_readfirstlane_b32 s4, v4
; GFX10-NEXT: v_readfirstlane_b32 s5, v5 ; GFX10-NEXT: v_readfirstlane_b32 s5, v5
; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo
; GFX10-NEXT: v_readfirstlane_b32 s6, v6 ; GFX10-NEXT: v_readfirstlane_b32 s6, v6
; GFX10-NEXT: v_readfirstlane_b32 s7, v7 ; GFX10-NEXT: v_readfirstlane_b32 s7, v7
; GFX10-NEXT: v_readfirstlane_b32 s8, v8
; GFX10-NEXT: v_readfirstlane_b32 s9, v9
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: dyn_insertelement_v5f64_v_v_v: ; GFX11-LABEL: dyn_insertelement_v5f64_v_v_v:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v12 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v12
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v12 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v12
; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 4, v12 ; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 4, v12
; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v10 :: v_dual_cndmask_b32 v1, v1, v11 ; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v10 :: v_dual_cndmask_b32 v1, v1, v11
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12 ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v10, s0
; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v10, s0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v12
; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v11, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v11, s0
; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v12
; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v10, s1 ; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v10, s1
; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v11, s1 ; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v11, s1
; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v10 :: v_dual_cndmask_b32 v3, v3, v11 ; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v10 :: v_dual_cndmask_b32 v5, v5, v11
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v12 ; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v10, s0
; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, v11, s0
; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: v_readfirstlane_b32 s1, v1 ; GFX11-NEXT: v_readfirstlane_b32 s1, v1
; GFX11-NEXT: v_readfirstlane_b32 s2, v2 ; GFX11-NEXT: v_readfirstlane_b32 s2, v2
; GFX11-NEXT: v_readfirstlane_b32 s3, v3 ; GFX11-NEXT: v_readfirstlane_b32 s3, v3
; GFX11-NEXT: v_dual_cndmask_b32 v6, v6, v10 :: v_dual_cndmask_b32 v7, v7, v11
; GFX11-NEXT: v_readfirstlane_b32 s4, v4 ; GFX11-NEXT: v_readfirstlane_b32 s4, v4
; GFX11-NEXT: v_readfirstlane_b32 s5, v5 ; GFX11-NEXT: v_readfirstlane_b32 s5, v5
; GFX11-NEXT: v_readfirstlane_b32 s8, v8
; GFX11-NEXT: v_readfirstlane_b32 s6, v6 ; GFX11-NEXT: v_readfirstlane_b32 s6, v6
; GFX11-NEXT: v_readfirstlane_b32 s7, v7 ; GFX11-NEXT: v_readfirstlane_b32 s7, v7
; GFX11-NEXT: v_readfirstlane_b32 s8, v8
; GFX11-NEXT: v_readfirstlane_b32 s9, v9 ; GFX11-NEXT: v_readfirstlane_b32 s9, v9
; GFX11-NEXT: ; return to shader part epilog ; GFX11-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <5 x double> %vec, double %val, i32 %idx %insert = insertelement <5 x double> %vec, double %val, i32 %idx
ret <5 x double> %insert ret <5 x double> %insert
} }

llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll

Show First 20 Lines • Show All 575 Lines • ▼ Show 20 Lines
; GFX908-NEXT: v_mov_b32_e32 v8, s8 ; GFX908-NEXT: v_mov_b32_e32 v8, s8
; GFX908-NEXT: v_mov_b32_e32 v6, s8 ; GFX908-NEXT: v_mov_b32_e32 v6, s8
; GFX908-NEXT: v_mov_b32_e32 v5, s9 ; GFX908-NEXT: v_mov_b32_e32 v5, s9
; GFX908-NEXT: v_mov_b32_e32 v9, s9 ; GFX908-NEXT: v_mov_b32_e32 v9, s9
; GFX908-NEXT: v_mov_b32_e32 v7, s9 ; GFX908-NEXT: v_mov_b32_e32 v7, s9
; GFX908-NEXT: v_cmp_lt_i64_e64 s[14:15], s[6:7], 0 ; GFX908-NEXT: v_cmp_lt_i64_e64 s[14:15], s[6:7], 0
; GFX908-NEXT: v_cmp_gt_i64_e64 s[16:17], s[6:7], -1 ; GFX908-NEXT: v_cmp_gt_i64_e64 s[16:17], s[6:7], -1
; GFX908-NEXT: v_mov_b32_e32 v11, v5 ; GFX908-NEXT: v_mov_b32_e32 v11, v5
; GFX908-NEXT: s_mov_b64 s[20:21], s[10:11] ; GFX908-NEXT: s_mov_b64 s[18:19], s[10:11]
; GFX908-NEXT: v_mov_b32_e32 v10, v4 ; GFX908-NEXT: v_mov_b32_e32 v10, v4
; GFX908-NEXT: s_waitcnt vmcnt(0) ; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: v_readfirstlane_b32 s5, v2 ; GFX908-NEXT: v_readfirstlane_b32 s5, v2
; GFX908-NEXT: v_readfirstlane_b32 s9, v3 ; GFX908-NEXT: v_readfirstlane_b32 s9, v3
; GFX908-NEXT: s_add_u32 s5, s5, 1 ; GFX908-NEXT: s_add_u32 s5, s5, 1
; GFX908-NEXT: s_addc_u32 s9, s9, 0 ; GFX908-NEXT: s_addc_u32 s9, s9, 0
; GFX908-NEXT: s_mul_hi_u32 s19, s2, s5 ; GFX908-NEXT: s_mul_hi_u32 s20, s2, s5
; GFX908-NEXT: s_mul_i32 s22, s3, s5 ; GFX908-NEXT: s_mul_i32 s9, s2, s9
; GFX908-NEXT: s_mul_i32 s18, s2, s5 ; GFX908-NEXT: s_mul_i32 s21, s3, s5
; GFX908-NEXT: s_mul_i32 s5, s2, s9 ; GFX908-NEXT: s_add_i32 s9, s20, s9
; GFX908-NEXT: s_add_i32 s5, s19, s5 ; GFX908-NEXT: s_mul_i32 s5, s2, s5
; GFX908-NEXT: s_add_i32 s5, s5, s22 ; GFX908-NEXT: s_add_i32 s9, s9, s21
; GFX908-NEXT: s_branch .LBB3_5 ; GFX908-NEXT: s_branch .LBB3_5
; GFX908-NEXT: .LBB3_4: ; %bb58 ; GFX908-NEXT: .LBB3_4: ; %bb58
; GFX908-NEXT: ; in Loop: Header=BB3_5 Depth=2 ; GFX908-NEXT: ; in Loop: Header=BB3_5 Depth=2
; GFX908-NEXT: v_add_co_u32_sdwa v2, vcc, v2, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 ; GFX908-NEXT: v_add_co_u32_sdwa v2, vcc, v2, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX908-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX908-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
; GFX908-NEXT: s_add_u32 s20, s20, s0 ; GFX908-NEXT: s_add_u32 s18, s18, s0
; GFX908-NEXT: v_cmp_lt_i64_e64 s[24:25], -1, v[2:3] ; GFX908-NEXT: v_cmp_lt_i64_e64 s[22:23], -1, v[2:3]
; GFX908-NEXT: s_addc_u32 s21, s21, s1 ; GFX908-NEXT: s_addc_u32 s19, s19, s1
; GFX908-NEXT: s_mov_b64 s[22:23], 0 ; GFX908-NEXT: s_mov_b64 s[20:21], 0
; GFX908-NEXT: s_andn2_b64 vcc, exec, s[24:25] ; GFX908-NEXT: s_andn2_b64 vcc, exec, s[22:23]
; GFX908-NEXT: s_cbranch_vccz .LBB3_9 ; GFX908-NEXT: s_cbranch_vccz .LBB3_9
; GFX908-NEXT: .LBB3_5: ; %bb16 ; GFX908-NEXT: .LBB3_5: ; %bb16
; GFX908-NEXT: ; Parent Loop BB3_2 Depth=1 ; GFX908-NEXT: ; Parent Loop BB3_2 Depth=1
; GFX908-NEXT: ; => This Inner Loop Header: Depth=2 ; GFX908-NEXT: ; => This Inner Loop Header: Depth=2
; GFX908-NEXT: s_add_u32 s22, s20, s18 ; GFX908-NEXT: s_add_u32 s20, s18, s5
; GFX908-NEXT: s_addc_u32 s23, s21, s5 ; GFX908-NEXT: s_addc_u32 s21, s19, s9
; GFX908-NEXT: global_load_dword v21, v19, s[22:23] offset:-12 glc ; GFX908-NEXT: global_load_dword v21, v19, s[20:21] offset:-12 glc
; GFX908-NEXT: s_waitcnt vmcnt(0) ; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: global_load_dword v20, v19, s[22:23] offset:-8 glc ; GFX908-NEXT: global_load_dword v20, v19, s[20:21] offset:-8 glc
; GFX908-NEXT: s_waitcnt vmcnt(0) ; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: global_load_dword v12, v19, s[22:23] offset:-4 glc ; GFX908-NEXT: global_load_dword v12, v19, s[20:21] offset:-4 glc
; GFX908-NEXT: s_waitcnt vmcnt(0) ; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: global_load_dword v12, v19, s[22:23] glc ; GFX908-NEXT: global_load_dword v12, v19, s[20:21] glc
; GFX908-NEXT: s_waitcnt vmcnt(0) ; GFX908-NEXT: s_waitcnt vmcnt(0)
; GFX908-NEXT: ds_read_b64 v[12:13], v19 ; GFX908-NEXT: ds_read_b64 v[12:13], v19
; GFX908-NEXT: ds_read_b64 v[14:15], v0 ; GFX908-NEXT: ds_read_b64 v[14:15], v0
; GFX908-NEXT: s_andn2_b64 vcc, exec, s[16:17] ; GFX908-NEXT: s_andn2_b64 vcc, exec, s[16:17]
; GFX908-NEXT: s_waitcnt lgkmcnt(0) ; GFX908-NEXT: s_waitcnt lgkmcnt(0)
; GFX908-NEXT: s_cbranch_vccnz .LBB3_7 ; GFX908-NEXT: s_cbranch_vccnz .LBB3_7
; GFX908-NEXT: ; %bb.6: ; %bb51 ; GFX908-NEXT: ; %bb.6: ; %bb51
; GFX908-NEXT: ; in Loop: Header=BB3_5 Depth=2 ; GFX908-NEXT: ; in Loop: Header=BB3_5 Depth=2
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; GFX908-NEXT: v_add_f32_e32 v5, v5, v25 ; GFX908-NEXT: v_add_f32_e32 v5, v5, v25
; GFX908-NEXT: v_add_f32_e32 v4, v4, v24 ; GFX908-NEXT: v_add_f32_e32 v4, v4, v24
; GFX908-NEXT: v_add_f32_e32 v9, v9, v27 ; GFX908-NEXT: v_add_f32_e32 v9, v9, v27
; GFX908-NEXT: v_add_f32_e32 v8, v8, v26 ; GFX908-NEXT: v_add_f32_e32 v8, v8, v26
; GFX908-NEXT: v_add_f32_e32 v6, v6, v14 ; GFX908-NEXT: v_add_f32_e32 v6, v6, v14
; GFX908-NEXT: v_add_f32_e32 v7, v7, v15 ; GFX908-NEXT: v_add_f32_e32 v7, v7, v15
; GFX908-NEXT: v_add_f32_e32 v10, v10, v12 ; GFX908-NEXT: v_add_f32_e32 v10, v10, v12
; GFX908-NEXT: v_add_f32_e32 v11, v11, v13 ; GFX908-NEXT: v_add_f32_e32 v11, v11, v13
; GFX908-NEXT: s_mov_b64 s[22:23], -1 ; GFX908-NEXT: s_mov_b64 s[20:21], -1
; GFX908-NEXT: s_branch .LBB3_4 ; GFX908-NEXT: s_branch .LBB3_4
; GFX908-NEXT: .LBB3_7: ; in Loop: Header=BB3_5 Depth=2 ; GFX908-NEXT: .LBB3_7: ; in Loop: Header=BB3_5 Depth=2
; GFX908-NEXT: s_mov_b64 s[22:23], s[14:15] ; GFX908-NEXT: s_mov_b64 s[20:21], s[14:15]
; GFX908-NEXT: s_andn2_b64 vcc, exec, s[22:23] ; GFX908-NEXT: s_andn2_b64 vcc, exec, s[20:21]
; GFX908-NEXT: s_cbranch_vccz .LBB3_4 ; GFX908-NEXT: s_cbranch_vccz .LBB3_4
; GFX908-NEXT: ; %bb.8: ; in Loop: Header=BB3_2 Depth=1 ; GFX908-NEXT: ; %bb.8: ; in Loop: Header=BB3_2 Depth=1
; GFX908-NEXT: ; implicit-def: $vgpr10_vgpr11 ; GFX908-NEXT: ; implicit-def: $vgpr10_vgpr11
; GFX908-NEXT: ; implicit-def: $vgpr6_vgpr7 ; GFX908-NEXT: ; implicit-def: $vgpr6_vgpr7
; GFX908-NEXT: ; implicit-def: $vgpr8_vgpr9 ; GFX908-NEXT: ; implicit-def: $vgpr8_vgpr9
; GFX908-NEXT: ; implicit-def: $vgpr4_vgpr5 ; GFX908-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX908-NEXT: ; implicit-def: $vgpr2_vgpr3 ; GFX908-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX908-NEXT: ; implicit-def: $sgpr20_sgpr21 ; GFX908-NEXT: ; implicit-def: $sgpr18_sgpr19
; GFX908-NEXT: .LBB3_9: ; %loop.exit.guard ; GFX908-NEXT: .LBB3_9: ; %loop.exit.guard
; GFX908-NEXT: ; in Loop: Header=BB3_2 Depth=1 ; GFX908-NEXT: ; in Loop: Header=BB3_2 Depth=1
; GFX908-NEXT: s_xor_b64 s[16:17], s[22:23], -1 ; GFX908-NEXT: s_xor_b64 s[16:17], s[20:21], -1
; GFX908-NEXT: .LBB3_10: ; %Flow19 ; GFX908-NEXT: .LBB3_10: ; %Flow19
; GFX908-NEXT: ; in Loop: Header=BB3_2 Depth=1 ; GFX908-NEXT: ; in Loop: Header=BB3_2 Depth=1
; GFX908-NEXT: s_mov_b64 s[14:15], -1 ; GFX908-NEXT: s_mov_b64 s[14:15], -1
; GFX908-NEXT: s_and_b64 vcc, exec, s[16:17] ; GFX908-NEXT: s_and_b64 vcc, exec, s[16:17]
; GFX908-NEXT: s_cbranch_vccz .LBB3_1 ; GFX908-NEXT: s_cbranch_vccz .LBB3_1
; GFX908-NEXT: ; %bb.11: ; %bb12 ; GFX908-NEXT: ; %bb.11: ; %bb12
; GFX908-NEXT: ; in Loop: Header=BB3_2 Depth=1 ; GFX908-NEXT: ; in Loop: Header=BB3_2 Depth=1
; GFX908-NEXT: s_add_u32 s6, s6, s4 ; GFX908-NEXT: s_add_u32 s6, s6, s4
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; GFX90A-NEXT: ; in Loop: Header=BB3_2 Depth=1 ; GFX90A-NEXT: ; in Loop: Header=BB3_2 Depth=1
; GFX90A-NEXT: global_load_dwordx2 v[4:5], v[2:3], off ; GFX90A-NEXT: global_load_dwordx2 v[4:5], v[2:3], off
; GFX90A-NEXT: s_mov_b32 s9, s8 ; GFX90A-NEXT: s_mov_b32 s9, s8
; GFX90A-NEXT: v_pk_mov_b32 v[6:7], s[8:9], s[8:9] op_sel:[0,1] ; GFX90A-NEXT: v_pk_mov_b32 v[6:7], s[8:9], s[8:9] op_sel:[0,1]
; GFX90A-NEXT: v_pk_mov_b32 v[10:11], s[8:9], s[8:9] op_sel:[0,1] ; GFX90A-NEXT: v_pk_mov_b32 v[10:11], s[8:9], s[8:9] op_sel:[0,1]
; GFX90A-NEXT: v_pk_mov_b32 v[8:9], s[8:9], s[8:9] op_sel:[0,1] ; GFX90A-NEXT: v_pk_mov_b32 v[8:9], s[8:9], s[8:9] op_sel:[0,1]
; GFX90A-NEXT: v_cmp_lt_i64_e64 s[14:15], s[6:7], 0 ; GFX90A-NEXT: v_cmp_lt_i64_e64 s[14:15], s[6:7], 0
; GFX90A-NEXT: v_cmp_gt_i64_e64 s[16:17], s[6:7], -1 ; GFX90A-NEXT: v_cmp_gt_i64_e64 s[16:17], s[6:7], -1
; GFX90A-NEXT: s_mov_b64 s[20:21], s[10:11] ; GFX90A-NEXT: s_mov_b64 s[18:19], s[10:11]
; GFX90A-NEXT: v_pk_mov_b32 v[12:13], v[6:7], v[6:7] op_sel:[0,1] ; GFX90A-NEXT: v_pk_mov_b32 v[12:13], v[6:7], v[6:7] op_sel:[0,1]
; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: v_readfirstlane_b32 s5, v4 ; GFX90A-NEXT: v_readfirstlane_b32 s5, v4
; GFX90A-NEXT: v_readfirstlane_b32 s9, v5 ; GFX90A-NEXT: v_readfirstlane_b32 s9, v5
; GFX90A-NEXT: s_add_u32 s5, s5, 1 ; GFX90A-NEXT: s_add_u32 s5, s5, 1
; GFX90A-NEXT: s_addc_u32 s9, s9, 0 ; GFX90A-NEXT: s_addc_u32 s9, s9, 0
; GFX90A-NEXT: s_mul_hi_u32 s19, s2, s5 ; GFX90A-NEXT: s_mul_hi_u32 s20, s2, s5
; GFX90A-NEXT: s_mul_i32 s22, s3, s5 ; GFX90A-NEXT: s_mul_i32 s9, s2, s9
; GFX90A-NEXT: s_mul_i32 s18, s2, s5 ; GFX90A-NEXT: s_mul_i32 s21, s3, s5
; GFX90A-NEXT: s_mul_i32 s5, s2, s9 ; GFX90A-NEXT: s_add_i32 s9, s20, s9
; GFX90A-NEXT: s_add_i32 s5, s19, s5 ; GFX90A-NEXT: s_mul_i32 s5, s2, s5
; GFX90A-NEXT: s_add_i32 s5, s5, s22 ; GFX90A-NEXT: s_add_i32 s9, s9, s21
; GFX90A-NEXT: s_branch .LBB3_5 ; GFX90A-NEXT: s_branch .LBB3_5
; GFX90A-NEXT: .LBB3_4: ; %bb58 ; GFX90A-NEXT: .LBB3_4: ; %bb58
; GFX90A-NEXT: ; in Loop: Header=BB3_5 Depth=2 ; GFX90A-NEXT: ; in Loop: Header=BB3_5 Depth=2
; GFX90A-NEXT: v_add_co_u32_sdwa v4, vcc, v4, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 ; GFX90A-NEXT: v_add_co_u32_sdwa v4, vcc, v4, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX90A-NEXT: s_add_u32 s20, s20, s0 ; GFX90A-NEXT: s_add_u32 s18, s18, s0
; GFX90A-NEXT: s_addc_u32 s21, s21, s1 ; GFX90A-NEXT: s_addc_u32 s19, s19, s1
; GFX90A-NEXT: v_cmp_lt_i64_e64 s[24:25], -1, v[4:5] ; GFX90A-NEXT: v_cmp_lt_i64_e64 s[22:23], -1, v[4:5]
; GFX90A-NEXT: s_mov_b64 s[22:23], 0 ; GFX90A-NEXT: s_mov_b64 s[20:21], 0
; GFX90A-NEXT: s_andn2_b64 vcc, exec, s[24:25] ; GFX90A-NEXT: s_andn2_b64 vcc, exec, s[22:23]
; GFX90A-NEXT: s_cbranch_vccz .LBB3_9 ; GFX90A-NEXT: s_cbranch_vccz .LBB3_9
; GFX90A-NEXT: .LBB3_5: ; %bb16 ; GFX90A-NEXT: .LBB3_5: ; %bb16
; GFX90A-NEXT: ; Parent Loop BB3_2 Depth=1 ; GFX90A-NEXT: ; Parent Loop BB3_2 Depth=1
; GFX90A-NEXT: ; => This Inner Loop Header: Depth=2 ; GFX90A-NEXT: ; => This Inner Loop Header: Depth=2
; GFX90A-NEXT: s_add_u32 s22, s20, s18 ; GFX90A-NEXT: s_add_u32 s20, s18, s5
; GFX90A-NEXT: s_addc_u32 s23, s21, s5 ; GFX90A-NEXT: s_addc_u32 s21, s19, s9
; GFX90A-NEXT: global_load_dword v21, v19, s[22:23] offset:-12 glc ; GFX90A-NEXT: global_load_dword v21, v19, s[20:21] offset:-12 glc
; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: global_load_dword v20, v19, s[22:23] offset:-8 glc ; GFX90A-NEXT: global_load_dword v20, v19, s[20:21] offset:-8 glc
; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: global_load_dword v14, v19, s[22:23] offset:-4 glc ; GFX90A-NEXT: global_load_dword v14, v19, s[20:21] offset:-4 glc
; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: global_load_dword v14, v19, s[22:23] glc ; GFX90A-NEXT: global_load_dword v14, v19, s[20:21] glc
; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: ds_read_b64 v[14:15], v19 ; GFX90A-NEXT: ds_read_b64 v[14:15], v19
; GFX90A-NEXT: ds_read_b64 v[16:17], v0 ; GFX90A-NEXT: ds_read_b64 v[16:17], v0
; GFX90A-NEXT: s_andn2_b64 vcc, exec, s[16:17] ; GFX90A-NEXT: s_andn2_b64 vcc, exec, s[16:17]
; GFX90A-NEXT: ; kill: killed $sgpr22 killed $sgpr23 ; GFX90A-NEXT: ; kill: killed $sgpr20 killed $sgpr21
; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: s_cbranch_vccnz .LBB3_7 ; GFX90A-NEXT: s_cbranch_vccnz .LBB3_7
; GFX90A-NEXT: ; %bb.6: ; %bb51 ; GFX90A-NEXT: ; %bb.6: ; %bb51
; GFX90A-NEXT: ; in Loop: Header=BB3_5 Depth=2 ; GFX90A-NEXT: ; in Loop: Header=BB3_5 Depth=2
; GFX90A-NEXT: v_cvt_f32_f16_sdwa v23, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX90A-NEXT: v_cvt_f32_f16_sdwa v23, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX90A-NEXT: v_cvt_f32_f16_e32 v22, v21 ; GFX90A-NEXT: v_cvt_f32_f16_e32 v22, v21
; GFX90A-NEXT: v_cvt_f32_f16_sdwa v21, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX90A-NEXT: v_cvt_f32_f16_sdwa v21, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX90A-NEXT: v_cvt_f32_f16_e32 v20, v20 ; GFX90A-NEXT: v_cvt_f32_f16_e32 v20, v20
; GFX90A-NEXT: v_pk_add_f32 v[24:25], v[0:1], v[14:15] ; GFX90A-NEXT: v_pk_add_f32 v[24:25], v[0:1], v[14:15]
; GFX90A-NEXT: v_pk_add_f32 v[26:27], v[14:15], 0 op_sel_hi:[1,0] ; GFX90A-NEXT: v_pk_add_f32 v[26:27], v[14:15], 0 op_sel_hi:[1,0]
; GFX90A-NEXT: v_pk_add_f32 v[16:17], v[22:23], v[16:17] ; GFX90A-NEXT: v_pk_add_f32 v[16:17], v[22:23], v[16:17]
; GFX90A-NEXT: v_pk_add_f32 v[14:15], v[20:21], v[14:15] ; GFX90A-NEXT: v_pk_add_f32 v[14:15], v[20:21], v[14:15]
; GFX90A-NEXT: v_pk_add_f32 v[6:7], v[6:7], v[24:25] ; GFX90A-NEXT: v_pk_add_f32 v[6:7], v[6:7], v[24:25]
; GFX90A-NEXT: v_pk_add_f32 v[10:11], v[10:11], v[26:27] ; GFX90A-NEXT: v_pk_add_f32 v[10:11], v[10:11], v[26:27]
; GFX90A-NEXT: v_pk_add_f32 v[8:9], v[8:9], v[16:17] ; GFX90A-NEXT: v_pk_add_f32 v[8:9], v[8:9], v[16:17]
; GFX90A-NEXT: v_pk_add_f32 v[12:13], v[12:13], v[14:15] ; GFX90A-NEXT: v_pk_add_f32 v[12:13], v[12:13], v[14:15]
; GFX90A-NEXT: s_mov_b64 s[22:23], -1 ; GFX90A-NEXT: s_mov_b64 s[20:21], -1
; GFX90A-NEXT: s_branch .LBB3_4 ; GFX90A-NEXT: s_branch .LBB3_4
; GFX90A-NEXT: .LBB3_7: ; in Loop: Header=BB3_5 Depth=2 ; GFX90A-NEXT: .LBB3_7: ; in Loop: Header=BB3_5 Depth=2
; GFX90A-NEXT: s_mov_b64 s[22:23], s[14:15] ; GFX90A-NEXT: s_mov_b64 s[20:21], s[14:15]
; GFX90A-NEXT: s_andn2_b64 vcc, exec, s[22:23] ; GFX90A-NEXT: s_andn2_b64 vcc, exec, s[20:21]
; GFX90A-NEXT: s_cbranch_vccz .LBB3_4 ; GFX90A-NEXT: s_cbranch_vccz .LBB3_4
; GFX90A-NEXT: ; %bb.8: ; in Loop: Header=BB3_2 Depth=1 ; GFX90A-NEXT: ; %bb.8: ; in Loop: Header=BB3_2 Depth=1
; GFX90A-NEXT: ; implicit-def: $vgpr12_vgpr13 ; GFX90A-NEXT: ; implicit-def: $vgpr12_vgpr13
; GFX90A-NEXT: ; implicit-def: $vgpr8_vgpr9 ; GFX90A-NEXT: ; implicit-def: $vgpr8_vgpr9
; GFX90A-NEXT: ; implicit-def: $vgpr10_vgpr11 ; GFX90A-NEXT: ; implicit-def: $vgpr10_vgpr11
; GFX90A-NEXT: ; implicit-def: $vgpr6_vgpr7 ; GFX90A-NEXT: ; implicit-def: $vgpr6_vgpr7
; GFX90A-NEXT: ; implicit-def: $vgpr4_vgpr5 ; GFX90A-NEXT: ; implicit-def: $vgpr4_vgpr5
; GFX90A-NEXT: ; implicit-def: $sgpr20_sgpr21 ; GFX90A-NEXT: ; implicit-def: $sgpr18_sgpr19
; GFX90A-NEXT: .LBB3_9: ; %loop.exit.guard ; GFX90A-NEXT: .LBB3_9: ; %loop.exit.guard
; GFX90A-NEXT: ; in Loop: Header=BB3_2 Depth=1 ; GFX90A-NEXT: ; in Loop: Header=BB3_2 Depth=1
; GFX90A-NEXT: s_xor_b64 s[16:17], s[22:23], -1 ; GFX90A-NEXT: s_xor_b64 s[16:17], s[20:21], -1
; GFX90A-NEXT: .LBB3_10: ; %Flow19 ; GFX90A-NEXT: .LBB3_10: ; %Flow19
; GFX90A-NEXT: ; in Loop: Header=BB3_2 Depth=1 ; GFX90A-NEXT: ; in Loop: Header=BB3_2 Depth=1
; GFX90A-NEXT: s_mov_b64 s[14:15], -1 ; GFX90A-NEXT: s_mov_b64 s[14:15], -1
; GFX90A-NEXT: s_and_b64 vcc, exec, s[16:17] ; GFX90A-NEXT: s_and_b64 vcc, exec, s[16:17]
; GFX90A-NEXT: s_cbranch_vccz .LBB3_1 ; GFX90A-NEXT: s_cbranch_vccz .LBB3_1
; GFX90A-NEXT: ; %bb.11: ; %bb12 ; GFX90A-NEXT: ; %bb.11: ; %bb12
; GFX90A-NEXT: ; in Loop: Header=BB3_2 Depth=1 ; GFX90A-NEXT: ; in Loop: Header=BB3_2 Depth=1
; GFX90A-NEXT: s_add_u32 s6, s6, s4 ; GFX90A-NEXT: s_add_u32 s6, s6, s4
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llvm/test/CodeGen/AMDGPU/coalesce-identity-copies-undef-subregs.mir

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name: identity_copy_undef_subrange name: identity_copy_undef_subrange
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
; CHECK-LABEL: name: identity_copy_undef_subrange ; CHECK-LABEL: name: identity_copy_undef_subrange
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $vgpr0 ; CHECK-NEXT: liveins: $vgpr0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: undef %0.sub1:vreg_64 = COPY $vgpr0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1: ; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec ; CHECK-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec
; CHECK-NEXT: S_BRANCH %bb.2 ; CHECK-NEXT: S_BRANCH %bb.2
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2: ; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: undef %0.sub1:vreg_64 = nofpexcept V_CEIL_F32_e32 %0.sub1, implicit $mode, implicit $exec ; CHECK-NEXT: [[V_CEIL_F32_e32_:%[0-9]+]]:vgpr_32 = nofpexcept V_CEIL_F32_e32 [[V_CEIL_F32_e32_]], implicit $mode, implicit $exec
; CHECK-NEXT: S_BRANCH %bb.1 ; CHECK-NEXT: S_BRANCH %bb.1
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
undef %0.sub1:vreg_64 = COPY killed $vgpr0 undef %0.sub1:vreg_64 = COPY killed $vgpr0
bb.1: bb.1:
successors: %bb.2, %bb.1 successors: %bb.2, %bb.1
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name: second_identity_copy name: second_identity_copy
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
; CHECK-LABEL: name: second_identity_copy ; CHECK-LABEL: name: second_identity_copy
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $vgpr0 ; CHECK-NEXT: liveins: $vgpr0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: undef %0.sub1:vreg_64 = COPY $vgpr0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1: ; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec ; CHECK-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec
; CHECK-NEXT: S_BRANCH %bb.2 ; CHECK-NEXT: S_BRANCH %bb.2
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2: ; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: undef %0.sub1:vreg_64 = nofpexcept V_MUL_F32_e32 0, %0.sub1, implicit $mode, implicit $exec ; CHECK-NEXT: [[V_MUL_F32_e32_:%[0-9]+]]:vgpr_32 = nofpexcept V_MUL_F32_e32 0, [[V_MUL_F32_e32_]], implicit $mode, implicit $exec
; CHECK-NEXT: S_BRANCH %bb.1 ; CHECK-NEXT: S_BRANCH %bb.1
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
undef %0.sub1:vreg_64 = COPY killed $vgpr0 undef %0.sub1:vreg_64 = COPY killed $vgpr0
bb.1: bb.1:
successors: %bb.2, %bb.1 successors: %bb.2, %bb.1
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name: second_identity_copy_undef_lane_outblock name: second_identity_copy_undef_lane_outblock
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
; CHECK-LABEL: name: second_identity_copy_undef_lane_outblock ; CHECK-LABEL: name: second_identity_copy_undef_lane_outblock
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $vgpr0 ; CHECK-NEXT: liveins: $vgpr0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: undef %0.sub1:vreg_64 = COPY $vgpr0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1: ; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec ; CHECK-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec
; CHECK-NEXT: S_BRANCH %bb.2 ; CHECK-NEXT: S_BRANCH %bb.2
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2: ; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %0.sub1:vreg_64 = nofpexcept V_MUL_F32_e32 0, %0.sub1, implicit $mode, implicit $exec ; CHECK-NEXT: [[V_MUL_F32_e32_:%[0-9]+]]:vgpr_32 = nofpexcept V_MUL_F32_e32 0, [[V_MUL_F32_e32_]], implicit $mode, implicit $exec
; CHECK-NEXT: S_BRANCH %bb.1 ; CHECK-NEXT: S_BRANCH %bb.1
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
undef %0.sub1:vreg_64 = COPY killed $vgpr0 undef %0.sub1:vreg_64 = COPY killed $vgpr0
bb.1: bb.1:
successors: %bb.2, %bb.1 successors: %bb.2, %bb.1
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name: undef_copy_self_loop1 name: undef_copy_self_loop1
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
; CHECK-LABEL: name: undef_copy_self_loop1 ; CHECK-LABEL: name: undef_copy_self_loop1
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $vgpr0 ; CHECK-NEXT: liveins: $vgpr0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: undef %0.sub1:vreg_64 = COPY $vgpr0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1: ; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec ; CHECK-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2: ; CHECK-NEXT: bb.2:
; CHECK-NEXT: S_NOP 0, implicit %0.sub1 ; CHECK-NEXT: S_NOP 0, implicit [[COPY]]
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
undef %0.sub1:vreg_64 = COPY killed $vgpr0 undef %0.sub1:vreg_64 = COPY killed $vgpr0
bb.1: bb.1:
%0:vreg_64 = COPY %0 %0:vreg_64 = COPY %0
S_CBRANCH_EXECNZ %bb.1, implicit $exec S_CBRANCH_EXECNZ %bb.1, implicit $exec
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name: prune_subrange_phi_value_0 name: prune_subrange_phi_value_0
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
; CHECK-LABEL: name: prune_subrange_phi_value_0 ; CHECK-LABEL: name: prune_subrange_phi_value_0
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $vgpr0 ; CHECK-NEXT: liveins: $vgpr0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: dead undef %2.sub1:vreg_64 = COPY $vgpr0 ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1: ; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec ; CHECK-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec
; CHECK-NEXT: S_BRANCH %bb.2 ; CHECK-NEXT: S_BRANCH %bb.2
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2: ; CHECK-NEXT: bb.2:
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name: prune_subrange_phi_value_0_0 name: prune_subrange_phi_value_0_0
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
; CHECK-LABEL: name: prune_subrange_phi_value_0_0 ; CHECK-LABEL: name: prune_subrange_phi_value_0_0
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $vgpr0 ; CHECK-NEXT: liveins: $vgpr0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: dead undef %0.sub1:vreg_64 = COPY $vgpr0 ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1: ; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec ; CHECK-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec
; CHECK-NEXT: S_BRANCH %bb.2 ; CHECK-NEXT: S_BRANCH %bb.2
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2: ; CHECK-NEXT: bb.2:
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name: prune_subrange_phi_value_0_1 name: prune_subrange_phi_value_0_1
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
; CHECK-LABEL: name: prune_subrange_phi_value_0_1 ; CHECK-LABEL: name: prune_subrange_phi_value_0_1
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $vgpr0 ; CHECK-NEXT: liveins: $vgpr0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: dead undef %0.sub1:vreg_64 = COPY $vgpr0 ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1: ; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec ; CHECK-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec
; CHECK-NEXT: S_BRANCH %bb.2 ; CHECK-NEXT: S_BRANCH %bb.2
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2: ; CHECK-NEXT: bb.2:
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name: prune_subrange_phi_value_1 name: prune_subrange_phi_value_1
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
; CHECK-LABEL: name: prune_subrange_phi_value_1 ; CHECK-LABEL: name: prune_subrange_phi_value_1
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $vgpr0 ; CHECK-NEXT: liveins: $vgpr0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: undef %0.sub1:vreg_64 = COPY $vgpr0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1: ; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec ; CHECK-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec
; CHECK-NEXT: S_BRANCH %bb.2 ; CHECK-NEXT: S_BRANCH %bb.2
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2: ; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: undef %0.sub1:vreg_64 = nofpexcept V_CEIL_F32_e32 %0.sub1, implicit $mode, implicit $exec ; CHECK-NEXT: [[V_CEIL_F32_e32_:%[0-9]+]]:vgpr_32 = nofpexcept V_CEIL_F32_e32 [[V_CEIL_F32_e32_]], implicit $mode, implicit $exec
; CHECK-NEXT: S_BRANCH %bb.1 ; CHECK-NEXT: S_BRANCH %bb.1
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
undef %0.sub1:vreg_64 = COPY killed $vgpr0 undef %0.sub1:vreg_64 = COPY killed $vgpr0
bb.1: bb.1:
successors: %bb.2, %bb.1 successors: %bb.2, %bb.1
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name: prune_subrange_phi_value_2 name: prune_subrange_phi_value_2
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
; CHECK-LABEL: name: prune_subrange_phi_value_2 ; CHECK-LABEL: name: prune_subrange_phi_value_2
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $vgpr0 ; CHECK-NEXT: liveins: $vgpr0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: undef %0.sub1:vreg_64 = COPY $vgpr0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1: ; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec ; CHECK-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec
; CHECK-NEXT: S_BRANCH %bb.2 ; CHECK-NEXT: S_BRANCH %bb.2
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2: ; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %0.sub1:vreg_64 = nofpexcept V_CEIL_F32_e32 %0.sub1, implicit $mode, implicit $exec ; CHECK-NEXT: [[V_CEIL_F32_e32_:%[0-9]+]]:vgpr_32 = nofpexcept V_CEIL_F32_e32 [[V_CEIL_F32_e32_]], implicit $mode, implicit $exec
; CHECK-NEXT: S_BRANCH %bb.1 ; CHECK-NEXT: S_BRANCH %bb.1
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
undef %0.sub1:vreg_64 = COPY killed $vgpr0 undef %0.sub1:vreg_64 = COPY killed $vgpr0
bb.1: bb.1:
successors: %bb.2, %bb.1 successors: %bb.2, %bb.1
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llvm/test/CodeGen/AMDGPU/dead-lane.mir

# RUN: llc -march=amdgcn -mcpu=tonga %s -start-before detect-dead-lanes -stop-before machine-scheduler -verify-machineinstrs -o - | FileCheck -check-prefix=GCN %s # RUN: llc -amdgpu-enable-rewrite-partial-reg-uses=false -march=amdgcn -mcpu=tonga %s -start-before detect-dead-lanes -stop-before machine-scheduler -verify-machineinstrs -o - | FileCheck -check-prefix=GCN %s
# RUN: llc -march=amdgcn -mcpu=tonga %s -start-before detect-dead-lanes -stop-before machine-scheduler -verify-machineinstrs -early-live-intervals -o - | FileCheck -check-prefix=GCN %s # RUN: llc -amdgpu-enable-rewrite-partial-reg-uses=false -march=amdgcn -mcpu=tonga %s -start-before detect-dead-lanes -stop-before machine-scheduler -verify-machineinstrs -early-live-intervals -o - | FileCheck -check-prefix=GCN %s
# GCN-LABEL: name: dead_lane # GCN-LABEL: name: dead_lane
# GCN: bb.0: # GCN: bb.0:
# GCN-NEXT: undef %3.sub0:vreg_64 = nofpexcept V_MAC_F32_e32 undef %1:vgpr_32, undef %1:vgpr_32, undef %3.sub0, implicit $mode, implicit $exec # GCN-NEXT: undef %3.sub0:vreg_64 = nofpexcept V_MAC_F32_e32 undef %1:vgpr_32, undef %1:vgpr_32, undef %3.sub0, implicit $mode, implicit $exec
# GCN-NEXT: FLAT_STORE_DWORD undef %4:vreg_64, %3.sub0, # GCN-NEXT: FLAT_STORE_DWORD undef %4:vreg_64, %3.sub0,
--- ---
name: dead_lane name: dead_lane
tracksRegLiveness: true tracksRegLiveness: true
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llvm/test/CodeGen/AMDGPU/idiv-licm.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s
; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX10 %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX10 %s
; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX11 %s ; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX11 %s
define amdgpu_kernel void @udiv32_invariant_denom(ptr addrspace(1) nocapture %arg, i32 %arg1) { define amdgpu_kernel void @udiv32_invariant_denom(ptr addrspace(1) nocapture %arg, i32 %arg1) {
; GFX9-LABEL: udiv32_invariant_denom: ; GFX9-LABEL: udiv32_invariant_denom:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_load_dword s5, s[0:1], 0x2c ; GFX9-NEXT: s_load_dword s6, s[0:1], 0x2c
; GFX9-NEXT: s_mov_b32 s8, 0 ; GFX9-NEXT: s_mov_b32 s7, 0
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: s_mov_b64 s[2:3], 0 ; GFX9-NEXT: s_mov_b64 s[2:3], 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s5 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s6
; GFX9-NEXT: s_sub_i32 s4, 0, s5 ; GFX9-NEXT: s_sub_i32 s4, 0, s6
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v0
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_readfirstlane_b32 s6, v1 ; GFX9-NEXT: v_readfirstlane_b32 s5, v1
; GFX9-NEXT: s_mul_i32 s4, s4, s6 ; GFX9-NEXT: s_mul_i32 s4, s4, s5
; GFX9-NEXT: s_mul_hi_u32 s4, s6, s4 ; GFX9-NEXT: s_mul_hi_u32 s4, s5, s4
; GFX9-NEXT: s_add_i32 s4, s6, s4 ; GFX9-NEXT: s_add_i32 s8, s5, s4
; GFX9-NEXT: s_mov_b64 s[6:7], 0 ; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: .LBB0_1: ; %bb3 ; GFX9-NEXT: .LBB0_1: ; %bb3
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_not_b32 s10, s7 ; GFX9-NEXT: s_not_b32 s10, s5
; GFX9-NEXT: s_mul_i32 s9, s5, s7 ; GFX9-NEXT: s_mul_i32 s9, s6, s5
; GFX9-NEXT: s_mul_i32 s10, s5, s10 ; GFX9-NEXT: s_mul_i32 s10, s6, s10
; GFX9-NEXT: s_add_i32 s11, s7, 1 ; GFX9-NEXT: s_add_i32 s11, s5, 1
; GFX9-NEXT: s_sub_i32 s9, s8, s9 ; GFX9-NEXT: s_sub_i32 s9, s7, s9
; GFX9-NEXT: s_add_i32 s10, s8, s10 ; GFX9-NEXT: s_add_i32 s10, s7, s10
; GFX9-NEXT: s_cmp_ge_u32 s9, s5 ; GFX9-NEXT: s_cmp_ge_u32 s9, s6
; GFX9-NEXT: s_cselect_b32 s11, s11, s7 ; GFX9-NEXT: s_cselect_b32 s11, s11, s5
; GFX9-NEXT: s_cselect_b32 s9, s10, s9 ; GFX9-NEXT: s_cselect_b32 s9, s10, s9
; GFX9-NEXT: s_add_i32 s10, s11, 1 ; GFX9-NEXT: s_add_i32 s10, s11, 1
; GFX9-NEXT: s_cmp_ge_u32 s9, s5 ; GFX9-NEXT: s_cmp_ge_u32 s9, s6
; GFX9-NEXT: s_cselect_b32 s9, s10, s11 ; GFX9-NEXT: s_cselect_b32 s9, s10, s11
; GFX9-NEXT: s_add_u32 s10, s0, s2 ; GFX9-NEXT: s_add_u32 s10, s0, s2
; GFX9-NEXT: s_addc_u32 s11, s1, s3 ; GFX9-NEXT: s_addc_u32 s11, s1, s3
; GFX9-NEXT: s_add_i32 s8, s8, 1 ; GFX9-NEXT: s_add_i32 s7, s7, 1
; GFX9-NEXT: s_add_u32 s6, s6, s4 ; GFX9-NEXT: s_add_u32 s4, s4, s8
; GFX9-NEXT: s_addc_u32 s7, s7, 0 ; GFX9-NEXT: s_addc_u32 s5, s5, 0
; GFX9-NEXT: s_add_u32 s2, s2, 4 ; GFX9-NEXT: s_add_u32 s2, s2, 4
; GFX9-NEXT: s_addc_u32 s3, s3, 0 ; GFX9-NEXT: s_addc_u32 s3, s3, 0
; GFX9-NEXT: v_mov_b32_e32 v1, s9 ; GFX9-NEXT: v_mov_b32_e32 v1, s9
; GFX9-NEXT: s_cmpk_eq_i32 s2, 0x1000 ; GFX9-NEXT: s_cmpk_eq_i32 s2, 0x1000
; GFX9-NEXT: global_store_dword v0, v1, s[10:11] ; GFX9-NEXT: global_store_dword v0, v1, s[10:11]
; GFX9-NEXT: s_cbranch_scc0 .LBB0_1 ; GFX9-NEXT: s_cbranch_scc0 .LBB0_1
; GFX9-NEXT: ; %bb.2: ; %bb2 ; GFX9-NEXT: ; %bb.2: ; %bb2
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: udiv32_invariant_denom: ; GFX10-LABEL: udiv32_invariant_denom:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_load_dword s5, s[0:1], 0x2c ; GFX10-NEXT: s_load_dword s6, s[0:1], 0x2c
; GFX10-NEXT: s_mov_b32 s8, 0 ; GFX10-NEXT: s_mov_b32 s7, 0
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s5 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s6
; GFX10-NEXT: s_sub_i32 s2, 0, s5 ; GFX10-NEXT: s_sub_i32 s2, 0, s6
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: v_readfirstlane_b32 s4, v0 ; GFX10-NEXT: v_readfirstlane_b32 s4, v0
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_mul_i32 s2, s2, s4 ; GFX10-NEXT: s_mul_i32 s2, s2, s4
; GFX10-NEXT: s_mul_hi_u32 s6, s4, s2 ; GFX10-NEXT: s_mul_hi_u32 s5, s4, s2
; GFX10-NEXT: s_mov_b64 s[2:3], 0 ; GFX10-NEXT: s_mov_b64 s[2:3], 0
; GFX10-NEXT: s_add_i32 s4, s4, s6 ; GFX10-NEXT: s_add_i32 s8, s4, s5
; GFX10-NEXT: s_mov_b64 s[6:7], 0 ; GFX10-NEXT: s_mov_b64 s[4:5], 0
; GFX10-NEXT: .LBB0_1: ; %bb3 ; GFX10-NEXT: .LBB0_1: ; %bb3
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_not_b32 s10, s7 ; GFX10-NEXT: s_not_b32 s10, s5
; GFX10-NEXT: s_mul_i32 s9, s5, s7 ; GFX10-NEXT: s_mul_i32 s9, s6, s5
; GFX10-NEXT: s_mul_i32 s10, s5, s10 ; GFX10-NEXT: s_mul_i32 s10, s6, s10
; GFX10-NEXT: s_sub_i32 s9, s8, s9 ; GFX10-NEXT: s_sub_i32 s9, s7, s9
; GFX10-NEXT: s_add_i32 s11, s7, 1 ; GFX10-NEXT: s_add_i32 s11, s5, 1
; GFX10-NEXT: s_add_i32 s10, s8, s10 ; GFX10-NEXT: s_add_i32 s10, s7, s10
; GFX10-NEXT: s_cmp_ge_u32 s9, s5 ; GFX10-NEXT: s_cmp_ge_u32 s9, s6
; GFX10-NEXT: s_cselect_b32 s11, s11, s7 ; GFX10-NEXT: s_cselect_b32 s11, s11, s5
; GFX10-NEXT: s_cselect_b32 s9, s10, s9 ; GFX10-NEXT: s_cselect_b32 s9, s10, s9
; GFX10-NEXT: s_add_i32 s10, s11, 1 ; GFX10-NEXT: s_add_i32 s10, s11, 1
; GFX10-NEXT: s_cmp_ge_u32 s9, s5 ; GFX10-NEXT: s_cmp_ge_u32 s9, s6
; GFX10-NEXT: s_cselect_b32 s9, s10, s11 ; GFX10-NEXT: s_cselect_b32 s9, s10, s11
; GFX10-NEXT: s_add_u32 s10, s0, s2 ; GFX10-NEXT: s_add_u32 s10, s0, s2
; GFX10-NEXT: s_addc_u32 s11, s1, s3 ; GFX10-NEXT: s_addc_u32 s11, s1, s3
; GFX10-NEXT: s_add_i32 s8, s8, 1 ; GFX10-NEXT: s_add_i32 s7, s7, 1
; GFX10-NEXT: s_add_u32 s6, s6, s4 ; GFX10-NEXT: s_add_u32 s4, s4, s8
; GFX10-NEXT: v_mov_b32_e32 v1, s9 ; GFX10-NEXT: v_mov_b32_e32 v1, s9
; GFX10-NEXT: s_addc_u32 s7, s7, 0 ; GFX10-NEXT: s_addc_u32 s5, s5, 0
; GFX10-NEXT: s_add_u32 s2, s2, 4 ; GFX10-NEXT: s_add_u32 s2, s2, 4
; GFX10-NEXT: s_addc_u32 s3, s3, 0 ; GFX10-NEXT: s_addc_u32 s3, s3, 0
; GFX10-NEXT: s_cmpk_eq_i32 s2, 0x1000 ; GFX10-NEXT: s_cmpk_eq_i32 s2, 0x1000
; GFX10-NEXT: global_store_dword v0, v1, s[10:11] ; GFX10-NEXT: global_store_dword v0, v1, s[10:11]
; GFX10-NEXT: s_cbranch_scc0 .LBB0_1 ; GFX10-NEXT: s_cbranch_scc0 .LBB0_1
; GFX10-NEXT: ; %bb.2: ; %bb2 ; GFX10-NEXT: ; %bb.2: ; %bb2
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: udiv32_invariant_denom: ; GFX11-LABEL: udiv32_invariant_denom:
; GFX11: ; %bb.0: ; %bb ; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b32 s5, s[0:1], 0x2c ; GFX11-NEXT: s_load_b32 s6, s[0:1], 0x2c
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
; GFX11-NEXT: s_mov_b32 s8, 0 ; GFX11-NEXT: s_mov_b32 s7, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s5 ; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s6
; GFX11-NEXT: s_sub_i32 s2, 0, s5 ; GFX11-NEXT: s_sub_i32 s2, 0, s6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr 0xfff ; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_readfirstlane_b32 s4, v0 ; GFX11-NEXT: v_readfirstlane_b32 s4, v0
; GFX11-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-NEXT: v_mov_b32_e32 v0, 0
; GFX11-NEXT: s_mul_i32 s2, s2, s4 ; GFX11-NEXT: s_mul_i32 s2, s2, s4
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_mul_hi_u32 s6, s4, s2 ; GFX11-NEXT: s_mul_hi_u32 s5, s4, s2
; GFX11-NEXT: s_mov_b64 s[2:3], 0 ; GFX11-NEXT: s_mov_b64 s[2:3], 0
; GFX11-NEXT: s_add_i32 s4, s4, s6 ; GFX11-NEXT: s_add_i32 s8, s4, s5
; GFX11-NEXT: s_mov_b64 s[6:7], 0 ; GFX11-NEXT: s_mov_b64 s[4:5], 0
; GFX11-NEXT: .p2align 6 ; GFX11-NEXT: .p2align 6
; GFX11-NEXT: .LBB0_1: ; %bb3 ; GFX11-NEXT: .LBB0_1: ; %bb3
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_not_b32 s10, s7 ; GFX11-NEXT: s_not_b32 s10, s5
; GFX11-NEXT: s_mul_i32 s9, s5, s7 ; GFX11-NEXT: s_mul_i32 s9, s6, s5
; GFX11-NEXT: s_mul_i32 s10, s5, s10 ; GFX11-NEXT: s_mul_i32 s10, s6, s10
; GFX11-NEXT: s_sub_i32 s9, s8, s9 ; GFX11-NEXT: s_sub_i32 s9, s7, s9
; GFX11-NEXT: s_add_i32 s11, s7, 1 ; GFX11-NEXT: s_add_i32 s11, s5, 1
; GFX11-NEXT: s_add_i32 s10, s8, s10 ; GFX11-NEXT: s_add_i32 s10, s7, s10
; GFX11-NEXT: s_cmp_ge_u32 s9, s5 ; GFX11-NEXT: s_cmp_ge_u32 s9, s6
; GFX11-NEXT: s_cselect_b32 s11, s11, s7 ; GFX11-NEXT: s_cselect_b32 s11, s11, s5
; GFX11-NEXT: s_cselect_b32 s9, s10, s9 ; GFX11-NEXT: s_cselect_b32 s9, s10, s9
; GFX11-NEXT: s_add_i32 s10, s11, 1 ; GFX11-NEXT: s_add_i32 s10, s11, 1
; GFX11-NEXT: s_cmp_ge_u32 s9, s5 ; GFX11-NEXT: s_cmp_ge_u32 s9, s6
; GFX11-NEXT: s_cselect_b32 s9, s10, s11 ; GFX11-NEXT: s_cselect_b32 s9, s10, s11
; GFX11-NEXT: s_add_u32 s10, s0, s2 ; GFX11-NEXT: s_add_u32 s10, s0, s2
; GFX11-NEXT: s_addc_u32 s11, s1, s3 ; GFX11-NEXT: s_addc_u32 s11, s1, s3
; GFX11-NEXT: s_add_i32 s8, s8, 1 ; GFX11-NEXT: s_add_i32 s7, s7, 1
; GFX11-NEXT: s_add_u32 s6, s6, s4 ; GFX11-NEXT: s_add_u32 s4, s4, s8
; GFX11-NEXT: v_mov_b32_e32 v1, s9 ; GFX11-NEXT: v_mov_b32_e32 v1, s9
; GFX11-NEXT: s_addc_u32 s7, s7, 0 ; GFX11-NEXT: s_addc_u32 s5, s5, 0
; GFX11-NEXT: s_add_u32 s2, s2, 4 ; GFX11-NEXT: s_add_u32 s2, s2, 4
; GFX11-NEXT: s_addc_u32 s3, s3, 0 ; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_cmpk_eq_i32 s2, 0x1000 ; GFX11-NEXT: s_cmpk_eq_i32 s2, 0x1000
; GFX11-NEXT: global_store_b32 v0, v1, s[10:11] ; GFX11-NEXT: global_store_b32 v0, v1, s[10:11]
; GFX11-NEXT: s_cbranch_scc0 .LBB0_1 ; GFX11-NEXT: s_cbranch_scc0 .LBB0_1
; GFX11-NEXT: ; %bb.2: ; %bb2 ; GFX11-NEXT: ; %bb.2: ; %bb2
; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_nop 0
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
Show All 13 Linesbb3: ; preds = %bb3, %bb
%tmp7 = add nuw nsw i32 %tmp, 1 %tmp7 = add nuw nsw i32 %tmp, 1
%tmp8 = icmp eq i32 %tmp7, 1024 %tmp8 = icmp eq i32 %tmp7, 1024
br i1 %tmp8, label %bb2, label %bb3 br i1 %tmp8, label %bb2, label %bb3
} }
define amdgpu_kernel void @urem32_invariant_denom(ptr addrspace(1) nocapture %arg, i32 %arg1) { define amdgpu_kernel void @urem32_invariant_denom(ptr addrspace(1) nocapture %arg, i32 %arg1) {
; GFX9-LABEL: urem32_invariant_denom: ; GFX9-LABEL: urem32_invariant_denom:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_load_dword s5, s[0:1], 0x2c ; GFX9-NEXT: s_load_dword s6, s[0:1], 0x2c
; GFX9-NEXT: s_mov_b32 s8, 0 ; GFX9-NEXT: s_mov_b32 s7, 0
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: s_mov_b64 s[2:3], 0 ; GFX9-NEXT: s_mov_b64 s[2:3], 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s5 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s6
; GFX9-NEXT: s_sub_i32 s4, 0, s5 ; GFX9-NEXT: s_sub_i32 s4, 0, s6
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v0
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_readfirstlane_b32 s6, v1 ; GFX9-NEXT: v_readfirstlane_b32 s5, v1
; GFX9-NEXT: s_mul_i32 s4, s4, s6 ; GFX9-NEXT: s_mul_i32 s4, s4, s5
; GFX9-NEXT: s_mul_hi_u32 s4, s6, s4 ; GFX9-NEXT: s_mul_hi_u32 s4, s5, s4
; GFX9-NEXT: s_add_i32 s4, s6, s4 ; GFX9-NEXT: s_add_i32 s8, s5, s4
; GFX9-NEXT: s_mov_b64 s[6:7], 0 ; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: .LBB1_1: ; %bb3 ; GFX9-NEXT: .LBB1_1: ; %bb3
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_not_b32 s10, s7 ; GFX9-NEXT: s_not_b32 s10, s5
; GFX9-NEXT: s_mul_i32 s9, s5, s7 ; GFX9-NEXT: s_mul_i32 s9, s6, s5
; GFX9-NEXT: s_mul_i32 s10, s5, s10 ; GFX9-NEXT: s_mul_i32 s10, s6, s10
; GFX9-NEXT: s_sub_i32 s9, s8, s9 ; GFX9-NEXT: s_sub_i32 s9, s7, s9
; GFX9-NEXT: s_add_i32 s10, s8, s10 ; GFX9-NEXT: s_add_i32 s10, s7, s10
; GFX9-NEXT: s_cmp_ge_u32 s9, s5 ; GFX9-NEXT: s_cmp_ge_u32 s9, s6
; GFX9-NEXT: s_cselect_b32 s9, s10, s9 ; GFX9-NEXT: s_cselect_b32 s9, s10, s9
; GFX9-NEXT: s_sub_i32 s10, s9, s5 ; GFX9-NEXT: s_sub_i32 s10, s9, s6
; GFX9-NEXT: s_cmp_ge_u32 s9, s5 ; GFX9-NEXT: s_cmp_ge_u32 s9, s6
; GFX9-NEXT: s_cselect_b32 s9, s10, s9 ; GFX9-NEXT: s_cselect_b32 s9, s10, s9
; GFX9-NEXT: s_add_u32 s10, s0, s2 ; GFX9-NEXT: s_add_u32 s10, s0, s2
; GFX9-NEXT: s_addc_u32 s11, s1, s3 ; GFX9-NEXT: s_addc_u32 s11, s1, s3
; GFX9-NEXT: s_add_i32 s8, s8, 1 ; GFX9-NEXT: s_add_i32 s7, s7, 1
; GFX9-NEXT: s_add_u32 s6, s6, s4 ; GFX9-NEXT: s_add_u32 s4, s4, s8
; GFX9-NEXT: s_addc_u32 s7, s7, 0 ; GFX9-NEXT: s_addc_u32 s5, s5, 0
; GFX9-NEXT: s_add_u32 s2, s2, 4 ; GFX9-NEXT: s_add_u32 s2, s2, 4
; GFX9-NEXT: s_addc_u32 s3, s3, 0 ; GFX9-NEXT: s_addc_u32 s3, s3, 0
; GFX9-NEXT: v_mov_b32_e32 v1, s9 ; GFX9-NEXT: v_mov_b32_e32 v1, s9
; GFX9-NEXT: s_cmpk_eq_i32 s2, 0x1000 ; GFX9-NEXT: s_cmpk_eq_i32 s2, 0x1000
; GFX9-NEXT: global_store_dword v0, v1, s[10:11] ; GFX9-NEXT: global_store_dword v0, v1, s[10:11]
; GFX9-NEXT: s_cbranch_scc0 .LBB1_1 ; GFX9-NEXT: s_cbranch_scc0 .LBB1_1
; GFX9-NEXT: ; %bb.2: ; %bb2 ; GFX9-NEXT: ; %bb.2: ; %bb2
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: urem32_invariant_denom: ; GFX10-LABEL: urem32_invariant_denom:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_load_dword s5, s[0:1], 0x2c ; GFX10-NEXT: s_load_dword s6, s[0:1], 0x2c
; GFX10-NEXT: s_mov_b32 s8, 0 ; GFX10-NEXT: s_mov_b32 s7, 0
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s5 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s6
; GFX10-NEXT: s_sub_i32 s2, 0, s5 ; GFX10-NEXT: s_sub_i32 s2, 0, s6
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: v_readfirstlane_b32 s4, v0 ; GFX10-NEXT: v_readfirstlane_b32 s4, v0
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_mul_i32 s2, s2, s4 ; GFX10-NEXT: s_mul_i32 s2, s2, s4
; GFX10-NEXT: s_mul_hi_u32 s6, s4, s2 ; GFX10-NEXT: s_mul_hi_u32 s5, s4, s2
; GFX10-NEXT: s_mov_b64 s[2:3], 0 ; GFX10-NEXT: s_mov_b64 s[2:3], 0
; GFX10-NEXT: s_add_i32 s4, s4, s6 ; GFX10-NEXT: s_add_i32 s8, s4, s5
; GFX10-NEXT: s_mov_b64 s[6:7], 0 ; GFX10-NEXT: s_mov_b64 s[4:5], 0
; GFX10-NEXT: .LBB1_1: ; %bb3 ; GFX10-NEXT: .LBB1_1: ; %bb3
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: s_not_b32 s9, s7 ; GFX10-NEXT: s_not_b32 s9, s5
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mul_i32 s10, s5, s7 ; GFX10-NEXT: s_mul_i32 s10, s6, s5
; GFX10-NEXT: s_mul_i32 s9, s5, s9 ; GFX10-NEXT: s_mul_i32 s9, s6, s9
; GFX10-NEXT: s_sub_i32 s10, s8, s10 ; GFX10-NEXT: s_sub_i32 s10, s7, s10
; GFX10-NEXT: s_add_i32 s9, s8, s9 ; GFX10-NEXT: s_add_i32 s9, s7, s9
; GFX10-NEXT: s_cmp_ge_u32 s10, s5 ; GFX10-NEXT: s_cmp_ge_u32 s10, s6
; GFX10-NEXT: s_cselect_b32 s9, s9, s10 ; GFX10-NEXT: s_cselect_b32 s9, s9, s10
; GFX10-NEXT: s_sub_i32 s10, s9, s5 ; GFX10-NEXT: s_sub_i32 s10, s9, s6
; GFX10-NEXT: s_cmp_ge_u32 s9, s5 ; GFX10-NEXT: s_cmp_ge_u32 s9, s6
; GFX10-NEXT: s_cselect_b32 s9, s10, s9 ; GFX10-NEXT: s_cselect_b32 s9, s10, s9
; GFX10-NEXT: s_add_u32 s10, s0, s2 ; GFX10-NEXT: s_add_u32 s10, s0, s2
; GFX10-NEXT: s_addc_u32 s11, s1, s3 ; GFX10-NEXT: s_addc_u32 s11, s1, s3
; GFX10-NEXT: s_add_i32 s8, s8, 1 ; GFX10-NEXT: s_add_i32 s7, s7, 1
; GFX10-NEXT: s_add_u32 s6, s6, s4 ; GFX10-NEXT: s_add_u32 s4, s4, s8
; GFX10-NEXT: v_mov_b32_e32 v1, s9 ; GFX10-NEXT: v_mov_b32_e32 v1, s9
; GFX10-NEXT: s_addc_u32 s7, s7, 0 ; GFX10-NEXT: s_addc_u32 s5, s5, 0
; GFX10-NEXT: s_add_u32 s2, s2, 4 ; GFX10-NEXT: s_add_u32 s2, s2, 4
; GFX10-NEXT: s_addc_u32 s3, s3, 0 ; GFX10-NEXT: s_addc_u32 s3, s3, 0
; GFX10-NEXT: s_cmpk_eq_i32 s2, 0x1000 ; GFX10-NEXT: s_cmpk_eq_i32 s2, 0x1000
; GFX10-NEXT: global_store_dword v0, v1, s[10:11] ; GFX10-NEXT: global_store_dword v0, v1, s[10:11]
; GFX10-NEXT: s_cbranch_scc0 .LBB1_1 ; GFX10-NEXT: s_cbranch_scc0 .LBB1_1
; GFX10-NEXT: ; %bb.2: ; %bb2 ; GFX10-NEXT: ; %bb.2: ; %bb2
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: urem32_invariant_denom: ; GFX11-LABEL: urem32_invariant_denom:
; GFX11: ; %bb.0: ; %bb ; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b32 s5, s[0:1], 0x2c ; GFX11-NEXT: s_load_b32 s6, s[0:1], 0x2c
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
; GFX11-NEXT: s_mov_b32 s8, 0 ; GFX11-NEXT: s_mov_b32 s7, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s5 ; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s6
; GFX11-NEXT: s_sub_i32 s2, 0, s5 ; GFX11-NEXT: s_sub_i32 s2, 0, s6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr 0xfff ; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_readfirstlane_b32 s4, v0 ; GFX11-NEXT: v_readfirstlane_b32 s4, v0
; GFX11-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-NEXT: v_mov_b32_e32 v0, 0
; GFX11-NEXT: s_mul_i32 s2, s2, s4 ; GFX11-NEXT: s_mul_i32 s2, s2, s4
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_mul_hi_u32 s6, s4, s2 ; GFX11-NEXT: s_mul_hi_u32 s5, s4, s2
; GFX11-NEXT: s_mov_b64 s[2:3], 0 ; GFX11-NEXT: s_mov_b64 s[2:3], 0
; GFX11-NEXT: s_add_i32 s4, s4, s6 ; GFX11-NEXT: s_add_i32 s8, s4, s5
; GFX11-NEXT: s_mov_b64 s[6:7], 0 ; GFX11-NEXT: s_mov_b64 s[4:5], 0
; GFX11-NEXT: .p2align 6 ; GFX11-NEXT: .p2align 6
; GFX11-NEXT: .LBB1_1: ; %bb3 ; GFX11-NEXT: .LBB1_1: ; %bb3
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_not_b32 s9, s7 ; GFX11-NEXT: s_not_b32 s9, s5
; GFX11-NEXT: s_mul_i32 s10, s5, s7 ; GFX11-NEXT: s_mul_i32 s10, s6, s5
; GFX11-NEXT: s_mul_i32 s9, s5, s9 ; GFX11-NEXT: s_mul_i32 s9, s6, s9
; GFX11-NEXT: s_sub_i32 s10, s8, s10 ; GFX11-NEXT: s_sub_i32 s10, s7, s10
; GFX11-NEXT: s_add_i32 s9, s8, s9 ; GFX11-NEXT: s_add_i32 s9, s7, s9
; GFX11-NEXT: s_cmp_ge_u32 s10, s5 ; GFX11-NEXT: s_cmp_ge_u32 s10, s6
; GFX11-NEXT: s_cselect_b32 s9, s9, s10 ; GFX11-NEXT: s_cselect_b32 s9, s9, s10
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_sub_i32 s10, s9, s5 ; GFX11-NEXT: s_sub_i32 s10, s9, s6
; GFX11-NEXT: s_cmp_ge_u32 s9, s5 ; GFX11-NEXT: s_cmp_ge_u32 s9, s6
; GFX11-NEXT: s_cselect_b32 s9, s10, s9 ; GFX11-NEXT: s_cselect_b32 s9, s10, s9
; GFX11-NEXT: s_add_u32 s10, s0, s2 ; GFX11-NEXT: s_add_u32 s10, s0, s2
; GFX11-NEXT: s_addc_u32 s11, s1, s3 ; GFX11-NEXT: s_addc_u32 s11, s1, s3
; GFX11-NEXT: s_add_i32 s8, s8, 1 ; GFX11-NEXT: s_add_i32 s7, s7, 1
; GFX11-NEXT: s_add_u32 s6, s6, s4 ; GFX11-NEXT: s_add_u32 s4, s4, s8
; GFX11-NEXT: v_mov_b32_e32 v1, s9 ; GFX11-NEXT: v_mov_b32_e32 v1, s9
; GFX11-NEXT: s_addc_u32 s7, s7, 0 ; GFX11-NEXT: s_addc_u32 s5, s5, 0
; GFX11-NEXT: s_add_u32 s2, s2, 4 ; GFX11-NEXT: s_add_u32 s2, s2, 4
; GFX11-NEXT: s_addc_u32 s3, s3, 0 ; GFX11-NEXT: s_addc_u32 s3, s3, 0
; GFX11-NEXT: s_cmpk_eq_i32 s2, 0x1000 ; GFX11-NEXT: s_cmpk_eq_i32 s2, 0x1000
; GFX11-NEXT: global_store_b32 v0, v1, s[10:11] ; GFX11-NEXT: global_store_b32 v0, v1, s[10:11]
; GFX11-NEXT: s_cbranch_scc0 .LBB1_1 ; GFX11-NEXT: s_cbranch_scc0 .LBB1_1
; GFX11-NEXT: ; %bb.2: ; %bb2 ; GFX11-NEXT: ; %bb.2: ; %bb2
; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_nop 0
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
Show All 13 Linesbb3: ; preds = %bb3, %bb
%tmp7 = add nuw nsw i32 %tmp, 1 %tmp7 = add nuw nsw i32 %tmp, 1
%tmp8 = icmp eq i32 %tmp7, 1024 %tmp8 = icmp eq i32 %tmp7, 1024
br i1 %tmp8, label %bb2, label %bb3 br i1 %tmp8, label %bb2, label %bb3
} }
define amdgpu_kernel void @sdiv32_invariant_denom(ptr addrspace(1) nocapture %arg, i32 %arg1) { define amdgpu_kernel void @sdiv32_invariant_denom(ptr addrspace(1) nocapture %arg, i32 %arg1) {
; GFX9-LABEL: sdiv32_invariant_denom: ; GFX9-LABEL: sdiv32_invariant_denom:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c ; GFX9-NEXT: s_load_dword s3, s[0:1], 0x2c
; GFX9-NEXT: s_mov_b32 s5, 0 ; GFX9-NEXT: s_mov_b32 s4, 0
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_ashr_i32 s3, s2, 31 ; GFX9-NEXT: s_ashr_i32 s2, s3, 31
; GFX9-NEXT: s_add_i32 s2, s2, s3 ; GFX9-NEXT: s_add_i32 s3, s3, s2
; GFX9-NEXT: s_xor_b32 s4, s2, s3 ; GFX9-NEXT: s_xor_b32 s3, s3, s2
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s4 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s3
; GFX9-NEXT: s_sub_i32 s2, 0, s4 ; GFX9-NEXT: s_sub_i32 s5, 0, s3
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_readfirstlane_b32 s6, v0 ; GFX9-NEXT: v_readfirstlane_b32 s6, v0
; GFX9-NEXT: s_mul_i32 s2, s2, s6 ; GFX9-NEXT: s_mul_i32 s5, s5, s6
; GFX9-NEXT: s_mul_hi_u32 s2, s6, s2 ; GFX9-NEXT: s_mul_hi_u32 s5, s6, s5
; GFX9-NEXT: s_add_i32 s2, s6, s2 ; GFX9-NEXT: s_add_i32 s5, s6, s5
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: .LBB2_1: ; %bb3 ; GFX9-NEXT: .LBB2_1: ; %bb3
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_mul_hi_u32 s6, s5, s2 ; GFX9-NEXT: s_mul_hi_u32 s6, s4, s5
; GFX9-NEXT: s_mul_i32 s7, s6, s4 ; GFX9-NEXT: s_mul_i32 s7, s6, s3
; GFX9-NEXT: s_sub_i32 s7, s5, s7 ; GFX9-NEXT: s_sub_i32 s7, s4, s7
; GFX9-NEXT: s_add_i32 s8, s6, 1 ; GFX9-NEXT: s_add_i32 s8, s6, 1
; GFX9-NEXT: s_sub_i32 s9, s7, s4 ; GFX9-NEXT: s_sub_i32 s9, s7, s3
; GFX9-NEXT: s_cmp_ge_u32 s7, s4 ; GFX9-NEXT: s_cmp_ge_u32 s7, s3
; GFX9-NEXT: s_cselect_b32 s6, s8, s6 ; GFX9-NEXT: s_cselect_b32 s6, s8, s6
; GFX9-NEXT: s_cselect_b32 s7, s9, s7 ; GFX9-NEXT: s_cselect_b32 s7, s9, s7
; GFX9-NEXT: s_add_i32 s8, s6, 1 ; GFX9-NEXT: s_add_i32 s8, s6, 1
; GFX9-NEXT: s_cmp_ge_u32 s7, s4 ; GFX9-NEXT: s_cmp_ge_u32 s7, s3
; GFX9-NEXT: s_cselect_b32 s6, s8, s6 ; GFX9-NEXT: s_cselect_b32 s6, s8, s6
; GFX9-NEXT: s_xor_b32 s6, s6, s3 ; GFX9-NEXT: s_xor_b32 s6, s6, s2
; GFX9-NEXT: s_sub_i32 s6, s6, s3 ; GFX9-NEXT: s_sub_i32 s6, s6, s2
; GFX9-NEXT: s_add_i32 s5, s5, 1 ; GFX9-NEXT: s_add_i32 s4, s4, 1
; GFX9-NEXT: v_mov_b32_e32 v1, s6 ; GFX9-NEXT: v_mov_b32_e32 v1, s6
; GFX9-NEXT: global_store_dword v0, v1, s[0:1] ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9-NEXT: s_add_u32 s0, s0, 4 ; GFX9-NEXT: s_add_u32 s0, s0, 4
; GFX9-NEXT: s_addc_u32 s1, s1, 0 ; GFX9-NEXT: s_addc_u32 s1, s1, 0
; GFX9-NEXT: s_cmpk_eq_i32 s5, 0x400 ; GFX9-NEXT: s_cmpk_eq_i32 s4, 0x400
; GFX9-NEXT: s_cbranch_scc0 .LBB2_1 ; GFX9-NEXT: s_cbranch_scc0 .LBB2_1
; GFX9-NEXT: ; %bb.2: ; %bb2 ; GFX9-NEXT: ; %bb.2: ; %bb2
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: sdiv32_invariant_denom: ; GFX10-LABEL: sdiv32_invariant_denom:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_load_dword s2, s[0:1], 0x2c ; GFX10-NEXT: s_load_dword s3, s[0:1], 0x2c
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_ashr_i32 s3, s2, 31 ; GFX10-NEXT: s_ashr_i32 s2, s3, 31
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX10-NEXT: s_add_i32 s2, s2, s3 ; GFX10-NEXT: s_add_i32 s3, s3, s2
; GFX10-NEXT: s_xor_b32 s4, s2, s3 ; GFX10-NEXT: s_xor_b32 s3, s3, s2
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s4 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s3
; GFX10-NEXT: s_sub_i32 s5, 0, s4 ; GFX10-NEXT: s_sub_i32 s4, 0, s3
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: v_readfirstlane_b32 s2, v0 ; GFX10-NEXT: v_readfirstlane_b32 s5, v0
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_mul_i32 s5, s5, s2 ; GFX10-NEXT: s_mul_i32 s4, s4, s5
; GFX10-NEXT: s_mul_hi_u32 s6, s2, s5 ; GFX10-NEXT: s_mul_hi_u32 s6, s5, s4
; GFX10-NEXT: s_mov_b32 s5, 0 ; GFX10-NEXT: s_mov_b32 s4, 0
; GFX10-NEXT: s_add_i32 s2, s2, s6 ; GFX10-NEXT: s_add_i32 s5, s5, s6
; GFX10-NEXT: .LBB2_1: ; %bb3 ; GFX10-NEXT: .LBB2_1: ; %bb3
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: s_mul_hi_u32 s6, s5, s2 ; GFX10-NEXT: s_mul_hi_u32 s6, s4, s5
; GFX10-NEXT: s_mul_i32 s7, s6, s4 ; GFX10-NEXT: s_mul_i32 s7, s6, s3
; GFX10-NEXT: s_add_i32 s8, s6, 1 ; GFX10-NEXT: s_add_i32 s8, s6, 1
; GFX10-NEXT: s_sub_i32 s7, s5, s7 ; GFX10-NEXT: s_sub_i32 s7, s4, s7
; GFX10-NEXT: s_sub_i32 s9, s7, s4 ; GFX10-NEXT: s_sub_i32 s9, s7, s3
; GFX10-NEXT: s_cmp_ge_u32 s7, s4 ; GFX10-NEXT: s_cmp_ge_u32 s7, s3
; GFX10-NEXT: s_cselect_b32 s6, s8, s6 ; GFX10-NEXT: s_cselect_b32 s6, s8, s6
; GFX10-NEXT: s_cselect_b32 s7, s9, s7 ; GFX10-NEXT: s_cselect_b32 s7, s9, s7
; GFX10-NEXT: s_add_i32 s8, s6, 1 ; GFX10-NEXT: s_add_i32 s8, s6, 1
; GFX10-NEXT: s_cmp_ge_u32 s7, s4 ; GFX10-NEXT: s_cmp_ge_u32 s7, s3
; GFX10-NEXT: s_cselect_b32 s6, s8, s6 ; GFX10-NEXT: s_cselect_b32 s6, s8, s6
; GFX10-NEXT: s_add_i32 s5, s5, 1 ; GFX10-NEXT: s_add_i32 s4, s4, 1
; GFX10-NEXT: s_xor_b32 s6, s6, s3 ; GFX10-NEXT: s_xor_b32 s6, s6, s2
; GFX10-NEXT: s_sub_i32 s6, s6, s3 ; GFX10-NEXT: s_sub_i32 s6, s6, s2
; GFX10-NEXT: v_mov_b32_e32 v1, s6 ; GFX10-NEXT: v_mov_b32_e32 v1, s6
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_store_dword v0, v1, s[0:1] ; GFX10-NEXT: global_store_dword v0, v1, s[0:1]
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_add_u32 s0, s0, 4 ; GFX10-NEXT: s_add_u32 s0, s0, 4
; GFX10-NEXT: s_addc_u32 s1, s1, 0 ; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_cmpk_eq_i32 s5, 0x400 ; GFX10-NEXT: s_cmpk_eq_i32 s4, 0x400
; GFX10-NEXT: s_cbranch_scc0 .LBB2_1 ; GFX10-NEXT: s_cbranch_scc0 .LBB2_1
; GFX10-NEXT: ; %bb.2: ; %bb2 ; GFX10-NEXT: ; %bb.2: ; %bb2
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: sdiv32_invariant_denom: ; GFX11-LABEL: sdiv32_invariant_denom:
; GFX11: ; %bb.0: ; %bb ; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c ; GFX11-NEXT: s_load_b32 s3, s[0:1], 0x2c
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_ashr_i32 s3, s2, 31 ; GFX11-NEXT: s_ashr_i32 s2, s3, 31
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, s3 ; GFX11-NEXT: s_add_i32 s3, s3, s2
; GFX11-NEXT: s_xor_b32 s4, s2, s3 ; GFX11-NEXT: s_xor_b32 s3, s3, s2
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s4 ; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s3
; GFX11-NEXT: s_sub_i32 s5, 0, s4 ; GFX11-NEXT: s_sub_i32 s4, 0, s3
; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr 0xfff ; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-NEXT: v_readfirstlane_b32 s2, v0 ; GFX11-NEXT: v_readfirstlane_b32 s5, v0
; GFX11-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-NEXT: v_mov_b32_e32 v0, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_mul_i32 s5, s5, s2 ; GFX11-NEXT: s_mul_i32 s4, s4, s5
; GFX11-NEXT: s_mul_hi_u32 s6, s2, s5 ; GFX11-NEXT: s_mul_hi_u32 s6, s5, s4
; GFX11-NEXT: s_mov_b32 s5, 0 ; GFX11-NEXT: s_mov_b32 s4, 0
; GFX11-NEXT: s_add_i32 s2, s2, s6 ; GFX11-NEXT: s_add_i32 s5, s5, s6
; GFX11-NEXT: .p2align 6 ; GFX11-NEXT: .p2align 6
; GFX11-NEXT: .LBB2_1: ; %bb3 ; GFX11-NEXT: .LBB2_1: ; %bb3
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_mul_hi_u32 s6, s5, s2 ; GFX11-NEXT: s_mul_hi_u32 s6, s4, s5
; GFX11-NEXT: s_mul_i32 s7, s6, s4 ; GFX11-NEXT: s_mul_i32 s7, s6, s3
; GFX11-NEXT: s_add_i32 s8, s6, 1 ; GFX11-NEXT: s_add_i32 s8, s6, 1
; GFX11-NEXT: s_sub_i32 s7, s5, s7 ; GFX11-NEXT: s_sub_i32 s7, s4, s7
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_sub_i32 s9, s7, s4 ; GFX11-NEXT: s_sub_i32 s9, s7, s3
; GFX11-NEXT: s_cmp_ge_u32 s7, s4 ; GFX11-NEXT: s_cmp_ge_u32 s7, s3
; GFX11-NEXT: s_cselect_b32 s6, s8, s6 ; GFX11-NEXT: s_cselect_b32 s6, s8, s6
; GFX11-NEXT: s_cselect_b32 s7, s9, s7 ; GFX11-NEXT: s_cselect_b32 s7, s9, s7
; GFX11-NEXT: s_add_i32 s8, s6, 1 ; GFX11-NEXT: s_add_i32 s8, s6, 1
; GFX11-NEXT: s_cmp_ge_u32 s7, s4 ; GFX11-NEXT: s_cmp_ge_u32 s7, s3
; GFX11-NEXT: s_cselect_b32 s6, s8, s6 ; GFX11-NEXT: s_cselect_b32 s6, s8, s6
; GFX11-NEXT: s_add_i32 s5, s5, 1 ; GFX11-NEXT: s_add_i32 s4, s4, 1
; GFX11-NEXT: s_xor_b32 s6, s6, s3 ; GFX11-NEXT: s_xor_b32 s6, s6, s2
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_sub_i32 s6, s6, s3 ; GFX11-NEXT: s_sub_i32 s6, s6, s2
; GFX11-NEXT: v_mov_b32_e32 v1, s6 ; GFX11-NEXT: v_mov_b32_e32 v1, s6
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-NEXT: s_add_u32 s0, s0, 4 ; GFX11-NEXT: s_add_u32 s0, s0, 4
; GFX11-NEXT: s_addc_u32 s1, s1, 0 ; GFX11-NEXT: s_addc_u32 s1, s1, 0
; GFX11-NEXT: s_cmpk_eq_i32 s5, 0x400 ; GFX11-NEXT: s_cmpk_eq_i32 s4, 0x400
; GFX11-NEXT: s_cbranch_scc0 .LBB2_1 ; GFX11-NEXT: s_cbranch_scc0 .LBB2_1
; GFX11-NEXT: ; %bb.2: ; %bb2 ; GFX11-NEXT: ; %bb.2: ; %bb2
; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_nop 0
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-NEXT: s_endpgm ; GFX11-NEXT: s_endpgm
bb: bb:
br label %bb3 br label %bb3
Show All 10 Linesbb3: ; preds = %bb3, %bb
%tmp8 = icmp eq i32 %tmp7, 1024 %tmp8 = icmp eq i32 %tmp7, 1024
br i1 %tmp8, label %bb2, label %bb3 br i1 %tmp8, label %bb2, label %bb3
} }
define amdgpu_kernel void @srem32_invariant_denom(ptr addrspace(1) nocapture %arg, i32 %arg1) { define amdgpu_kernel void @srem32_invariant_denom(ptr addrspace(1) nocapture %arg, i32 %arg1) {
; GFX9-LABEL: srem32_invariant_denom: ; GFX9-LABEL: srem32_invariant_denom:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c ; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c
; GFX9-NEXT: s_mov_b32 s4, 0
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_ashr_i32 s3, s2, 31 ; GFX9-NEXT: s_ashr_i32 s3, s2, 31
; GFX9-NEXT: s_add_i32 s2, s2, s3 ; GFX9-NEXT: s_add_i32 s2, s2, s3
; GFX9-NEXT: s_xor_b32 s3, s2, s3 ; GFX9-NEXT: s_xor_b32 s2, s2, s3
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s3 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX9-NEXT: s_sub_i32 s2, 0, s3 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX9-NEXT: s_sub_i32 s4, 0, s2
; GFX9-NEXT: s_mov_b32 s3, 0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: v_readfirstlane_b32 s5, v0 ; GFX9-NEXT: v_readfirstlane_b32 s5, v0
; GFX9-NEXT: s_mul_i32 s2, s2, s5 ; GFX9-NEXT: s_mul_i32 s4, s4, s5
; GFX9-NEXT: s_mul_hi_u32 s2, s5, s2 ; GFX9-NEXT: s_mul_hi_u32 s4, s5, s4
; GFX9-NEXT: s_add_i32 s2, s5, s2 ; GFX9-NEXT: s_add_i32 s4, s5, s4
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: .LBB3_1: ; %bb3 ; GFX9-NEXT: .LBB3_1: ; %bb3
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_mul_hi_u32 s5, s4, s2 ; GFX9-NEXT: s_mul_hi_u32 s5, s3, s4
; GFX9-NEXT: s_mul_i32 s5, s5, s3 ; GFX9-NEXT: s_mul_i32 s5, s5, s2
; GFX9-NEXT: s_sub_i32 s5, s4, s5 ; GFX9-NEXT: s_sub_i32 s5, s3, s5
; GFX9-NEXT: s_sub_i32 s6, s5, s3 ; GFX9-NEXT: s_sub_i32 s6, s5, s2
; GFX9-NEXT: s_cmp_ge_u32 s5, s3 ; GFX9-NEXT: s_cmp_ge_u32 s5, s2
; GFX9-NEXT: s_cselect_b32 s5, s6, s5 ; GFX9-NEXT: s_cselect_b32 s5, s6, s5
; GFX9-NEXT: s_sub_i32 s6, s5, s3 ; GFX9-NEXT: s_sub_i32 s6, s5, s2
; GFX9-NEXT: s_cmp_ge_u32 s5, s3 ; GFX9-NEXT: s_cmp_ge_u32 s5, s2
; GFX9-NEXT: s_cselect_b32 s5, s6, s5 ; GFX9-NEXT: s_cselect_b32 s5, s6, s5
; GFX9-NEXT: s_add_i32 s4, s4, 1 ; GFX9-NEXT: s_add_i32 s3, s3, 1
; GFX9-NEXT: v_mov_b32_e32 v1, s5 ; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dword v0, v1, s[0:1] ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9-NEXT: s_add_u32 s0, s0, 4 ; GFX9-NEXT: s_add_u32 s0, s0, 4
; GFX9-NEXT: s_addc_u32 s1, s1, 0 ; GFX9-NEXT: s_addc_u32 s1, s1, 0
; GFX9-NEXT: s_cmpk_eq_i32 s4, 0x400 ; GFX9-NEXT: s_cmpk_eq_i32 s3, 0x400
; GFX9-NEXT: s_cbranch_scc0 .LBB3_1 ; GFX9-NEXT: s_cbranch_scc0 .LBB3_1
; GFX9-NEXT: ; %bb.2: ; %bb2 ; GFX9-NEXT: ; %bb.2: ; %bb2
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: srem32_invariant_denom: ; GFX10-LABEL: srem32_invariant_denom:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_load_dword s2, s[0:1], 0x2c ; GFX10-NEXT: s_load_dword s2, s[0:1], 0x2c
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_ashr_i32 s3, s2, 31 ; GFX10-NEXT: s_ashr_i32 s3, s2, 31
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX10-NEXT: s_add_i32 s2, s2, s3 ; GFX10-NEXT: s_add_i32 s2, s2, s3
; GFX10-NEXT: s_xor_b32 s3, s2, s3 ; GFX10-NEXT: s_xor_b32 s2, s2, s3
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s3 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX10-NEXT: s_sub_i32 s4, 0, s3 ; GFX10-NEXT: s_sub_i32 s3, 0, s2
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: v_readfirstlane_b32 s2, v0 ; GFX10-NEXT: v_readfirstlane_b32 s4, v0
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_mul_i32 s4, s4, s2 ; GFX10-NEXT: s_mul_i32 s3, s3, s4
; GFX10-NEXT: s_mul_hi_u32 s5, s2, s4 ; GFX10-NEXT: s_mul_hi_u32 s5, s4, s3
; GFX10-NEXT: s_mov_b32 s4, 0 ; GFX10-NEXT: s_mov_b32 s3, 0
; GFX10-NEXT: s_add_i32 s2, s2, s5 ; GFX10-NEXT: s_add_i32 s4, s4, s5
; GFX10-NEXT: .LBB3_1: ; %bb3 ; GFX10-NEXT: .LBB3_1: ; %bb3
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: s_mul_hi_u32 s5, s4, s2 ; GFX10-NEXT: s_mul_hi_u32 s5, s3, s4
; GFX10-NEXT: s_mul_i32 s5, s5, s3 ; GFX10-NEXT: s_mul_i32 s5, s5, s2
; GFX10-NEXT: s_sub_i32 s5, s4, s5 ; GFX10-NEXT: s_sub_i32 s5, s3, s5
; GFX10-NEXT: s_sub_i32 s6, s5, s3 ; GFX10-NEXT: s_sub_i32 s6, s5, s2
; GFX10-NEXT: s_cmp_ge_u32 s5, s3 ; GFX10-NEXT: s_cmp_ge_u32 s5, s2
; GFX10-NEXT: s_cselect_b32 s5, s6, s5 ; GFX10-NEXT: s_cselect_b32 s5, s6, s5
; GFX10-NEXT: s_sub_i32 s6, s5, s3 ; GFX10-NEXT: s_sub_i32 s6, s5, s2
; GFX10-NEXT: s_cmp_ge_u32 s5, s3 ; GFX10-NEXT: s_cmp_ge_u32 s5, s2
; GFX10-NEXT: s_cselect_b32 s5, s6, s5 ; GFX10-NEXT: s_cselect_b32 s5, s6, s5
; GFX10-NEXT: s_add_i32 s4, s4, 1 ; GFX10-NEXT: s_add_i32 s3, s3, 1
; GFX10-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-NEXT: v_mov_b32_e32 v1, s5
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_store_dword v0, v1, s[0:1] ; GFX10-NEXT: global_store_dword v0, v1, s[0:1]
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_add_u32 s0, s0, 4 ; GFX10-NEXT: s_add_u32 s0, s0, 4
; GFX10-NEXT: s_addc_u32 s1, s1, 0 ; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_cmpk_eq_i32 s4, 0x400 ; GFX10-NEXT: s_cmpk_eq_i32 s3, 0x400
; GFX10-NEXT: s_cbranch_scc0 .LBB3_1 ; GFX10-NEXT: s_cbranch_scc0 .LBB3_1
; GFX10-NEXT: ; %bb.2: ; %bb2 ; GFX10-NEXT: ; %bb.2: ; %bb2
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: srem32_invariant_denom: ; GFX11-LABEL: srem32_invariant_denom:
; GFX11: ; %bb.0: ; %bb ; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_ashr_i32 s3, s2, 31 ; GFX11-NEXT: s_ashr_i32 s3, s2, 31
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_add_i32 s2, s2, s3 ; GFX11-NEXT: s_add_i32 s2, s2, s3
; GFX11-NEXT: s_xor_b32 s3, s2, s3 ; GFX11-NEXT: s_xor_b32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s3 ; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s2
; GFX11-NEXT: s_sub_i32 s4, 0, s3 ; GFX11-NEXT: s_sub_i32 s3, 0, s2
; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr 0xfff ; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-NEXT: v_readfirstlane_b32 s2, v0 ; GFX11-NEXT: v_readfirstlane_b32 s4, v0
; GFX11-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-NEXT: v_mov_b32_e32 v0, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_mul_i32 s4, s4, s2 ; GFX11-NEXT: s_mul_i32 s3, s3, s4
; GFX11-NEXT: s_mul_hi_u32 s5, s2, s4 ; GFX11-NEXT: s_mul_hi_u32 s5, s4, s3
; GFX11-NEXT: s_mov_b32 s4, 0 ; GFX11-NEXT: s_mov_b32 s3, 0
; GFX11-NEXT: s_add_i32 s2, s2, s5 ; GFX11-NEXT: s_add_i32 s4, s4, s5
; GFX11-NEXT: .p2align 6 ; GFX11-NEXT: .p2align 6
; GFX11-NEXT: .LBB3_1: ; %bb3 ; GFX11-NEXT: .LBB3_1: ; %bb3
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_mul_hi_u32 s5, s4, s2 ; GFX11-NEXT: s_mul_hi_u32 s5, s3, s4
; GFX11-NEXT: s_mul_i32 s5, s5, s3 ; GFX11-NEXT: s_mul_i32 s5, s5, s2
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_sub_i32 s5, s4, s5 ; GFX11-NEXT: s_sub_i32 s5, s3, s5
; GFX11-NEXT: s_sub_i32 s6, s5, s3 ; GFX11-NEXT: s_sub_i32 s6, s5, s2
; GFX11-NEXT: s_cmp_ge_u32 s5, s3 ; GFX11-NEXT: s_cmp_ge_u32 s5, s2
; GFX11-NEXT: s_cselect_b32 s5, s6, s5 ; GFX11-NEXT: s_cselect_b32 s5, s6, s5
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_sub_i32 s6, s5, s3 ; GFX11-NEXT: s_sub_i32 s6, s5, s2
; GFX11-NEXT: s_cmp_ge_u32 s5, s3 ; GFX11-NEXT: s_cmp_ge_u32 s5, s2
; GFX11-NEXT: s_cselect_b32 s5, s6, s5 ; GFX11-NEXT: s_cselect_b32 s5, s6, s5
; GFX11-NEXT: s_add_i32 s4, s4, 1 ; GFX11-NEXT: s_add_i32 s3, s3, 1
; GFX11-NEXT: v_mov_b32_e32 v1, s5 ; GFX11-NEXT: v_mov_b32_e32 v1, s5
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-NEXT: s_add_u32 s0, s0, 4 ; GFX11-NEXT: s_add_u32 s0, s0, 4
; GFX11-NEXT: s_addc_u32 s1, s1, 0 ; GFX11-NEXT: s_addc_u32 s1, s1, 0
; GFX11-NEXT: s_cmpk_eq_i32 s4, 0x400 ; GFX11-NEXT: s_cmpk_eq_i32 s3, 0x400
; GFX11-NEXT: s_cbranch_scc0 .LBB3_1 ; GFX11-NEXT: s_cbranch_scc0 .LBB3_1
; GFX11-NEXT: ; %bb.2: ; %bb2 ; GFX11-NEXT: ; %bb.2: ; %bb2
; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_nop 0
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-NEXT: s_endpgm ; GFX11-NEXT: s_endpgm
bb: bb:
br label %bb3 br label %bb3
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llvm/test/CodeGen/AMDGPU/llc-pipeline.ll

Show First 20 Lines • Show All 330 Lines • ▼ Show 20 Lines
; GCN-O1-NEXT: Eliminate PHI nodes for register allocation ; GCN-O1-NEXT: Eliminate PHI nodes for register allocation
; GCN-O1-NEXT: SI Lower control flow pseudo instructions ; GCN-O1-NEXT: SI Lower control flow pseudo instructions
; GCN-O1-NEXT: Two-Address instruction pass ; GCN-O1-NEXT: Two-Address instruction pass
; GCN-O1-NEXT: Slot index numbering ; GCN-O1-NEXT: Slot index numbering
; GCN-O1-NEXT: Live Interval Analysis ; GCN-O1-NEXT: Live Interval Analysis
; GCN-O1-NEXT: Machine Natural Loop Construction ; GCN-O1-NEXT: Machine Natural Loop Construction
; GCN-O1-NEXT: Register Coalescer ; GCN-O1-NEXT: Register Coalescer
; GCN-O1-NEXT: Rename Disconnected Subregister Components ; GCN-O1-NEXT: Rename Disconnected Subregister Components
; GCN-O1-NEXT: Rewrite Partial Register Uses
; GCN-O1-NEXT: Machine Instruction Scheduler ; GCN-O1-NEXT: Machine Instruction Scheduler
; GCN-O1-NEXT: MachinePostDominator Tree Construction ; GCN-O1-NEXT: MachinePostDominator Tree Construction
; GCN-O1-NEXT: SI Whole Quad Mode ; GCN-O1-NEXT: SI Whole Quad Mode
; GCN-O1-NEXT: Virtual Register Map ; GCN-O1-NEXT: Virtual Register Map
; GCN-O1-NEXT: Live Register Matrix ; GCN-O1-NEXT: Live Register Matrix
; GCN-O1-NEXT: SI Pre-allocate WWM Registers ; GCN-O1-NEXT: SI Pre-allocate WWM Registers
; GCN-O1-NEXT: SI optimize exec mask operations pre-RA ; GCN-O1-NEXT: SI optimize exec mask operations pre-RA
; GCN-O1-NEXT: AMDGPU Pre-RA Long Branch Reg ; GCN-O1-NEXT: AMDGPU Pre-RA Long Branch Reg
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; GCN-O1-OPTS-NEXT: Eliminate PHI nodes for register allocation ; GCN-O1-OPTS-NEXT: Eliminate PHI nodes for register allocation
; GCN-O1-OPTS-NEXT: SI Lower control flow pseudo instructions ; GCN-O1-OPTS-NEXT: SI Lower control flow pseudo instructions
; GCN-O1-OPTS-NEXT: Two-Address instruction pass ; GCN-O1-OPTS-NEXT: Two-Address instruction pass
; GCN-O1-OPTS-NEXT: Slot index numbering ; GCN-O1-OPTS-NEXT: Slot index numbering
; GCN-O1-OPTS-NEXT: Live Interval Analysis ; GCN-O1-OPTS-NEXT: Live Interval Analysis
; GCN-O1-OPTS-NEXT: Machine Natural Loop Construction ; GCN-O1-OPTS-NEXT: Machine Natural Loop Construction
; GCN-O1-OPTS-NEXT: Register Coalescer ; GCN-O1-OPTS-NEXT: Register Coalescer
; GCN-O1-OPTS-NEXT: Rename Disconnected Subregister Components ; GCN-O1-OPTS-NEXT: Rename Disconnected Subregister Components
; GCN-O1-OPTS-NEXT: Rewrite Partial Register Uses
; GCN-O1-OPTS-NEXT: AMDGPU Pre-RA optimizations ; GCN-O1-OPTS-NEXT: AMDGPU Pre-RA optimizations
; GCN-O1-OPTS-NEXT: Machine Instruction Scheduler ; GCN-O1-OPTS-NEXT: Machine Instruction Scheduler
; GCN-O1-OPTS-NEXT: MachinePostDominator Tree Construction ; GCN-O1-OPTS-NEXT: MachinePostDominator Tree Construction
; GCN-O1-OPTS-NEXT: SI Whole Quad Mode ; GCN-O1-OPTS-NEXT: SI Whole Quad Mode
; GCN-O1-OPTS-NEXT: Virtual Register Map ; GCN-O1-OPTS-NEXT: Virtual Register Map
; GCN-O1-OPTS-NEXT: Live Register Matrix ; GCN-O1-OPTS-NEXT: Live Register Matrix
; GCN-O1-OPTS-NEXT: SI Pre-allocate WWM Registers ; GCN-O1-OPTS-NEXT: SI Pre-allocate WWM Registers
; GCN-O1-OPTS-NEXT: SI optimize exec mask operations pre-RA ; GCN-O1-OPTS-NEXT: SI optimize exec mask operations pre-RA
▲ Show 20 Lines • Show All 286 Lines • ▼ Show 20 Lines
; GCN-O2-NEXT: Eliminate PHI nodes for register allocation ; GCN-O2-NEXT: Eliminate PHI nodes for register allocation
; GCN-O2-NEXT: SI Lower control flow pseudo instructions ; GCN-O2-NEXT: SI Lower control flow pseudo instructions
; GCN-O2-NEXT: Two-Address instruction pass ; GCN-O2-NEXT: Two-Address instruction pass
; GCN-O2-NEXT: Slot index numbering ; GCN-O2-NEXT: Slot index numbering
; GCN-O2-NEXT: Live Interval Analysis ; GCN-O2-NEXT: Live Interval Analysis
; GCN-O2-NEXT: Machine Natural Loop Construction ; GCN-O2-NEXT: Machine Natural Loop Construction
; GCN-O2-NEXT: Register Coalescer ; GCN-O2-NEXT: Register Coalescer
; GCN-O2-NEXT: Rename Disconnected Subregister Components ; GCN-O2-NEXT: Rename Disconnected Subregister Components
; GCN-O2-NEXT: Rewrite Partial Register Uses
; GCN-O2-NEXT: AMDGPU Pre-RA optimizations ; GCN-O2-NEXT: AMDGPU Pre-RA optimizations
; GCN-O2-NEXT: Machine Instruction Scheduler ; GCN-O2-NEXT: Machine Instruction Scheduler
; GCN-O2-NEXT: MachinePostDominator Tree Construction ; GCN-O2-NEXT: MachinePostDominator Tree Construction
; GCN-O2-NEXT: SI Whole Quad Mode ; GCN-O2-NEXT: SI Whole Quad Mode
; GCN-O2-NEXT: Virtual Register Map ; GCN-O2-NEXT: Virtual Register Map
; GCN-O2-NEXT: Live Register Matrix ; GCN-O2-NEXT: Live Register Matrix
; GCN-O2-NEXT: SI Pre-allocate WWM Registers ; GCN-O2-NEXT: SI Pre-allocate WWM Registers
; GCN-O2-NEXT: SI optimize exec mask operations pre-RA ; GCN-O2-NEXT: SI optimize exec mask operations pre-RA
▲ Show 20 Lines • Show All 299 Lines • ▼ Show 20 Lines
; GCN-O3-NEXT: Eliminate PHI nodes for register allocation ; GCN-O3-NEXT: Eliminate PHI nodes for register allocation
; GCN-O3-NEXT: SI Lower control flow pseudo instructions ; GCN-O3-NEXT: SI Lower control flow pseudo instructions
; GCN-O3-NEXT: Two-Address instruction pass ; GCN-O3-NEXT: Two-Address instruction pass
; GCN-O3-NEXT: Slot index numbering ; GCN-O3-NEXT: Slot index numbering
; GCN-O3-NEXT: Live Interval Analysis ; GCN-O3-NEXT: Live Interval Analysis
; GCN-O3-NEXT: Machine Natural Loop Construction ; GCN-O3-NEXT: Machine Natural Loop Construction
; GCN-O3-NEXT: Register Coalescer ; GCN-O3-NEXT: Register Coalescer
; GCN-O3-NEXT: Rename Disconnected Subregister Components ; GCN-O3-NEXT: Rename Disconnected Subregister Components
; GCN-O3-NEXT: Rewrite Partial Register Uses
; GCN-O3-NEXT: AMDGPU Pre-RA optimizations ; GCN-O3-NEXT: AMDGPU Pre-RA optimizations
; GCN-O3-NEXT: Machine Instruction Scheduler ; GCN-O3-NEXT: Machine Instruction Scheduler
; GCN-O3-NEXT: MachinePostDominator Tree Construction ; GCN-O3-NEXT: MachinePostDominator Tree Construction
; GCN-O3-NEXT: SI Whole Quad Mode ; GCN-O3-NEXT: SI Whole Quad Mode
; GCN-O3-NEXT: Virtual Register Map ; GCN-O3-NEXT: Virtual Register Map
; GCN-O3-NEXT: Live Register Matrix ; GCN-O3-NEXT: Live Register Matrix
; GCN-O3-NEXT: SI Pre-allocate WWM Registers ; GCN-O3-NEXT: SI Pre-allocate WWM Registers
; GCN-O3-NEXT: SI optimize exec mask operations pre-RA ; GCN-O3-NEXT: SI optimize exec mask operations pre-RA
▲ Show 20 Lines • Show All 80 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/llvm.mulo.ll

Show First 20 Lines • Show All 175 Lines • ▼ Show 20 Lines
; ;
; GFX10-LABEL: smulo_i64_v_v: ; GFX10-LABEL: smulo_i64_v_v:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v4, v0 ; GFX10-NEXT: v_mov_b32_e32 v4, v0
; GFX10-NEXT: v_mov_b32_e32 v5, v1 ; GFX10-NEXT: v_mov_b32_e32 v5, v1
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v4, v2, 0 ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s4, v4, v2, 0
; GFX10-NEXT: v_mad_u64_u32 v[6:7], s4, v4, v3, 0 ; GFX10-NEXT: v_mad_u64_u32 v[6:7], s4, v4, v3, 0
; GFX10-NEXT: v_mad_u64_u32 v[9:10], s4, v5, v2, 0 ; GFX10-NEXT: v_mad_u64_u32 v[8:9], s4, v5, v2, 0
; GFX10-NEXT: v_mad_i64_i32 v[11:12], s4, v5, v3, 0 ; GFX10-NEXT: v_mad_i64_i32 v[10:11], s4, v5, v3, 0
; GFX10-NEXT: v_mov_b32_e32 v8, v1 ; GFX10-NEXT: v_mov_b32_e32 v12, v1
; GFX10-NEXT: v_add3_u32 v1, v1, v6, v9 ; GFX10-NEXT: v_add3_u32 v1, v1, v6, v8
; GFX10-NEXT: v_add_co_u32 v8, vcc_lo, v8, v6 ; GFX10-NEXT: v_add_co_u32 v12, vcc_lo, v12, v6
; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
; GFX10-NEXT: v_add_co_u32 v8, vcc_lo, v8, v9 ; GFX10-NEXT: v_add_co_u32 v12, vcc_lo, v12, v8
; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, v7, v10, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0, v12, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0, v11, vcc_lo
; GFX10-NEXT: v_add_co_u32 v7, vcc_lo, v7, v11 ; GFX10-NEXT: v_add_co_u32 v7, vcc_lo, v7, v10
; GFX10-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, v7, v2 ; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, v7, v2
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v10, vcc_lo, 0, v8, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v10, vcc_lo, 0, v9, vcc_lo
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v5 ; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v5
; GFX10-NEXT: v_cndmask_b32_e32 v6, v7, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v6, v7, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc_lo
; GFX10-NEXT: v_ashrrev_i32_e32 v2, 31, v1 ; GFX10-NEXT: v_ashrrev_i32_e32 v2, 31, v1
; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v6, v4 ; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v6, v4
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, 0, v5, vcc_lo ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, 0, v5, vcc_lo
; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v3 ; GFX10-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v3
; GFX10-NEXT: v_mov_b32_e32 v3, v2 ; GFX10-NEXT: v_mov_b32_e32 v3, v2
; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc_lo
; GFX10-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[2:3] ; GFX10-NEXT: v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[2:3]
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: smulo_i64_v_v: ; GFX11-LABEL: smulo_i64_v_v:
; GFX11: ; %bb.0: ; %bb ; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_dual_mov_b32 v4, v0 :: v_dual_mov_b32 v5, v1 ; GFX11-NEXT: v_dual_mov_b32 v4, v0 :: v_dual_mov_b32 v5, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v4, v2, 0 ; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v4, v2, 0
; GFX11-NEXT: v_mad_u64_u32 v[6:7], null, v4, v3, 0 ; GFX11-NEXT: v_mad_u64_u32 v[6:7], null, v4, v3, 0
; GFX11-NEXT: v_mad_u64_u32 v[9:10], null, v5, v2, 0 ; GFX11-NEXT: v_mad_u64_u32 v[8:9], null, v5, v2, 0
; GFX11-NEXT: v_mad_i64_i32 v[11:12], null, v5, v3, 0 ; GFX11-NEXT: v_mad_i64_i32 v[10:11], null, v5, v3, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_mov_b32_e32 v8, v1 ; GFX11-NEXT: v_mov_b32_e32 v12, v1
; GFX11-NEXT: v_add3_u32 v1, v1, v6, v9 ; GFX11-NEXT: v_add3_u32 v1, v1, v6, v8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v8, v6 ; GFX11-NEXT: v_add_co_u32 v12, vcc_lo, v12, v6
; GFX11-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v8, v9 ; GFX11-NEXT: v_add_co_u32 v12, vcc_lo, v12, v8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, v7, v10, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo
; GFX11-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0, v12, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0, v11, vcc_lo
; GFX11-NEXT: v_add_co_u32 v7, vcc_lo, v7, v11 ; GFX11-NEXT: v_add_co_u32 v7, vcc_lo, v7, v10
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
; GFX11-NEXT: v_sub_co_u32 v2, vcc_lo, v7, v2 ; GFX11-NEXT: v_sub_co_u32 v2, vcc_lo, v7, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_subrev_co_ci_u32_e32 v10, vcc_lo, 0, v8, vcc_lo ; GFX11-NEXT: v_subrev_co_ci_u32_e32 v10, vcc_lo, 0, v9, vcc_lo
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v5 ; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v5
; GFX11-NEXT: v_cndmask_b32_e32 v6, v7, v2, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v6, v7, v2, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e32 v5, v9, v10, vcc_lo
; GFX11-NEXT: v_ashrrev_i32_e32 v2, 31, v1 ; GFX11-NEXT: v_ashrrev_i32_e32 v2, 31, v1
; GFX11-NEXT: v_sub_co_u32 v4, vcc_lo, v6, v4 ; GFX11-NEXT: v_sub_co_u32 v4, vcc_lo, v6, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, 0, v5, vcc_lo ; GFX11-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, 0, v5, vcc_lo
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v3 ; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v3
; GFX11-NEXT: v_mov_b32_e32 v3, v2 ; GFX11-NEXT: v_mov_b32_e32 v3, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_dual_cndmask_b32 v4, v6, v4 :: v_dual_cndmask_b32 v5, v5, v7 ; GFX11-NEXT: v_dual_cndmask_b32 v4, v6, v4 :: v_dual_cndmask_b32 v5, v5, v7
▲ Show 20 Lines • Show All 436 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/load-constant-i1.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 3,556 Lines • ▼ Show 20 Lines
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX8-LABEL: constant_sextload_i1_to_i64: ; GFX8-LABEL: constant_sextload_i1_to_i64:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: flat_load_ubyte v2, v[0:1]
; GFX8-NEXT: v_mov_b32_e32 v1, s0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v2, s1 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_bfe_i32 v3, v0, 0, 1 ; GFX8-NEXT: v_bfe_i32 v2, v2, 0, 1
; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v3 ; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX8-NEXT: flat_store_dwordx2 v[1:2], v[3:4] ; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; EG-LABEL: constant_sextload_i1_to_i64: ; EG-LABEL: constant_sextload_i1_to_i64:
; EG: ; %bb.0: ; EG: ; %bb.0:
; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6 ; EG-NEXT: TEX 0 @6
; EG-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX8-LABEL: constant_sextload_v1i1_to_v1i64: ; GFX8-LABEL: constant_sextload_v1i1_to_v1i64:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: flat_load_ubyte v0, v[0:1] ; GFX8-NEXT: flat_load_ubyte v2, v[0:1]
; GFX8-NEXT: v_mov_b32_e32 v1, s0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v2, s1 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_bfe_i32 v3, v0, 0, 1 ; GFX8-NEXT: v_bfe_i32 v2, v2, 0, 1
; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v3 ; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX8-NEXT: flat_store_dwordx2 v[1:2], v[3:4] ; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; EG-LABEL: constant_sextload_v1i1_to_v1i64: ; EG-LABEL: constant_sextload_v1i1_to_v1i64:
; EG: ; %bb.0: ; EG: ; %bb.0:
; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6 ; EG-NEXT: TEX 0 @6
; EG-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
▲ Show 20 Lines • Show All 1,053 Lines • ▼ Show 20 Lines
; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b32 s2, -1 ; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_mov_b32 s10, s2 ; GFX6-NEXT: s_mov_b32 s10, s2
; GFX6-NEXT: s_mov_b32 s11, s3 ; GFX6-NEXT: s_mov_b32 s11, s3
; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s8, s6 ; GFX6-NEXT: s_mov_b32 s8, s6
; GFX6-NEXT: s_mov_b32 s9, s7 ; GFX6-NEXT: s_mov_b32 s9, s7
; GFX6-NEXT: buffer_load_ushort v5, off, s[8:11], 0 ; GFX6-NEXT: buffer_load_ushort v1, off, s[8:11], 0
; GFX6-NEXT: s_mov_b32 s0, s4 ; GFX6-NEXT: s_mov_b32 s0, s4
; GFX6-NEXT: s_mov_b32 s1, s5 ; GFX6-NEXT: s_mov_b32 s1, s5
; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 14, v5 ; GFX6-NEXT: v_lshrrev_b32_e32 v3, 14, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 15, v5 ; GFX6-NEXT: v_lshrrev_b32_e32 v5, 15, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v7, 12, v5 ; GFX6-NEXT: v_lshrrev_b32_e32 v7, 12, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v9, 10, v5 ; GFX6-NEXT: v_lshrrev_b32_e32 v9, 13, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v11, 11, v5 ; GFX6-NEXT: v_lshrrev_b32_e32 v11, 10, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v12, 8, v5 ; GFX6-NEXT: v_lshrrev_b32_e32 v12, 8, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v13, 9, v5 ; GFX6-NEXT: v_lshrrev_b32_e32 v13, 9, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v8, 6, v5 ; GFX6-NEXT: v_lshrrev_b32_e32 v8, 6, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v10, 7, v5 ; GFX6-NEXT: v_lshrrev_b32_e32 v10, 7, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 4, v5 ; GFX6-NEXT: v_lshrrev_b32_e32 v4, 4, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v6, 5, v5 ; GFX6-NEXT: v_lshrrev_b32_e32 v6, 5, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v14, 2, v5 ; GFX6-NEXT: v_lshrrev_b32_e32 v0, 2, v1
; GFX6-NEXT: v_bfe_i32 v2, v1, 0, 1 ; GFX6-NEXT: v_lshrrev_b32_e32 v2, 3, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v16, 1, v1
; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 1
; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 1 ; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 1
; GFX6-NEXT: v_lshrrev_b32_e32 v15, 3, v5
; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 1, v5
; GFX6-NEXT: v_bfe_i32 v2, v15, 0, 1
; GFX6-NEXT: v_bfe_i32 v0, v14, 0, 1
; GFX6-NEXT: v_bfe_i32 v6, v6, 0, 1 ; GFX6-NEXT: v_bfe_i32 v6, v6, 0, 1
; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 1 ; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 1
; GFX6-NEXT: v_bfe_i32 v10, v10, 0, 1 ; GFX6-NEXT: v_bfe_i32 v10, v10, 0, 1
; GFX6-NEXT: v_bfe_i32 v8, v8, 0, 1 ; GFX6-NEXT: v_bfe_i32 v8, v8, 0, 1
; GFX6-NEXT: v_bfe_i32 v14, v13, 0, 1 ; GFX6-NEXT: v_bfe_i32 v14, v13, 0, 1
; GFX6-NEXT: v_bfe_i32 v12, v12, 0, 1 ; GFX6-NEXT: v_bfe_i32 v12, v12, 0, 1
; GFX6-NEXT: v_bfe_i32 v18, v11, 0, 1 ; GFX6-NEXT: v_bfe_i32 v17, v5, 0, 1
; GFX6-NEXT: v_bfe_i32 v16, v9, 0, 1 ; GFX6-NEXT: v_bfe_i32 v15, v3, 0, 1
; GFX6-NEXT: v_bfe_i32 v22, v1, 0, 1 ; GFX6-NEXT: v_bfe_i32 v21, v16, 0, 1
; GFX6-NEXT: v_bfe_i32 v20, v5, 0, 1 ; GFX6-NEXT: v_bfe_i32 v19, v1, 0, 1
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 13, v5 ; GFX6-NEXT: v_lshrrev_b32_e32 v1, 11, v1
; GFX6-NEXT: v_bfe_i32 v26, v1, 0, 1 ; GFX6-NEXT: v_ashrrev_i32_e32 v18, 31, v17
; GFX6-NEXT: v_bfe_i32 v24, v7, 0, 1 ; GFX6-NEXT: v_ashrrev_i32_e32 v16, 31, v15
; GFX6-NEXT: v_ashrrev_i32_e32 v21, 31, v20 ; GFX6-NEXT: buffer_store_dwordx4 v[15:18], off, s[0:3], 0 offset:112
; GFX6-NEXT: v_ashrrev_i32_e32 v23, 31, v22 ; GFX6-NEXT: v_bfe_i32 v25, v1, 0, 1
; GFX6-NEXT: v_bfe_i32 v23, v11, 0, 1
; GFX6-NEXT: v_bfe_i32 v29, v9, 0, 1
; GFX6-NEXT: v_bfe_i32 v27, v7, 0, 1
; GFX6-NEXT: v_ashrrev_i32_e32 v20, 31, v19
; GFX6-NEXT: v_ashrrev_i32_e32 v22, 31, v21
; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v2 ; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX6-NEXT: v_ashrrev_i32_e32 v7, 31, v6 ; GFX6-NEXT: v_ashrrev_i32_e32 v7, 31, v6
; GFX6-NEXT: v_ashrrev_i32_e32 v5, 31, v4 ; GFX6-NEXT: v_ashrrev_i32_e32 v5, 31, v4
; GFX6-NEXT: v_ashrrev_i32_e32 v11, 31, v10 ; GFX6-NEXT: v_ashrrev_i32_e32 v11, 31, v10
; GFX6-NEXT: v_ashrrev_i32_e32 v9, 31, v8 ; GFX6-NEXT: v_ashrrev_i32_e32 v9, 31, v8
; GFX6-NEXT: s_waitcnt expcnt(0)
; GFX6-NEXT: v_ashrrev_i32_e32 v15, 31, v14 ; GFX6-NEXT: v_ashrrev_i32_e32 v15, 31, v14
; GFX6-NEXT: v_ashrrev_i32_e32 v13, 31, v12 ; GFX6-NEXT: v_ashrrev_i32_e32 v13, 31, v12
; GFX6-NEXT: v_ashrrev_i32_e32 v19, 31, v18 ; GFX6-NEXT: v_ashrrev_i32_e32 v26, 31, v25
; GFX6-NEXT: v_ashrrev_i32_e32 v17, 31, v16 ; GFX6-NEXT: v_ashrrev_i32_e32 v24, 31, v23
; GFX6-NEXT: v_ashrrev_i32_e32 v27, 31, v26 ; GFX6-NEXT: v_ashrrev_i32_e32 v30, 31, v29
; GFX6-NEXT: v_ashrrev_i32_e32 v25, 31, v24 ; GFX6-NEXT: v_ashrrev_i32_e32 v28, 31, v27
; GFX6-NEXT: buffer_store_dwordx4 v[24:27], off, s[0:3], 0 offset:96 ; GFX6-NEXT: buffer_store_dwordx4 v[27:30], off, s[0:3], 0 offset:96
; GFX6-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:80 ; GFX6-NEXT: buffer_store_dwordx4 v[23:26], off, s[0:3], 0 offset:80
; GFX6-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:64 ; GFX6-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:64
; GFX6-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:48 ; GFX6-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:48
; GFX6-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:32 ; GFX6-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:32
; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16 ; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
; GFX6-NEXT: buffer_store_dwordx4 v[20:23], off, s[0:3], 0 ; GFX6-NEXT: buffer_store_dwordx4 v[19:22], off, s[0:3], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX8-LABEL: constant_sextload_v16i1_to_v16i64: ; GFX8-LABEL: constant_sextload_v16i1_to_v16i64:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: flat_load_ushort v0, v[0:1] ; GFX8-NEXT: flat_load_ushort v0, v[0:1]
; GFX8-NEXT: s_add_u32 s2, s0, 0x70 ; GFX8-NEXT: s_add_u32 s2, s0, 0x70
; GFX8-NEXT: s_addc_u32 s3, s1, 0 ; GFX8-NEXT: s_addc_u32 s3, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v6, s3 ; GFX8-NEXT: v_mov_b32_e32 v6, s3
; GFX8-NEXT: v_mov_b32_e32 v5, s2 ; GFX8-NEXT: v_mov_b32_e32 v5, s2
; GFX8-NEXT: s_add_u32 s2, s0, 0x60 ; GFX8-NEXT: s_add_u32 s2, s0, 0x60
; GFX8-NEXT: s_addc_u32 s3, s1, 0 ; GFX8-NEXT: s_addc_u32 s3, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v8, s3 ; GFX8-NEXT: v_mov_b32_e32 v8, s3
; GFX8-NEXT: v_mov_b32_e32 v7, s2 ; GFX8-NEXT: v_mov_b32_e32 v7, s2
; GFX8-NEXT: s_add_u32 s2, s0, 0x50 ; GFX8-NEXT: s_add_u32 s2, s0, 0x50
; GFX8-NEXT: s_addc_u32 s3, s1, 0 ; GFX8-NEXT: s_addc_u32 s3, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v10, s3 ; GFX8-NEXT: v_mov_b32_e32 v10, s3
; GFX8-NEXT: v_mov_b32_e32 v9, s2 ; GFX8-NEXT: v_mov_b32_e32 v9, s2
; GFX8-NEXT: s_add_u32 s2, s0, 64 ; GFX8-NEXT: s_add_u32 s2, s0, 64
; GFX8-NEXT: s_addc_u32 s3, s1, 0 ; GFX8-NEXT: s_addc_u32 s3, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v12, s3 ; GFX8-NEXT: v_mov_b32_e32 v16, s3
; GFX8-NEXT: v_mov_b32_e32 v11, s2 ; GFX8-NEXT: v_mov_b32_e32 v15, s2
; GFX8-NEXT: s_add_u32 s2, s0, 48 ; GFX8-NEXT: s_add_u32 s2, s0, 48
; GFX8-NEXT: s_addc_u32 s3, s1, 0 ; GFX8-NEXT: s_addc_u32 s3, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v19, s3 ; GFX8-NEXT: v_mov_b32_e32 v23, s3
; GFX8-NEXT: v_mov_b32_e32 v18, s2 ; GFX8-NEXT: v_mov_b32_e32 v22, s2
; GFX8-NEXT: s_add_u32 s2, s0, 32 ; GFX8-NEXT: s_add_u32 s2, s0, 32
; GFX8-NEXT: v_mov_b32_e32 v17, s1 ; GFX8-NEXT: v_mov_b32_e32 v21, s1
; GFX8-NEXT: s_addc_u32 s3, s1, 0 ; GFX8-NEXT: s_addc_u32 s3, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v16, s0 ; GFX8-NEXT: v_mov_b32_e32 v20, s0
; GFX8-NEXT: s_add_u32 s0, s0, 16 ; GFX8-NEXT: s_add_u32 s0, s0, 16
; GFX8-NEXT: s_addc_u32 s1, s1, 0 ; GFX8-NEXT: s_addc_u32 s1, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v21, s3 ; GFX8-NEXT: v_mov_b32_e32 v25, s3
; GFX8-NEXT: v_mov_b32_e32 v23, s1 ; GFX8-NEXT: v_mov_b32_e32 v27, s1
; GFX8-NEXT: v_mov_b32_e32 v20, s2 ; GFX8-NEXT: v_mov_b32_e32 v24, s2
; GFX8-NEXT: v_mov_b32_e32 v22, s0 ; GFX8-NEXT: v_mov_b32_e32 v26, s0
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b16_e32 v1, 14, v0 ; GFX8-NEXT: v_lshrrev_b16_e32 v1, 14, v0
; GFX8-NEXT: v_lshrrev_b16_e32 v2, 15, v0 ; GFX8-NEXT: v_lshrrev_b16_e32 v2, 15, v0
; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 1 ; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 1
; GFX8-NEXT: v_bfe_i32 v1, v1, 0, 1 ; GFX8-NEXT: v_bfe_i32 v1, v1, 0, 1
; GFX8-NEXT: v_lshrrev_b16_e32 v13, 12, v0 ; GFX8-NEXT: v_lshrrev_b16_e32 v11, 12, v0
; GFX8-NEXT: v_lshrrev_b16_e32 v14, 13, v0 ; GFX8-NEXT: v_lshrrev_b16_e32 v12, 13, v0
; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v3 ; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v3
; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v1 ; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v1
; GFX8-NEXT: flat_store_dwordx4 v[5:6], v[1:4] ; GFX8-NEXT: flat_store_dwordx4 v[5:6], v[1:4]
; GFX8-NEXT: v_lshrrev_b16_e32 v15, 10, v0 ; GFX8-NEXT: v_lshrrev_b16_e32 v13, 10, v0
; GFX8-NEXT: v_bfe_i32 v3, v14, 0, 1 ; GFX8-NEXT: v_bfe_i32 v3, v12, 0, 1
; GFX8-NEXT: v_bfe_i32 v1, v13, 0, 1 ; GFX8-NEXT: v_bfe_i32 v1, v11, 0, 1
; GFX8-NEXT: v_lshrrev_b16_e32 v5, 11, v0 ; GFX8-NEXT: v_lshrrev_b16_e32 v14, 11, v0
; GFX8-NEXT: v_lshrrev_b16_e32 v6, 3, v0
; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v3 ; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v3
; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v1 ; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v1
; GFX8-NEXT: v_lshrrev_b16_e32 v5, 2, v0
; GFX8-NEXT: flat_store_dwordx4 v[7:8], v[1:4] ; GFX8-NEXT: flat_store_dwordx4 v[7:8], v[1:4]
; GFX8-NEXT: v_lshrrev_b16_e32 v6, 8, v0 ; GFX8-NEXT: v_lshrrev_b16_e32 v17, 8, v0
; GFX8-NEXT: v_bfe_i32 v3, v5, 0, 1 ; GFX8-NEXT: v_bfe_i32 v3, v6, 0, 1
; GFX8-NEXT: v_bfe_i32 v1, v15, 0, 1 ; GFX8-NEXT: v_bfe_i32 v6, v14, 0, 1
; GFX8-NEXT: v_lshrrev_b16_e32 v13, 9, v0 ; GFX8-NEXT: v_bfe_i32 v4, v13, 0, 1
; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v3 ; GFX8-NEXT: v_lshrrev_b16_e32 v18, 9, v0
; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v1 ; GFX8-NEXT: v_bfe_i32 v1, v5, 0, 1
; GFX8-NEXT: flat_store_dwordx4 v[9:10], v[1:4]
; GFX8-NEXT: v_lshrrev_b16_e32 v7, 6, v0
; GFX8-NEXT: v_bfe_i32 v3, v13, 0, 1
; GFX8-NEXT: v_bfe_i32 v1, v6, 0, 1
; GFX8-NEXT: v_lshrrev_b16_e32 v14, 7, v0
; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v3
; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v1
; GFX8-NEXT: v_lshrrev_b16_e32 v5, 4, v0
; GFX8-NEXT: v_lshrrev_b16_e32 v8, 5, v0
; GFX8-NEXT: v_lshrrev_b16_e32 v9, 2, v0
; GFX8-NEXT: v_lshrrev_b16_e32 v6, 3, v0
; GFX8-NEXT: flat_store_dwordx4 v[11:12], v[1:4]
; GFX8-NEXT: v_bfe_i32 v14, v14, 0, 1
; GFX8-NEXT: v_lshrrev_b16_e32 v2, 1, v0
; GFX8-NEXT: v_bfe_i32 v12, v7, 0, 1
; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 1
; GFX8-NEXT: v_bfe_i32 v2, v2, 0, 1
; GFX8-NEXT: v_bfe_i32 v6, v6, 0, 1
; GFX8-NEXT: v_bfe_i32 v4, v9, 0, 1
; GFX8-NEXT: v_bfe_i32 v10, v8, 0, 1
; GFX8-NEXT: v_bfe_i32 v8, v5, 0, 1
; GFX8-NEXT: v_ashrrev_i32_e32 v15, 31, v14
; GFX8-NEXT: v_ashrrev_i32_e32 v13, 31, v12
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX8-NEXT: v_ashrrev_i32_e32 v7, 31, v6 ; GFX8-NEXT: v_ashrrev_i32_e32 v7, 31, v6
; GFX8-NEXT: v_ashrrev_i32_e32 v5, 31, v4 ; GFX8-NEXT: v_ashrrev_i32_e32 v5, 31, v4
; GFX8-NEXT: flat_store_dwordx4 v[9:10], v[4:7]
; GFX8-NEXT: v_bfe_i32 v10, v18, 0, 1
; GFX8-NEXT: v_bfe_i32 v8, v17, 0, 1
; GFX8-NEXT: v_lshrrev_b16_e32 v19, 6, v0
; GFX8-NEXT: v_lshrrev_b16_e32 v28, 4, v0
; GFX8-NEXT: v_lshrrev_b16_e32 v29, 5, v0
; GFX8-NEXT: v_lshrrev_b16_e32 v2, 1, v0
; GFX8-NEXT: v_bfe_i32 v12, v0, 0, 1
; GFX8-NEXT: v_lshrrev_b16_e32 v0, 7, v0
; GFX8-NEXT: v_ashrrev_i32_e32 v11, 31, v10 ; GFX8-NEXT: v_ashrrev_i32_e32 v11, 31, v10
; GFX8-NEXT: v_ashrrev_i32_e32 v9, 31, v8 ; GFX8-NEXT: v_ashrrev_i32_e32 v9, 31, v8
; GFX8-NEXT: flat_store_dwordx4 v[18:19], v[12:15] ; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[8:11]
; GFX8-NEXT: flat_store_dwordx4 v[20:21], v[8:11] ; GFX8-NEXT: v_bfe_i32 v18, v0, 0, 1
; GFX8-NEXT: flat_store_dwordx4 v[22:23], v[4:7] ; GFX8-NEXT: v_bfe_i32 v16, v19, 0, 1
; GFX8-NEXT: flat_store_dwordx4 v[16:17], v[0:3] ; GFX8-NEXT: v_bfe_i32 v7, v29, 0, 1
; GFX8-NEXT: v_bfe_i32 v5, v28, 0, 1
; GFX8-NEXT: v_bfe_i32 v14, v2, 0, 1
; GFX8-NEXT: v_ashrrev_i32_e32 v19, 31, v18
; GFX8-NEXT: v_ashrrev_i32_e32 v17, 31, v16
; GFX8-NEXT: v_ashrrev_i32_e32 v13, 31, v12
; GFX8-NEXT: v_ashrrev_i32_e32 v15, 31, v14
; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v3
; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v1
; GFX8-NEXT: v_ashrrev_i32_e32 v8, 31, v7
; GFX8-NEXT: v_ashrrev_i32_e32 v6, 31, v5
; GFX8-NEXT: flat_store_dwordx4 v[22:23], v[16:19]
; GFX8-NEXT: flat_store_dwordx4 v[24:25], v[5:8]
; GFX8-NEXT: flat_store_dwordx4 v[26:27], v[1:4]
; GFX8-NEXT: flat_store_dwordx4 v[20:21], v[12:15]
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; EG-LABEL: constant_sextload_v16i1_to_v16i64: ; EG-LABEL: constant_sextload_v16i1_to_v16i64:
; EG: ; %bb.0: ; EG: ; %bb.0:
; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @12 ; EG-NEXT: TEX 0 @12
; EG-NEXT: ALU 78, @15, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 78, @15, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T14.XYZW, T22.X, 0 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T14.XYZW, T22.X, 0
▲ Show 20 Lines • Show All 718 Lines • ▼ Show 20 Lines
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX8-LABEL: constant_sextload_v32i1_to_v32i64: ; GFX8-LABEL: constant_sextload_v32i1_to_v32i64:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_load_dword s4, s[2:3], 0x0 ; GFX8-NEXT: s_load_dword s4, s[2:3], 0x0
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_lshr_b32 s10, s4, 22 ; GFX8-NEXT: s_lshr_b32 s6, s4, 22
; GFX8-NEXT: s_lshr_b32 s12, s4, 23 ; GFX8-NEXT: s_lshr_b32 s8, s4, 23
; GFX8-NEXT: s_lshr_b32 s14, s4, 20 ; GFX8-NEXT: s_lshr_b32 s10, s4, 20
; GFX8-NEXT: s_lshr_b32 s16, s4, 21 ; GFX8-NEXT: s_lshr_b32 s12, s4, 21
; GFX8-NEXT: s_lshr_b32 s18, s4, 18 ; GFX8-NEXT: s_lshr_b32 s14, s4, 18
; GFX8-NEXT: s_lshr_b32 s20, s4, 19 ; GFX8-NEXT: s_lshr_b32 s16, s4, 19
; GFX8-NEXT: s_lshr_b32 s22, s4, 16 ; GFX8-NEXT: s_lshr_b32 s18, s4, 16
; GFX8-NEXT: s_lshr_b32 s24, s4, 17 ; GFX8-NEXT: s_lshr_b32 s20, s4, 17
; GFX8-NEXT: s_lshr_b32 s6, s4, 24 ; GFX8-NEXT: s_lshr_b32 s2, s4, 24
; GFX8-NEXT: s_bfe_i64 s[2:3], s[6:7], 0x10000 ; GFX8-NEXT: v_lshrrev_b16_e64 v15, 14, s4
; GFX8-NEXT: s_bfe_i64 s[8:9], s[4:5], 0x10000 ; GFX8-NEXT: v_lshrrev_b16_e64 v16, 15, s4
; GFX8-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000 ; GFX8-NEXT: v_lshrrev_b16_e64 v12, 12, s4
; GFX8-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000 ; GFX8-NEXT: v_lshrrev_b16_e64 v14, 13, s4
; GFX8-NEXT: v_lshrrev_b16_e64 v9, 10, s4
; GFX8-NEXT: v_lshrrev_b16_e64 v10, 11, s4
; GFX8-NEXT: v_lshrrev_b16_e64 v7, 8, s4
; GFX8-NEXT: v_lshrrev_b16_e64 v8, 9, s4
; GFX8-NEXT: v_lshrrev_b16_e64 v4, 6, s4
; GFX8-NEXT: v_lshrrev_b16_e64 v5, 7, s4
; GFX8-NEXT: v_lshrrev_b16_e64 v2, 4, s4
; GFX8-NEXT: v_lshrrev_b16_e64 v3, 5, s4
; GFX8-NEXT: v_lshrrev_b16_e64 v0, 2, s4
; GFX8-NEXT: v_lshrrev_b16_e64 v1, 3, s4
; GFX8-NEXT: v_lshrrev_b16_e64 v6, 1, s4
; GFX8-NEXT: v_lshrrev_b16_e64 v11, 6, s2
; GFX8-NEXT: v_lshrrev_b16_e64 v13, 7, s2
; GFX8-NEXT: v_lshrrev_b16_e64 v17, 4, s2
; GFX8-NEXT: v_lshrrev_b16_e64 v18, 5, s2
; GFX8-NEXT: v_lshrrev_b16_e64 v19, 2, s2
; GFX8-NEXT: v_lshrrev_b16_e64 v20, 3, s2
; GFX8-NEXT: v_lshrrev_b16_e64 v27, 1, s2
; GFX8-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
; GFX8-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x10000
; GFX8-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000 ; GFX8-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
; GFX8-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000 ; GFX8-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
; GFX8-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000 ; GFX8-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000
; GFX8-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000 ; GFX8-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
; GFX8-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000 ; GFX8-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
; GFX8-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000 ; GFX8-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000
; GFX8-NEXT: v_mov_b32_e32 v11, s10 ; GFX8-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x10000
; GFX8-NEXT: s_add_u32 s10, s0, 0xb0 ; GFX8-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
; GFX8-NEXT: v_mov_b32_e32 v12, s11 ; GFX8-NEXT: v_mov_b32_e32 v21, s6
; GFX8-NEXT: s_addc_u32 s11, s1, 0 ; GFX8-NEXT: s_add_u32 s6, s0, 0xb0
; GFX8-NEXT: v_mov_b32_e32 v16, s11 ; GFX8-NEXT: v_mov_b32_e32 v22, s7
; GFX8-NEXT: v_mov_b32_e32 v15, s10 ; GFX8-NEXT: s_addc_u32 s7, s1, 0
; GFX8-NEXT: s_add_u32 s10, s0, 0xa0 ; GFX8-NEXT: v_mov_b32_e32 v26, s7
; GFX8-NEXT: v_mov_b32_e32 v13, s12 ; GFX8-NEXT: v_mov_b32_e32 v25, s6
; GFX8-NEXT: v_mov_b32_e32 v14, s13 ; GFX8-NEXT: s_add_u32 s6, s0, 0xa0
; GFX8-NEXT: s_addc_u32 s11, s1, 0 ; GFX8-NEXT: v_mov_b32_e32 v23, s8
; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[11:14] ; GFX8-NEXT: v_mov_b32_e32 v24, s9
; GFX8-NEXT: v_mov_b32_e32 v16, s11 ; GFX8-NEXT: s_addc_u32 s7, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v15, s10 ; GFX8-NEXT: flat_store_dwordx4 v[25:26], v[21:24]
; GFX8-NEXT: s_add_u32 s10, s0, 0x90 ; GFX8-NEXT: v_mov_b32_e32 v26, s7
; GFX8-NEXT: v_mov_b32_e32 v11, s14 ; GFX8-NEXT: v_mov_b32_e32 v25, s6
; GFX8-NEXT: v_mov_b32_e32 v12, s15 ; GFX8-NEXT: s_add_u32 s6, s0, 0x90
; GFX8-NEXT: v_mov_b32_e32 v13, s16 ; GFX8-NEXT: v_mov_b32_e32 v21, s10
; GFX8-NEXT: v_mov_b32_e32 v14, s17 ; GFX8-NEXT: v_mov_b32_e32 v22, s11
; GFX8-NEXT: s_addc_u32 s11, s1, 0 ; GFX8-NEXT: v_mov_b32_e32 v23, s12
; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[11:14] ; GFX8-NEXT: v_mov_b32_e32 v24, s13
; GFX8-NEXT: v_mov_b32_e32 v16, s11 ; GFX8-NEXT: s_addc_u32 s7, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v15, s10 ; GFX8-NEXT: flat_store_dwordx4 v[25:26], v[21:24]
; GFX8-NEXT: s_add_u32 s10, s0, 0x80 ; GFX8-NEXT: v_mov_b32_e32 v26, s7
; GFX8-NEXT: v_mov_b32_e32 v11, s18 ; GFX8-NEXT: v_mov_b32_e32 v25, s6
; GFX8-NEXT: v_mov_b32_e32 v12, s19 ; GFX8-NEXT: s_add_u32 s6, s0, 0x80
; GFX8-NEXT: v_mov_b32_e32 v13, s20 ; GFX8-NEXT: v_mov_b32_e32 v21, s14
; GFX8-NEXT: v_mov_b32_e32 v14, s21 ; GFX8-NEXT: v_mov_b32_e32 v22, s15
; GFX8-NEXT: s_addc_u32 s11, s1, 0 ; GFX8-NEXT: v_mov_b32_e32 v23, s16
; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[11:14] ; GFX8-NEXT: v_mov_b32_e32 v24, s17
; GFX8-NEXT: v_mov_b32_e32 v16, s11 ; GFX8-NEXT: s_addc_u32 s7, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v15, s10 ; GFX8-NEXT: flat_store_dwordx4 v[25:26], v[21:24]
; GFX8-NEXT: s_add_u32 s10, s0, 0x70 ; GFX8-NEXT: v_mov_b32_e32 v26, s7
; GFX8-NEXT: v_lshrrev_b16_e64 v9, 14, s4 ; GFX8-NEXT: v_mov_b32_e32 v25, s6
; GFX8-NEXT: v_lshrrev_b16_e64 v10, 15, s4 ; GFX8-NEXT: s_add_u32 s6, s0, 0x70
; GFX8-NEXT: v_mov_b32_e32 v11, s22 ; GFX8-NEXT: v_mov_b32_e32 v21, s18
; GFX8-NEXT: v_mov_b32_e32 v12, s23 ; GFX8-NEXT: v_mov_b32_e32 v22, s19
; GFX8-NEXT: v_mov_b32_e32 v13, s24 ; GFX8-NEXT: v_mov_b32_e32 v23, s20
; GFX8-NEXT: v_mov_b32_e32 v14, s25 ; GFX8-NEXT: v_mov_b32_e32 v24, s21
; GFX8-NEXT: s_addc_u32 s11, s1, 0 ; GFX8-NEXT: s_addc_u32 s7, s1, 0
; GFX8-NEXT: v_lshrrev_b16_e64 v7, 12, s4 ; GFX8-NEXT: flat_store_dwordx4 v[25:26], v[21:24]
; GFX8-NEXT: v_lshrrev_b16_e64 v8, 13, s4
; GFX8-NEXT: v_lshrrev_b16_e64 v5, 10, s4
; GFX8-NEXT: v_lshrrev_b16_e64 v6, 11, s4
; GFX8-NEXT: v_lshrrev_b16_e64 v3, 8, s4
; GFX8-NEXT: v_lshrrev_b16_e64 v4, 9, s4
; GFX8-NEXT: v_lshrrev_b16_e64 v1, 6, s4
; GFX8-NEXT: v_lshrrev_b16_e64 v2, 7, s4
; GFX8-NEXT: v_lshrrev_b16_e64 v0, 4, s4
; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[11:14]
; GFX8-NEXT: v_lshrrev_b16_e64 v16, 5, s4
; GFX8-NEXT: v_lshrrev_b16_e64 v20, 2, s4
; GFX8-NEXT: v_bfe_i32 v11, v10, 0, 1
; GFX8-NEXT: v_bfe_i32 v9, v9, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v14, s11
; GFX8-NEXT: v_lshrrev_b16_e64 v21, 3, s4
; GFX8-NEXT: v_lshrrev_b16_e64 v22, 1, s4
; GFX8-NEXT: s_add_u32 s4, s0, 0x60
; GFX8-NEXT: v_ashrrev_i32_e32 v12, 31, v11
; GFX8-NEXT: v_ashrrev_i32_e32 v10, 31, v9
; GFX8-NEXT: v_mov_b32_e32 v13, s10
; GFX8-NEXT: s_addc_u32 s5, s1, 0
; GFX8-NEXT: flat_store_dwordx4 v[13:14], v[9:12]
; GFX8-NEXT: v_bfe_i32 v7, v7, 0, 1 ; GFX8-NEXT: v_bfe_i32 v7, v7, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v12, s5 ; GFX8-NEXT: v_bfe_i32 v23, v16, 0, 1
; GFX8-NEXT: v_bfe_i32 v21, v15, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v16, s7
; GFX8-NEXT: v_mov_b32_e32 v15, s6
; GFX8-NEXT: s_add_u32 s6, s0, 0x60
; GFX8-NEXT: s_addc_u32 s7, s1, 0
; GFX8-NEXT: v_ashrrev_i32_e32 v24, 31, v23
; GFX8-NEXT: v_ashrrev_i32_e32 v22, 31, v21
; GFX8-NEXT: v_mov_b32_e32 v26, s7
; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[21:24]
; GFX8-NEXT: v_mov_b32_e32 v25, s6
; GFX8-NEXT: v_bfe_i32 v23, v14, 0, 1
; GFX8-NEXT: v_bfe_i32 v21, v12, 0, 1
; GFX8-NEXT: s_add_u32 s6, s0, 0x50
; GFX8-NEXT: v_ashrrev_i32_e32 v24, 31, v23
; GFX8-NEXT: v_ashrrev_i32_e32 v22, 31, v21
; GFX8-NEXT: s_addc_u32 s7, s1, 0
; GFX8-NEXT: flat_store_dwordx4 v[25:26], v[21:24]
; GFX8-NEXT: v_bfe_i32 v25, v10, 0, 1
; GFX8-NEXT: v_bfe_i32 v23, v9, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v10, s7
; GFX8-NEXT: v_mov_b32_e32 v9, s6
; GFX8-NEXT: s_add_u32 s6, s0, 64
; GFX8-NEXT: v_ashrrev_i32_e32 v26, 31, v25
; GFX8-NEXT: v_ashrrev_i32_e32 v24, 31, v23
; GFX8-NEXT: s_addc_u32 s7, s1, 0
; GFX8-NEXT: flat_store_dwordx4 v[9:10], v[23:26]
; GFX8-NEXT: v_bfe_i32 v9, v8, 0, 1 ; GFX8-NEXT: v_bfe_i32 v9, v8, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v11, s4 ; GFX8-NEXT: v_bfe_i32 v25, v18, 0, 1
; GFX8-NEXT: s_add_u32 s4, s0, 0x50 ; GFX8-NEXT: v_bfe_i32 v23, v17, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v18, s7
; GFX8-NEXT: v_ashrrev_i32_e32 v10, 31, v9 ; GFX8-NEXT: v_ashrrev_i32_e32 v10, 31, v9
; GFX8-NEXT: v_ashrrev_i32_e32 v8, 31, v7 ; GFX8-NEXT: v_ashrrev_i32_e32 v8, 31, v7
; GFX8-NEXT: s_addc_u32 s5, s1, 0 ; GFX8-NEXT: v_mov_b32_e32 v17, s6
; GFX8-NEXT: flat_store_dwordx4 v[11:12], v[7:10] ; GFX8-NEXT: s_add_u32 s6, s0, 48
; GFX8-NEXT: v_bfe_i32 v5, v5, 0, 1 ; GFX8-NEXT: flat_store_dwordx4 v[17:18], v[7:10]
; GFX8-NEXT: v_mov_b32_e32 v10, s5 ; GFX8-NEXT: s_addc_u32 s7, s1, 0
; GFX8-NEXT: v_bfe_i32 v7, v6, 0, 1 ; GFX8-NEXT: v_bfe_i32 v9, v13, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v9, s4 ; GFX8-NEXT: v_bfe_i32 v7, v11, 0, 1
; GFX8-NEXT: s_add_u32 s4, s0, 64 ; GFX8-NEXT: v_bfe_i32 v13, v5, 0, 1
; GFX8-NEXT: v_ashrrev_i32_e32 v8, 31, v7 ; GFX8-NEXT: v_bfe_i32 v11, v4, 0, 1
; GFX8-NEXT: v_ashrrev_i32_e32 v6, 31, v5 ; GFX8-NEXT: v_mov_b32_e32 v4, s6
; GFX8-NEXT: s_addc_u32 s5, s1, 0 ; GFX8-NEXT: v_ashrrev_i32_e32 v14, 31, v13
; GFX8-NEXT: flat_store_dwordx4 v[9:10], v[5:8] ; GFX8-NEXT: v_ashrrev_i32_e32 v12, 31, v11
; GFX8-NEXT: v_mov_b32_e32 v11, s5 ; GFX8-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NEXT: v_bfe_i32 v5, v4, 0, 1 ; GFX8-NEXT: s_add_u32 s6, s0, 32
; GFX8-NEXT: v_bfe_i32 v3, v3, 0, 1 ; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[11:14]
; GFX8-NEXT: v_mov_b32_e32 v10, s4 ; GFX8-NEXT: s_addc_u32 s7, s1, 0
; GFX8-NEXT: s_add_u32 s4, s0, 48 ; GFX8-NEXT: v_bfe_i32 v13, v3, 0, 1
; GFX8-NEXT: v_ashrrev_i32_e32 v6, 31, v5 ; GFX8-NEXT: v_bfe_i32 v11, v2, 0, 1
; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v3 ; GFX8-NEXT: v_mov_b32_e32 v2, s6
; GFX8-NEXT: s_addc_u32 s5, s1, 0 ; GFX8-NEXT: v_mov_b32_e32 v3, s7
; GFX8-NEXT: flat_store_dwordx4 v[10:11], v[3:6] ; GFX8-NEXT: s_add_u32 s6, s0, 16
; GFX8-NEXT: v_bfe_i32 v1, v1, 0, 1 ; GFX8-NEXT: v_ashrrev_i32_e32 v14, 31, v13
; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 1 ; GFX8-NEXT: v_ashrrev_i32_e32 v12, 31, v11
; GFX8-NEXT: v_mov_b32_e32 v11, s5 ; GFX8-NEXT: s_addc_u32 s7, s1, 0
; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v3 ; GFX8-NEXT: flat_store_dwordx4 v[2:3], v[11:14]
; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v1
; GFX8-NEXT: v_mov_b32_e32 v10, s4
; GFX8-NEXT: flat_store_dwordx4 v[10:11], v[1:4]
; GFX8-NEXT: s_add_u32 s4, s0, 32
; GFX8-NEXT: v_lshrrev_b16_e64 v1, 1, s6
; GFX8-NEXT: v_bfe_i32 v2, v1, 0, 1 ; GFX8-NEXT: v_bfe_i32 v2, v1, 0, 1
; GFX8-NEXT: v_bfe_i32 v18, v16, 0, 1 ; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 1
; GFX8-NEXT: v_bfe_i32 v16, v0, 0, 1 ; GFX8-NEXT: v_mov_b32_e32 v12, s7
; GFX8-NEXT: s_addc_u32 s5, s1, 0 ; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX8-NEXT: v_mov_b32_e32 v0, s4 ; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX8-NEXT: v_ashrrev_i32_e32 v19, 31, v18 ; GFX8-NEXT: v_mov_b32_e32 v11, s6
; GFX8-NEXT: v_ashrrev_i32_e32 v17, 31, v16 ; GFX8-NEXT: v_bfe_i32 v4, v6, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v1, s5 ; GFX8-NEXT: flat_store_dwordx4 v[11:12], v[0:3]
; GFX8-NEXT: s_add_u32 s4, s0, 16 ; GFX8-NEXT: v_ashrrev_i32_e32 v5, 31, v4
; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[16:19]
; GFX8-NEXT: v_bfe_i32 v20, v20, 0, 1
; GFX8-NEXT: v_bfe_i32 v18, v22, 0, 1
; GFX8-NEXT: v_bfe_i32 v22, v21, 0, 1
; GFX8-NEXT: s_addc_u32 s5, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_ashrrev_i32_e32 v23, 31, v22
; GFX8-NEXT: v_ashrrev_i32_e32 v21, 31, v20
; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[20:23]
; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_lshrrev_b16_e64 v12, 6, s6 ; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: v_lshrrev_b16_e64 v13, 7, s6 ; GFX8-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NEXT: v_ashrrev_i32_e32 v19, 31, v18
; GFX8-NEXT: v_mov_b32_e32 v16, s8
; GFX8-NEXT: v_mov_b32_e32 v17, s9
; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: s_add_u32 s4, s0, 0xf0 ; GFX8-NEXT: s_add_u32 s4, s0, 0xf0
; GFX8-NEXT: v_bfe_i32 v14, v13, 0, 1 ; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[2:5]
; GFX8-NEXT: v_bfe_i32 v12, v12, 0, 1
; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[16:19]
; GFX8-NEXT: s_addc_u32 s5, s1, 0 ; GFX8-NEXT: s_addc_u32 s5, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v0, s4 ; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_ashrrev_i32_e32 v15, 31, v14 ; GFX8-NEXT: v_ashrrev_i32_e32 v10, 31, v9
; GFX8-NEXT: v_ashrrev_i32_e32 v13, 31, v12 ; GFX8-NEXT: v_ashrrev_i32_e32 v8, 31, v7
; GFX8-NEXT: v_mov_b32_e32 v1, s5 ; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_add_u32 s4, s0, 0xe0 ; GFX8-NEXT: s_add_u32 s4, s0, 0xe0
; GFX8-NEXT: v_lshrrev_b16_e64 v8, 4, s6 ; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[7:10]
; GFX8-NEXT: v_lshrrev_b16_e64 v9, 5, s6
; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[12:15]
; GFX8-NEXT: s_addc_u32 s5, s1, 0 ; GFX8-NEXT: s_addc_u32 s5, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v0, s4 ; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_bfe_i32 v10, v9, 0, 1 ; GFX8-NEXT: v_ashrrev_i32_e32 v26, 31, v25
; GFX8-NEXT: v_bfe_i32 v8, v8, 0, 1 ; GFX8-NEXT: v_ashrrev_i32_e32 v24, 31, v23
; GFX8-NEXT: v_mov_b32_e32 v1, s5 ; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_add_u32 s4, s0, 0xd0 ; GFX8-NEXT: s_add_u32 s4, s0, 0xd0
; GFX8-NEXT: v_lshrrev_b16_e64 v5, 2, s6 ; GFX8-NEXT: v_bfe_i32 v21, v20, 0, 1
; GFX8-NEXT: v_lshrrev_b16_e64 v6, 3, s6 ; GFX8-NEXT: v_bfe_i32 v19, v19, 0, 1
; GFX8-NEXT: v_ashrrev_i32_e32 v11, 31, v10 ; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[23:26]
; GFX8-NEXT: v_ashrrev_i32_e32 v9, 31, v8
; GFX8-NEXT: s_addc_u32 s5, s1, 0 ; GFX8-NEXT: s_addc_u32 s5, s1, 0
; GFX8-NEXT: v_bfe_i32 v6, v6, 0, 1
; GFX8-NEXT: v_bfe_i32 v4, v5, 0, 1
; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
; GFX8-NEXT: v_mov_b32_e32 v0, s4 ; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_add_u32 s0, s0, 0xc0 ; GFX8-NEXT: v_ashrrev_i32_e32 v22, 31, v21
; GFX8-NEXT: v_ashrrev_i32_e32 v7, 31, v6 ; GFX8-NEXT: v_ashrrev_i32_e32 v20, 31, v19
; GFX8-NEXT: v_ashrrev_i32_e32 v5, 31, v4
; GFX8-NEXT: v_mov_b32_e32 v1, s5 ; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_add_u32 s0, s0, 0xc0
; GFX8-NEXT: v_bfe_i32 v15, v27, 0, 1
; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[19:22]
; GFX8-NEXT: s_addc_u32 s1, s1, 0 ; GFX8-NEXT: s_addc_u32 s1, s1, 0
; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7] ; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2 ; GFX8-NEXT: v_ashrrev_i32_e32 v16, 31, v15
; GFX8-NEXT: v_mov_b32_e32 v5, s1 ; GFX8-NEXT: v_mov_b32_e32 v13, s2
; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v14, s3
; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s0 ; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[13:16]
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; EG-LABEL: constant_sextload_v32i1_to_v32i64: ; EG-LABEL: constant_sextload_v32i1_to_v32i64:
; EG: ; %bb.0: ; EG: ; %bb.0:
; EG-NEXT: ALU 0, @24, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 0, @24, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @22 ; EG-NEXT: TEX 0 @22
; EG-NEXT: ALU 92, @25, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 92, @25, KC0[CB0:0-32], KC1[]
; EG-NEXT: ALU 65, @118, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 65, @118, KC0[CB0:0-32], KC1[]
▲ Show 20 Lines • Show All 1,371 Lines • ▼ Show 20 Lines
; GFX6-NEXT: v_mov_b32_e32 v6, s4 ; GFX6-NEXT: v_mov_b32_e32 v6, s4
; GFX6-NEXT: v_mov_b32_e32 v7, s5 ; GFX6-NEXT: v_mov_b32_e32 v7, s5
; GFX6-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 ; GFX6-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0
; GFX6-NEXT: s_endpgm ; GFX6-NEXT: s_endpgm
; ;
; GFX8-LABEL: constant_sextload_v64i1_to_v64i64: ; GFX8-LABEL: constant_sextload_v64i1_to_v64i64:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX8-NEXT: s_mov_b32 s13, 0 ; GFX8-NEXT: s_mov_b32 s11, 0
; GFX8-NEXT: s_mov_b32 s11, s13 ; GFX8-NEXT: s_mov_b32 s13, s11
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 ; GFX8-NEXT: s_load_dwordx2 s[6:7], s[2:3], 0x0
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_lshr_b32 s14, s5, 22 ; GFX8-NEXT: s_lshr_b32 s14, s7, 22
; GFX8-NEXT: s_lshr_b32 s16, s5, 23 ; GFX8-NEXT: s_lshr_b32 s16, s7, 23
; GFX8-NEXT: s_lshr_b32 s20, s5, 20 ; GFX8-NEXT: s_lshr_b32 s20, s7, 20
; GFX8-NEXT: s_lshr_b32 s22, s5, 21 ; GFX8-NEXT: s_lshr_b32 s22, s7, 21
; GFX8-NEXT: s_lshr_b32 s24, s5, 18 ; GFX8-NEXT: s_lshr_b32 s24, s7, 18
; GFX8-NEXT: s_lshr_b32 s26, s5, 19 ; GFX8-NEXT: s_lshr_b32 s26, s7, 19
; GFX8-NEXT: s_lshr_b32 s28, s5, 16 ; GFX8-NEXT: s_lshr_b32 s28, s7, 16
; GFX8-NEXT: s_lshr_b32 s30, s5, 17 ; GFX8-NEXT: s_lshr_b32 s30, s7, 17
; GFX8-NEXT: s_lshr_b32 s34, s4, 22 ; GFX8-NEXT: s_lshr_b32 s34, s6, 22
; GFX8-NEXT: s_lshr_b32 s36, s4, 23 ; GFX8-NEXT: s_lshr_b32 s36, s6, 23
; GFX8-NEXT: s_lshr_b32 s38, s4, 20 ; GFX8-NEXT: s_lshr_b32 s38, s6, 20
; GFX8-NEXT: s_lshr_b32 s40, s4, 21 ; GFX8-NEXT: s_lshr_b32 s40, s6, 21
; GFX8-NEXT: s_lshr_b32 s42, s4, 18 ; GFX8-NEXT: s_lshr_b32 s42, s6, 18
; GFX8-NEXT: s_lshr_b32 s44, s4, 19 ; GFX8-NEXT: s_lshr_b32 s44, s6, 19
; GFX8-NEXT: s_lshr_b32 s46, s4, 16 ; GFX8-NEXT: s_lshr_b32 s46, s6, 16
; GFX8-NEXT: s_lshr_b32 s48, s4, 17 ; GFX8-NEXT: s_lshr_b32 s48, s6, 17
; GFX8-NEXT: s_mov_b32 s12, s5 ; GFX8-NEXT: s_mov_b32 s10, s7
; GFX8-NEXT: s_lshr_b32 s10, s5, 24 ; GFX8-NEXT: s_lshr_b32 s12, s7, 24
; GFX8-NEXT: s_lshr_b32 s6, s4, 24 ; GFX8-NEXT: s_lshr_b32 s8, s6, 24
; GFX8-NEXT: s_bfe_i64 s[2:3], s[6:7], 0x10000 ; GFX8-NEXT: s_bfe_i64 s[2:3], s[8:9], 0x10000
; GFX8-NEXT: s_bfe_i64 s[8:9], s[10:11], 0x10000 ; GFX8-NEXT: s_bfe_i64 s[4:5], s[12:13], 0x10000
; GFX8-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000 ; GFX8-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000
; GFX8-NEXT: s_bfe_i64 s[18:19], s[4:5], 0x10000 ; GFX8-NEXT: s_bfe_i64 s[18:19], s[6:7], 0x10000
; GFX8-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x10000 ; GFX8-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x10000
; GFX8-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x10000 ; GFX8-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x10000
; GFX8-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x10000 ; GFX8-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x10000
; GFX8-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x10000 ; GFX8-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x10000
; GFX8-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x10000 ; GFX8-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x10000
; GFX8-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x10000 ; GFX8-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x10000
; GFX8-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x10000 ; GFX8-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x10000
; GFX8-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x10000 ; GFX8-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x10000
; GFX8-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000 ; GFX8-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
; GFX8-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000 ; GFX8-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
; GFX8-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000 ; GFX8-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
; GFX8-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000 ; GFX8-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
; GFX8-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000 ; GFX8-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
; GFX8-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000 ; GFX8-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
; GFX8-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000 ; GFX8-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000
; GFX8-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000 ; GFX8-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
; GFX8-NEXT: v_mov_b32_e32 v11, s14 ; GFX8-NEXT: v_mov_b32_e32 v22, s14
; GFX8-NEXT: s_add_u32 s14, s0, 0x1b0 ; GFX8-NEXT: s_add_u32 s14, s0, 0x1b0
; GFX8-NEXT: v_mov_b32_e32 v12, s15 ; GFX8-NEXT: v_mov_b32_e32 v23, s15
; GFX8-NEXT: s_addc_u32 s15, s1, 0 ; GFX8-NEXT: s_addc_u32 s15, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v16, s15 ; GFX8-NEXT: v_mov_b32_e32 v27, s15
; GFX8-NEXT: v_mov_b32_e32 v15, s14 ; GFX8-NEXT: v_mov_b32_e32 v26, s14
; GFX8-NEXT: s_add_u32 s14, s0, 0x1a0 ; GFX8-NEXT: s_add_u32 s14, s0, 0x1a0
; GFX8-NEXT: v_mov_b32_e32 v13, s16 ; GFX8-NEXT: v_mov_b32_e32 v24, s16
; GFX8-NEXT: v_mov_b32_e32 v14, s17 ; GFX8-NEXT: v_mov_b32_e32 v25, s17
; GFX8-NEXT: s_addc_u32 s15, s1, 0 ; GFX8-NEXT: s_addc_u32 s15, s1, 0
; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[11:14] ; GFX8-NEXT: flat_store_dwordx4 v[26:27], v[22:25]
; GFX8-NEXT: v_mov_b32_e32 v16, s15 ; GFX8-NEXT: v_mov_b32_e32 v27, s15
; GFX8-NEXT: v_mov_b32_e32 v15, s14 ; GFX8-NEXT: v_mov_b32_e32 v26, s14
; GFX8-NEXT: s_add_u32 s14, s0, 0x190 ; GFX8-NEXT: s_add_u32 s14, s0, 0x190
; GFX8-NEXT: v_mov_b32_e32 v11, s20 ; GFX8-NEXT: v_mov_b32_e32 v22, s20
; GFX8-NEXT: v_mov_b32_e32 v12, s21 ; GFX8-NEXT: v_mov_b32_e32 v23, s21
; GFX8-NEXT: v_mov_b32_e32 v13, s22 ; GFX8-NEXT: v_mov_b32_e32 v24, s22
; GFX8-NEXT: v_mov_b32_e32 v14, s23 ; GFX8-NEXT: v_mov_b32_e32 v25, s23
; GFX8-NEXT: s_addc_u32 s15, s1, 0 ; GFX8-NEXT: s_addc_u32 s15, s1, 0
; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[11:14] ; GFX8-NEXT: flat_store_dwordx4 v[26:27], v[22:25]
; GFX8-NEXT: v_mov_b32_e32 v16, s15 ; GFX8-NEXT: v_mov_b32_e32 v27, s15
; GFX8-NEXT: v_mov_b32_e32 v15, s14 ; GFX8-NEXT: v_mov_b32_e32 v26, s14
; GFX8-NEXT: s_add_u32 s14, s0, 0x180 ; GFX8-NEXT: s_add_u32 s14, s0, 0x180
; GFX8-NEXT: v_mov_b32_e32 v11, s24 ; GFX8-NEXT: v_mov_b32_e32 v22, s24
; GFX8-NEXT: v_mov_b32_e32 v12, s25 ; GFX8-NEXT: v_mov_b32_e32 v23, s25
; GFX8-NEXT: v_mov_b32_e32 v13, s26 ; GFX8-NEXT: v_mov_b32_e32 v24, s26
; GFX8-NEXT: v_mov_b32_e32 v14, s27 ; GFX8-NEXT: v_mov_b32_e32 v25, s27
; GFX8-NEXT: s_addc_u32 s15, s1, 0 ; GFX8-NEXT: s_addc_u32 s15, s1, 0
; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[11:14] ; GFX8-NEXT: flat_store_dwordx4 v[26:27], v[22:25]
; GFX8-NEXT: v_mov_b32_e32 v16, s15 ; GFX8-NEXT: v_mov_b32_e32 v27, s15
; GFX8-NEXT: v_mov_b32_e32 v15, s14 ; GFX8-NEXT: v_mov_b32_e32 v26, s14
; GFX8-NEXT: s_add_u32 s14, s0, 0xb0 ; GFX8-NEXT: s_add_u32 s14, s0, 0xb0
; GFX8-NEXT: v_mov_b32_e32 v11, s28 ; GFX8-NEXT: v_mov_b32_e32 v22, s28
; GFX8-NEXT: v_mov_b32_e32 v12, s29 ; GFX8-NEXT: v_mov_b32_e32 v23, s29
; GFX8-NEXT: v_mov_b32_e32 v13, s30 ; GFX8-NEXT: v_mov_b32_e32 v24, s30
; GFX8-NEXT: v_mov_b32_e32 v14, s31 ; GFX8-NEXT: v_mov_b32_e32 v25, s31
; GFX8-NEXT: s_addc_u32 s15, s1, 0 ; GFX8-NEXT: s_addc_u32 s15, s1, 0
; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[11:14] ; GFX8-NEXT: flat_store_dwordx4 v[26:27], v[22:25]
; GFX8-NEXT: v_mov_b32_e32 v16, s15 ; GFX8-NEXT: v_mov_b32_e32 v27, s15
; GFX8-NEXT: v_mov_b32_e32 v15, s14 ; GFX8-NEXT: v_mov_b32_e32 v26, s14
; GFX8-NEXT: s_add_u32 s14, s0, 0xa0 ; GFX8-NEXT: s_add_u32 s14, s0, 0xa0
; GFX8-NEXT: v_mov_b32_e32 v11, s34 ; GFX8-NEXT: v_mov_b32_e32 v22, s34
; GFX8-NEXT: v_mov_b32_e32 v12, s35 ; GFX8-NEXT: v_mov_b32_e32 v23, s35
; GFX8-NEXT: v_mov_b32_e32 v13, s36 ; GFX8-NEXT: v_mov_b32_e32 v24, s36
; GFX8-NEXT: v_mov_b32_e32 v14, s37 ; GFX8-NEXT: v_mov_b32_e32 v25, s37
; GFX8-NEXT: s_addc_u32 s15, s1, 0 ; GFX8-NEXT: s_addc_u32 s15, s1, 0
; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[11:14] ; GFX8-NEXT: flat_store_dwordx4 v[26:27], v[22:25]
; GFX8-NEXT: v_mov_b32_e32 v16, s15 ; GFX8-NEXT: v_mov_b32_e32 v27, s15
; GFX8-NEXT: v_mov_b32_e32 v15, s14 ; GFX8-NEXT: v_mov_b32_e32 v26, s14
; GFX8-NEXT: s_add_u32 s14, s0, 0x90 ; GFX8-NEXT: s_add_u32 s14, s0, 0x90
; GFX8-NEXT: v_mov_b32_e32 v11, s38 ; GFX8-NEXT: v_mov_b32_e32 v22, s38
; GFX8-NEXT: v_mov_b32_e32 v12, s39 ; GFX8-NEXT: v_mov_b32_e32 v23, s39
; GFX8-NEXT: v_mov_b32_e32 v13, s40 ; GFX8-NEXT: v_mov_b32_e32 v24, s40
; GFX8-NEXT: v_mov_b32_e32 v14, s41 ; GFX8-NEXT: v_mov_b32_e32 v25, s41
; GFX8-NEXT: s_addc_u32 s15, s1, 0 ; GFX8-NEXT: s_addc_u32 s15, s1, 0
; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[11:14] ; GFX8-NEXT: flat_store_dwordx4 v[26:27], v[22:25]
; GFX8-NEXT: v_mov_b32_e32 v16, s15 ; GFX8-NEXT: v_mov_b32_e32 v27, s15
; GFX8-NEXT: v_mov_b32_e32 v15, s14 ; GFX8-NEXT: v_mov_b32_e32 v26, s14
; GFX8-NEXT: s_add_u32 s14, s0, 0x80 ; GFX8-NEXT: s_add_u32 s14, s0, 0x80
; GFX8-NEXT: v_mov_b32_e32 v11, s42 ; GFX8-NEXT: v_mov_b32_e32 v22, s42
; GFX8-NEXT: v_mov_b32_e32 v12, s43 ; GFX8-NEXT: v_mov_b32_e32 v23, s43
; GFX8-NEXT: v_mov_b32_e32 v13, s44 ; GFX8-NEXT: v_mov_b32_e32 v24, s44
; GFX8-NEXT: v_mov_b32_e32 v14, s45 ; GFX8-NEXT: v_mov_b32_e32 v25, s45
; GFX8-NEXT: s_addc_u32 s15, s1, 0 ; GFX8-NEXT: s_addc_u32 s15, s1, 0
; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[11:14] ; GFX8-NEXT: flat_store_dwordx4 v[26:27], v[22:25]
; GFX8-NEXT: v_mov_b32_e32 v16, s15 ; GFX8-NEXT: v_mov_b32_e32 v27, s15
; GFX8-NEXT: v_mov_b32_e32 v15, s14 ; GFX8-NEXT: v_mov_b32_e32 v26, s14
; GFX8-NEXT: s_add_u32 s14, s0, 0x70 ; GFX8-NEXT: s_add_u32 s14, s0, 0x70
; GFX8-NEXT: v_mov_b32_e32 v11, s46 ; GFX8-NEXT: v_mov_b32_e32 v22, s46
; GFX8-NEXT: v_mov_b32_e32 v12, s47 ; GFX8-NEXT: v_mov_b32_e32 v23, s47
; GFX8-NEXT: v_mov_b32_e32 v13, s48 ; GFX8-NEXT: v_mov_b32_e32 v24, s48
; GFX8-NEXT: v_mov_b32_e32 v14, s49 ; GFX8-NEXT: v_mov_b32_e32 v25, s49
; GFX8-NEXT: s_addc_u32 s15, s1, 0 ; GFX8-NEXT: s_addc_u32 s15, s1, 0
; GFX8-NEXT: v_lshrrev_b16_e64 v9, 14, s4 ; GFX8-NEXT: v_lshrrev_b16_e64 v20, 14, s6
; GFX8-NEXT: v_lshrrev_b16_e64 v10, 15, s4 ; GFX8-NEXT: v_lshrrev_b16_e64 v21, 15, s6
; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[11:14] ; GFX8-NEXT: flat_store_dwordx4 v[26:27], v[22:25]
; GFX8-NEXT: v_mov_b32_e32 v16, s15 ; GFX8-NEXT: v_bfe_i32 v20, v20, 0, 1
; GFX8-NEXT: v_bfe_i32 v11, v10, 0, 1 ; GFX8-NEXT: v_mov_b32_e32 v25, s15
; GFX8-NEXT: v_bfe_i32 v9, v9, 0, 1 ; GFX8-NEXT: v_bfe_i32 v22, v21, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v15, s14 ; GFX8-NEXT: v_mov_b32_e32 v24, s14
; GFX8-NEXT: s_add_u32 s14, s0, 0x60 ; GFX8-NEXT: s_add_u32 s14, s0, 0x60
; GFX8-NEXT: v_ashrrev_i32_e32 v12, 31, v11 ; GFX8-NEXT: v_ashrrev_i32_e32 v23, 31, v22
; GFX8-NEXT: v_ashrrev_i32_e32 v10, 31, v9 ; GFX8-NEXT: v_ashrrev_i32_e32 v21, 31, v20
; GFX8-NEXT: s_addc_u32 s15, s1, 0 ; GFX8-NEXT: s_addc_u32 s15, s1, 0
; GFX8-NEXT: v_lshrrev_b16_e64 v7, 12, s4 ; GFX8-NEXT: v_lshrrev_b16_e64 v18, 12, s6
; GFX8-NEXT: v_lshrrev_b16_e64 v8, 13, s4 ; GFX8-NEXT: v_lshrrev_b16_e64 v19, 13, s6
; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[9:12] ; GFX8-NEXT: flat_store_dwordx4 v[24:25], v[20:23]
; GFX8-NEXT: v_mov_b32_e32 v16, s15 ; GFX8-NEXT: v_bfe_i32 v18, v18, 0, 1
; GFX8-NEXT: v_bfe_i32 v9, v8, 0, 1 ; GFX8-NEXT: v_mov_b32_e32 v23, s15
; GFX8-NEXT: v_bfe_i32 v7, v7, 0, 1 ; GFX8-NEXT: v_bfe_i32 v20, v19, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v15, s14 ; GFX8-NEXT: v_mov_b32_e32 v22, s14
; GFX8-NEXT: s_add_u32 s14, s0, 0x50 ; GFX8-NEXT: s_add_u32 s14, s0, 0x50
; GFX8-NEXT: v_ashrrev_i32_e32 v10, 31, v9 ; GFX8-NEXT: v_lshrrev_b16_e64 v16, 10, s6
; GFX8-NEXT: v_ashrrev_i32_e32 v8, 31, v7 ; GFX8-NEXT: v_lshrrev_b16_e64 v17, 11, s6
; GFX8-NEXT: v_ashrrev_i32_e32 v21, 31, v20
; GFX8-NEXT: v_ashrrev_i32_e32 v19, 31, v18
; GFX8-NEXT: s_addc_u32 s15, s1, 0 ; GFX8-NEXT: s_addc_u32 s15, s1, 0
; GFX8-NEXT: v_lshrrev_b16_e64 v5, 10, s4 ; GFX8-NEXT: flat_store_dwordx4 v[22:23], v[18:21]
; GFX8-NEXT: v_lshrrev_b16_e64 v6, 11, s4 ; GFX8-NEXT: v_bfe_i32 v16, v16, 0, 1
; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[7:10] ; GFX8-NEXT: v_bfe_i32 v18, v17, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v16, s15 ; GFX8-NEXT: v_mov_b32_e32 v21, s15
; GFX8-NEXT: v_bfe_i32 v7, v6, 0, 1 ; GFX8-NEXT: v_lshrrev_b16_e64 v14, 8, s6
; GFX8-NEXT: v_lshrrev_b16_e64 v15, 9, s6
; GFX8-NEXT: v_lshrrev_b16_e64 v12, 6, s6
; GFX8-NEXT: v_lshrrev_b16_e64 v13, 7, s6
; GFX8-NEXT: v_lshrrev_b16_e64 v10, 4, s6
; GFX8-NEXT: v_lshrrev_b16_e64 v11, 5, s6
; GFX8-NEXT: v_lshrrev_b16_e64 v8, 2, s6
; GFX8-NEXT: v_lshrrev_b16_e64 v9, 3, s6
; GFX8-NEXT: v_lshrrev_b16_e64 v7, 1, s6
; GFX8-NEXT: v_ashrrev_i32_e32 v19, 31, v18
; GFX8-NEXT: v_ashrrev_i32_e32 v17, 31, v16
; GFX8-NEXT: v_mov_b32_e32 v20, s14
; GFX8-NEXT: s_add_u32 s6, s0, 64
; GFX8-NEXT: v_lshrrev_b16_e64 v5, 14, s7
; GFX8-NEXT: v_lshrrev_b16_e64 v6, 15, s7
; GFX8-NEXT: v_lshrrev_b16_e64 v3, 12, s7
; GFX8-NEXT: v_lshrrev_b16_e64 v4, 13, s7
; GFX8-NEXT: v_lshrrev_b16_e64 v1, 10, s7
; GFX8-NEXT: v_lshrrev_b16_e64 v2, 11, s7
; GFX8-NEXT: v_lshrrev_b16_e64 v0, 8, s7
; GFX8-NEXT: v_lshrrev_b16_e64 v26, 9, s7
; GFX8-NEXT: v_lshrrev_b16_e64 v27, 6, s7
; GFX8-NEXT: v_lshrrev_b16_e64 v24, 7, s7
; GFX8-NEXT: v_lshrrev_b16_e64 v25, 4, s7
; GFX8-NEXT: v_lshrrev_b16_e64 v22, 5, s7
; GFX8-NEXT: v_lshrrev_b16_e64 v23, 2, s7
; GFX8-NEXT: flat_store_dwordx4 v[20:21], v[16:19]
; GFX8-NEXT: v_lshrrev_b16_e64 v20, 3, s7
; GFX8-NEXT: v_lshrrev_b16_e64 v21, 1, s7
; GFX8-NEXT: s_addc_u32 s7, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v19, s7
; GFX8-NEXT: v_bfe_i32 v16, v15, 0, 1
; GFX8-NEXT: v_bfe_i32 v14, v14, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v18, s6
; GFX8-NEXT: s_add_u32 s6, s0, 48
; GFX8-NEXT: v_ashrrev_i32_e32 v17, 31, v16
; GFX8-NEXT: v_ashrrev_i32_e32 v15, 31, v14
; GFX8-NEXT: s_addc_u32 s7, s1, 0
; GFX8-NEXT: flat_store_dwordx4 v[18:19], v[14:17]
; GFX8-NEXT: v_bfe_i32 v12, v12, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v17, s7
; GFX8-NEXT: v_bfe_i32 v14, v13, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v16, s6
; GFX8-NEXT: s_add_u32 s6, s0, 32
; GFX8-NEXT: v_ashrrev_i32_e32 v15, 31, v14
; GFX8-NEXT: v_ashrrev_i32_e32 v13, 31, v12
; GFX8-NEXT: s_addc_u32 s7, s1, 0
; GFX8-NEXT: flat_store_dwordx4 v[16:17], v[12:15]
; GFX8-NEXT: v_bfe_i32 v10, v10, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v15, s7
; GFX8-NEXT: v_bfe_i32 v12, v11, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v14, s6
; GFX8-NEXT: s_add_u32 s6, s0, 16
; GFX8-NEXT: v_ashrrev_i32_e32 v13, 31, v12
; GFX8-NEXT: v_ashrrev_i32_e32 v11, 31, v10
; GFX8-NEXT: s_addc_u32 s7, s1, 0
; GFX8-NEXT: flat_store_dwordx4 v[14:15], v[10:13]
; GFX8-NEXT: v_bfe_i32 v8, v8, 0, 1
; GFX8-NEXT: v_bfe_i32 v10, v9, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v13, s7
; GFX8-NEXT: v_ashrrev_i32_e32 v11, 31, v10
; GFX8-NEXT: v_ashrrev_i32_e32 v9, 31, v8
; GFX8-NEXT: v_mov_b32_e32 v12, s6
; GFX8-NEXT: flat_store_dwordx4 v[12:13], v[8:11]
; GFX8-NEXT: v_mov_b32_e32 v12, s1
; GFX8-NEXT: v_bfe_i32 v9, v7, 0, 1
; GFX8-NEXT: s_add_u32 s6, s0, 0x170
; GFX8-NEXT: v_ashrrev_i32_e32 v10, 31, v9
; GFX8-NEXT: v_mov_b32_e32 v7, s18
; GFX8-NEXT: v_mov_b32_e32 v8, s19
; GFX8-NEXT: v_mov_b32_e32 v11, s0
; GFX8-NEXT: s_addc_u32 s7, s1, 0
; GFX8-NEXT: flat_store_dwordx4 v[11:12], v[7:10]
; GFX8-NEXT: v_bfe_i32 v5, v5, 0, 1 ; GFX8-NEXT: v_bfe_i32 v5, v5, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v15, s14 ; GFX8-NEXT: v_mov_b32_e32 v10, s7
; GFX8-NEXT: s_add_u32 s14, s0, 64 ; GFX8-NEXT: v_bfe_i32 v7, v6, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v9, s6
; GFX8-NEXT: s_add_u32 s6, s0, 0x160
; GFX8-NEXT: v_ashrrev_i32_e32 v8, 31, v7 ; GFX8-NEXT: v_ashrrev_i32_e32 v8, 31, v7
; GFX8-NEXT: v_ashrrev_i32_e32 v6, 31, v5 ; GFX8-NEXT: v_ashrrev_i32_e32 v6, 31, v5
; GFX8-NEXT: s_addc_u32 s15, s1, 0 ; GFX8-NEXT: s_addc_u32 s7, s1, 0
; GFX8-NEXT: v_lshrrev_b16_e64 v3, 8, s4 ; GFX8-NEXT: flat_store_dwordx4 v[9:10], v[5:8]
; GFX8-NEXT: v_lshrrev_b16_e64 v4, 9, s4
; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[5:8]
; GFX8-NEXT: v_mov_b32_e32 v16, s15
; GFX8-NEXT: v_bfe_i32 v5, v4, 0, 1
; GFX8-NEXT: v_bfe_i32 v3, v3, 0, 1 ; GFX8-NEXT: v_bfe_i32 v3, v3, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v15, s14 ; GFX8-NEXT: v_bfe_i32 v5, v4, 0, 1
; GFX8-NEXT: s_add_u32 s14, s0, 48 ; GFX8-NEXT: v_mov_b32_e32 v8, s7
; GFX8-NEXT: v_ashrrev_i32_e32 v6, 31, v5 ; GFX8-NEXT: v_ashrrev_i32_e32 v6, 31, v5
; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v3 ; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v3
; GFX8-NEXT: s_addc_u32 s15, s1, 0 ; GFX8-NEXT: v_mov_b32_e32 v7, s6
; GFX8-NEXT: v_lshrrev_b16_e64 v1, 6, s4 ; GFX8-NEXT: s_add_u32 s6, s0, 0x150
; GFX8-NEXT: v_lshrrev_b16_e64 v2, 7, s4 ; GFX8-NEXT: flat_store_dwordx4 v[7:8], v[3:6]
; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[3:6]
; GFX8-NEXT: v_mov_b32_e32 v16, s15
; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 1
; GFX8-NEXT: v_bfe_i32 v1, v1, 0, 1 ; GFX8-NEXT: v_bfe_i32 v1, v1, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v15, s14 ; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 1
; GFX8-NEXT: s_add_u32 s14, s0, 32 ; GFX8-NEXT: s_addc_u32 s7, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v5, s6
; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v3 ; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v3
; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v1 ; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v1
; GFX8-NEXT: s_addc_u32 s15, s1, 0 ; GFX8-NEXT: v_mov_b32_e32 v6, s7
; GFX8-NEXT: v_lshrrev_b16_e64 v0, 4, s4 ; GFX8-NEXT: s_add_u32 s6, s0, 0x140
; GFX8-NEXT: v_lshrrev_b16_e64 v13, 5, s4 ; GFX8-NEXT: flat_store_dwordx4 v[5:6], v[1:4]
; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[1:4]
; GFX8-NEXT: v_mov_b32_e32 v17, s15
; GFX8-NEXT: v_bfe_i32 v2, v13, 0, 1
; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 1 ; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v16, s14 ; GFX8-NEXT: v_bfe_i32 v2, v26, 0, 1
; GFX8-NEXT: s_add_u32 s14, s0, 16 ; GFX8-NEXT: s_addc_u32 s7, s1, 0
; GFX8-NEXT: v_lshrrev_b16_e64 v14, 2, s4 ; GFX8-NEXT: v_mov_b32_e32 v4, s6
; GFX8-NEXT: v_lshrrev_b16_e64 v11, 3, s4 ; GFX8-NEXT: v_lshrrev_b16_e64 v6, 1, s8
; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX8-NEXT: s_addc_u32 s15, s1, 0
; GFX8-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v18, s15
; GFX8-NEXT: v_bfe_i32 v2, v11, 0, 1
; GFX8-NEXT: v_bfe_i32 v0, v14, 0, 1
; GFX8-NEXT: v_lshrrev_b16_e64 v12, 1, s4
; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX8-NEXT: v_mov_b32_e32 v17, s14
; GFX8-NEXT: flat_store_dwordx4 v[17:18], v[0:3]
; GFX8-NEXT: v_mov_b32_e32 v18, s1
; GFX8-NEXT: v_bfe_i32 v2, v12, 0, 1
; GFX8-NEXT: v_lshrrev_b16_e64 v9, 14, s5
; GFX8-NEXT: v_lshrrev_b16_e64 v10, 15, s5
; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX8-NEXT: v_mov_b32_e32 v0, s18
; GFX8-NEXT: v_mov_b32_e32 v1, s19
; GFX8-NEXT: v_mov_b32_e32 v17, s0
; GFX8-NEXT: s_add_u32 s14, s0, 0x170
; GFX8-NEXT: flat_store_dwordx4 v[17:18], v[0:3]
; GFX8-NEXT: s_addc_u32 s15, s1, 0
; GFX8-NEXT: v_bfe_i32 v2, v10, 0, 1
; GFX8-NEXT: v_bfe_i32 v0, v9, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v9, s14
; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX8-NEXT: v_mov_b32_e32 v10, s15
; GFX8-NEXT: s_add_u32 s4, s0, 0x160
; GFX8-NEXT: v_lshrrev_b16_e64 v7, 12, s5
; GFX8-NEXT: v_lshrrev_b16_e64 v8, 13, s5
; GFX8-NEXT: v_lshrrev_b16_e64 v5, 10, s5
; GFX8-NEXT: v_lshrrev_b16_e64 v6, 11, s5
; GFX8-NEXT: v_lshrrev_b16_e64 v4, 8, s5
; GFX8-NEXT: v_lshrrev_b16_e64 v15, 9, s5
; GFX8-NEXT: v_lshrrev_b16_e64 v13, 6, s5
; GFX8-NEXT: v_lshrrev_b16_e64 v16, 7, s5
; GFX8-NEXT: v_lshrrev_b16_e64 v11, 4, s5
; GFX8-NEXT: v_lshrrev_b16_e64 v12, 5, s5
; GFX8-NEXT: v_lshrrev_b16_e64 v14, 2, s5
; GFX8-NEXT: flat_store_dwordx4 v[9:10], v[0:3]
; GFX8-NEXT: v_lshrrev_b16_e64 v9, 3, s5
; GFX8-NEXT: v_lshrrev_b16_e64 v10, 1, s5
; GFX8-NEXT: s_addc_u32 s5, s1, 0
; GFX8-NEXT: v_bfe_i32 v2, v8, 0, 1
; GFX8-NEXT: v_bfe_i32 v0, v7, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v8, s5
; GFX8-NEXT: v_mov_b32_e32 v7, s4
; GFX8-NEXT: s_add_u32 s4, s0, 0x150
; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX8-NEXT: s_addc_u32 s5, s1, 0
; GFX8-NEXT: flat_store_dwordx4 v[7:8], v[0:3]
; GFX8-NEXT: v_lshrrev_b16_e64 v7, 6, s10
; GFX8-NEXT: v_bfe_i32 v2, v6, 0, 1
; GFX8-NEXT: v_bfe_i32 v0, v5, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v6, s5
; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX8-NEXT: v_mov_b32_e32 v5, s4
; GFX8-NEXT: s_add_u32 s4, s0, 0x140
; GFX8-NEXT: flat_store_dwordx4 v[5:6], v[0:3]
; GFX8-NEXT: s_addc_u32 s5, s1, 0
; GFX8-NEXT: v_bfe_i32 v2, v15, 0, 1
; GFX8-NEXT: v_bfe_i32 v0, v4, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: s_add_u32 s4, s0, 0x130
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s5, s1, 0
; GFX8-NEXT: v_bfe_i32 v2, v16, 0, 1
; GFX8-NEXT: v_bfe_i32 v0, v13, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: s_add_u32 s4, s0, 0x120
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s5, s1, 0
; GFX8-NEXT: v_bfe_i32 v2, v12, 0, 1
; GFX8-NEXT: v_bfe_i32 v0, v11, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX8-NEXT: v_mov_b32_e32 v5, s5
; GFX8-NEXT: s_add_u32 s4, s0, 0x110
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s5, s1, 0
; GFX8-NEXT: v_bfe_i32 v2, v9, 0, 1
; GFX8-NEXT: v_bfe_i32 v0, v14, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2 ; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX8-NEXT: v_mov_b32_e32 v5, s5 ; GFX8-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NEXT: s_add_u32 s4, s0, 0x100 ; GFX8-NEXT: s_add_u32 s6, s0, 0x130
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3] ; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_addc_u32 s5, s1, 0 ; GFX8-NEXT: v_bfe_i32 v4, v27, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v4, s4 ; GFX8-NEXT: v_bfe_i32 v2, v6, 0, 1
; GFX8-NEXT: v_bfe_i32 v2, v10, 0, 1 ; GFX8-NEXT: v_bfe_i32 v6, v24, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v5, s5 ; GFX8-NEXT: s_addc_u32 s7, s1, 0
; GFX8-NEXT: s_add_u32 s4, s0, 0x1f0 ; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_lshrrev_b16_e64 v8, 7, s10 ; GFX8-NEXT: v_lshrrev_b16_e64 v8, 2, s8
; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2 ; GFX8-NEXT: v_ashrrev_i32_e32 v7, 31, v6
; GFX8-NEXT: v_mov_b32_e32 v0, s12 ; GFX8-NEXT: v_ashrrev_i32_e32 v5, 31, v4
; GFX8-NEXT: v_mov_b32_e32 v1, s13 ; GFX8-NEXT: v_mov_b32_e32 v1, s7
; GFX8-NEXT: s_addc_u32 s5, s1, 0 ; GFX8-NEXT: s_add_u32 s6, s0, 0x120
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3] ; GFX8-NEXT: v_lshrrev_b16_e64 v9, 3, s8
; GFX8-NEXT: v_lshrrev_b16_e64 v17, 4, s10 ; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GFX8-NEXT: v_bfe_i32 v2, v8, 0, 1 ; GFX8-NEXT: v_bfe_i32 v10, v22, 0, 1
; GFX8-NEXT: v_bfe_i32 v0, v7, 0, 1 ; GFX8-NEXT: v_bfe_i32 v4, v8, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v7, s5 ; GFX8-NEXT: v_bfe_i32 v8, v25, 0, 1
; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2 ; GFX8-NEXT: s_addc_u32 s7, s1, 0
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_mov_b32_e32 v6, s4 ; GFX8-NEXT: v_lshrrev_b16_e64 v12, 4, s8
; GFX8-NEXT: v_lshrrev_b16_e64 v18, 5, s10 ; GFX8-NEXT: v_bfe_i32 v6, v9, 0, 1
; GFX8-NEXT: flat_store_dwordx4 v[6:7], v[0:3] ; GFX8-NEXT: v_ashrrev_i32_e32 v11, 31, v10
; GFX8-NEXT: s_add_u32 s4, s0, 0x1e0 ; GFX8-NEXT: v_ashrrev_i32_e32 v9, 31, v8
; GFX8-NEXT: v_lshrrev_b16_e64 v0, 1, s6 ; GFX8-NEXT: v_mov_b32_e32 v1, s7
; GFX8-NEXT: v_bfe_i32 v2, v0, 0, 1 ; GFX8-NEXT: s_add_u32 s6, s0, 0x110
; GFX8-NEXT: v_lshrrev_b16_e64 v13, 5, s8
; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
; GFX8-NEXT: v_bfe_i32 v14, v20, 0, 1
; GFX8-NEXT: v_bfe_i32 v8, v12, 0, 1
; GFX8-NEXT: v_bfe_i32 v12, v23, 0, 1
; GFX8-NEXT: s_addc_u32 s7, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_bfe_i32 v10, v13, 0, 1
; GFX8-NEXT: v_ashrrev_i32_e32 v15, 31, v14
; GFX8-NEXT: v_ashrrev_i32_e32 v13, 31, v12
; GFX8-NEXT: v_mov_b32_e32 v1, s7
; GFX8-NEXT: s_add_u32 s6, s0, 0x100
; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[12:15]
; GFX8-NEXT: s_addc_u32 s7, s1, 0
; GFX8-NEXT: v_bfe_i32 v14, v21, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_lshrrev_b16_e64 v28, 6, s12
; GFX8-NEXT: v_lshrrev_b16_e64 v18, 7, s12
; GFX8-NEXT: v_lshrrev_b16_e64 v16, 6, s8
; GFX8-NEXT: v_ashrrev_i32_e32 v15, 31, v14
; GFX8-NEXT: v_mov_b32_e32 v12, s10
; GFX8-NEXT: v_mov_b32_e32 v13, s11
; GFX8-NEXT: v_mov_b32_e32 v1, s7
; GFX8-NEXT: s_add_u32 s6, s0, 0x1f0
; GFX8-NEXT: v_lshrrev_b16_e64 v17, 7, s8
; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[12:15]
; GFX8-NEXT: v_bfe_i32 v18, v18, 0, 1 ; GFX8-NEXT: v_bfe_i32 v18, v18, 0, 1
; GFX8-NEXT: v_bfe_i32 v16, v17, 0, 1 ; GFX8-NEXT: v_bfe_i32 v12, v16, 0, 1
; GFX8-NEXT: s_addc_u32 s5, s1, 0 ; GFX8-NEXT: v_bfe_i32 v16, v28, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v0, s4 ; GFX8-NEXT: s_addc_u32 s7, s1, 0
; GFX8-NEXT: v_lshrrev_b16_e64 v20, 2, s10 ; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_lshrrev_b16_e64 v21, 3, s10 ; GFX8-NEXT: v_lshrrev_b16_e64 v29, 4, s12
; GFX8-NEXT: v_lshrrev_b16_e64 v22, 1, s10 ; GFX8-NEXT: v_lshrrev_b16_e64 v30, 5, s12
; GFX8-NEXT: v_bfe_i32 v14, v17, 0, 1
; GFX8-NEXT: v_ashrrev_i32_e32 v19, 31, v18 ; GFX8-NEXT: v_ashrrev_i32_e32 v19, 31, v18
; GFX8-NEXT: v_ashrrev_i32_e32 v17, 31, v16 ; GFX8-NEXT: v_ashrrev_i32_e32 v17, 31, v16
; GFX8-NEXT: v_mov_b32_e32 v1, s5 ; GFX8-NEXT: v_mov_b32_e32 v1, s7
; GFX8-NEXT: s_add_u32 s4, s0, 0x1d0 ; GFX8-NEXT: s_add_u32 s6, s0, 0x1e0
; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[16:19] ; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[16:19]
; GFX8-NEXT: v_bfe_i32 v20, v20, 0, 1 ; GFX8-NEXT: v_bfe_i32 v22, v30, 0, 1
; GFX8-NEXT: v_bfe_i32 v18, v22, 0, 1 ; GFX8-NEXT: v_bfe_i32 v20, v29, 0, 1
; GFX8-NEXT: v_bfe_i32 v22, v21, 0, 1 ; GFX8-NEXT: s_addc_u32 s7, s1, 0
; GFX8-NEXT: s_addc_u32 s5, s1, 0 ; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_mov_b32_e32 v0, s4 ; GFX8-NEXT: v_lshrrev_b16_e64 v31, 2, s12
; GFX8-NEXT: v_lshrrev_b16_e64 v32, 3, s12
; GFX8-NEXT: v_ashrrev_i32_e32 v23, 31, v22 ; GFX8-NEXT: v_ashrrev_i32_e32 v23, 31, v22
; GFX8-NEXT: v_ashrrev_i32_e32 v21, 31, v20 ; GFX8-NEXT: v_ashrrev_i32_e32 v21, 31, v20
; GFX8-NEXT: v_mov_b32_e32 v1, s5 ; GFX8-NEXT: v_mov_b32_e32 v1, s7
; GFX8-NEXT: s_add_u32 s6, s0, 0x1d0
; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[20:23]
; GFX8-NEXT: s_addc_u32 s7, s1, 0
; GFX8-NEXT: v_bfe_i32 v22, v32, 0, 1
; GFX8-NEXT: v_bfe_i32 v20, v31, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v0, s6
; GFX8-NEXT: v_lshrrev_b16_e64 v33, 1, s12
; GFX8-NEXT: v_ashrrev_i32_e32 v23, 31, v22
; GFX8-NEXT: v_ashrrev_i32_e32 v21, 31, v20
; GFX8-NEXT: v_mov_b32_e32 v1, s7
; GFX8-NEXT: v_mov_b32_e32 v16, s4
; GFX8-NEXT: s_add_u32 s4, s0, 0x1c0 ; GFX8-NEXT: s_add_u32 s4, s0, 0x1c0
; GFX8-NEXT: v_bfe_i32 v18, v33, 0, 1
; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[20:23] ; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[20:23]
; GFX8-NEXT: v_mov_b32_e32 v17, s5
; GFX8-NEXT: s_addc_u32 s5, s1, 0 ; GFX8-NEXT: s_addc_u32 s5, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v0, s4 ; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_lshrrev_b16_e64 v13, 6, s6
; GFX8-NEXT: v_lshrrev_b16_e64 v12, 7, s6
; GFX8-NEXT: v_ashrrev_i32_e32 v19, 31, v18 ; GFX8-NEXT: v_ashrrev_i32_e32 v19, 31, v18
; GFX8-NEXT: v_mov_b32_e32 v16, s8
; GFX8-NEXT: v_mov_b32_e32 v17, s9
; GFX8-NEXT: v_mov_b32_e32 v1, s5 ; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_add_u32 s4, s0, 0xf0 ; GFX8-NEXT: s_add_u32 s4, s0, 0xf0
; GFX8-NEXT: v_lshrrev_b16_e64 v15, 4, s6
; GFX8-NEXT: v_bfe_i32 v14, v12, 0, 1
; GFX8-NEXT: v_bfe_i32 v12, v13, 0, 1
; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[16:19] ; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[16:19]
; GFX8-NEXT: s_addc_u32 s5, s1, 0 ; GFX8-NEXT: s_addc_u32 s5, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v0, s4 ; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_bfe_i32 v8, v15, 0, 1
; GFX8-NEXT: v_ashrrev_i32_e32 v15, 31, v14 ; GFX8-NEXT: v_ashrrev_i32_e32 v15, 31, v14
; GFX8-NEXT: v_ashrrev_i32_e32 v13, 31, v12 ; GFX8-NEXT: v_ashrrev_i32_e32 v13, 31, v12
; GFX8-NEXT: v_mov_b32_e32 v1, s5 ; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_add_u32 s4, s0, 0xe0 ; GFX8-NEXT: s_add_u32 s4, s0, 0xe0
; GFX8-NEXT: v_lshrrev_b16_e64 v9, 5, s6
; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[12:15] ; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[12:15]
; GFX8-NEXT: s_addc_u32 s5, s1, 0 ; GFX8-NEXT: s_addc_u32 s5, s1, 0
; GFX8-NEXT: v_mov_b32_e32 v0, s4 ; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_bfe_i32 v10, v9, 0, 1
; GFX8-NEXT: v_mov_b32_e32 v1, s5 ; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_add_u32 s4, s0, 0xd0 ; GFX8-NEXT: s_add_u32 s4, s0, 0xd0
; GFX8-NEXT: v_lshrrev_b16_e64 v4, 2, s6
; GFX8-NEXT: v_lshrrev_b16_e64 v5, 3, s6
; GFX8-NEXT: v_ashrrev_i32_e32 v11, 31, v10 ; GFX8-NEXT: v_ashrrev_i32_e32 v11, 31, v10
; GFX8-NEXT: v_ashrrev_i32_e32 v9, 31, v8 ; GFX8-NEXT: v_ashrrev_i32_e32 v9, 31, v8
; GFX8-NEXT: s_addc_u32 s5, s1, 0 ; GFX8-NEXT: s_addc_u32 s5, s1, 0
; GFX8-NEXT: v_bfe_i32 v6, v5, 0, 1
; GFX8-NEXT: v_bfe_i32 v4, v4, 0, 1
; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[8:11] ; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
; GFX8-NEXT: v_mov_b32_e32 v0, s4 ; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: s_add_u32 s0, s0, 0xc0 ; GFX8-NEXT: s_add_u32 s0, s0, 0xc0
; GFX8-NEXT: v_ashrrev_i32_e32 v7, 31, v6 ; GFX8-NEXT: v_ashrrev_i32_e32 v7, 31, v6
; GFX8-NEXT: v_ashrrev_i32_e32 v5, 31, v4 ; GFX8-NEXT: v_ashrrev_i32_e32 v5, 31, v4
; GFX8-NEXT: v_mov_b32_e32 v1, s5 ; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: s_addc_u32 s1, s1, 0 ; GFX8-NEXT: s_addc_u32 s1, s1, 0
; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7] ; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
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llvm/test/CodeGen/AMDGPU/load-constant-i32.ll

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define amdgpu_kernel void @constant_sextload_v2i32_to_v2i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 { define amdgpu_kernel void @constant_sextload_v2i32_to_v2i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
; GFX6-NOHSA-LABEL: constant_sextload_v2i32_to_v2i64: ; GFX6-NOHSA-LABEL: constant_sextload_v2i32_to_v2i64:
; GFX6-NOHSA: ; %bb.0: ; GFX6-NOHSA: ; %bb.0:
; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NOHSA-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 ; GFX6-NOHSA-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NOHSA-NEXT: s_ashr_i32 s7, s5, 31 ; GFX6-NOHSA-NEXT: s_ashr_i32 s6, s5, 31
; GFX6-NOHSA-NEXT: s_ashr_i32 s8, s4, 31 ; GFX6-NOHSA-NEXT: s_ashr_i32 s7, s4, 31
; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1 ; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4 ; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s5 ; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s5
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s8 ; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s7
; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s7 ; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s6
; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX6-NOHSA-NEXT: s_endpgm ; GFX6-NOHSA-NEXT: s_endpgm
; ;
; GFX7-HSA-LABEL: constant_sextload_v2i32_to_v2i64: ; GFX7-HSA-LABEL: constant_sextload_v2i32_to_v2i64:
; GFX7-HSA: ; %bb.0: ; GFX7-HSA: ; %bb.0:
; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-HSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; GFX7-HSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0 ; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1 ; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-HSA-NEXT: s_ashr_i32 s1, s3, 31 ; GFX7-HSA-NEXT: s_ashr_i32 s0, s3, 31
; GFX7-HSA-NEXT: s_mov_b32 s0, s3 ; GFX7-HSA-NEXT: s_mov_b32 s1, s3
; GFX7-HSA-NEXT: s_ashr_i32 s3, s2, 31 ; GFX7-HSA-NEXT: s_ashr_i32 s3, s2, 31
; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2 ; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3 ; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s0 ; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s1
; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s1 ; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s0
; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3] ; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX7-HSA-NEXT: s_endpgm ; GFX7-HSA-NEXT: s_endpgm
; ;
; GFX8-NOHSA-LABEL: constant_sextload_v2i32_to_v2i64: ; GFX8-NOHSA-LABEL: constant_sextload_v2i32_to_v2i64:
; GFX8-NOHSA: ; %bb.0: ; GFX8-NOHSA: ; %bb.0:
; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NOHSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; GFX8-NOHSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NOHSA-NEXT: s_ashr_i32 s1, s3, 31 ; GFX8-NOHSA-NEXT: s_ashr_i32 s0, s3, 31
; GFX8-NOHSA-NEXT: s_mov_b32 s0, s3 ; GFX8-NOHSA-NEXT: s_mov_b32 s1, s3
; GFX8-NOHSA-NEXT: s_ashr_i32 s3, s2, 31 ; GFX8-NOHSA-NEXT: s_ashr_i32 s3, s2, 31
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s0 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s1
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s1 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s0
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3] ; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NOHSA-NEXT: s_endpgm ; GFX8-NOHSA-NEXT: s_endpgm
; ;
; EG-LABEL: constant_sextload_v2i32_to_v2i64: ; EG-LABEL: constant_sextload_v2i32_to_v2i64:
; EG: ; %bb.0: ; EG: ; %bb.0:
; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 0 @6 ; EG-NEXT: TEX 0 @6
; EG-NEXT: ALU 7, @9, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 7, @9, KC0[CB0:0-32], KC1[]
Show All 16 Lines
; ;
; GFX9-HSA-LABEL: constant_sextload_v2i32_to_v2i64: ; GFX9-HSA-LABEL: constant_sextload_v2i32_to_v2i64:
; GFX9-HSA: ; %bb.0: ; GFX9-HSA: ; %bb.0:
; GFX9-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; GFX9-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX9-HSA-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-HSA-NEXT: v_mov_b32_e32 v4, 0
; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-HSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; GFX9-HSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-HSA-NEXT: s_ashr_i32 s5, s3, 31 ; GFX9-HSA-NEXT: s_ashr_i32 s4, s3, 31
; GFX9-HSA-NEXT: s_mov_b32 s4, s3 ; GFX9-HSA-NEXT: s_ashr_i32 s5, s2, 31
; GFX9-HSA-NEXT: s_ashr_i32 s3, s2, 31
; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s2
; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s5
; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s4 ; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s3
; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s5 ; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s4
; GFX9-HSA-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] ; GFX9-HSA-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX9-HSA-NEXT: s_endpgm ; GFX9-HSA-NEXT: s_endpgm
%ld = load <2 x i32>, ptr addrspace(4) %in %ld = load <2 x i32>, ptr addrspace(4) %in
%ext = sext <2 x i32> %ld to <2 x i64> %ext = sext <2 x i32> %ld to <2 x i64>
store <2 x i64> %ext, ptr addrspace(1) %out store <2 x i64> %ext, ptr addrspace(1) %out
ret void ret void
} }
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llvm/test/CodeGen/AMDGPU/load-constant-i8.ll

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; GFX8-NOHSA-NEXT: s_lshr_b32 s46, s2, 24 ; GFX8-NOHSA-NEXT: s_lshr_b32 s46, s2, 24
; GFX8-NOHSA-NEXT: s_lshr_b32 s26, s1, 16 ; GFX8-NOHSA-NEXT: s_lshr_b32 s26, s1, 16
; GFX8-NOHSA-NEXT: s_lshr_b32 s22, s0, 16 ; GFX8-NOHSA-NEXT: s_lshr_b32 s22, s0, 16
; GFX8-NOHSA-NEXT: s_lshr_b32 s20, s0, 24 ; GFX8-NOHSA-NEXT: s_lshr_b32 s20, s0, 24
; GFX8-NOHSA-NEXT: s_mov_b32 s48, s7 ; GFX8-NOHSA-NEXT: s_mov_b32 s48, s7
; GFX8-NOHSA-NEXT: s_mov_b32 s50, s5 ; GFX8-NOHSA-NEXT: s_mov_b32 s50, s5
; GFX8-NOHSA-NEXT: s_mov_b32 s52, s3 ; GFX8-NOHSA-NEXT: s_mov_b32 s52, s3
; GFX8-NOHSA-NEXT: s_mov_b32 s54, s1 ; GFX8-NOHSA-NEXT: s_mov_b32 s54, s1
; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v5, 8, s7 ; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v4, 8, s7
; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v1, 8, s6 ; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v1, 8, s6
; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v0, 8, s5 ; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v0, 8, s5
; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v4, 8, s4 ; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v5, 8, s4
; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v8, 8, s3 ; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v8, 8, s3
; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v9, 8, s2 ; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v9, 8, s2
; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v6, 8, s1 ; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v6, 8, s1
; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v2, 8, s0 ; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v2, 8, s0
; GFX8-NOHSA-NEXT: s_bfe_i64 s[10:11], s[0:1], 0x80000 ; GFX8-NOHSA-NEXT: s_bfe_i64 s[10:11], s[0:1], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[12:13], s[2:3], 0x80000 ; GFX8-NOHSA-NEXT: s_bfe_i64 s[12:13], s[2:3], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[14:15], s[4:5], 0x80000 ; GFX8-NOHSA-NEXT: s_bfe_i64 s[14:15], s[4:5], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[16:17], s[6:7], 0x80000 ; GFX8-NOHSA-NEXT: s_bfe_i64 s[16:17], s[6:7], 0x80000
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; GFX8-NOHSA-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x80000 ; GFX8-NOHSA-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x80000 ; GFX8-NOHSA-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x80000 ; GFX8-NOHSA-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x80000 ; GFX8-NOHSA-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x80000 ; GFX8-NOHSA-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x80000 ; GFX8-NOHSA-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x80000 ; GFX8-NOHSA-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x80000
; GFX8-NOHSA-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x80000 ; GFX8-NOHSA-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x80000
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s28
; GFX8-NOHSA-NEXT: s_add_u32 s28, s8, 0xf0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s29
; GFX8-NOHSA-NEXT: s_addc_u32 s29, s9, 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s28 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s28
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s58 ; GFX8-NOHSA-NEXT: s_add_u32 s28, s8, 0xf0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s59 ; GFX8-NOHSA-NEXT: v_bfe_i32 v10, v9, 0, 8
; GFX8-NOHSA-NEXT: v_bfe_i32 v14, v8, 0, 8
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s29 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s29
; GFX8-NOHSA-NEXT: s_addc_u32 s29, s9, 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s28
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v18, s58
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v19, s59
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s29
; GFX8-NOHSA-NEXT: s_add_u32 s28, s8, 0xd0 ; GFX8-NOHSA-NEXT: s_add_u32 s28, s8, 0xd0
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[16:17], v[12:15] ; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[8:9], v[16:19]
; GFX8-NOHSA-NEXT: s_addc_u32 s29, s9, 0 ; GFX8-NOHSA-NEXT: s_addc_u32 s29, s9, 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s28 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s28
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s30 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s30
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s31 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s31
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s34 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v18, s34
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s35 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v19, s35
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s29 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s29
; GFX8-NOHSA-NEXT: s_add_u32 s28, s8, 0xb0 ; GFX8-NOHSA-NEXT: s_add_u32 s28, s8, 0xb0
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[16:17], v[12:15] ; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[8:9], v[16:19]
; GFX8-NOHSA-NEXT: s_addc_u32 s29, s9, 0 ; GFX8-NOHSA-NEXT: s_addc_u32 s29, s9, 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s28 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s28
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s36 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s36
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s37 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s37
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s56 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v18, s56
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s57 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v19, s57
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s29 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s29
; GFX8-NOHSA-NEXT: s_add_u32 s28, s8, 0x90 ; GFX8-NOHSA-NEXT: s_add_u32 s28, s8, 0x90
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[16:17], v[12:15] ; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[8:9], v[16:19]
; GFX8-NOHSA-NEXT: s_addc_u32 s29, s9, 0 ; GFX8-NOHSA-NEXT: s_addc_u32 s29, s9, 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s28 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s28
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s38 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s38
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s39 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s39
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s40 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v18, s40
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s41 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v19, s41
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s29 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s29
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[16:17], v[12:15] ; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[8:9], v[16:19]
; GFX8-NOHSA-NEXT: v_bfe_i32 v10, v9, 0, 8 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v20, s6
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s24 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v18, s24
; GFX8-NOHSA-NEXT: s_add_u32 s24, s8, 0x70 ; GFX8-NOHSA-NEXT: s_add_u32 s24, s8, 0x70
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s25 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v19, s25
; GFX8-NOHSA-NEXT: s_addc_u32 s25, s9, 0 ; GFX8-NOHSA-NEXT: s_addc_u32 s25, s9, 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s24 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s24
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s42 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s42
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s43 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s43
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s25 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s25
; GFX8-NOHSA-NEXT: s_add_u32 s24, s8, 0x50 ; GFX8-NOHSA-NEXT: s_add_u32 s24, s8, 0x50
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[16:17], v[12:15] ; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[8:9], v[16:19]
; GFX8-NOHSA-NEXT: s_addc_u32 s25, s9, 0 ; GFX8-NOHSA-NEXT: s_addc_u32 s25, s9, 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s24 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s24
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s44 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s44
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s45 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s45
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s46 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v18, s46
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s47 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v19, s47
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s25 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s25
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[16:17], v[12:15] ; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[8:9], v[16:19]
; GFX8-NOHSA-NEXT: v_bfe_i32 v18, v5, 0, 8 ; GFX8-NOHSA-NEXT: v_bfe_i32 v22, v4, 0, 8
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s18 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v18, s18
; GFX8-NOHSA-NEXT: s_add_u32 s18, s8, 48 ; GFX8-NOHSA-NEXT: s_add_u32 s18, s8, 48
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s19 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v19, s19
; GFX8-NOHSA-NEXT: s_addc_u32 s19, s9, 0 ; GFX8-NOHSA-NEXT: s_addc_u32 s19, s9, 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s18 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s18
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s26 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s26
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s27 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s27
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s19 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s19
; GFX8-NOHSA-NEXT: s_add_u32 s18, s8, 16 ; GFX8-NOHSA-NEXT: s_add_u32 s18, s8, 16
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[16:17], v[12:15] ; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[8:9], v[16:19]
; GFX8-NOHSA-NEXT: s_addc_u32 s19, s9, 0 ; GFX8-NOHSA-NEXT: s_addc_u32 s19, s9, 0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s18 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s18
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s22 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s22
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s23 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s23
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s20 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v18, s20
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s21 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v19, s21
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s19 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s19
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[16:17], v[12:15]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s6
; GFX8-NOHSA-NEXT: s_add_u32 s6, s8, 0xe0 ; GFX8-NOHSA-NEXT: s_add_u32 s6, s8, 0xe0
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s7 ; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[8:9], v[16:19]
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v21, s7
; GFX8-NOHSA-NEXT: v_bfe_i32 v18, v5, 0, 8
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s9, 0 ; GFX8-NOHSA-NEXT: s_addc_u32 s7, s9, 0
; GFX8-NOHSA-NEXT: v_bfe_i32 v14, v8, 0, 8 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s7 ; GFX8-NOHSA-NEXT: v_ashrrev_i32_e32 v23, 31, v22
; GFX8-NOHSA-NEXT: v_ashrrev_i32_e32 v19, 31, v18 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s6
; GFX8-NOHSA-NEXT: s_add_u32 s6, s8, 0xc0 ; GFX8-NOHSA-NEXT: s_add_u32 s6, s8, 0xc0
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[8:9], v[16:19] ; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[20:23]
; GFX8-NOHSA-NEXT: v_bfe_i32 v22, v1, 0, 8
; GFX8-NOHSA-NEXT: v_bfe_i32 v18, v4, 0, 8
; GFX8-NOHSA-NEXT: s_addc_u32 s7, s9, 0 ; GFX8-NOHSA-NEXT: s_addc_u32 s7, s9, 0
; GFX8-NOHSA-NEXT: v_bfe_i32 v22, v1, 0, 8
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
; GFX8-NOHSA-NEXT: v_ashrrev_i32_e32 v23, 31, v22 ; GFX8-NOHSA-NEXT: v_ashrrev_i32_e32 v23, 31, v22
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v20, s16 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v20, s16
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v21, s17 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v21, s17
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[20:23] ; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[20:23]
; GFX8-NOHSA-NEXT: v_ashrrev_i32_e32 v19, 31, v18 ; GFX8-NOHSA-NEXT: v_ashrrev_i32_e32 v19, 31, v18
; GFX8-NOHSA-NEXT: v_mov_b32_e32 v20, s4 ; GFX8-NOHSA-NEXT: v_mov_b32_e32 v20, s4
▲ Show 20 Lines • Show All 3,275 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/load-global-i16.ll

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Show First 20 Lines • Show All 6,258 Lines • ▼ Show 20 Lines
; GCN-HSA-NEXT: v_mov_b32_e32 v21, s3 ; GCN-HSA-NEXT: v_mov_b32_e32 v21, s3
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0 ; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v20, s2 ; GCN-HSA-NEXT: v_mov_b32_e32 v20, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v23, s1 ; GCN-HSA-NEXT: v_mov_b32_e32 v23, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v22, s0 ; GCN-HSA-NEXT: v_mov_b32_e32 v22, s0
; GCN-HSA-NEXT: s_waitcnt vmcnt(0) ; GCN-HSA-NEXT: s_waitcnt vmcnt(0)
; GCN-HSA-NEXT: v_mov_b32_e32 v7, v3 ; GCN-HSA-NEXT: v_mov_b32_e32 v7, v3
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v10, 16, v2 ; GCN-HSA-NEXT: v_lshrrev_b32_e32 v10, 16, v2
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v5, 16, v0 ; GCN-HSA-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; GCN-HSA-NEXT: v_ashr_i64 v[14:15], v[0:1], 48 ; GCN-HSA-NEXT: v_ashr_i64 v[14:15], v[0:1], 48
; GCN-HSA-NEXT: v_bfe_i32 v12, v1, 0, 16 ; GCN-HSA-NEXT: v_bfe_i32 v12, v1, 0, 16
; GCN-HSA-NEXT: v_bfe_i32 v4, v0, 0, 16 ; GCN-HSA-NEXT: v_bfe_i32 v4, v0, 0, 16
; GCN-HSA-NEXT: v_bfe_i32 v8, v2, 0, 16 ; GCN-HSA-NEXT: v_bfe_i32 v8, v2, 0, 16
; GCN-HSA-NEXT: v_bfe_i32 v6, v5, 0, 16
; GCN-HSA-NEXT: v_ashr_i64 v[2:3], v[2:3], 48 ; GCN-HSA-NEXT: v_ashr_i64 v[2:3], v[2:3], 48
; GCN-HSA-NEXT: v_bfe_i32 v6, v6, 0, 16
; GCN-HSA-NEXT: v_bfe_i32 v10, v10, 0, 16 ; GCN-HSA-NEXT: v_bfe_i32 v10, v10, 0, 16
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v13, 31, v12 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v13, 31, v12
; GCN-HSA-NEXT: v_bfe_i32 v0, v7, 0, 16 ; GCN-HSA-NEXT: v_bfe_i32 v0, v7, 0, 16
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v5, 31, v4 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v5, 31, v4
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v9, 31, v8 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v9, 31, v8
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v7, 31, v6 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v7, 31, v6
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v11, 31, v10 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v11, 31, v10
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v1, 31, v0
▲ Show 20 Lines • Show All 538 Lines • ▼ Show 20 Lines
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16 ; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
; GCN-NOHSA-SI-NEXT: s_mov_b32 s0, s4 ; GCN-NOHSA-SI-NEXT: s_mov_b32 s0, s4
; GCN-NOHSA-SI-NEXT: s_mov_b32 s1, s5 ; GCN-NOHSA-SI-NEXT: s_mov_b32 s1, s5
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0) ; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v9, v7 ; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v9, v7
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v10, v3 ; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v10, v3
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v11, 16, v4 ; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v11, 16, v4
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v13, 16, v2 ; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v13, 16, v2
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v17, 16, v0 ; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v14, 16, v0
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v8, v0, 0, 16 ; GCN-NOHSA-SI-NEXT: v_bfe_i32 v8, v0, 0, 16
; GCN-NOHSA-SI-NEXT: v_ashr_i64 v[14:15], v[0:1], 48 ; GCN-NOHSA-SI-NEXT: v_bfe_i32 v12, v2, 0, 16
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v16, v10, 0, 16 ; GCN-NOHSA-SI-NEXT: v_ashr_i64 v[18:19], v[0:1], 48
; GCN-NOHSA-SI-NEXT: v_ashr_i64 v[18:19], v[2:3], 48 ; GCN-NOHSA-SI-NEXT: v_bfe_i32 v16, v1, 0, 16
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v12, v1, 0, 16 ; GCN-NOHSA-SI-NEXT: v_ashr_i64 v[2:3], v[2:3], 48
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v0, v2, 0, 16 ; GCN-NOHSA-SI-NEXT: v_bfe_i32 v0, v10, 0, 16
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v10, v17, 0, 16
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v2, v13, 0, 16
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v20, v4, 0, 16 ; GCN-NOHSA-SI-NEXT: v_bfe_i32 v20, v4, 0, 16
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v10, v14, 0, 16
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v14, v13, 0, 16
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v22, v11, 0, 16 ; GCN-NOHSA-SI-NEXT: v_bfe_i32 v22, v11, 0, 16
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v23, v9, 0, 16 ; GCN-NOHSA-SI-NEXT: v_bfe_i32 v23, v9, 0, 16
; GCN-NOHSA-SI-NEXT: v_ashr_i64 v[25:26], v[6:7], 48 ; GCN-NOHSA-SI-NEXT: v_ashr_i64 v[25:26], v[6:7], 48
; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v24, 31, v23 ; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v24, 31, v23
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[23:26], off, s[0:3], 0 offset:112 ; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[23:26], off, s[0:3], 0 offset:112
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0) ; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
; GCN-NOHSA-SI-NEXT: v_ashr_i64 v[26:27], v[4:5], 48 ; GCN-NOHSA-SI-NEXT: v_ashr_i64 v[26:27], v[4:5], 48
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v24, v5, 0, 16 ; GCN-NOHSA-SI-NEXT: v_bfe_i32 v24, v5, 0, 16
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v1, 16, v6 ; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v1, 16, v6
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v4, v6, 0, 16 ; GCN-NOHSA-SI-NEXT: v_bfe_i32 v4, v6, 0, 16
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v6, v1, 0, 16 ; GCN-NOHSA-SI-NEXT: v_bfe_i32 v6, v1, 0, 16
; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v9, 31, v8 ; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v9, 31, v8
; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v13, 31, v12
; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v21, 31, v20 ; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v21, 31, v20
; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v5, 31, v4 ; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v5, 31, v4
; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v13, 31, v12
; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v17, 31, v16 ; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v17, 31, v16
; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v25, 31, v24 ; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v25, 31, v24
; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v11, 31, v10 ; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v11, 31, v10
; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v3, 31, v2 ; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v15, 31, v14
; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v23, 31, v22 ; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v23, 31, v22
; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v7, 31, v6 ; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v7, 31, v6
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[24:27], off, s[0:3], 0 offset:80 ; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[24:27], off, s[0:3], 0 offset:80
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:48 ; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:16 ; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:16
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:96 ; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:96
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[20:23], off, s[0:3], 0 offset:64 ; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[20:23], off, s[0:3], 0 offset:64
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32 ; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:32
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 ; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0
; GCN-NOHSA-SI-NEXT: s_endpgm ; GCN-NOHSA-SI-NEXT: s_endpgm
; ;
; GCN-HSA-LABEL: global_sextload_v16i16_to_v16i64: ; GCN-HSA-LABEL: global_sextload_v16i16_to_v16i64:
; GCN-HSA: ; %bb.0: ; GCN-HSA: ; %bb.0:
; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; GCN-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0) ; GCN-HSA-NEXT: s_waitcnt lgkmcnt(0)
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2 ; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
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; GCN-HSA-NEXT: v_mov_b32_e32 v24, s2 ; GCN-HSA-NEXT: v_mov_b32_e32 v24, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v26, s0 ; GCN-HSA-NEXT: v_mov_b32_e32 v26, s0
; GCN-HSA-NEXT: s_waitcnt vmcnt(1) ; GCN-HSA-NEXT: s_waitcnt vmcnt(1)
; GCN-HSA-NEXT: v_ashr_i64 v[10:11], v[0:1], 48 ; GCN-HSA-NEXT: v_ashr_i64 v[10:11], v[0:1], 48
; GCN-HSA-NEXT: v_bfe_i32 v8, v1, 0, 16 ; GCN-HSA-NEXT: v_bfe_i32 v8, v1, 0, 16
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v9, 31, v8 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v9, 31, v8
; GCN-HSA-NEXT: v_mov_b32_e32 v1, v3 ; GCN-HSA-NEXT: v_mov_b32_e32 v1, v3
; GCN-HSA-NEXT: flat_store_dwordx4 v[16:17], v[8:11] ; GCN-HSA-NEXT: flat_store_dwordx4 v[16:17], v[8:11]
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v16, 16, v2 ; GCN-HSA-NEXT: v_lshrrev_b32_e32 v17, 16, v0
; GCN-HSA-NEXT: v_bfe_i32 v8, v1, 0, 16 ; GCN-HSA-NEXT: v_bfe_i32 v8, v1, 0, 16
; GCN-HSA-NEXT: v_ashr_i64 v[10:11], v[2:3], 48 ; GCN-HSA-NEXT: v_ashr_i64 v[10:11], v[2:3], 48
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v9, 31, v8 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v9, 31, v8
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v3, 16, v0 ; GCN-HSA-NEXT: v_lshrrev_b32_e32 v16, 16, v2
; GCN-HSA-NEXT: flat_store_dwordx4 v[14:15], v[8:11] ; GCN-HSA-NEXT: flat_store_dwordx4 v[14:15], v[8:11]
; GCN-HSA-NEXT: v_bfe_i32 v0, v0, 0, 16 ; GCN-HSA-NEXT: v_bfe_i32 v0, v0, 0, 16
; GCN-HSA-NEXT: v_bfe_i32 v8, v2, 0, 16 ; GCN-HSA-NEXT: v_bfe_i32 v8, v2, 0, 16
; GCN-HSA-NEXT: v_bfe_i32 v2, v3, 0, 16 ; GCN-HSA-NEXT: v_bfe_i32 v2, v17, 0, 16
; GCN-HSA-NEXT: v_bfe_i32 v10, v16, 0, 16
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v9, 31, v8 ; GCN-HSA-NEXT: v_bfe_i32 v10, v16, 0, 16
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v11, 31, v10
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v3, 31, v2 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v9, 31, v8
; GCN-HSA-NEXT: s_waitcnt vmcnt(2) ; GCN-HSA-NEXT: s_waitcnt vmcnt(2)
; GCN-HSA-NEXT: v_mov_b32_e32 v16, v7 ; GCN-HSA-NEXT: v_mov_b32_e32 v16, v7
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v17, 16, v6 ; GCN-HSA-NEXT: v_lshrrev_b32_e32 v17, 16, v6
; GCN-HSA-NEXT: flat_store_dwordx4 v[22:23], v[8:11] ; GCN-HSA-NEXT: v_lshrrev_b32_e32 v28, 16, v4
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v11, 31, v10
; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[0:3] ; GCN-HSA-NEXT: flat_store_dwordx4 v[12:13], v[0:3]
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v9, 16, v4
; GCN-HSA-NEXT: v_ashr_i64 v[14:15], v[4:5], 48 ; GCN-HSA-NEXT: v_ashr_i64 v[14:15], v[4:5], 48
; GCN-HSA-NEXT: v_bfe_i32 v12, v5, 0, 16 ; GCN-HSA-NEXT: v_bfe_i32 v12, v5, 0, 16
; GCN-HSA-NEXT: v_bfe_i32 v8, v4, 0, 16 ; GCN-HSA-NEXT: flat_store_dwordx4 v[22:23], v[8:11]
; GCN-HSA-NEXT: v_bfe_i32 v0, v6, 0, 16 ; GCN-HSA-NEXT: v_bfe_i32 v0, v6, 0, 16
; GCN-HSA-NEXT: v_bfe_i32 v10, v9, 0, 16 ; GCN-HSA-NEXT: v_bfe_i32 v8, v4, 0, 16
; GCN-HSA-NEXT: v_ashr_i64 v[6:7], v[6:7], 48 ; GCN-HSA-NEXT: v_ashr_i64 v[6:7], v[6:7], 48
; GCN-HSA-NEXT: v_bfe_i32 v10, v28, 0, 16
; GCN-HSA-NEXT: v_bfe_i32 v2, v17, 0, 16 ; GCN-HSA-NEXT: v_bfe_i32 v2, v17, 0, 16
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v13, 31, v12 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v13, 31, v12
; GCN-HSA-NEXT: v_bfe_i32 v4, v16, 0, 16 ; GCN-HSA-NEXT: v_bfe_i32 v4, v16, 0, 16
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v9, 31, v8 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v9, 31, v8
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v11, 31, v10 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v11, 31, v10
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v3, 31, v2 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v5, 31, v4 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v5, 31, v4
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; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16 ; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
; GCN-NOHSA-VI-NEXT: s_mov_b32 s0, s4 ; GCN-NOHSA-VI-NEXT: s_mov_b32 s0, s4
; GCN-NOHSA-VI-NEXT: s_mov_b32 s1, s5 ; GCN-NOHSA-VI-NEXT: s_mov_b32 s1, s5
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(1) ; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(1)
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v8, v0, 0, 16 ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v8, v0, 0, 16
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v9, 16, v0 ; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v9, 16, v0
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v0, v1, 0, 16 ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v0, v1, 0, 16
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 ; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v10, 16, v5
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v12, v2, 0, 16 ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v12, v2, 0, 16
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v15, v10, 0, 16 ; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v11, 16, v2
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v13, v5, 0, 16
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v2, v1, 0, 16 ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v2, v1, 0, 16
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v1, 16, v7 ; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v14, 31, v13 ; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v1, 16, v5
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v16, 31, v15 ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v17, v1, 0, 16
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v22, v1, 0, 16
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v1, 16, v4 ; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v1, 16, v4
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[13:16], off, s[0:3], 0 offset:80 ; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v13, v3
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v11, v3
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3 ; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v13, 16, v6 ; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v20, 16, v6
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v10, v9, 0, 16 ; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v22, v7
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v9, v7 ; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v24, v6, 0, 16 ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v15, v5, 0, 16
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v27, v6, 0, 16
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v4, v4, 0, 16 ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v4, v4, 0, 16
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v6, v1, 0, 16 ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v6, v1, 0, 16
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v14, v5, 0, 16 ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v10, v9, 0, 16
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v16, v11, 0, 16 ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v14, v11, 0, 16
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v18, v3, 0, 16 ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v19, v13, 0, 16
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v20, v9, 0, 16 ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v21, v3, 0, 16
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v26, v13, 0, 16 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v16, 31, v15
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v18, 31, v17
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v23, v22, 0, 16
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v25, v7, 0, 16
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v29, v20, 0, 16
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v5, 31, v4 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v5, 31, v4
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v7, 31, v6 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v7, 31, v6
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[15:18], off, s[0:3], 0 offset:80
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v9, 31, v8 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v9, 31, v8
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v13, 31, v12 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v13, 31, v12
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v25, 31, v24 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v28, 31, v27
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v11, 31, v10 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v11, 31, v10
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v3, 31, v2 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v15, 31, v14 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v15, 31, v14
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v17, 31, v16 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v20, 31, v19
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v19, 31, v18 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v22, 31, v21
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v27, 31, v26 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v30, 31, v29
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v21, 31, v20 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v24, 31, v23
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v23, 31, v22 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v26, 31, v25
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:64 ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:64
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[20:23], off, s[0:3], 0 offset:112 ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[23:26], off, s[0:3], 0 offset:112
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[24:27], off, s[0:3], 0 offset:96 ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[27:30], off, s[0:3], 0 offset:96
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:48 ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[19:22], off, s[0:3], 0 offset:48
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:32 ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:32
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16 ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0
; GCN-NOHSA-VI-NEXT: s_endpgm ; GCN-NOHSA-VI-NEXT: s_endpgm
; ;
; EG-LABEL: global_sextload_v16i16_to_v16i64: ; EG-LABEL: global_sextload_v16i16_to_v16i64:
; EG: ; %bb.0: ; EG: ; %bb.0:
; EG-NEXT: ALU 0, @16, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 0, @16, KC0[CB0:0-32], KC1[]
▲ Show 20 Lines • Show All 924 Lines • ▼ Show 20 Lines
; GCN-NOHSA-SI-NEXT: s_mov_b32 s9, s7 ; GCN-NOHSA-SI-NEXT: s_mov_b32 s9, s7
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[12:15], off, s[8:11], 0 ; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[12:15], off, s[8:11], 0
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[8:11], off, s[8:11], 0 offset:16 ; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[8:11], off, s[8:11], 0 offset:16
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:32 ; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:32
; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 offset:48 ; GCN-NOHSA-SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 offset:48
; GCN-NOHSA-SI-NEXT: s_mov_b32 s0, s4 ; GCN-NOHSA-SI-NEXT: s_mov_b32 s0, s4
; GCN-NOHSA-SI-NEXT: s_mov_b32 s1, s5 ; GCN-NOHSA-SI-NEXT: s_mov_b32 s1, s5
; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0) ; GCN-NOHSA-SI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v17, v3 ; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v20, v3
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v21, v7 ; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v24, v7
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v22, v11 ; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v25, v11
; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v23, v15 ; GCN-NOHSA-SI-NEXT: v_mov_b32_e32 v26, v15
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v16, 16, v2 ; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v19, 16, v2
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v17, v17, 0, 16 ; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v16, 16, v4
; GCN-NOHSA-SI-NEXT: v_ashr_i64 v[19:20], v[2:3], 48 ; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v17, 16, v10
; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v18, 31, v17 ; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v18, 16, v8
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[17:20], off, s[0:3], 0 offset:240 ; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v27, 16, v14
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0) ; GCN-NOHSA-SI-NEXT: v_bfe_i32 v20, v20, 0, 16
; GCN-NOHSA-SI-NEXT: v_ashr_i64 v[19:20], v[0:1], 48 ; GCN-NOHSA-SI-NEXT: v_ashr_i64 v[22:23], v[2:3], 48
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v17, v1, 0, 16 ; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v21, 31, v20
; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v18, 31, v17 ; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[20:23], off, s[0:3], 0 offset:240
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[17:20], off, s[0:3], 0 offset:208
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v24, 16, v4
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0) ; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v17, v21, 0, 16 ; GCN-NOHSA-SI-NEXT: v_ashr_i64 v[22:23], v[0:1], 48
; GCN-NOHSA-SI-NEXT: v_ashr_i64 v[19:20], v[6:7], 48 ; GCN-NOHSA-SI-NEXT: v_bfe_i32 v20, v1, 0, 16
; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v18, 31, v17 ; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v21, 31, v20
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[17:20], off, s[0:3], 0 offset:176 ; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[20:23], off, s[0:3], 0 offset:208
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v3, 16, v12
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0) ; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
; GCN-NOHSA-SI-NEXT: v_ashr_i64 v[19:20], v[4:5], 48 ; GCN-NOHSA-SI-NEXT: v_bfe_i32 v20, v24, 0, 16
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v17, v5, 0, 16 ; GCN-NOHSA-SI-NEXT: v_ashr_i64 v[22:23], v[6:7], 48
; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v18, 31, v17 ; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v21, 31, v20
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[17:20], off, s[0:3], 0 offset:144 ; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[20:23], off, s[0:3], 0 offset:176
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v21, 16, v10
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0) ; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v17, v22, 0, 16 ; GCN-NOHSA-SI-NEXT: v_ashr_i64 v[22:23], v[4:5], 48
; GCN-NOHSA-SI-NEXT: v_ashr_i64 v[19:20], v[10:11], 48 ; GCN-NOHSA-SI-NEXT: v_bfe_i32 v20, v5, 0, 16
; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v18, 31, v17 ; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v21, 31, v20
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[17:20], off, s[0:3], 0 offset:112 ; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[20:23], off, s[0:3], 0 offset:144
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0) ; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
; GCN-NOHSA-SI-NEXT: v_ashr_i64 v[19:20], v[8:9], 48 ; GCN-NOHSA-SI-NEXT: v_ashr_i64 v[22:23], v[10:11], 48
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v17, v9, 0, 16 ; GCN-NOHSA-SI-NEXT: v_bfe_i32 v20, v25, 0, 16
; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v18, 31, v17 ; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v21, 31, v20
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[17:20], off, s[0:3], 0 offset:80 ; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[20:23], off, s[0:3], 0 offset:112
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v9, 16, v8
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0) ; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v17, v23, 0, 16 ; GCN-NOHSA-SI-NEXT: v_ashr_i64 v[22:23], v[8:9], 48
; GCN-NOHSA-SI-NEXT: v_ashr_i64 v[19:20], v[14:15], 48 ; GCN-NOHSA-SI-NEXT: v_bfe_i32 v20, v9, 0, 16
; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v18, 31, v17 ; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v21, 31, v20
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[17:20], off, s[0:3], 0 offset:48 ; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[20:23], off, s[0:3], 0 offset:80
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0) ; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
; GCN-NOHSA-SI-NEXT: v_ashr_i64 v[19:20], v[12:13], 48 ; GCN-NOHSA-SI-NEXT: v_ashr_i64 v[22:23], v[14:15], 48
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v17, v13, 0, 16 ; GCN-NOHSA-SI-NEXT: v_bfe_i32 v20, v26, 0, 16
; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v18, 31, v17 ; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v21, 31, v20
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[17:20], off, s[0:3], 0 offset:16 ; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[20:23], off, s[0:3], 0 offset:48
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v7, 16, v14
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0) ; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v17, v16, 0, 16 ; GCN-NOHSA-SI-NEXT: v_ashr_i64 v[22:23], v[12:13], 48
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v15, v2, 0, 16 ; GCN-NOHSA-SI-NEXT: v_bfe_i32 v20, v13, 0, 16
; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v16, 31, v15 ; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v21, 31, v20
; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v18, 31, v17 ; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[20:23], off, s[0:3], 0 offset:16
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[15:18], off, s[0:3], 0 offset:224
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v1, 16, v12
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v3, v1, 0, 16
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v1, v12, 0, 16 ; GCN-NOHSA-SI-NEXT: v_bfe_i32 v1, v12, 0, 16
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v5, v14, 0, 16 ; GCN-NOHSA-SI-NEXT: v_bfe_i32 v5, v14, 0, 16
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v7, v7, 0, 16 ; GCN-NOHSA-SI-NEXT: v_bfe_i32 v3, v3, 0, 16
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v11, v9, 0, 16 ; GCN-NOHSA-SI-NEXT: v_bfe_i32 v13, v19, 0, 16
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v11, v2, 0, 16
; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v12, 31, v11
; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v14, 31, v13
; GCN-NOHSA-SI-NEXT: buffer_store_dwordx4 v[11:14], off, s[0:3], 0 offset:224
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v9, v8, 0, 16 ; GCN-NOHSA-SI-NEXT: v_bfe_i32 v9, v8, 0, 16
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v13, v10, 0, 16
; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0) ; GCN-NOHSA-SI-NEXT: s_waitcnt expcnt(0)
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v15, v21, 0, 16 ; GCN-NOHSA-SI-NEXT: v_bfe_i32 v13, v10, 0, 16
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v19, v24, 0, 16 ; GCN-NOHSA-SI-NEXT: v_bfe_i32 v7, v27, 0, 16
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v11, v18, 0, 16
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v15, v17, 0, 16
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v19, v16, 0, 16
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v17, v4, 0, 16 ; GCN-NOHSA-SI-NEXT: v_bfe_i32 v17, v4, 0, 16
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v2, 16, v6 ; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v2, 16, v6
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v21, v6, 0, 16 ; GCN-NOHSA-SI-NEXT: v_bfe_i32 v21, v6, 0, 16
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v23, v2, 0, 16 ; GCN-NOHSA-SI-NEXT: v_bfe_i32 v23, v2, 0, 16
; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v2, 16, v0 ; GCN-NOHSA-SI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v25, v0, 0, 16 ; GCN-NOHSA-SI-NEXT: v_bfe_i32 v25, v0, 0, 16
; GCN-NOHSA-SI-NEXT: v_bfe_i32 v27, v2, 0, 16 ; GCN-NOHSA-SI-NEXT: v_bfe_i32 v27, v2, 0, 16
; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v2, 31, v1 ; GCN-NOHSA-SI-NEXT: v_ashrrev_i32_e32 v2, 31, v1
Show All 38 Lines
; GCN-HSA-NEXT: flat_load_dwordx4 v[8:11], v[8:9] ; GCN-HSA-NEXT: flat_load_dwordx4 v[8:11], v[8:9]
; GCN-HSA-NEXT: s_add_u32 s2, s2, 16 ; GCN-HSA-NEXT: s_add_u32 s2, s2, 16
; GCN-HSA-NEXT: s_addc_u32 s3, s3, 0 ; GCN-HSA-NEXT: s_addc_u32 s3, s3, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s3 ; GCN-HSA-NEXT: v_mov_b32_e32 v13, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v12, s2 ; GCN-HSA-NEXT: v_mov_b32_e32 v12, s2
; GCN-HSA-NEXT: flat_load_dwordx4 v[12:15], v[12:13] ; GCN-HSA-NEXT: flat_load_dwordx4 v[12:15], v[12:13]
; GCN-HSA-NEXT: s_add_u32 s2, s0, 48 ; GCN-HSA-NEXT: s_add_u32 s2, s0, 48
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0 ; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v21, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v20, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 16
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v23, s3 ; GCN-HSA-NEXT: v_mov_b32_e32 v23, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v22, s2 ; GCN-HSA-NEXT: v_mov_b32_e32 v22, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 16 ; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xf0
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0 ; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v25, s3 ; GCN-HSA-NEXT: v_mov_b32_e32 v25, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v24, s2 ; GCN-HSA-NEXT: v_mov_b32_e32 v24, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xf0 ; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xd0
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0 ; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v27, s3 ; GCN-HSA-NEXT: v_mov_b32_e32 v27, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v26, s2 ; GCN-HSA-NEXT: v_mov_b32_e32 v26, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xd0 ; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xb0
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0 ; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v21, s1
; GCN-HSA-NEXT: v_mov_b32_e32 v20, s0
; GCN-HSA-NEXT: s_waitcnt vmcnt(3) ; GCN-HSA-NEXT: s_waitcnt vmcnt(3)
; GCN-HSA-NEXT: v_ashr_i64 v[18:19], v[4:5], 48 ; GCN-HSA-NEXT: v_ashr_i64 v[18:19], v[4:5], 48
; GCN-HSA-NEXT: v_bfe_i32 v16, v5, 0, 16 ; GCN-HSA-NEXT: v_bfe_i32 v16, v5, 0, 16
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v17, 31, v16 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v17, 31, v16
; GCN-HSA-NEXT: flat_store_dwordx4 v[24:25], v[16:19] ; GCN-HSA-NEXT: flat_store_dwordx4 v[22:23], v[16:19]
; GCN-HSA-NEXT: v_mov_b32_e32 v25, s3 ; GCN-HSA-NEXT: v_mov_b32_e32 v23, s3
; GCN-HSA-NEXT: v_mov_b32_e32 v24, s2 ; GCN-HSA-NEXT: v_mov_b32_e32 v22, s2
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xb0 ; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x90
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0 ; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: s_add_u32 s4, s0, 0x90 ; GCN-HSA-NEXT: s_add_u32 s4, s0, 0x70
; GCN-HSA-NEXT: v_mov_b32_e32 v5, v7
; GCN-HSA-NEXT: s_addc_u32 s5, s1, 0 ; GCN-HSA-NEXT: s_addc_u32 s5, s1, 0
; GCN-HSA-NEXT: s_add_u32 s6, s0, 0x50
; GCN-HSA-NEXT: s_addc_u32 s7, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v5, v7
; GCN-HSA-NEXT: s_add_u32 s8, s0, 32
; GCN-HSA-NEXT: v_bfe_i32 v16, v5, 0, 16 ; GCN-HSA-NEXT: v_bfe_i32 v16, v5, 0, 16
; GCN-HSA-NEXT: v_ashr_i64 v[18:19], v[6:7], 48 ; GCN-HSA-NEXT: v_ashr_i64 v[18:19], v[6:7], 48
; GCN-HSA-NEXT: s_add_u32 s6, s0, 0x70 ; GCN-HSA-NEXT: s_addc_u32 s9, s1, 0
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v17, 31, v16 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v17, 31, v16
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v5, 16, v6 ; GCN-HSA-NEXT: v_lshrrev_b32_e32 v5, 16, v6
; GCN-HSA-NEXT: s_addc_u32 s7, s1, 0 ; GCN-HSA-NEXT: flat_store_dwordx4 v[20:21], v[16:19]
; GCN-HSA-NEXT: flat_store_dwordx4 v[22:23], v[16:19] ; GCN-HSA-NEXT: v_mov_b32_e32 v21, s9
; GCN-HSA-NEXT: s_add_u32 s8, s0, 0x50
; GCN-HSA-NEXT: v_bfe_i32 v18, v5, 0, 16 ; GCN-HSA-NEXT: v_bfe_i32 v18, v5, 0, 16
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v5, 16, v4
; GCN-HSA-NEXT: v_bfe_i32 v16, v6, 0, 16 ; GCN-HSA-NEXT: v_bfe_i32 v16, v6, 0, 16
; GCN-HSA-NEXT: v_bfe_i32 v4, v4, 0, 16 ; GCN-HSA-NEXT: v_mov_b32_e32 v20, s8
; GCN-HSA-NEXT: v_bfe_i32 v6, v5, 0, 16 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v17, 31, v16
; GCN-HSA-NEXT: s_addc_u32 s9, s1, 0 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v19, 31, v18
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v5, 31, v4 ; GCN-HSA-NEXT: flat_store_dwordx4 v[20:21], v[16:19]
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v7, 31, v6 ; GCN-HSA-NEXT: v_mov_b32_e32 v6, s3
; GCN-HSA-NEXT: s_add_u32 s10, s0, 32
; GCN-HSA-NEXT: flat_store_dwordx4 v[20:21], v[4:7]
; GCN-HSA-NEXT: s_addc_u32 s11, s1, 0
; GCN-HSA-NEXT: s_waitcnt vmcnt(5) ; GCN-HSA-NEXT: s_waitcnt vmcnt(5)
; GCN-HSA-NEXT: v_ashr_i64 v[6:7], v[0:1], 48 ; GCN-HSA-NEXT: v_ashr_i64 v[18:19], v[0:1], 48
; GCN-HSA-NEXT: v_bfe_i32 v4, v1, 0, 16 ; GCN-HSA-NEXT: v_bfe_i32 v16, v1, 0, 16
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v5, 31, v4 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v17, 31, v16
; GCN-HSA-NEXT: v_mov_b32_e32 v1, v3 ; GCN-HSA-NEXT: v_mov_b32_e32 v1, v3
; GCN-HSA-NEXT: v_mov_b32_e32 v23, s11 ; GCN-HSA-NEXT: flat_store_dwordx4 v[26:27], v[16:19]
; GCN-HSA-NEXT: flat_store_dwordx4 v[24:25], v[4:7] ; GCN-HSA-NEXT: v_mov_b32_e32 v5, s2
; GCN-HSA-NEXT: v_mov_b32_e32 v22, s10 ; GCN-HSA-NEXT: v_bfe_i32 v16, v1, 0, 16
; GCN-HSA-NEXT: v_bfe_i32 v4, v1, 0, 16 ; GCN-HSA-NEXT: v_ashr_i64 v[18:19], v[2:3], 48
; GCN-HSA-NEXT: v_ashr_i64 v[6:7], v[2:3], 48
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v17, 31, v16 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v17, 31, v16
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v19, 31, v18 ; GCN-HSA-NEXT: flat_store_dwordx4 v[24:25], v[16:19]
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v1, 16, v4
; GCN-HSA-NEXT: s_waitcnt vmcnt(6)
; GCN-HSA-NEXT: v_ashr_i64 v[18:19], v[8:9], 48
; GCN-HSA-NEXT: v_bfe_i32 v16, v9, 0, 16
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v17, 31, v16
; GCN-HSA-NEXT: v_bfe_i32 v3, v4, 0, 16
; GCN-HSA-NEXT: v_mov_b32_e32 v4, v11
; GCN-HSA-NEXT: flat_store_dwordx4 v[5:6], v[16:19]
; GCN-HSA-NEXT: v_bfe_i32 v4, v4, 0, 16
; GCN-HSA-NEXT: v_ashr_i64 v[6:7], v[10:11], 48
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v5, 31, v4 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v5, 31, v4
; GCN-HSA-NEXT: flat_store_dwordx4 v[22:23], v[16:19] ; GCN-HSA-NEXT: v_mov_b32_e32 v25, s7
; GCN-HSA-NEXT: flat_store_dwordx4 v[26:27], v[4:7] ; GCN-HSA-NEXT: flat_store_dwordx4 v[22:23], v[4:7]
; GCN-HSA-NEXT: v_mov_b32_e32 v19, s5 ; GCN-HSA-NEXT: v_mov_b32_e32 v24, s6
; GCN-HSA-NEXT: s_waitcnt vmcnt(7) ; GCN-HSA-NEXT: s_waitcnt vmcnt(7)
; GCN-HSA-NEXT: v_ashr_i64 v[5:6], v[8:9], 48 ; GCN-HSA-NEXT: v_ashr_i64 v[6:7], v[12:13], 48
; GCN-HSA-NEXT: v_bfe_i32 v3, v9, 0, 16 ; GCN-HSA-NEXT: v_bfe_i32 v4, v13, 0, 16
; GCN-HSA-NEXT: v_mov_b32_e32 v18, s4 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v5, 31, v4
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v4, 31, v3 ; GCN-HSA-NEXT: flat_store_dwordx4 v[24:25], v[4:7]
; GCN-HSA-NEXT: flat_store_dwordx4 v[18:19], v[3:6] ; GCN-HSA-NEXT: v_mov_b32_e32 v21, s5
; GCN-HSA-NEXT: v_mov_b32_e32 v17, s3 ; GCN-HSA-NEXT: v_mov_b32_e32 v4, v15
; GCN-HSA-NEXT: v_mov_b32_e32 v3, v11 ; GCN-HSA-NEXT: v_bfe_i32 v4, v4, 0, 16
; GCN-HSA-NEXT: v_bfe_i32 v3, v3, 0, 16 ; GCN-HSA-NEXT: v_ashr_i64 v[6:7], v[14:15], 48
; GCN-HSA-NEXT: v_ashr_i64 v[5:6], v[10:11], 48 ; GCN-HSA-NEXT: v_mov_b32_e32 v20, s4
; GCN-HSA-NEXT: v_mov_b32_e32 v16, s2 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v5, 31, v4
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v4, 31, v3 ; GCN-HSA-NEXT: v_lshrrev_b32_e32 v17, 16, v14
; GCN-HSA-NEXT: v_mov_b32_e32 v21, s9 ; GCN-HSA-NEXT: flat_store_dwordx4 v[20:21], v[4:7]
; GCN-HSA-NEXT: flat_store_dwordx4 v[16:17], v[3:6] ; GCN-HSA-NEXT: v_bfe_i32 v15, v14, 0, 16
; GCN-HSA-NEXT: v_mov_b32_e32 v20, s8 ; GCN-HSA-NEXT: v_bfe_i32 v5, v1, 0, 16
; GCN-HSA-NEXT: s_waitcnt vmcnt(8) ; GCN-HSA-NEXT: v_mov_b32_e32 v14, s1
; GCN-HSA-NEXT: v_ashr_i64 v[5:6], v[12:13], 48 ; GCN-HSA-NEXT: v_lshrrev_b32_e32 v26, 16, v2
; GCN-HSA-NEXT: v_bfe_i32 v3, v13, 0, 16 ; GCN-HSA-NEXT: v_lshrrev_b32_e32 v25, 16, v8
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v4, 31, v3
; GCN-HSA-NEXT: flat_store_dwordx4 v[20:21], v[3:6]
; GCN-HSA-NEXT: v_mov_b32_e32 v23, s7
; GCN-HSA-NEXT: v_mov_b32_e32 v3, v15
; GCN-HSA-NEXT: v_bfe_i32 v3, v3, 0, 16
; GCN-HSA-NEXT: v_ashr_i64 v[5:6], v[14:15], 48
; GCN-HSA-NEXT: v_mov_b32_e32 v22, s6
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v25, 16, v2
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v4, 31, v3 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v4, 31, v3
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v6, 31, v5
; GCN-HSA-NEXT: v_mov_b32_e32 v13, s0
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xe0 ; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xe0
; GCN-HSA-NEXT: flat_store_dwordx4 v[22:23], v[3:6] ; GCN-HSA-NEXT: v_lshrrev_b32_e32 v22, 16, v0
; GCN-HSA-NEXT: flat_store_dwordx4 v[13:14], v[3:6]
; GCN-HSA-NEXT: v_bfe_i32 v19, v0, 0, 16 ; GCN-HSA-NEXT: v_bfe_i32 v19, v0, 0, 16
; GCN-HSA-NEXT: v_bfe_i32 v23, v2, 0, 16 ; GCN-HSA-NEXT: v_bfe_i32 v23, v2, 0, 16
; GCN-HSA-NEXT: v_bfe_i32 v21, v1, 0, 16 ; GCN-HSA-NEXT: v_bfe_i32 v5, v25, 0, 16
; GCN-HSA-NEXT: v_bfe_i32 v25, v25, 0, 16 ; GCN-HSA-NEXT: v_bfe_i32 v25, v26, 0, 16
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0 ; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2 ; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v24, 31, v23 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v24, 31, v23
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v26, 31, v25 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v26, 31, v25
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3 ; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xc0 ; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xc0
; GCN-HSA-NEXT: v_bfe_i32 v21, v22, 0, 16
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[23:26] ; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[23:26]
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0 ; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2 ; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v18, 16, v10 ; GCN-HSA-NEXT: v_lshrrev_b32_e32 v9, 16, v10
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v20, 31, v19 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v20, 31, v19
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v22, 31, v21 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v22, 31, v21
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3 ; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xa0 ; GCN-HSA-NEXT: s_add_u32 s2, s0, 0xa0
; GCN-HSA-NEXT: v_bfe_i32 v15, v10, 0, 16 ; GCN-HSA-NEXT: v_bfe_i32 v7, v10, 0, 16
; GCN-HSA-NEXT: v_bfe_i32 v17, v18, 0, 16 ; GCN-HSA-NEXT: v_bfe_i32 v9, v9, 0, 16
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[19:22] ; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[19:22]
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0 ; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2 ; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v9, 16, v8 ; GCN-HSA-NEXT: v_bfe_i32 v3, v8, 0, 16
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v7, 16, v14 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v8, 31, v7
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v16, 31, v15 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v10, 31, v9
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v18, 31, v17
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3 ; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x80 ; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x80
; GCN-HSA-NEXT: v_bfe_i32 v13, v7, 0, 16 ; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[7:10]
; GCN-HSA-NEXT: v_bfe_i32 v7, v8, 0, 16
; GCN-HSA-NEXT: v_bfe_i32 v9, v9, 0, 16
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[15:18]
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0 ; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2 ; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v8, 31, v7 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v4, 31, v3
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v10, 31, v9 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v6, 31, v5
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3 ; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x60 ; GCN-HSA-NEXT: s_add_u32 s2, s0, 0x60
; GCN-HSA-NEXT: v_bfe_i32 v11, v14, 0, 16 ; GCN-HSA-NEXT: v_lshrrev_b32_e32 v18, 16, v12
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[7:10] ; GCN-HSA-NEXT: v_bfe_i32 v17, v17, 0, 16
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[3:6]
; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0 ; GCN-HSA-NEXT: s_addc_u32 s3, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2 ; GCN-HSA-NEXT: v_mov_b32_e32 v0, s2
; GCN-HSA-NEXT: v_lshrrev_b32_e32 v5, 16, v12 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v16, 31, v15
; GCN-HSA-NEXT: v_bfe_i32 v3, v12, 0, 16 ; GCN-HSA-NEXT: v_bfe_i32 v13, v18, 0, 16
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v12, 31, v11 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v18, 31, v17
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v14, 31, v13
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3 ; GCN-HSA-NEXT: v_mov_b32_e32 v1, s3
; GCN-HSA-NEXT: s_add_u32 s0, s0, 64 ; GCN-HSA-NEXT: s_add_u32 s0, s0, 64
; GCN-HSA-NEXT: v_bfe_i32 v5, v5, 0, 16 ; GCN-HSA-NEXT: v_bfe_i32 v11, v12, 0, 16
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[11:14] ; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[15:18]
; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0 ; GCN-HSA-NEXT: s_addc_u32 s1, s1, 0
; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0 ; GCN-HSA-NEXT: v_mov_b32_e32 v0, s0
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v4, 31, v3 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v12, 31, v11
; GCN-HSA-NEXT: v_ashrrev_i32_e32 v6, 31, v5 ; GCN-HSA-NEXT: v_ashrrev_i32_e32 v14, 31, v13
; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1 ; GCN-HSA-NEXT: v_mov_b32_e32 v1, s1
; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[3:6] ; GCN-HSA-NEXT: flat_store_dwordx4 v[0:1], v[11:14]
; GCN-HSA-NEXT: s_endpgm ; GCN-HSA-NEXT: s_endpgm
; ;
; GCN-NOHSA-VI-LABEL: global_sextload_v32i16_to_v32i64: ; GCN-NOHSA-VI-LABEL: global_sextload_v32i16_to_v32i64:
; GCN-NOHSA-VI: ; %bb.0: ; GCN-NOHSA-VI: ; %bb.0:
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN-NOHSA-VI-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NOHSA-VI-NEXT: s_mov_b32 s3, 0xf000
; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, -1 ; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, -1
; GCN-NOHSA-VI-NEXT: s_mov_b32 s10, s2 ; GCN-NOHSA-VI-NEXT: s_mov_b32 s10, s2
; GCN-NOHSA-VI-NEXT: s_mov_b32 s11, s3 ; GCN-NOHSA-VI-NEXT: s_mov_b32 s11, s3
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-VI-NEXT: s_mov_b32 s8, s6 ; GCN-NOHSA-VI-NEXT: s_mov_b32 s8, s6
; GCN-NOHSA-VI-NEXT: s_mov_b32 s9, s7 ; GCN-NOHSA-VI-NEXT: s_mov_b32 s9, s7
; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 offset:48 ; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 offset:48
; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:32 ; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:32
; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[8:11], off, s[8:11], 0 offset:16 ; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[8:11], off, s[8:11], 0 offset:16
; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[12:15], off, s[8:11], 0 ; GCN-NOHSA-VI-NEXT: buffer_load_dwordx4 v[12:15], off, s[8:11], 0
; GCN-NOHSA-VI-NEXT: s_mov_b32 s0, s4 ; GCN-NOHSA-VI-NEXT: s_mov_b32 s0, s4
; GCN-NOHSA-VI-NEXT: s_mov_b32 s1, s5 ; GCN-NOHSA-VI-NEXT: s_mov_b32 s1, s5
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(3) ; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(3)
; GCN-NOHSA-VI-NEXT: v_ashrrev_i64 v[22:23], 48, v[0:1] ; GCN-NOHSA-VI-NEXT: v_ashrrev_i64 v[26:27], 48, v[0:1]
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v20, v1, 0, 16 ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v24, v1, 0, 16
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v21, 31, v20 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v25, 31, v24
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[20:23], off, s[0:3], 0 offset:208 ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[24:27], off, s[0:3], 0 offset:208
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v19, v3 ; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v22, v3
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(3) ; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(3)
; GCN-NOHSA-VI-NEXT: v_ashrrev_i64 v[22:23], 48, v[4:5] ; GCN-NOHSA-VI-NEXT: v_ashrrev_i64 v[26:27], 48, v[4:5]
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v20, v5, 0, 16 ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v24, v5, 0, 16
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v21, 31, v20 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v25, 31, v24
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[20:23], off, s[0:3], 0 offset:144 ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[24:27], off, s[0:3], 0 offset:144
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v19, v19, 0, 16 ; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v20, v7
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(3) ; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(3)
; GCN-NOHSA-VI-NEXT: v_ashrrev_i64 v[22:23], 48, v[8:9] ; GCN-NOHSA-VI-NEXT: v_ashrrev_i64 v[26:27], 48, v[8:9]
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v20, v9, 0, 16 ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v24, v9, 0, 16
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v21, 31, v20 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v25, 31, v24
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[20:23], off, s[0:3], 0 offset:80 ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[24:27], off, s[0:3], 0 offset:80
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v18, v7 ; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v19, v11
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(3) ; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(3)
; GCN-NOHSA-VI-NEXT: v_ashrrev_i64 v[22:23], 48, v[12:13] ; GCN-NOHSA-VI-NEXT: v_ashrrev_i64 v[26:27], 48, v[12:13]
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v20, v13, 0, 16 ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v24, v13, 0, 16
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v21, 31, v20 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v25, 31, v24
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[20:23], off, s[0:3], 0 offset:16 ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[24:27], off, s[0:3], 0 offset:16
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v18, v18, 0, 16 ; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v17, 16, v2
; GCN-NOHSA-VI-NEXT: v_ashrrev_i64 v[21:22], 48, v[2:3] ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v24, v22, 0, 16
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v20, 31, v19 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i64 v[26:27], 48, v[2:3]
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[19:22], off, s[0:3], 0 offset:240 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v25, 31, v24
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v17, v11 ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[24:27], off, s[0:3], 0 offset:240
; GCN-NOHSA-VI-NEXT: v_ashrrev_i64 v[20:21], 48, v[6:7] ; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v18, v15
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v19, 31, v18 ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v24, v20, 0, 16
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[18:21], off, s[0:3], 0 offset:176 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i64 v[26:27], 48, v[6:7]
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v17, v17, 0, 16 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v25, 31, v24
; GCN-NOHSA-VI-NEXT: v_ashrrev_i64 v[19:20], 48, v[10:11] ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[24:27], off, s[0:3], 0 offset:176
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v16, v15 ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v13, v17, 0, 16
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v18, 31, v17 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i64 v[26:27], 48, v[10:11]
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[17:20], off, s[0:3], 0 offset:112 ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v24, v19, 0, 16
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v16, v16, 0, 16 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v25, 31, v24
; GCN-NOHSA-VI-NEXT: v_ashrrev_i64 v[18:19], 48, v[14:15] ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v11, v2, 0, 16
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2 ; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v23, 16, v8
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v17, 31, v16 ; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v28, 16, v14
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v15, v2, 0, 16 ; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v3, 16, v12
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[24:27], off, s[0:3], 0 offset:112
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v1, v12, 0, 16
; GCN-NOHSA-VI-NEXT: v_ashrrev_i64 v[26:27], 48, v[14:15]
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v24, v18, 0, 16
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v5, v14, 0, 16
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v12, 31, v11
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v14, 31, v13
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v2, 16, v6 ; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v2, 16, v6
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:48 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v25, 31, v24
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[11:14], off, s[0:3], 0 offset:224
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v16, 16, v4
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v11, v23, 0, 16
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v23, v2, 0, 16 ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v23, v2, 0, 16
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v17, v1, 0, 16
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0 ; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v22, 16, v4
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v21, 16, v10 ; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v21, 16, v10
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v9, 16, v8 ; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[24:27], off, s[0:3], 0 offset:48
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v7, 16, v14 ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v3, v3, 0, 16
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v16, 31, v15
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v18, 31, v17
; GCN-NOHSA-VI-NEXT: v_lshrrev_b32_e32 v1, 16, v12
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v25, v0, 0, 16 ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v25, v0, 0, 16
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v27, v2, 0, 16 ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v27, v2, 0, 16
; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[15:18], off, s[0:3], 0 offset:224
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v3, v1, 0, 16
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v1, v12, 0, 16
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v5, v14, 0, 16
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v7, v7, 0, 16
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v11, v9, 0, 16
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v9, v8, 0, 16 ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v9, v8, 0, 16
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v13, v10, 0, 16 ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v13, v10, 0, 16
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v7, v28, 0, 16
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v15, v21, 0, 16 ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v15, v21, 0, 16
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v19, v22, 0, 16 ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v19, v16, 0, 16
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v17, v4, 0, 16 ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v17, v4, 0, 16
; GCN-NOHSA-VI-NEXT: v_bfe_i32 v21, v6, 0, 16 ; GCN-NOHSA-VI-NEXT: v_bfe_i32 v21, v6, 0, 16
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v26, 31, v25 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v26, 31, v25
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v28, 31, v27 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v28, 31, v27
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v2, 31, v1 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v2, 31, v1
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v6, 31, v5 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v6, 31, v5
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v10, 31, v9 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v10, 31, v9
; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v14, 31, v13 ; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v14, 31, v13
▲ Show 20 Lines • Show All 369 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/loop-live-out-copy-undef-subrange.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -amdgpu-enable-rewrite-partial-reg-uses=false -verify-machineinstrs < %s | FileCheck %s
; This example used to produce a verifier error resulting from the ; This example used to produce a verifier error resulting from the
; register coalescer leaving behind a false live interval when a live ; register coalescer leaving behind a false live interval when a live
; out copy introduced new liveness for a subregister. ; out copy introduced new liveness for a subregister.
define <3 x float> @liveout_undef_subrange(<3 x float> %arg) { define <3 x float> @liveout_undef_subrange(<3 x float> %arg) {
; CHECK-LABEL: liveout_undef_subrange: ; CHECK-LABEL: liveout_undef_subrange:
; CHECK: ; %bb.0: ; %bb ; CHECK: ; %bb.0: ; %bb
Show All 40 Lines

llvm/test/CodeGen/AMDGPU/mad_64_32.ll

Show First 20 Lines • Show All 149 Lines • ▼ Show 20 Lines; GFX11-NEXT: s_setpc_b64 s[30:31]
ret i64 %mad ret i64 %mad
} }
define i128 @mad_i64_i32_sextops_i32_i128(i32 %arg0, i32 %arg1, i128 %arg2) #0 { define i128 @mad_i64_i32_sextops_i32_i128(i32 %arg0, i32 %arg1, i128 %arg2) #0 {
; CI-LABEL: mad_i64_i32_sextops_i32_i128: ; CI-LABEL: mad_i64_i32_sextops_i32_i128:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v0, v1, 0 ; CI-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v0, v1, 0
; CI-NEXT: v_ashrrev_i32_e32 v13, 31, v0 ; CI-NEXT: v_ashrrev_i32_e32 v12, 31, v0
; CI-NEXT: v_mov_b32_e32 v8, 0 ; CI-NEXT: v_mov_b32_e32 v8, 0
; CI-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v13, v1, v[7:8] ; CI-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v12, v1, v[7:8]
; CI-NEXT: v_ashrrev_i32_e32 v14, 31, v1 ; CI-NEXT: v_ashrrev_i32_e32 v13, 31, v1
; CI-NEXT: v_mad_i64_i32 v[11:12], s[4:5], v1, v13, 0 ; CI-NEXT: v_mov_b32_e32 v11, v10
; CI-NEXT: v_mov_b32_e32 v7, v10
; CI-NEXT: v_mov_b32_e32 v10, v8 ; CI-NEXT: v_mov_b32_e32 v10, v8
; CI-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v0, v14, v[9:10] ; CI-NEXT: v_mad_u64_u32 v[7:8], s[4:5], v0, v13, v[9:10]
; CI-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v14, v0, v[11:12] ; CI-NEXT: v_add_i32_e32 v8, vcc, v11, v8
; CI-NEXT: v_add_i32_e32 v9, vcc, v7, v9 ; CI-NEXT: v_mad_i64_i32 v[10:11], s[4:5], v1, v12, 0
; CI-NEXT: v_addc_u32_e64 v10, s[4:5], 0, 0, vcc ; CI-NEXT: v_addc_u32_e64 v9, s[4:5], 0, 0, vcc
; CI-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v13, v14, v[9:10] ; CI-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v12, v13, v[8:9]
; CI-NEXT: v_add_i32_e32 v7, vcc, v9, v0 ; CI-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v13, v0, v[10:11]
; CI-NEXT: v_addc_u32_e32 v9, vcc, v10, v1, vcc ; CI-NEXT: v_add_i32_e32 v8, vcc, v8, v0
; CI-NEXT: v_mov_b32_e32 v1, v8 ; CI-NEXT: v_addc_u32_e32 v9, vcc, v9, v1, vcc
; CI-NEXT: v_mov_b32_e32 v1, v7
; CI-NEXT: v_add_i32_e32 v0, vcc, v6, v2 ; CI-NEXT: v_add_i32_e32 v0, vcc, v6, v2
; CI-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; CI-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc ; CI-NEXT: v_addc_u32_e32 v2, vcc, v8, v4, vcc
; CI-NEXT: v_addc_u32_e32 v3, vcc, v9, v5, vcc ; CI-NEXT: v_addc_u32_e32 v3, vcc, v9, v5, vcc
; CI-NEXT: s_setpc_b64 s[30:31] ; CI-NEXT: s_setpc_b64 s[30:31]
; ;
; SI-LABEL: mad_i64_i32_sextops_i32_i128: ; SI-LABEL: mad_i64_i32_sextops_i32_i128:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_ashrrev_i32_e32 v6, 31, v0 ; SI-NEXT: v_ashrrev_i32_e32 v6, 31, v0
; SI-NEXT: v_mul_lo_u32 v11, v6, v1 ; SI-NEXT: v_mul_lo_u32 v11, v6, v1
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_mad_u64_u32 v[6:7], null, v0, v1, 0 ; GFX11-NEXT: v_mad_u64_u32 v[6:7], null, v0, v1, 0
; GFX11-NEXT: v_mov_b32_e32 v8, 0 ; GFX11-NEXT: v_mov_b32_e32 v8, 0
; GFX11-NEXT: v_ashrrev_i32_e32 v14, 31, v0 ; GFX11-NEXT: v_ashrrev_i32_e32 v14, 31, v0
; GFX11-NEXT: v_ashrrev_i32_e32 v15, 31, v1 ; GFX11-NEXT: v_ashrrev_i32_e32 v15, 31, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mad_u64_u32 v[9:10], null, v14, v1, v[7:8] ; GFX11-NEXT: v_mad_u64_u32 v[9:10], null, v14, v1, v[7:8]
; GFX11-NEXT: v_dual_mov_b32 v7, v10 :: v_dual_mov_b32 v10, v8 ; GFX11-NEXT: v_dual_mov_b32 v11, v10 :: v_dual_mov_b32 v10, v8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_mad_u64_u32 v[11:12], null, v0, v15, v[9:10]
; GFX11-NEXT: v_mad_i64_i32 v[9:10], null, v1, v14, 0
; GFX11-NEXT: v_mov_b32_e32 v8, v12
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_mad_i64_i32 v[12:13], null, v15, v0, v[9:10]
; GFX11-NEXT: v_add_co_u32 v7, s0, v7, v8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v8, null, 0, 0, s0 ; GFX11-NEXT: v_mad_u64_u32 v[7:8], null, v0, v15, v[9:10]
; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v14, v15, v[7:8] ; GFX11-NEXT: v_mov_b32_e32 v10, v8
; GFX11-NEXT: v_mov_b32_e32 v7, v11 ; GFX11-NEXT: v_mad_i64_i32 v[8:9], null, v1, v14, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_u32 v10, s0, v11, v10
; GFX11-NEXT: v_add_co_ci_u32_e64 v11, null, 0, 0, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_mad_i64_i32 v[12:13], null, v15, v0, v[8:9]
; GFX11-NEXT: v_mad_u64_u32 v[0:1], null, v14, v15, v[10:11]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v0, v12 ; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v0, v12
; GFX11-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, v1, v13, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, v1, v13, vcc_lo
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v6, v2 ; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v6, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v7, v3, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v7, v3, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v8, v4, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v8, v4, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v9, v5, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v9, v5, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
%sext0 = sext i32 %arg0 to i128 %sext0 = sext i32 %arg0 to i128
%sext1 = sext i32 %arg1 to i128 %sext1 = sext i32 %arg1 to i128
%mul = mul i128 %sext0, %sext1 %mul = mul i128 %sext0, %sext1
%mad = add i128 %mul, %arg2 %mad = add i128 %mul, %arg2
ret i128 %mad ret i128 %mad
} }
▲ Show 20 Lines • Show All 649 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/mul.ll

Show First 20 Lines • Show All 2,193 Lines • ▼ Show 20 Lines
; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v3, vcc
; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1] ; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
; VI-NEXT: flat_load_dwordx4 v[4:7], v[8:9] ; VI-NEXT: flat_load_dwordx4 v[4:7], v[8:9]
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mul_lo_u32 v10, v4, v3 ; VI-NEXT: v_mul_lo_u32 v10, v4, v3
; VI-NEXT: v_mad_u64_u32 v[12:13], s[0:1], v4, v2, 0 ; VI-NEXT: v_mad_u64_u32 v[12:13], s[0:1], v4, v2, 0
; VI-NEXT: v_mul_lo_u32 v14, v5, v2 ; VI-NEXT: v_mul_lo_u32 v14, v5, v2
; VI-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v0, v4, 0 ; VI-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v0, v4, 0
; VI-NEXT: v_mul_lo_u32 v15, v7, v0 ; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v10
; VI-NEXT: v_add_u32_e32 v7, vcc, v13, v10
; VI-NEXT: v_mov_b32_e32 v10, v3 ; VI-NEXT: v_mov_b32_e32 v10, v3
; VI-NEXT: v_mad_u64_u32 v[3:4], s[0:1], v1, v4, v[10:11] ; VI-NEXT: v_mad_u64_u32 v[3:4], s[0:1], v1, v4, v[10:11]
; VI-NEXT: v_add_u32_e32 v13, vcc, v7, v14 ; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v14
; VI-NEXT: v_mov_b32_e32 v7, v4 ; VI-NEXT: v_mov_b32_e32 v10, v4
; VI-NEXT: v_mov_b32_e32 v4, v11 ; VI-NEXT: v_mov_b32_e32 v4, v11
; VI-NEXT: v_mul_lo_u32 v7, v7, v0
; VI-NEXT: v_mad_u64_u32 v[12:13], s[0:1], v6, v0, v[12:13] ; VI-NEXT: v_mad_u64_u32 v[12:13], s[0:1], v6, v0, v[12:13]
; VI-NEXT: v_mad_u64_u32 v[3:4], s[0:1], v0, v5, v[3:4] ; VI-NEXT: v_mad_u64_u32 v[3:4], s[0:1], v0, v5, v[3:4]
; VI-NEXT: v_add_u32_e32 v11, vcc, v15, v13 ; VI-NEXT: v_add_u32_e32 v13, vcc, v7, v13
; VI-NEXT: v_mov_b32_e32 v0, v4 ; VI-NEXT: v_mov_b32_e32 v0, v4
; VI-NEXT: v_mul_lo_u32 v10, v6, v1 ; VI-NEXT: v_mul_lo_u32 v11, v6, v1
; VI-NEXT: v_add_u32_e32 v6, vcc, v7, v0 ; VI-NEXT: v_add_u32_e32 v6, vcc, v10, v0
; VI-NEXT: v_addc_u32_e64 v7, s[0:1], 0, 0, vcc ; VI-NEXT: v_addc_u32_e64 v7, s[0:1], 0, 0, vcc
; VI-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v1, v5, v[6:7] ; VI-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v1, v5, v[6:7]
; VI-NEXT: v_add_u32_e32 v5, vcc, v10, v11 ; VI-NEXT: v_add_u32_e32 v5, vcc, v11, v13
; VI-NEXT: v_add_u32_e32 v4, vcc, v0, v12 ; VI-NEXT: v_add_u32_e32 v4, vcc, v0, v12
; VI-NEXT: v_addc_u32_e32 v5, vcc, v1, v5, vcc ; VI-NEXT: v_addc_u32_e32 v5, vcc, v1, v5, vcc
; VI-NEXT: flat_store_dwordx4 v[8:9], v[2:5] ; VI-NEXT: flat_store_dwordx4 v[8:9], v[2:5]
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_mul_i128: ; GFX9-LABEL: v_mul_i128:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x2c ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x2c
; GFX9-NEXT: v_lshlrev_b32_e32 v13, 4, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v13, 4, v0
; GFX9-NEXT: v_mov_b32_e32 v10, 0 ; GFX9-NEXT: v_mov_b32_e32 v10, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dwordx4 v[0:3], v13, s[0:1] ; GFX9-NEXT: global_load_dwordx4 v[0:3], v13, s[0:1]
; GFX9-NEXT: global_load_dwordx4 v[4:7], v13, s[2:3] ; GFX9-NEXT: global_load_dwordx4 v[4:7], v13, s[2:3]
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mad_u64_u32 v[8:9], s[0:1], v0, v4, 0 ; GFX9-NEXT: v_mad_u64_u32 v[8:9], s[0:1], v0, v4, 0
; GFX9-NEXT: v_mul_lo_u32 v14, v5, v2 ; GFX9-NEXT: v_mul_lo_u32 v14, v5, v2
; GFX9-NEXT: v_mul_lo_u32 v15, v4, v3 ; GFX9-NEXT: v_mul_lo_u32 v15, v4, v3
; GFX9-NEXT: v_mad_u64_u32 v[11:12], s[0:1], v1, v4, v[9:10] ; GFX9-NEXT: v_mad_u64_u32 v[11:12], s[0:1], v1, v4, v[9:10]
; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v4, v2, 0 ; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v4, v2, 0
; GFX9-NEXT: v_mov_b32_e32 v4, v12 ; GFX9-NEXT: v_mul_lo_u32 v16, v7, v0
; GFX9-NEXT: v_mov_b32_e32 v7, v12
; GFX9-NEXT: v_mov_b32_e32 v12, v10 ; GFX9-NEXT: v_mov_b32_e32 v12, v10
; GFX9-NEXT: v_mad_u64_u32 v[9:10], s[0:1], v0, v5, v[11:12] ; GFX9-NEXT: v_mad_u64_u32 v[9:10], s[0:1], v0, v5, v[11:12]
; GFX9-NEXT: v_add3_u32 v3, v3, v15, v14 ; GFX9-NEXT: v_add3_u32 v3, v3, v15, v14
; GFX9-NEXT: v_mul_lo_u32 v17, v7, v0
; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v6, v0, v[2:3] ; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v6, v0, v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v0, v10 ; GFX9-NEXT: v_mov_b32_e32 v0, v10
; GFX9-NEXT: v_mul_lo_u32 v16, v6, v1 ; GFX9-NEXT: v_mul_lo_u32 v4, v6, v1
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v4, v0 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v0
; GFX9-NEXT: v_addc_co_u32_e64 v7, s[0:1], 0, 0, vcc ; GFX9-NEXT: v_addc_co_u32_e64 v7, s[0:1], 0, 0, vcc
; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v1, v5, v[6:7] ; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v1, v5, v[6:7]
; GFX9-NEXT: v_add3_u32 v3, v17, v3, v16 ; GFX9-NEXT: v_add3_u32 v3, v16, v3, v4
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v0, v2 ; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v0, v2
; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v1, v3, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v1, v3, vcc
; GFX9-NEXT: global_store_dwordx4 v13, v[8:11], s[2:3] ; GFX9-NEXT: global_store_dwordx4 v13, v[8:11], s[2:3]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: v_mul_i128: ; GFX10-LABEL: v_mul_i128:
; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x2c ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x2c
; GFX10-NEXT: v_lshlrev_b32_e32 v14, 4, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v13, 4, v0
; GFX10-NEXT: v_mov_b32_e32 v10, 0 ; GFX10-NEXT: v_mov_b32_e32 v10, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: global_load_dwordx4 v[0:3], v14, s[0:1] ; GFX10-NEXT: global_load_dwordx4 v[0:3], v13, s[0:1]
; GFX10-NEXT: global_load_dwordx4 v[4:7], v14, s[2:3] ; GFX10-NEXT: global_load_dwordx4 v[4:7], v13, s[2:3]
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_mad_u64_u32 v[8:9], s0, v0, v4, 0 ; GFX10-NEXT: v_mad_u64_u32 v[8:9], s0, v0, v4, 0
; GFX10-NEXT: v_mul_lo_u32 v15, v5, v2
; GFX10-NEXT: v_mul_lo_u32 v7, v7, v0 ; GFX10-NEXT: v_mul_lo_u32 v7, v7, v0
; GFX10-NEXT: v_mad_u64_u32 v[11:12], s0, v1, v4, v[9:10] ; GFX10-NEXT: v_mad_u64_u32 v[11:12], s0, v1, v4, v[9:10]
; GFX10-NEXT: v_mov_b32_e32 v9, v12 ; GFX10-NEXT: v_mov_b32_e32 v14, v12
; GFX10-NEXT: v_mov_b32_e32 v12, v10 ; GFX10-NEXT: v_mov_b32_e32 v12, v10
; GFX10-NEXT: v_mul_lo_u32 v10, v5, v2 ; GFX10-NEXT: v_mad_u64_u32 v[9:10], s0, v0, v5, v[11:12]
; GFX10-NEXT: v_mad_u64_u32 v[12:13], s0, v0, v5, v[11:12]
; GFX10-NEXT: v_mul_lo_u32 v11, v4, v3 ; GFX10-NEXT: v_mul_lo_u32 v11, v4, v3
; GFX10-NEXT: v_mad_u64_u32 v[2:3], s0, v4, v2, 0 ; GFX10-NEXT: v_mad_u64_u32 v[2:3], s0, v4, v2, 0
; GFX10-NEXT: v_mov_b32_e32 v4, v13 ; GFX10-NEXT: v_mul_lo_u32 v12, v6, v1
; GFX10-NEXT: v_mul_lo_u32 v13, v6, v1 ; GFX10-NEXT: v_mov_b32_e32 v4, v10
; GFX10-NEXT: v_add3_u32 v3, v3, v11, v10 ; GFX10-NEXT: v_add3_u32 v3, v3, v11, v15
; GFX10-NEXT: v_add_co_u32 v9, s0, v9, v4 ; GFX10-NEXT: v_add_co_u32 v10, s0, v14, v4
; GFX10-NEXT: v_add_co_ci_u32_e64 v10, s0, 0, 0, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v11, s0, 0, 0, s0
; GFX10-NEXT: v_mad_u64_u32 v[2:3], s0, v6, v0, v[2:3] ; GFX10-NEXT: v_mad_u64_u32 v[2:3], s0, v6, v0, v[2:3]
; GFX10-NEXT: v_mad_u64_u32 v[0:1], s0, v1, v5, v[9:10] ; GFX10-NEXT: v_mad_u64_u32 v[0:1], s0, v1, v5, v[10:11]
; GFX10-NEXT: v_mov_b32_e32 v9, v12 ; GFX10-NEXT: v_add3_u32 v3, v7, v3, v12
; GFX10-NEXT: v_add3_u32 v3, v7, v3, v13
; GFX10-NEXT: v_add_co_u32 v10, vcc_lo, v0, v2 ; GFX10-NEXT: v_add_co_u32 v10, vcc_lo, v0, v2
; GFX10-NEXT: v_add_co_ci_u32_e32 v11, vcc_lo, v1, v3, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v11, vcc_lo, v1, v3, vcc_lo
; GFX10-NEXT: global_store_dwordx4 v14, v[8:11], s[2:3] ; GFX10-NEXT: global_store_dwordx4 v13, v[8:11], s[2:3]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX11-LABEL: v_mul_i128: ; GFX11-LABEL: v_mul_i128:
; GFX11: ; %bb.0: ; %entry ; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x2c ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x2c
; GFX11-NEXT: v_lshlrev_b32_e32 v16, 4, v0 ; GFX11-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_lshlrev_b32 v15, 4, v0
; GFX11-NEXT: v_mov_b32_e32 v10, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: global_load_b128 v[0:3], v16, s[0:1] ; GFX11-NEXT: global_load_b128 v[0:3], v15, s[0:1]
; GFX11-NEXT: global_load_b128 v[4:7], v16, s[2:3] ; GFX11-NEXT: global_load_b128 v[4:7], v15, s[2:3]
; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_mad_u64_u32 v[8:9], null, v0, v4, 0 ; GFX11-NEXT: v_mad_u64_u32 v[8:9], null, v0, v4, 0
; GFX11-NEXT: v_mul_lo_u32 v15, v5, v2 ; GFX11-NEXT: v_mul_lo_u32 v14, v5, v2
; GFX11-NEXT: v_mul_lo_u32 v3, v4, v3 ; GFX11-NEXT: v_mul_lo_u32 v3, v4, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mad_u64_u32 v[11:12], null, v1, v4, v[9:10] ; GFX11-NEXT: v_mad_u64_u32 v[11:12], null, v1, v4, v[9:10]
; GFX11-NEXT: v_dual_mov_b32 v9, v12 :: v_dual_mov_b32 v12, v10 ; GFX11-NEXT: v_dual_mov_b32 v13, v12 :: v_dual_mov_b32 v12, v10
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_mad_u64_u32 v[13:14], null, v0, v5, v[11:12] ; GFX11-NEXT: v_mad_u64_u32 v[9:10], null, v0, v5, v[11:12]
; GFX11-NEXT: v_mad_u64_u32 v[10:11], null, v4, v2, 0 ; GFX11-NEXT: v_mad_u64_u32 v[11:12], null, v4, v2, 0
; GFX11-NEXT: v_mul_lo_u32 v4, v6, v1 ; GFX11-NEXT: v_mul_lo_u32 v4, v6, v1
; GFX11-NEXT: v_mul_lo_u32 v12, v7, v0 ; GFX11-NEXT: v_mov_b32_e32 v2, v10
; GFX11-NEXT: v_mov_b32_e32 v2, v14 ; GFX11-NEXT: v_mul_lo_u32 v10, v7, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_add3_u32 v11, v11, v3, v15 ; GFX11-NEXT: v_add3_u32 v12, v12, v3, v14
; GFX11-NEXT: v_add_co_u32 v2, s0, v9, v2 ; GFX11-NEXT: v_add_co_u32 v2, s0, v13, v2
; GFX11-NEXT: v_mov_b32_e32 v9, v13 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, 0, s0 ; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, 0, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_mad_u64_u32 v[13:14], null, v6, v0, v[11:12]
; GFX11-NEXT: v_mad_u64_u32 v[14:15], null, v6, v0, v[10:11] ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_mad_u64_u32 v[6:7], null, v1, v5, v[2:3] ; GFX11-NEXT: v_mad_u64_u32 v[6:7], null, v1, v5, v[2:3]
; GFX11-NEXT: v_add3_u32 v0, v10, v14, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add3_u32 v0, v12, v15, v4 ; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, v6, v13
; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, v6, v14
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_add_co_ci_u32_e32 v11, vcc_lo, v7, v0, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v11, vcc_lo, v7, v0, vcc_lo
; GFX11-NEXT: global_store_b128 v16, v[8:11], s[2:3] ; GFX11-NEXT: global_store_b128 v15, v[8:11], s[2:3]
; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_nop 0
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-NEXT: s_endpgm ; GFX11-NEXT: s_endpgm
; ;
; EG-LABEL: v_mul_i128: ; EG-LABEL: v_mul_i128:
; EG: ; %bb.0: ; %entry ; EG: ; %bb.0: ; %entry
; EG-NEXT: ALU 3, @10, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 3, @10, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 1 @6 ; EG-NEXT: TEX 1 @6
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llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll

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; GFX8-NEXT: v_mov_b32_e32 v31, v0 ; GFX8-NEXT: v_mov_b32_e32 v31, v0
; GFX8-NEXT: s_mov_b64 s[2:3], s[38:39] ; GFX8-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX8-NEXT: v_mov_b32_e32 v0, 0 ; GFX8-NEXT: v_mov_b32_e32 v0, 0
; GFX8-NEXT: s_mov_b32 s32, 0 ; GFX8-NEXT: s_mov_b32 s32, 0
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX8-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v0 ; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v0
; GFX8-NEXT: v_mov_b32_e32 v2, 0 ; GFX8-NEXT: v_mov_b32_e32 v2, 0
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 17, v0 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 17, v0
; GFX8-NEXT: v_lshlrev_b64 v[1:2], 3, v[1:2] ; GFX8-NEXT: v_lshlrev_b64 v[0:1], 3, v[1:2]
; GFX8-NEXT: v_and_b32_e32 v0, 0xfe000000, v0 ; GFX8-NEXT: v_and_b32_e32 v6, 0xfe000000, v3
; GFX8-NEXT: v_or_b32_e32 v1, v1, v0 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v6
; GFX8-NEXT: v_mov_b32_e32 v3, s35 ; GFX8-NEXT: v_mov_b32_e32 v2, s35
; GFX8-NEXT: v_add_u32_e32 v1, vcc, s34, v1 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s34, v0
; GFX8-NEXT: v_addc_u32_e32 v2, vcc, v2, v3, vcc ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
; GFX8-NEXT: s_movk_i32 s0, 0x5000 ; GFX8-NEXT: s_movk_i32 s0, 0x5000
; GFX8-NEXT: v_add_u32_e32 v1, vcc, s0, v1 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
; GFX8-NEXT: v_mov_b32_e32 v2, 0
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: v_mov_b32_e32 v3, 0 ; GFX8-NEXT: v_mov_b32_e32 v3, 0
; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc
; GFX8-NEXT: v_mov_b32_e32 v4, 0
; GFX8-NEXT: s_movk_i32 s0, 0x7f ; GFX8-NEXT: s_movk_i32 s0, 0x7f
; GFX8-NEXT: .LBB1_1: ; %for.cond.preheader ; GFX8-NEXT: .LBB1_1: ; %for.cond.preheader
; GFX8-NEXT: ; =>This Loop Header: Depth=1 ; GFX8-NEXT: ; =>This Loop Header: Depth=1
; GFX8-NEXT: ; Child Loop BB1_2 Depth 2 ; GFX8-NEXT: ; Child Loop BB1_2 Depth 2
; GFX8-NEXT: v_mov_b32_e32 v6, v2
; GFX8-NEXT: v_mov_b32_e32 v5, v1 ; GFX8-NEXT: v_mov_b32_e32 v5, v1
; GFX8-NEXT: v_mov_b32_e32 v4, v0
; GFX8-NEXT: s_mov_b32 s1, 0 ; GFX8-NEXT: s_mov_b32 s1, 0
; GFX8-NEXT: .LBB1_2: ; %for.body ; GFX8-NEXT: .LBB1_2: ; %for.body
; GFX8-NEXT: ; Parent Loop BB1_1 Depth=1 ; GFX8-NEXT: ; Parent Loop BB1_1 Depth=1
; GFX8-NEXT: ; => This Inner Loop Header: Depth=2 ; GFX8-NEXT: ; => This Inner Loop Header: Depth=2
; GFX8-NEXT: v_add_u32_e32 v7, vcc, 0xffffb000, v5 ; GFX8-NEXT: v_add_u32_e32 v7, vcc, 0xffffb000, v4
; GFX8-NEXT: v_addc_u32_e32 v8, vcc, -1, v6, vcc ; GFX8-NEXT: v_addc_u32_e32 v8, vcc, -1, v5, vcc
; GFX8-NEXT: v_add_u32_e32 v9, vcc, 0xffffb800, v5 ; GFX8-NEXT: v_add_u32_e32 v9, vcc, 0xffffb800, v4
; GFX8-NEXT: v_addc_u32_e32 v10, vcc, -1, v6, vcc ; GFX8-NEXT: v_addc_u32_e32 v10, vcc, -1, v5, vcc
; GFX8-NEXT: v_add_u32_e32 v11, vcc, 0xffffc000, v5 ; GFX8-NEXT: v_add_u32_e32 v11, vcc, 0xffffc000, v4
; GFX8-NEXT: flat_load_dwordx2 v[7:8], v[7:8] ; GFX8-NEXT: flat_load_dwordx2 v[7:8], v[7:8]
; GFX8-NEXT: flat_load_dwordx2 v[9:10], v[9:10] ; GFX8-NEXT: flat_load_dwordx2 v[9:10], v[9:10]
; GFX8-NEXT: v_addc_u32_e32 v12, vcc, -1, v6, vcc ; GFX8-NEXT: v_addc_u32_e32 v12, vcc, -1, v5, vcc
; GFX8-NEXT: v_add_u32_e32 v13, vcc, 0xffffc800, v5 ; GFX8-NEXT: v_add_u32_e32 v13, vcc, 0xffffc800, v4
; GFX8-NEXT: v_addc_u32_e32 v14, vcc, -1, v6, vcc ; GFX8-NEXT: v_addc_u32_e32 v14, vcc, -1, v5, vcc
; GFX8-NEXT: v_add_u32_e32 v15, vcc, 0xffffd000, v5 ; GFX8-NEXT: v_add_u32_e32 v15, vcc, 0xffffd000, v4
; GFX8-NEXT: flat_load_dwordx2 v[11:12], v[11:12] ; GFX8-NEXT: flat_load_dwordx2 v[11:12], v[11:12]
; GFX8-NEXT: flat_load_dwordx2 v[13:14], v[13:14] ; GFX8-NEXT: flat_load_dwordx2 v[13:14], v[13:14]
; GFX8-NEXT: v_addc_u32_e32 v16, vcc, -1, v6, vcc ; GFX8-NEXT: v_addc_u32_e32 v16, vcc, -1, v5, vcc
; GFX8-NEXT: v_add_u32_e32 v17, vcc, 0xffffd800, v5 ; GFX8-NEXT: v_add_u32_e32 v17, vcc, 0xffffd800, v4
; GFX8-NEXT: v_addc_u32_e32 v18, vcc, -1, v6, vcc ; GFX8-NEXT: v_addc_u32_e32 v18, vcc, -1, v5, vcc
; GFX8-NEXT: flat_load_dwordx2 v[15:16], v[15:16] ; GFX8-NEXT: flat_load_dwordx2 v[15:16], v[15:16]
; GFX8-NEXT: flat_load_dwordx2 v[17:18], v[17:18] ; GFX8-NEXT: flat_load_dwordx2 v[17:18], v[17:18]
; GFX8-NEXT: v_add_u32_e32 v19, vcc, 0xffffe000, v5 ; GFX8-NEXT: v_add_u32_e32 v19, vcc, 0xffffe000, v4
; GFX8-NEXT: v_addc_u32_e32 v20, vcc, -1, v6, vcc ; GFX8-NEXT: v_addc_u32_e32 v20, vcc, -1, v5, vcc
; GFX8-NEXT: v_add_u32_e32 v21, vcc, 0xffffe800, v5 ; GFX8-NEXT: v_add_u32_e32 v21, vcc, 0xffffe800, v4
; GFX8-NEXT: flat_load_dwordx2 v[19:20], v[19:20] ; GFX8-NEXT: flat_load_dwordx2 v[19:20], v[19:20]
; GFX8-NEXT: v_addc_u32_e32 v22, vcc, -1, v6, vcc ; GFX8-NEXT: v_addc_u32_e32 v22, vcc, -1, v5, vcc
; GFX8-NEXT: flat_load_dwordx2 v[21:22], v[21:22] ; GFX8-NEXT: flat_load_dwordx2 v[21:22], v[21:22]
; GFX8-NEXT: v_add_u32_e32 v23, vcc, 0xfffff000, v5 ; GFX8-NEXT: v_add_u32_e32 v23, vcc, 0xfffff000, v4
; GFX8-NEXT: v_addc_u32_e32 v24, vcc, -1, v6, vcc ; GFX8-NEXT: v_addc_u32_e32 v24, vcc, -1, v5, vcc
; GFX8-NEXT: flat_load_dwordx2 v[23:24], v[23:24] ; GFX8-NEXT: flat_load_dwordx2 v[23:24], v[23:24]
; GFX8-NEXT: v_add_u32_e32 v25, vcc, 0xfffff800, v5 ; GFX8-NEXT: v_add_u32_e32 v25, vcc, 0xfffff800, v4
; GFX8-NEXT: v_addc_u32_e32 v26, vcc, -1, v6, vcc ; GFX8-NEXT: v_addc_u32_e32 v26, vcc, -1, v5, vcc
; GFX8-NEXT: flat_load_dwordx2 v[25:26], v[25:26] ; GFX8-NEXT: flat_load_dwordx2 v[25:26], v[25:26]
; GFX8-NEXT: flat_load_dwordx2 v[27:28], v[5:6] ; GFX8-NEXT: flat_load_dwordx2 v[27:28], v[4:5]
; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x10000, v5 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, 0x10000, v4
; GFX8-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc ; GFX8-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; GFX8-NEXT: s_addk_i32 s1, 0x2000 ; GFX8-NEXT: s_addk_i32 s1, 0x2000
; GFX8-NEXT: s_cmp_gt_u32 s1, 0x3fffff ; GFX8-NEXT: s_cmp_gt_u32 s1, 0x3fffff
; GFX8-NEXT: s_waitcnt vmcnt(10) ; GFX8-NEXT: s_waitcnt vmcnt(10)
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v7, v3 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v7, v2
; GFX8-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc
; GFX8-NEXT: s_waitcnt vmcnt(9) ; GFX8-NEXT: s_waitcnt vmcnt(9)
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v9, v3 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v9, v2
; GFX8-NEXT: v_addc_u32_e32 v4, vcc, v10, v4, vcc ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v10, v3, vcc
; GFX8-NEXT: s_waitcnt vmcnt(8) ; GFX8-NEXT: s_waitcnt vmcnt(8)
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v11, v3 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v11, v2
; GFX8-NEXT: v_addc_u32_e32 v4, vcc, v12, v4, vcc ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v12, v3, vcc
; GFX8-NEXT: s_waitcnt vmcnt(7) ; GFX8-NEXT: s_waitcnt vmcnt(7)
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v13, v3 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v13, v2
; GFX8-NEXT: v_addc_u32_e32 v4, vcc, v14, v4, vcc ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v14, v3, vcc
; GFX8-NEXT: s_waitcnt vmcnt(6) ; GFX8-NEXT: s_waitcnt vmcnt(6)
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v15, v3 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v15, v2
; GFX8-NEXT: v_addc_u32_e32 v4, vcc, v16, v4, vcc ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v16, v3, vcc
; GFX8-NEXT: s_waitcnt vmcnt(5) ; GFX8-NEXT: s_waitcnt vmcnt(5)
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v17, v3 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v17, v2
; GFX8-NEXT: v_addc_u32_e32 v4, vcc, v18, v4, vcc ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v18, v3, vcc
; GFX8-NEXT: s_waitcnt vmcnt(4) ; GFX8-NEXT: s_waitcnt vmcnt(4)
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v19, v3 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v19, v2
; GFX8-NEXT: v_addc_u32_e32 v4, vcc, v20, v4, vcc ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v20, v3, vcc
; GFX8-NEXT: s_waitcnt vmcnt(3) ; GFX8-NEXT: s_waitcnt vmcnt(3)
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v21, v3 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v21, v2
; GFX8-NEXT: v_addc_u32_e32 v4, vcc, v22, v4, vcc ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v22, v3, vcc
; GFX8-NEXT: s_waitcnt vmcnt(2) ; GFX8-NEXT: s_waitcnt vmcnt(2)
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v23, v3 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v23, v2
; GFX8-NEXT: v_addc_u32_e32 v4, vcc, v24, v4, vcc ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v24, v3, vcc
; GFX8-NEXT: s_waitcnt vmcnt(1) ; GFX8-NEXT: s_waitcnt vmcnt(1)
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v25, v3 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v25, v2
; GFX8-NEXT: v_addc_u32_e32 v4, vcc, v26, v4, vcc ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v26, v3, vcc
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_add_u32_e32 v3, vcc, v27, v3 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v27, v2
; GFX8-NEXT: v_addc_u32_e32 v4, vcc, v28, v4, vcc ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v28, v3, vcc
; GFX8-NEXT: s_cbranch_scc0 .LBB1_2 ; GFX8-NEXT: s_cbranch_scc0 .LBB1_2
; GFX8-NEXT: ; %bb.3: ; %while.cond.loopexit ; GFX8-NEXT: ; %bb.3: ; %while.cond.loopexit
; GFX8-NEXT: ; in Loop: Header=BB1_1 Depth=1 ; GFX8-NEXT: ; in Loop: Header=BB1_1 Depth=1
; GFX8-NEXT: s_add_i32 s1, s0, -1 ; GFX8-NEXT: s_add_i32 s1, s0, -1
; GFX8-NEXT: s_cmp_eq_u32 s0, 0 ; GFX8-NEXT: s_cmp_eq_u32 s0, 0
; GFX8-NEXT: s_cbranch_scc1 .LBB1_5 ; GFX8-NEXT: s_cbranch_scc1 .LBB1_5
; GFX8-NEXT: ; %bb.4: ; in Loop: Header=BB1_1 Depth=1 ; GFX8-NEXT: ; %bb.4: ; in Loop: Header=BB1_1 Depth=1
; GFX8-NEXT: s_mov_b32 s0, s1 ; GFX8-NEXT: s_mov_b32 s0, s1
; GFX8-NEXT: s_branch .LBB1_1 ; GFX8-NEXT: s_branch .LBB1_1
; GFX8-NEXT: .LBB1_5: ; %while.end ; GFX8-NEXT: .LBB1_5: ; %while.end
; GFX8-NEXT: v_mov_b32_e32 v1, s35 ; GFX8-NEXT: v_mov_b32_e32 v1, s35
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s34, v0 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s34, v6
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[3:4] ; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX900-LABEL: clmem_read: ; GFX900-LABEL: clmem_read:
; GFX900: ; %bb.0: ; %entry ; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0 ; GFX900-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
; GFX900-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1 ; GFX900-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
; GFX900-NEXT: s_mov_b32 s38, -1 ; GFX900-NEXT: s_mov_b32 s38, -1
; GFX900-NEXT: s_mov_b32 s39, 0xe00000 ; GFX900-NEXT: s_mov_b32 s39, 0xe00000
; GFX900-NEXT: s_add_u32 s36, s36, s3 ; GFX900-NEXT: s_add_u32 s36, s36, s3
; GFX900-NEXT: s_addc_u32 s37, s37, 0 ; GFX900-NEXT: s_addc_u32 s37, s37, 0
; GFX900-NEXT: s_load_dwordx2 s[34:35], s[0:1], 0x24 ; GFX900-NEXT: s_load_dwordx2 s[34:35], s[0:1], 0x24
; GFX900-NEXT: s_getpc_b64 s[0:1] ; GFX900-NEXT: s_getpc_b64 s[0:1]
; GFX900-NEXT: s_add_u32 s0, s0, _Z13get_global_idj@gotpcrel32@lo+4 ; GFX900-NEXT: s_add_u32 s0, s0, _Z13get_global_idj@gotpcrel32@lo+4
; GFX900-NEXT: s_addc_u32 s1, s1, _Z13get_global_idj@gotpcrel32@hi+12 ; GFX900-NEXT: s_addc_u32 s1, s1, _Z13get_global_idj@gotpcrel32@hi+12
; GFX900-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0 ; GFX900-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
; GFX900-NEXT: s_mov_b64 s[0:1], s[36:37] ; GFX900-NEXT: s_mov_b64 s[0:1], s[36:37]
; GFX900-NEXT: v_mov_b32_e32 v31, v0 ; GFX900-NEXT: v_mov_b32_e32 v31, v0
; GFX900-NEXT: s_mov_b64 s[2:3], s[38:39] ; GFX900-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX900-NEXT: v_mov_b32_e32 v0, 0 ; GFX900-NEXT: v_mov_b32_e32 v0, 0
; GFX900-NEXT: s_mov_b32 s32, 0 ; GFX900-NEXT: s_mov_b32 s32, 0
; GFX900-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX900-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX900-NEXT: v_and_b32_e32 v1, 0xff, v0 ; GFX900-NEXT: v_and_b32_e32 v1, 0xff, v0
; GFX900-NEXT: v_mov_b32_e32 v2, 0 ; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_lshlrev_b32_e32 v0, 17, v0 ; GFX900-NEXT: v_lshlrev_b32_e32 v3, 17, v0
; GFX900-NEXT: v_lshlrev_b64 v[1:2], 3, v[1:2] ; GFX900-NEXT: v_lshlrev_b64 v[0:1], 3, v[1:2]
; GFX900-NEXT: v_and_b32_e32 v0, 0xfe000000, v0 ; GFX900-NEXT: v_and_b32_e32 v6, 0xfe000000, v3
; GFX900-NEXT: v_or_b32_e32 v1, v1, v0 ; GFX900-NEXT: v_or_b32_e32 v0, v0, v6
; GFX900-NEXT: v_mov_b32_e32 v3, s35 ; GFX900-NEXT: v_mov_b32_e32 v2, s35
; GFX900-NEXT: v_add_co_u32_e32 v1, vcc, s34, v1 ; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, s34, v0
; GFX900-NEXT: v_addc_co_u32_e32 v2, vcc, v2, v3, vcc ; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc
; GFX900-NEXT: s_movk_i32 s0, 0x5000 ; GFX900-NEXT: s_movk_i32 s0, 0x5000
; GFX900-NEXT: v_add_co_u32_e32 v1, vcc, s0, v1 ; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0
; GFX900-NEXT: v_mov_b32_e32 v3, 0 ; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc ; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX900-NEXT: s_movk_i32 s2, 0x7f ; GFX900-NEXT: s_movk_i32 s2, 0x7f
; GFX900-NEXT: v_mov_b32_e32 v4, 0 ; GFX900-NEXT: v_mov_b32_e32 v3, 0
; GFX900-NEXT: s_movk_i32 s0, 0xd000 ; GFX900-NEXT: s_movk_i32 s0, 0xd000
; GFX900-NEXT: s_movk_i32 s1, 0xe000 ; GFX900-NEXT: s_movk_i32 s1, 0xe000
; GFX900-NEXT: s_movk_i32 s3, 0xf000 ; GFX900-NEXT: s_movk_i32 s3, 0xf000
; GFX900-NEXT: .LBB1_1: ; %for.cond.preheader ; GFX900-NEXT: .LBB1_1: ; %for.cond.preheader
; GFX900-NEXT: ; =>This Loop Header: Depth=1 ; GFX900-NEXT: ; =>This Loop Header: Depth=1
; GFX900-NEXT: ; Child Loop BB1_2 Depth 2 ; GFX900-NEXT: ; Child Loop BB1_2 Depth 2
; GFX900-NEXT: v_mov_b32_e32 v6, v2
; GFX900-NEXT: v_mov_b32_e32 v5, v1 ; GFX900-NEXT: v_mov_b32_e32 v5, v1
; GFX900-NEXT: v_mov_b32_e32 v4, v0
; GFX900-NEXT: s_mov_b32 s4, 0 ; GFX900-NEXT: s_mov_b32 s4, 0
; GFX900-NEXT: .LBB1_2: ; %for.body ; GFX900-NEXT: .LBB1_2: ; %for.body
; GFX900-NEXT: ; Parent Loop BB1_1 Depth=1 ; GFX900-NEXT: ; Parent Loop BB1_1 Depth=1
; GFX900-NEXT: ; => This Inner Loop Header: Depth=2 ; GFX900-NEXT: ; => This Inner Loop Header: Depth=2
; GFX900-NEXT: v_add_co_u32_e32 v7, vcc, 0xffffb000, v5 ; GFX900-NEXT: v_add_co_u32_e32 v7, vcc, 0xffffb000, v4
; GFX900-NEXT: v_addc_co_u32_e32 v8, vcc, -1, v6, vcc ; GFX900-NEXT: v_addc_co_u32_e32 v8, vcc, -1, v5, vcc
; GFX900-NEXT: global_load_dwordx2 v[9:10], v[5:6], off offset:-4096 ; GFX900-NEXT: global_load_dwordx2 v[9:10], v[4:5], off offset:-4096
; GFX900-NEXT: global_load_dwordx2 v[11:12], v[5:6], off offset:-2048 ; GFX900-NEXT: global_load_dwordx2 v[11:12], v[4:5], off offset:-2048
; GFX900-NEXT: v_add_co_u32_e32 v13, vcc, 0xffffc000, v5 ; GFX900-NEXT: v_add_co_u32_e32 v13, vcc, 0xffffc000, v4
; GFX900-NEXT: global_load_dwordx2 v[7:8], v[7:8], off ; GFX900-NEXT: global_load_dwordx2 v[7:8], v[7:8], off
; GFX900-NEXT: v_addc_co_u32_e32 v14, vcc, -1, v6, vcc ; GFX900-NEXT: v_addc_co_u32_e32 v14, vcc, -1, v5, vcc
; GFX900-NEXT: global_load_dwordx2 v[17:18], v[13:14], off offset:-2048 ; GFX900-NEXT: global_load_dwordx2 v[17:18], v[13:14], off offset:-2048
; GFX900-NEXT: v_add_co_u32_e32 v15, vcc, s0, v5 ; GFX900-NEXT: v_add_co_u32_e32 v15, vcc, s0, v4
; GFX900-NEXT: v_addc_co_u32_e32 v16, vcc, -1, v6, vcc ; GFX900-NEXT: v_addc_co_u32_e32 v16, vcc, -1, v5, vcc
; GFX900-NEXT: global_load_dwordx2 v[15:16], v[15:16], off offset:-2048 ; GFX900-NEXT: global_load_dwordx2 v[15:16], v[15:16], off offset:-2048
; GFX900-NEXT: v_add_co_u32_e32 v19, vcc, s1, v5 ; GFX900-NEXT: v_add_co_u32_e32 v19, vcc, s1, v4
; GFX900-NEXT: global_load_dwordx2 v[13:14], v[13:14], off ; GFX900-NEXT: global_load_dwordx2 v[13:14], v[13:14], off
; GFX900-NEXT: v_addc_co_u32_e32 v20, vcc, -1, v6, vcc ; GFX900-NEXT: v_addc_co_u32_e32 v20, vcc, -1, v5, vcc
; GFX900-NEXT: global_load_dwordx2 v[23:24], v[19:20], off offset:-4096 ; GFX900-NEXT: global_load_dwordx2 v[23:24], v[19:20], off offset:-4096
; GFX900-NEXT: global_load_dwordx2 v[25:26], v[19:20], off offset:-2048 ; GFX900-NEXT: global_load_dwordx2 v[25:26], v[19:20], off offset:-2048
; GFX900-NEXT: global_load_dwordx2 v[27:28], v[19:20], off ; GFX900-NEXT: global_load_dwordx2 v[27:28], v[19:20], off
; GFX900-NEXT: v_add_co_u32_e32 v21, vcc, s3, v5 ; GFX900-NEXT: v_add_co_u32_e32 v21, vcc, s3, v4
; GFX900-NEXT: v_addc_co_u32_e32 v22, vcc, -1, v6, vcc ; GFX900-NEXT: v_addc_co_u32_e32 v22, vcc, -1, v5, vcc
; GFX900-NEXT: global_load_dwordx2 v[19:20], v[21:22], off offset:-2048 ; GFX900-NEXT: global_load_dwordx2 v[19:20], v[21:22], off offset:-2048
; GFX900-NEXT: global_load_dwordx2 v[29:30], v[5:6], off ; GFX900-NEXT: global_load_dwordx2 v[29:30], v[4:5], off
; GFX900-NEXT: v_add_co_u32_e32 v5, vcc, 0x10000, v5 ; GFX900-NEXT: v_add_co_u32_e32 v4, vcc, 0x10000, v4
; GFX900-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc ; GFX900-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX900-NEXT: s_addk_i32 s4, 0x2000 ; GFX900-NEXT: s_addk_i32 s4, 0x2000
; GFX900-NEXT: s_cmp_gt_u32 s4, 0x3fffff ; GFX900-NEXT: s_cmp_gt_u32 s4, 0x3fffff
; GFX900-NEXT: s_waitcnt vmcnt(8) ; GFX900-NEXT: s_waitcnt vmcnt(8)
; GFX900-NEXT: v_add_co_u32_e32 v3, vcc, v7, v3 ; GFX900-NEXT: v_add_co_u32_e32 v2, vcc, v7, v2
; GFX900-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc ; GFX900-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v3, vcc
; GFX900-NEXT: s_waitcnt vmcnt(7) ; GFX900-NEXT: s_waitcnt vmcnt(7)
; GFX900-NEXT: v_add_co_u32_e32 v3, vcc, v17, v3 ; GFX900-NEXT: v_add_co_u32_e32 v2, vcc, v17, v2
; GFX900-NEXT: v_addc_co_u32_e32 v4, vcc, v18, v4, vcc ; GFX900-NEXT: v_addc_co_u32_e32 v3, vcc, v18, v3, vcc
; GFX900-NEXT: s_waitcnt vmcnt(5) ; GFX900-NEXT: s_waitcnt vmcnt(5)
; GFX900-NEXT: v_add_co_u32_e32 v3, vcc, v13, v3 ; GFX900-NEXT: v_add_co_u32_e32 v2, vcc, v13, v2
; GFX900-NEXT: v_addc_co_u32_e32 v4, vcc, v14, v4, vcc ; GFX900-NEXT: v_addc_co_u32_e32 v3, vcc, v14, v3, vcc
; GFX900-NEXT: v_add_co_u32_e32 v3, vcc, v15, v3 ; GFX900-NEXT: v_add_co_u32_e32 v2, vcc, v15, v2
; GFX900-NEXT: v_addc_co_u32_e32 v4, vcc, v16, v4, vcc ; GFX900-NEXT: v_addc_co_u32_e32 v3, vcc, v16, v3, vcc
; GFX900-NEXT: s_waitcnt vmcnt(4) ; GFX900-NEXT: s_waitcnt vmcnt(4)
; GFX900-NEXT: v_add_co_u32_e32 v3, vcc, v23, v3 ; GFX900-NEXT: v_add_co_u32_e32 v2, vcc, v23, v2
; GFX900-NEXT: v_addc_co_u32_e32 v4, vcc, v24, v4, vcc ; GFX900-NEXT: v_addc_co_u32_e32 v3, vcc, v24, v3, vcc
; GFX900-NEXT: s_waitcnt vmcnt(3) ; GFX900-NEXT: s_waitcnt vmcnt(3)
; GFX900-NEXT: v_add_co_u32_e32 v3, vcc, v25, v3 ; GFX900-NEXT: v_add_co_u32_e32 v2, vcc, v25, v2
; GFX900-NEXT: v_addc_co_u32_e32 v4, vcc, v26, v4, vcc ; GFX900-NEXT: v_addc_co_u32_e32 v3, vcc, v26, v3, vcc
; GFX900-NEXT: s_waitcnt vmcnt(2) ; GFX900-NEXT: s_waitcnt vmcnt(2)
; GFX900-NEXT: v_add_co_u32_e32 v3, vcc, v27, v3 ; GFX900-NEXT: v_add_co_u32_e32 v2, vcc, v27, v2
; GFX900-NEXT: v_addc_co_u32_e32 v4, vcc, v28, v4, vcc ; GFX900-NEXT: v_addc_co_u32_e32 v3, vcc, v28, v3, vcc
; GFX900-NEXT: s_waitcnt vmcnt(1) ; GFX900-NEXT: s_waitcnt vmcnt(1)
; GFX900-NEXT: v_add_co_u32_e32 v3, vcc, v19, v3 ; GFX900-NEXT: v_add_co_u32_e32 v2, vcc, v19, v2
; GFX900-NEXT: v_addc_co_u32_e32 v4, vcc, v20, v4, vcc ; GFX900-NEXT: v_addc_co_u32_e32 v3, vcc, v20, v3, vcc
; GFX900-NEXT: v_add_co_u32_e32 v3, vcc, v9, v3 ; GFX900-NEXT: v_add_co_u32_e32 v2, vcc, v9, v2
; GFX900-NEXT: v_addc_co_u32_e32 v4, vcc, v10, v4, vcc ; GFX900-NEXT: v_addc_co_u32_e32 v3, vcc, v10, v3, vcc
; GFX900-NEXT: v_add_co_u32_e32 v3, vcc, v11, v3 ; GFX900-NEXT: v_add_co_u32_e32 v2, vcc, v11, v2
; GFX900-NEXT: v_addc_co_u32_e32 v4, vcc, v12, v4, vcc ; GFX900-NEXT: v_addc_co_u32_e32 v3, vcc, v12, v3, vcc
; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: v_add_co_u32_e32 v3, vcc, v29, v3 ; GFX900-NEXT: v_add_co_u32_e32 v2, vcc, v29, v2
; GFX900-NEXT: v_addc_co_u32_e32 v4, vcc, v30, v4, vcc ; GFX900-NEXT: v_addc_co_u32_e32 v3, vcc, v30, v3, vcc
; GFX900-NEXT: s_cbranch_scc0 .LBB1_2 ; GFX900-NEXT: s_cbranch_scc0 .LBB1_2
; GFX900-NEXT: ; %bb.3: ; %while.cond.loopexit ; GFX900-NEXT: ; %bb.3: ; %while.cond.loopexit
; GFX900-NEXT: ; in Loop: Header=BB1_1 Depth=1 ; GFX900-NEXT: ; in Loop: Header=BB1_1 Depth=1
; GFX900-NEXT: s_add_i32 s4, s2, -1 ; GFX900-NEXT: s_add_i32 s4, s2, -1
; GFX900-NEXT: s_cmp_eq_u32 s2, 0 ; GFX900-NEXT: s_cmp_eq_u32 s2, 0
; GFX900-NEXT: s_cbranch_scc1 .LBB1_5 ; GFX900-NEXT: s_cbranch_scc1 .LBB1_5
; GFX900-NEXT: ; %bb.4: ; in Loop: Header=BB1_1 Depth=1 ; GFX900-NEXT: ; %bb.4: ; in Loop: Header=BB1_1 Depth=1
; GFX900-NEXT: s_mov_b32 s2, s4 ; GFX900-NEXT: s_mov_b32 s2, s4
; GFX900-NEXT: s_branch .LBB1_1 ; GFX900-NEXT: s_branch .LBB1_1
; GFX900-NEXT: .LBB1_5: ; %while.end ; GFX900-NEXT: .LBB1_5: ; %while.end
; GFX900-NEXT: v_mov_b32_e32 v1, s35 ; GFX900-NEXT: v_mov_b32_e32 v1, s35
; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, s34, v0 ; GFX900-NEXT: v_add_co_u32_e32 v0, vcc, s34, v6
; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX900-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX900-NEXT: global_store_dwordx2 v[0:1], v[3:4], off ; GFX900-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
; GFX900-NEXT: s_endpgm ; GFX900-NEXT: s_endpgm
; ;
; GFX10-LABEL: clmem_read: ; GFX10-LABEL: clmem_read:
; GFX10: ; %bb.0: ; %entry ; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0 ; GFX10-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
; GFX10-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1 ; GFX10-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
; GFX10-NEXT: s_mov_b32 s38, -1 ; GFX10-NEXT: s_mov_b32 s38, -1
; GFX10-NEXT: s_mov_b32 s39, 0x31c16000 ; GFX10-NEXT: s_mov_b32 s39, 0x31c16000
; GFX10-NEXT: s_add_u32 s36, s36, s3 ; GFX10-NEXT: s_add_u32 s36, s36, s3
; GFX10-NEXT: s_addc_u32 s37, s37, 0 ; GFX10-NEXT: s_addc_u32 s37, s37, 0
; GFX10-NEXT: s_getpc_b64 s[2:3] ; GFX10-NEXT: s_getpc_b64 s[2:3]
; GFX10-NEXT: s_add_u32 s2, s2, _Z13get_global_idj@gotpcrel32@lo+4 ; GFX10-NEXT: s_add_u32 s2, s2, _Z13get_global_idj@gotpcrel32@lo+4
; GFX10-NEXT: s_addc_u32 s3, s3, _Z13get_global_idj@gotpcrel32@hi+12 ; GFX10-NEXT: s_addc_u32 s3, s3, _Z13get_global_idj@gotpcrel32@hi+12
; GFX10-NEXT: v_mov_b32_e32 v31, v0 ; GFX10-NEXT: v_mov_b32_e32 v31, v0
; GFX10-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0 ; GFX10-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
; GFX10-NEXT: s_load_dwordx2 s[34:35], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[34:35], s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_mov_b64 s[0:1], s[36:37] ; GFX10-NEXT: s_mov_b64 s[0:1], s[36:37]
; GFX10-NEXT: s_mov_b64 s[2:3], s[38:39] ; GFX10-NEXT: s_mov_b64 s[2:3], s[38:39]
; GFX10-NEXT: s_mov_b32 s32, 0 ; GFX10-NEXT: s_mov_b32 s32, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v0 ; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 17, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v3, 17, v0
; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: s_movk_i32 s1, 0x7f ; GFX10-NEXT: s_movk_i32 s1, 0x7f
; GFX10-NEXT: v_lshlrev_b64 v[1:2], 3, v[1:2] ; GFX10-NEXT: v_lshlrev_b64 v[0:1], 3, v[1:2]
; GFX10-NEXT: v_and_b32_e32 v0, 0xfe000000, v0 ; GFX10-NEXT: v_and_b32_e32 v6, 0xfe000000, v3
; GFX10-NEXT: v_or_b32_e32 v1, v1, v0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: v_add_co_u32 v1, vcc_lo, v1, s34 ; GFX10-NEXT: v_mov_b32_e32 v3, 0
; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, s35, v2, vcc_lo ; GFX10-NEXT: v_or_b32_e32 v0, v0, v6
; GFX10-NEXT: v_add_co_u32 v1, vcc_lo, 0x5000, v1 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, s34
; GFX10-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, s35, v1, vcc_lo
; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x5000, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: .LBB1_1: ; %for.cond.preheader ; GFX10-NEXT: .LBB1_1: ; %for.cond.preheader
; GFX10-NEXT: ; =>This Loop Header: Depth=1 ; GFX10-NEXT: ; =>This Loop Header: Depth=1
; GFX10-NEXT: ; Child Loop BB1_2 Depth 2 ; GFX10-NEXT: ; Child Loop BB1_2 Depth 2
; GFX10-NEXT: v_mov_b32_e32 v6, v2
; GFX10-NEXT: v_mov_b32_e32 v5, v1 ; GFX10-NEXT: v_mov_b32_e32 v5, v1
; GFX10-NEXT: v_mov_b32_e32 v4, v0
; GFX10-NEXT: s_mov_b32 s2, 0 ; GFX10-NEXT: s_mov_b32 s2, 0
; GFX10-NEXT: .LBB1_2: ; %for.body ; GFX10-NEXT: .LBB1_2: ; %for.body
; GFX10-NEXT: ; Parent Loop BB1_1 Depth=1 ; GFX10-NEXT: ; Parent Loop BB1_1 Depth=1
; GFX10-NEXT: ; => This Inner Loop Header: Depth=2 ; GFX10-NEXT: ; => This Inner Loop Header: Depth=2
; GFX10-NEXT: v_add_co_u32 v7, vcc_lo, v5, 0xffffb800 ; GFX10-NEXT: v_add_co_u32 v7, vcc_lo, v4, 0xffffb800
; GFX10-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, -1, v6, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, -1, v5, vcc_lo
; GFX10-NEXT: v_add_co_u32 v9, vcc_lo, v5, 0xffffc800 ; GFX10-NEXT: v_add_co_u32 v9, vcc_lo, v4, 0xffffc800
; GFX10-NEXT: v_add_co_ci_u32_e32 v10, vcc_lo, -1, v6, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v10, vcc_lo, -1, v5, vcc_lo
; GFX10-NEXT: v_add_co_u32 v13, vcc_lo, v5, 0xffffd800 ; GFX10-NEXT: v_add_co_u32 v13, vcc_lo, v4, 0xffffd800
; GFX10-NEXT: v_add_co_ci_u32_e32 v14, vcc_lo, -1, v6, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v14, vcc_lo, -1, v5, vcc_lo
; GFX10-NEXT: v_add_co_u32 v17, vcc_lo, v5, 0xffffe800 ; GFX10-NEXT: v_add_co_u32 v17, vcc_lo, v4, 0xffffe800
; GFX10-NEXT: s_clause 0x2 ; GFX10-NEXT: s_clause 0x2
; GFX10-NEXT: global_load_dwordx2 v[11:12], v[7:8], off offset:-2048 ; GFX10-NEXT: global_load_dwordx2 v[11:12], v[7:8], off offset:-2048
; GFX10-NEXT: global_load_dwordx2 v[15:16], v[9:10], off offset:-2048 ; GFX10-NEXT: global_load_dwordx2 v[15:16], v[9:10], off offset:-2048
; GFX10-NEXT: global_load_dwordx2 v[19:20], v[13:14], off offset:-2048 ; GFX10-NEXT: global_load_dwordx2 v[19:20], v[13:14], off offset:-2048
; GFX10-NEXT: v_add_co_ci_u32_e32 v18, vcc_lo, -1, v6, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v18, vcc_lo, -1, v5, vcc_lo
; GFX10-NEXT: v_add_co_u32 v21, vcc_lo, 0xfffff000, v5 ; GFX10-NEXT: v_add_co_u32 v21, vcc_lo, 0xfffff000, v4
; GFX10-NEXT: v_add_co_ci_u32_e32 v22, vcc_lo, -1, v6, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v22, vcc_lo, -1, v5, vcc_lo
; GFX10-NEXT: s_clause 0x7 ; GFX10-NEXT: s_clause 0x7
; GFX10-NEXT: global_load_dwordx2 v[23:24], v[17:18], off offset:-2048 ; GFX10-NEXT: global_load_dwordx2 v[23:24], v[17:18], off offset:-2048
; GFX10-NEXT: global_load_dwordx2 v[7:8], v[7:8], off ; GFX10-NEXT: global_load_dwordx2 v[7:8], v[7:8], off
; GFX10-NEXT: global_load_dwordx2 v[9:10], v[9:10], off ; GFX10-NEXT: global_load_dwordx2 v[9:10], v[9:10], off
; GFX10-NEXT: global_load_dwordx2 v[13:14], v[13:14], off ; GFX10-NEXT: global_load_dwordx2 v[13:14], v[13:14], off
; GFX10-NEXT: global_load_dwordx2 v[25:26], v[17:18], off ; GFX10-NEXT: global_load_dwordx2 v[25:26], v[17:18], off
; GFX10-NEXT: global_load_dwordx2 v[27:28], v[21:22], off ; GFX10-NEXT: global_load_dwordx2 v[27:28], v[21:22], off
; GFX10-NEXT: global_load_dwordx2 v[29:30], v[5:6], off offset:-2048 ; GFX10-NEXT: global_load_dwordx2 v[29:30], v[4:5], off offset:-2048
; GFX10-NEXT: global_load_dwordx2 v[31:32], v[5:6], off ; GFX10-NEXT: global_load_dwordx2 v[31:32], v[4:5], off
; GFX10-NEXT: v_add_co_u32 v5, vcc_lo, 0x10000, v5 ; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, 0x10000, v4
; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
; GFX10-NEXT: s_addk_i32 s2, 0x2000 ; GFX10-NEXT: s_addk_i32 s2, 0x2000
; GFX10-NEXT: s_cmp_gt_u32 s2, 0x3fffff ; GFX10-NEXT: s_cmp_gt_u32 s2, 0x3fffff
; GFX10-NEXT: s_waitcnt vmcnt(10) ; GFX10-NEXT: s_waitcnt vmcnt(10)
; GFX10-NEXT: v_add_co_u32 v3, s0, v11, v3 ; GFX10-NEXT: v_add_co_u32 v2, s0, v11, v2
; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s0, v12, v4, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s0, v12, v3, s0
; GFX10-NEXT: s_waitcnt vmcnt(6) ; GFX10-NEXT: s_waitcnt vmcnt(6)
; GFX10-NEXT: v_add_co_u32 v3, s0, v7, v3 ; GFX10-NEXT: v_add_co_u32 v2, s0, v7, v2
; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s0, v8, v4, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s0, v8, v3, s0
; GFX10-NEXT: v_add_co_u32 v3, s0, v15, v3 ; GFX10-NEXT: v_add_co_u32 v2, s0, v15, v2
; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s0, v16, v4, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s0, v16, v3, s0
; GFX10-NEXT: s_waitcnt vmcnt(5) ; GFX10-NEXT: s_waitcnt vmcnt(5)
; GFX10-NEXT: v_add_co_u32 v3, s0, v9, v3 ; GFX10-NEXT: v_add_co_u32 v2, s0, v9, v2
; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s0, v10, v4, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s0, v10, v3, s0
; GFX10-NEXT: v_add_co_u32 v3, s0, v19, v3 ; GFX10-NEXT: v_add_co_u32 v2, s0, v19, v2
; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s0, v20, v4, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s0, v20, v3, s0
; GFX10-NEXT: s_waitcnt vmcnt(4) ; GFX10-NEXT: s_waitcnt vmcnt(4)
; GFX10-NEXT: v_add_co_u32 v3, s0, v13, v3 ; GFX10-NEXT: v_add_co_u32 v2, s0, v13, v2
; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s0, v14, v4, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s0, v14, v3, s0
; GFX10-NEXT: v_add_co_u32 v3, s0, v23, v3 ; GFX10-NEXT: v_add_co_u32 v2, s0, v23, v2
; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s0, v24, v4, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s0, v24, v3, s0
; GFX10-NEXT: s_waitcnt vmcnt(3) ; GFX10-NEXT: s_waitcnt vmcnt(3)
; GFX10-NEXT: v_add_co_u32 v3, s0, v25, v3 ; GFX10-NEXT: v_add_co_u32 v2, s0, v25, v2
; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s0, v26, v4, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s0, v26, v3, s0
; GFX10-NEXT: s_waitcnt vmcnt(2) ; GFX10-NEXT: s_waitcnt vmcnt(2)
; GFX10-NEXT: v_add_co_u32 v3, s0, v27, v3 ; GFX10-NEXT: v_add_co_u32 v2, s0, v27, v2
; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s0, v28, v4, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s0, v28, v3, s0
; GFX10-NEXT: s_waitcnt vmcnt(1) ; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_add_co_u32 v3, s0, v29, v3 ; GFX10-NEXT: v_add_co_u32 v2, s0, v29, v2
; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s0, v30, v4, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s0, v30, v3, s0
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_add_co_u32 v3, vcc_lo, v31, v3 ; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v31, v2
; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v32, v4, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v32, v3, vcc_lo
; GFX10-NEXT: s_cbranch_scc0 .LBB1_2 ; GFX10-NEXT: s_cbranch_scc0 .LBB1_2
; GFX10-NEXT: ; %bb.3: ; %while.cond.loopexit ; GFX10-NEXT: ; %bb.3: ; %while.cond.loopexit
; GFX10-NEXT: ; in Loop: Header=BB1_1 Depth=1 ; GFX10-NEXT: ; in Loop: Header=BB1_1 Depth=1
; GFX10-NEXT: s_add_i32 s0, s1, -1 ; GFX10-NEXT: s_add_i32 s0, s1, -1
; GFX10-NEXT: s_cmp_eq_u32 s1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s1, 0
; GFX10-NEXT: s_cbranch_scc1 .LBB1_5 ; GFX10-NEXT: s_cbranch_scc1 .LBB1_5
; GFX10-NEXT: ; %bb.4: ; in Loop: Header=BB1_1 Depth=1 ; GFX10-NEXT: ; %bb.4: ; in Loop: Header=BB1_1 Depth=1
; GFX10-NEXT: s_mov_b32 s1, s0 ; GFX10-NEXT: s_mov_b32 s1, s0
; GFX10-NEXT: s_branch .LBB1_1 ; GFX10-NEXT: s_branch .LBB1_1
; GFX10-NEXT: .LBB1_5: ; %while.end ; GFX10-NEXT: .LBB1_5: ; %while.end
; GFX10-NEXT: v_add_co_u32 v0, s0, s34, v0 ; GFX10-NEXT: v_add_co_u32 v0, s0, s34, v6
; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s35, 0, s0 ; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, s35, 0, s0
; GFX10-NEXT: global_store_dwordx2 v[0:1], v[3:4], off ; GFX10-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX90A-LABEL: clmem_read: ; GFX90A-LABEL: clmem_read:
; GFX90A: ; %bb.0: ; %entry ; GFX90A: ; %bb.0: ; %entry
; GFX90A-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0 ; GFX90A-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
; GFX90A-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1 ; GFX90A-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
; GFX90A-NEXT: s_mov_b32 s38, -1 ; GFX90A-NEXT: s_mov_b32 s38, -1
; GFX90A-NEXT: s_mov_b32 s39, 0xe00000 ; GFX90A-NEXT: s_mov_b32 s39, 0xe00000
▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 Lines
; GFX11-NEXT: s_addc_u32 s3, s3, _Z13get_global_idj@gotpcrel32@hi+12 ; GFX11-NEXT: s_addc_u32 s3, s3, _Z13get_global_idj@gotpcrel32@hi+12
; GFX11-NEXT: v_dual_mov_b32 v31, v0 :: v_dual_mov_b32 v0, 0 ; GFX11-NEXT: v_dual_mov_b32 v31, v0 :: v_dual_mov_b32 v0, 0
; GFX11-NEXT: s_load_b64 s[2:3], s[2:3], 0x0 ; GFX11-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
; GFX11-NEXT: s_load_b64 s[34:35], s[0:1], 0x24 ; GFX11-NEXT: s_load_b64 s[34:35], s[0:1], 0x24
; GFX11-NEXT: s_mov_b32 s32, 0 ; GFX11-NEXT: s_mov_b32 s32, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] ; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v1, 0xff, v0 ; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v1, 0xff, v0
; GFX11-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v0, 17, v0 ; GFX11-NEXT: v_lshlrev_b32_e32 v3, 17, v0
; GFX11-NEXT: v_mov_b32_e32 v4, 0
; GFX11-NEXT: s_movk_i32 s1, 0x7f ; GFX11-NEXT: s_movk_i32 s1, 0x7f
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_lshlrev_b64 v[1:2], 3, v[1:2] ; GFX11-NEXT: v_lshlrev_b64 v[0:1], 3, v[1:2]
; GFX11-NEXT: v_and_b32_e32 v0, 0xfe000000, v0 ; GFX11-NEXT: v_and_b32_e32 v6, 0xfe000000, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: v_or_b32_e32 v1, v1, v0 ; GFX11-NEXT: v_mov_b32_e32 v3, 0
; GFX11-NEXT: v_add_co_u32 v1, vcc_lo, v1, s34 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_or_b32_e32 v0, v0, v6
; GFX11-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, s35, v2, vcc_lo ; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, s34
; GFX11-NEXT: v_add_co_u32 v1, vcc_lo, 0x5000, v1 ; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, s35, v1, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo ; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x5000, v0
; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
; GFX11-NEXT: .LBB1_1: ; %for.cond.preheader ; GFX11-NEXT: .LBB1_1: ; %for.cond.preheader
; GFX11-NEXT: ; =>This Loop Header: Depth=1 ; GFX11-NEXT: ; =>This Loop Header: Depth=1
; GFX11-NEXT: ; Child Loop BB1_2 Depth 2 ; GFX11-NEXT: ; Child Loop BB1_2 Depth 2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1 ; GFX11-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
; GFX11-NEXT: s_mov_b32 s2, 0 ; GFX11-NEXT: s_mov_b32 s2, 0
; GFX11-NEXT: .LBB1_2: ; %for.body ; GFX11-NEXT: .LBB1_2: ; %for.body
; GFX11-NEXT: ; Parent Loop BB1_1 Depth=1 ; GFX11-NEXT: ; Parent Loop BB1_1 Depth=1
; GFX11-NEXT: ; => This Inner Loop Header: Depth=2 ; GFX11-NEXT: ; => This Inner Loop Header: Depth=2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_co_u32 v7, vcc_lo, v5, 0xffffc000 ; GFX11-NEXT: v_add_co_u32 v7, vcc_lo, v4, 0xffffc000
; GFX11-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, -1, v6, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, -1, v5, vcc_lo
; GFX11-NEXT: v_add_co_u32 v9, vcc_lo, 0xffffc000, v5 ; GFX11-NEXT: v_add_co_u32 v9, vcc_lo, 0xffffc000, v4
; GFX11-NEXT: v_add_co_ci_u32_e32 v10, vcc_lo, -1, v6, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v10, vcc_lo, -1, v5, vcc_lo
; GFX11-NEXT: v_add_co_u32 v11, vcc_lo, 0xffffd000, v5 ; GFX11-NEXT: v_add_co_u32 v11, vcc_lo, 0xffffd000, v4
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: global_load_b64 v[13:14], v[7:8], off offset:-4096 ; GFX11-NEXT: global_load_b64 v[13:14], v[7:8], off offset:-4096
; GFX11-NEXT: global_load_b64 v[9:10], v[9:10], off offset:-2048 ; GFX11-NEXT: global_load_b64 v[9:10], v[9:10], off offset:-2048
; GFX11-NEXT: v_add_co_ci_u32_e32 v12, vcc_lo, -1, v6, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v12, vcc_lo, -1, v5, vcc_lo
; GFX11-NEXT: v_add_co_u32 v15, vcc_lo, v5, 0xffffe000 ; GFX11-NEXT: v_add_co_u32 v15, vcc_lo, v4, 0xffffe000
; GFX11-NEXT: v_add_co_ci_u32_e32 v16, vcc_lo, -1, v6, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v16, vcc_lo, -1, v5, vcc_lo
; GFX11-NEXT: global_load_b64 v[11:12], v[11:12], off offset:-2048 ; GFX11-NEXT: global_load_b64 v[11:12], v[11:12], off offset:-2048
; GFX11-NEXT: v_add_co_u32 v17, vcc_lo, 0xffffe000, v5 ; GFX11-NEXT: v_add_co_u32 v17, vcc_lo, 0xffffe000, v4
; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: global_load_b64 v[19:20], v[15:16], off offset:-4096 ; GFX11-NEXT: global_load_b64 v[19:20], v[15:16], off offset:-4096
; GFX11-NEXT: global_load_b64 v[7:8], v[7:8], off ; GFX11-NEXT: global_load_b64 v[7:8], v[7:8], off
; GFX11-NEXT: v_add_co_ci_u32_e32 v18, vcc_lo, -1, v6, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v18, vcc_lo, -1, v5, vcc_lo
; GFX11-NEXT: v_add_co_u32 v21, vcc_lo, 0xfffff000, v5 ; GFX11-NEXT: v_add_co_u32 v21, vcc_lo, 0xfffff000, v4
; GFX11-NEXT: v_add_co_ci_u32_e32 v22, vcc_lo, -1, v6, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v22, vcc_lo, -1, v5, vcc_lo
; GFX11-NEXT: s_clause 0x5 ; GFX11-NEXT: s_clause 0x5
; GFX11-NEXT: global_load_b64 v[17:18], v[17:18], off offset:-2048 ; GFX11-NEXT: global_load_b64 v[17:18], v[17:18], off offset:-2048
; GFX11-NEXT: global_load_b64 v[15:16], v[15:16], off ; GFX11-NEXT: global_load_b64 v[15:16], v[15:16], off
; GFX11-NEXT: global_load_b64 v[21:22], v[21:22], off offset:-2048 ; GFX11-NEXT: global_load_b64 v[21:22], v[21:22], off offset:-2048
; GFX11-NEXT: global_load_b64 v[23:24], v[5:6], off offset:-4096 ; GFX11-NEXT: global_load_b64 v[23:24], v[4:5], off offset:-4096
; GFX11-NEXT: global_load_b64 v[25:26], v[5:6], off offset:-2048 ; GFX11-NEXT: global_load_b64 v[25:26], v[4:5], off offset:-2048
; GFX11-NEXT: global_load_b64 v[27:28], v[5:6], off ; GFX11-NEXT: global_load_b64 v[27:28], v[4:5], off
; GFX11-NEXT: v_add_co_u32 v5, vcc_lo, 0x10000, v5 ; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, 0x10000, v4
; GFX11-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
; GFX11-NEXT: s_addk_i32 s2, 0x2000 ; GFX11-NEXT: s_addk_i32 s2, 0x2000
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: s_cmp_gt_u32 s2, 0x3fffff ; GFX11-NEXT: s_cmp_gt_u32 s2, 0x3fffff
; GFX11-NEXT: s_waitcnt vmcnt(10) ; GFX11-NEXT: s_waitcnt vmcnt(10)
; GFX11-NEXT: v_add_co_u32 v3, s0, v13, v3 ; GFX11-NEXT: v_add_co_u32 v2, s0, v13, v2
; GFX11-NEXT: v_add_co_ci_u32_e64 v4, s0, v14, v4, s0 ; GFX11-NEXT: v_add_co_ci_u32_e64 v3, s0, v14, v3, s0
; GFX11-NEXT: s_waitcnt vmcnt(9) ; GFX11-NEXT: s_waitcnt vmcnt(9)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_u32 v3, s0, v9, v3 ; GFX11-NEXT: v_add_co_u32 v2, s0, v9, v2
; GFX11-NEXT: v_add_co_ci_u32_e64 v4, s0, v10, v4, s0 ; GFX11-NEXT: v_add_co_ci_u32_e64 v3, s0, v10, v3, s0
; GFX11-NEXT: s_waitcnt vmcnt(6) ; GFX11-NEXT: s_waitcnt vmcnt(6)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_u32 v3, s0, v7, v3 ; GFX11-NEXT: v_add_co_u32 v2, s0, v7, v2
; GFX11-NEXT: v_add_co_ci_u32_e64 v4, s0, v8, v4, s0 ; GFX11-NEXT: v_add_co_ci_u32_e64 v3, s0, v8, v3, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_u32 v3, s0, v11, v3 ; GFX11-NEXT: v_add_co_u32 v2, s0, v11, v2
; GFX11-NEXT: v_add_co_ci_u32_e64 v4, s0, v12, v4, s0 ; GFX11-NEXT: v_add_co_ci_u32_e64 v3, s0, v12, v3, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_u32 v3, s0, v19, v3 ; GFX11-NEXT: v_add_co_u32 v2, s0, v19, v2
; GFX11-NEXT: v_add_co_ci_u32_e64 v4, s0, v20, v4, s0 ; GFX11-NEXT: v_add_co_ci_u32_e64 v3, s0, v20, v3, s0
; GFX11-NEXT: s_waitcnt vmcnt(5) ; GFX11-NEXT: s_waitcnt vmcnt(5)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_u32 v3, s0, v17, v3 ; GFX11-NEXT: v_add_co_u32 v2, s0, v17, v2
; GFX11-NEXT: v_add_co_ci_u32_e64 v4, s0, v18, v4, s0 ; GFX11-NEXT: v_add_co_ci_u32_e64 v3, s0, v18, v3, s0
; GFX11-NEXT: s_waitcnt vmcnt(4) ; GFX11-NEXT: s_waitcnt vmcnt(4)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_u32 v3, s0, v15, v3 ; GFX11-NEXT: v_add_co_u32 v2, s0, v15, v2
; GFX11-NEXT: v_add_co_ci_u32_e64 v4, s0, v16, v4, s0 ; GFX11-NEXT: v_add_co_ci_u32_e64 v3, s0, v16, v3, s0
; GFX11-NEXT: s_waitcnt vmcnt(3) ; GFX11-NEXT: s_waitcnt vmcnt(3)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_u32 v3, s0, v21, v3 ; GFX11-NEXT: v_add_co_u32 v2, s0, v21, v2
; GFX11-NEXT: v_add_co_ci_u32_e64 v4, s0, v22, v4, s0 ; GFX11-NEXT: v_add_co_ci_u32_e64 v3, s0, v22, v3, s0
; GFX11-NEXT: s_waitcnt vmcnt(2) ; GFX11-NEXT: s_waitcnt vmcnt(2)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_u32 v3, s0, v23, v3 ; GFX11-NEXT: v_add_co_u32 v2, s0, v23, v2
; GFX11-NEXT: v_add_co_ci_u32_e64 v4, s0, v24, v4, s0 ; GFX11-NEXT: v_add_co_ci_u32_e64 v3, s0, v24, v3, s0
; GFX11-NEXT: s_waitcnt vmcnt(1) ; GFX11-NEXT: s_waitcnt vmcnt(1)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_add_co_u32 v3, s0, v25, v3 ; GFX11-NEXT: v_add_co_u32 v2, s0, v25, v2
; GFX11-NEXT: v_add_co_ci_u32_e64 v4, s0, v26, v4, s0 ; GFX11-NEXT: v_add_co_ci_u32_e64 v3, s0, v26, v3, s0
; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_co_u32 v3, vcc_lo, v27, v3 ; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v27, v2
; GFX11-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, v28, v4, vcc_lo ; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v28, v3, vcc_lo
; GFX11-NEXT: s_cbranch_scc0 .LBB1_2 ; GFX11-NEXT: s_cbranch_scc0 .LBB1_2
; GFX11-NEXT: ; %bb.3: ; %while.cond.loopexit ; GFX11-NEXT: ; %bb.3: ; %while.cond.loopexit
; GFX11-NEXT: ; in Loop: Header=BB1_1 Depth=1 ; GFX11-NEXT: ; in Loop: Header=BB1_1 Depth=1
; GFX11-NEXT: s_add_i32 s0, s1, -1 ; GFX11-NEXT: s_add_i32 s0, s1, -1
; GFX11-NEXT: s_cmp_eq_u32 s1, 0 ; GFX11-NEXT: s_cmp_eq_u32 s1, 0
; GFX11-NEXT: s_cbranch_scc1 .LBB1_5 ; GFX11-NEXT: s_cbranch_scc1 .LBB1_5
; GFX11-NEXT: ; %bb.4: ; in Loop: Header=BB1_1 Depth=1 ; GFX11-NEXT: ; %bb.4: ; in Loop: Header=BB1_1 Depth=1
; GFX11-NEXT: s_mov_b32 s1, s0 ; GFX11-NEXT: s_mov_b32 s1, s0
; GFX11-NEXT: s_branch .LBB1_1 ; GFX11-NEXT: s_branch .LBB1_1
; GFX11-NEXT: .LBB1_5: ; %while.end ; GFX11-NEXT: .LBB1_5: ; %while.end
; GFX11-NEXT: v_add_co_u32 v0, s0, s34, v0 ; GFX11-NEXT: v_add_co_u32 v0, s0, s34, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s35, 0, s0 ; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s35, 0, s0
; GFX11-NEXT: global_store_b64 v[0:1], v[3:4], off ; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off
; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_nop 0
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11-NEXT: s_endpgm ; GFX11-NEXT: s_endpgm
entry: entry:
%call = tail call i64 @_Z13get_global_idj(i32 0) %call = tail call i64 @_Z13get_global_idj(i32 0)
%conv = and i64 %call, 255 %conv = and i64 %call, 255
%a0 = shl i64 %call, 17 %a0 = shl i64 %call, 17
%idx.ext11 = and i64 %a0, 4261412864 %idx.ext11 = and i64 %a0, 4261412864
▲ Show 20 Lines • Show All 1,922 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/sdiv64.ll

Show First 20 Lines • Show All 158 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[8:9] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[8:9]
; GCN-IR-NEXT: s_flbit_i32_b32 s8, s6 ; GCN-IR-NEXT: s_flbit_i32_b32 s8, s6
; GCN-IR-NEXT: s_add_i32 s8, s8, 32 ; GCN-IR-NEXT: s_add_i32 s8, s8, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s9, s7 ; GCN-IR-NEXT: s_flbit_i32_b32 s9, s7
; GCN-IR-NEXT: s_min_u32 s14, s8, s9 ; GCN-IR-NEXT: s_min_u32 s14, s8, s9
; GCN-IR-NEXT: s_flbit_i32_b32 s8, s12 ; GCN-IR-NEXT: s_flbit_i32_b32 s8, s12
; GCN-IR-NEXT: s_add_i32 s8, s8, 32 ; GCN-IR-NEXT: s_add_i32 s8, s8, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s9, s13 ; GCN-IR-NEXT: s_flbit_i32_b32 s9, s13
; GCN-IR-NEXT: s_min_u32 s18, s8, s9 ; GCN-IR-NEXT: s_min_u32 s20, s8, s9
; GCN-IR-NEXT: s_sub_u32 s16, s14, s18 ; GCN-IR-NEXT: s_sub_u32 s16, s14, s20
; GCN-IR-NEXT: s_subb_u32 s17, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s17, 0, 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[20:21], s[16:17], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[18:19], s[16:17], 63
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[22:23], s[16:17], 63 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[22:23], s[16:17], 63
; GCN-IR-NEXT: s_or_b64 s[20:21], s[10:11], s[20:21] ; GCN-IR-NEXT: s_or_b64 s[18:19], s[10:11], s[18:19]
; GCN-IR-NEXT: s_and_b64 s[10:11], s[20:21], exec ; GCN-IR-NEXT: s_and_b64 s[10:11], s[18:19], exec
; GCN-IR-NEXT: s_cselect_b32 s11, 0, s13 ; GCN-IR-NEXT: s_cselect_b32 s11, 0, s13
; GCN-IR-NEXT: s_cselect_b32 s10, 0, s12 ; GCN-IR-NEXT: s_cselect_b32 s10, 0, s12
; GCN-IR-NEXT: s_or_b64 s[20:21], s[20:21], s[22:23] ; GCN-IR-NEXT: s_or_b64 s[18:19], s[18:19], s[22:23]
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[20:21] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[18:19]
; GCN-IR-NEXT: s_cbranch_vccz .LBB0_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s20, s16, 1 ; GCN-IR-NEXT: s_add_u32 s18, s16, 1
; GCN-IR-NEXT: s_addc_u32 s21, s17, 0 ; GCN-IR-NEXT: s_addc_u32 s19, s17, 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[20:21], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[18:19], 0
; GCN-IR-NEXT: s_sub_i32 s16, 63, s16 ; GCN-IR-NEXT: s_sub_i32 s16, 63, s16
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11]
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[12:13], s16 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[12:13], s16
; GCN-IR-NEXT: s_cbranch_vccz .LBB0_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[16:17], s[12:13], s20 ; GCN-IR-NEXT: s_lshr_b64 s[16:17], s[12:13], s18
; GCN-IR-NEXT: s_add_u32 s19, s6, -1 ; GCN-IR-NEXT: s_add_u32 s18, s6, -1
; GCN-IR-NEXT: s_addc_u32 s20, s7, -1 ; GCN-IR-NEXT: s_addc_u32 s19, s7, -1
; GCN-IR-NEXT: s_not_b64 s[8:9], s[14:15] ; GCN-IR-NEXT: s_not_b64 s[8:9], s[14:15]
; GCN-IR-NEXT: s_add_u32 s12, s8, s18 ; GCN-IR-NEXT: s_add_u32 s12, s8, s20
; GCN-IR-NEXT: s_addc_u32 s13, s9, 0 ; GCN-IR-NEXT: s_addc_u32 s13, s9, 0
; GCN-IR-NEXT: s_mov_b64 s[14:15], 0 ; GCN-IR-NEXT: s_mov_b64 s[14:15], 0
; GCN-IR-NEXT: s_mov_b32 s9, 0 ; GCN-IR-NEXT: s_mov_b32 s9, 0
; GCN-IR-NEXT: .LBB0_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB0_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[16:17], s[16:17], 1 ; GCN-IR-NEXT: s_lshl_b64 s[16:17], s[16:17], 1
; GCN-IR-NEXT: s_lshr_b32 s8, s11, 31 ; GCN-IR-NEXT: s_lshr_b32 s8, s11, 31
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[8:9] ; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[8:9]
; GCN-IR-NEXT: s_or_b64 s[10:11], s[14:15], s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[14:15], s[10:11]
; GCN-IR-NEXT: s_sub_u32 s8, s19, s16 ; GCN-IR-NEXT: s_sub_u32 s8, s18, s16
; GCN-IR-NEXT: s_subb_u32 s8, s20, s17 ; GCN-IR-NEXT: s_subb_u32 s8, s19, s17
; GCN-IR-NEXT: s_ashr_i32 s14, s8, 31 ; GCN-IR-NEXT: s_ashr_i32 s14, s8, 31
; GCN-IR-NEXT: s_mov_b32 s15, s14 ; GCN-IR-NEXT: s_mov_b32 s15, s14
; GCN-IR-NEXT: s_and_b32 s8, s14, 1 ; GCN-IR-NEXT: s_and_b32 s8, s14, 1
; GCN-IR-NEXT: s_and_b64 s[14:15], s[14:15], s[6:7] ; GCN-IR-NEXT: s_and_b64 s[14:15], s[14:15], s[6:7]
; GCN-IR-NEXT: s_sub_u32 s16, s16, s14 ; GCN-IR-NEXT: s_sub_u32 s16, s16, s14
; GCN-IR-NEXT: s_subb_u32 s17, s17, s15 ; GCN-IR-NEXT: s_subb_u32 s17, s17, s15
; GCN-IR-NEXT: s_add_u32 s12, s12, 1 ; GCN-IR-NEXT: s_add_u32 s12, s12, 1
; GCN-IR-NEXT: s_addc_u32 s13, s13, 0 ; GCN-IR-NEXT: s_addc_u32 s13, s13, 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[22:23], s[12:13], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[20:21], s[12:13], 0
; GCN-IR-NEXT: s_mov_b64 s[14:15], s[8:9] ; GCN-IR-NEXT: s_mov_b64 s[14:15], s[8:9]
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[22:23] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[20:21]
; GCN-IR-NEXT: s_cbranch_vccz .LBB0_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_3
; GCN-IR-NEXT: .LBB0_4: ; %Flow7 ; GCN-IR-NEXT: .LBB0_4: ; %Flow7
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[10:11], 1 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[10:11], 1
; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[6:7]
; GCN-IR-NEXT: .LBB0_5: ; %udiv-end ; GCN-IR-NEXT: .LBB0_5: ; %udiv-end
; GCN-IR-NEXT: s_xor_b64 s[0:1], s[2:3], s[0:1] ; GCN-IR-NEXT: s_xor_b64 s[0:1], s[2:3], s[0:1]
; GCN-IR-NEXT: s_xor_b64 s[2:3], s[10:11], s[0:1] ; GCN-IR-NEXT: s_xor_b64 s[2:3], s[10:11], s[0:1]
; GCN-IR-NEXT: s_sub_u32 s0, s2, s0 ; GCN-IR-NEXT: s_sub_u32 s0, s2, s0
▲ Show 20 Lines • Show All 132 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_xor_b32_e32 v0, v1, v2 ; GCN-NEXT: v_xor_b32_e32 v0, v1, v2
; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v2, vcc ; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v2, vcc
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
; ;
; GCN-IR-LABEL: v_test_sdiv: ; GCN-IR-LABEL: v_test_sdiv:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IR-NEXT: v_ashrrev_i32_e32 v4, 31, v1 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v1
; GCN-IR-NEXT: v_xor_b32_e32 v0, v4, v0 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v12, v0
; GCN-IR-NEXT: v_ashrrev_i32_e32 v5, 31, v3 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v13, 31, v3
; GCN-IR-NEXT: v_xor_b32_e32 v1, v4, v1 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v12, v1
; GCN-IR-NEXT: v_sub_i32_e32 v10, vcc, v0, v4 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v0, v12
; GCN-IR-NEXT: v_subb_u32_e32 v11, vcc, v1, v4, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v7, vcc, v1, v12, vcc
; GCN-IR-NEXT: v_xor_b32_e32 v0, v5, v2 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v13, v2
; GCN-IR-NEXT: v_xor_b32_e32 v1, v5, v3 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v13, v3
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v5 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v13
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v13, vcc
; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0 ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0
; GCN-IR-NEXT: v_add_i32_e64 v2, s[6:7], 32, v2 ; GCN-IR-NEXT: v_add_i32_e64 v2, s[6:7], 32, v2
; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
; GCN-IR-NEXT: v_min_u32_e32 v12, v2, v3 ; GCN-IR-NEXT: v_min_u32_e32 v10, v2, v3
; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v10 ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v6
; GCN-IR-NEXT: v_add_i32_e64 v2, s[6:7], 32, v2 ; GCN-IR-NEXT: v_add_i32_e64 v2, s[6:7], 32, v2
; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v11 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v7
; GCN-IR-NEXT: v_min_u32_e32 v13, v2, v3 ; GCN-IR-NEXT: v_min_u32_e32 v11, v2, v3
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[6:7], v12, v13 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[6:7], v10, v11
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[10:11] ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[6:7]
; GCN-IR-NEXT: v_subb_u32_e64 v3, s[6:7], 0, 0, s[6:7] ; GCN-IR-NEXT: v_subb_u32_e64 v3, s[6:7], 0, 0, s[6:7]
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[6:7], 63, v[2:3] ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[6:7], 63, v[2:3]
; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[2:3] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[2:3]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
; GCN-IR-NEXT: v_mov_b32_e32 v6, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v14, v12
; GCN-IR-NEXT: v_mov_b32_e32 v7, v5 ; GCN-IR-NEXT: v_mov_b32_e32 v15, v13
; GCN-IR-NEXT: v_cndmask_b32_e64 v9, v11, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v7, 0, s[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v8, v10, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v6, 0, s[4:5]
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB1_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, 1, v2 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v2
; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, 0, v3, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v3, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[14:15] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[10:11], v2 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[6:7], v2
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB1_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_add_i32_e32 v16, vcc, -1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v16, vcc, -1, v0
; GCN-IR-NEXT: v_addc_u32_e32 v17, vcc, -1, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v17, vcc, -1, v1, vcc
; GCN-IR-NEXT: v_not_b32_e32 v9, v12 ; GCN-IR-NEXT: v_not_b32_e32 v5, v10
; GCN-IR-NEXT: v_lshr_b64 v[14:15], v[10:11], v14 ; GCN-IR-NEXT: v_lshr_b64 v[8:9], v[6:7], v8
; GCN-IR-NEXT: v_not_b32_e32 v8, 0 ; GCN-IR-NEXT: v_not_b32_e32 v4, 0
; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, v9, v13 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, v5, v11
; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v8, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v4, vcc
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v13, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: .LBB1_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB1_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[14:15], v[14:15], 1 ; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v8, 31, v3 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
; GCN-IR-NEXT: v_or_b32_e32 v14, v14, v8 ; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, v16, v14 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v16, v8
; GCN-IR-NEXT: v_subb_u32_e32 v8, vcc, v17, v15, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v17, v9, vcc
; GCN-IR-NEXT: v_or_b32_e32 v2, v12, v2 ; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2
; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v8 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4
; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v10 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v6
; GCN-IR-NEXT: v_or_b32_e32 v3, v13, v3 ; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3
; GCN-IR-NEXT: v_and_b32_e32 v8, 1, v12 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10
; GCN-IR-NEXT: v_and_b32_e32 v13, v12, v1 ; GCN-IR-NEXT: v_and_b32_e32 v11, v10, v1
; GCN-IR-NEXT: v_and_b32_e32 v12, v12, v0 ; GCN-IR-NEXT: v_and_b32_e32 v10, v10, v0
; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11] ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7]
; GCN-IR-NEXT: v_sub_i32_e64 v14, s[4:5], v14, v12 ; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v10
; GCN-IR-NEXT: v_subb_u32_e64 v15, s[4:5], v15, v13, s[4:5] ; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], v9, v11, s[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v13, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v5
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v12, v8 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execnz .LBB1_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB1_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: .LBB1_5: ; %Flow4 ; GCN-IR-NEXT: .LBB1_5: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1
; GCN-IR-NEXT: v_or_b32_e32 v9, v9, v1 ; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v1
; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v0 ; GCN-IR-NEXT: v_or_b32_e32 v4, v4, v0
; GCN-IR-NEXT: .LBB1_6: ; %Flow5 ; GCN-IR-NEXT: .LBB1_6: ; %Flow5
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_xor_b32_e32 v0, v5, v4 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v13, v12
; GCN-IR-NEXT: v_xor_b32_e32 v1, v7, v6 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v15, v14
; GCN-IR-NEXT: v_xor_b32_e32 v3, v8, v0 ; GCN-IR-NEXT: v_xor_b32_e32 v3, v4, v0
; GCN-IR-NEXT: v_xor_b32_e32 v2, v9, v1 ; GCN-IR-NEXT: v_xor_b32_e32 v2, v5, v1
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v3, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v3, v0
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc
; GCN-IR-NEXT: s_setpc_b64 s[30:31] ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = sdiv i64 %x, %y %result = sdiv i64 %x, %y
ret i64 %result ret i64 %result
} }
define amdgpu_kernel void @s_test_sdiv24_64(ptr addrspace(1) %out, i64 %x, i64 %y) { define amdgpu_kernel void @s_test_sdiv24_64(ptr addrspace(1) %out, i64 %x, i64 %y) {
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; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[10:11]
; GCN-IR-NEXT: s_flbit_i32_b32 s8, s6 ; GCN-IR-NEXT: s_flbit_i32_b32 s8, s6
; GCN-IR-NEXT: s_add_i32 s8, s8, 32 ; GCN-IR-NEXT: s_add_i32 s8, s8, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s9, s7 ; GCN-IR-NEXT: s_flbit_i32_b32 s9, s7
; GCN-IR-NEXT: s_min_u32 s14, s8, s9 ; GCN-IR-NEXT: s_min_u32 s14, s8, s9
; GCN-IR-NEXT: s_flbit_i32_b32 s8, s12 ; GCN-IR-NEXT: s_flbit_i32_b32 s8, s12
; GCN-IR-NEXT: s_add_i32 s8, s8, 32 ; GCN-IR-NEXT: s_add_i32 s8, s8, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s9, s13 ; GCN-IR-NEXT: s_flbit_i32_b32 s9, s13
; GCN-IR-NEXT: s_min_u32 s18, s8, s9 ; GCN-IR-NEXT: s_min_u32 s20, s8, s9
; GCN-IR-NEXT: s_sub_u32 s16, s14, s18 ; GCN-IR-NEXT: s_sub_u32 s16, s14, s20
; GCN-IR-NEXT: s_subb_u32 s17, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s17, 0, 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[20:21], s[16:17], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[18:19], s[16:17], 63
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[22:23], s[16:17], 63 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[22:23], s[16:17], 63
; GCN-IR-NEXT: s_or_b64 s[20:21], s[10:11], s[20:21] ; GCN-IR-NEXT: s_or_b64 s[18:19], s[10:11], s[18:19]
; GCN-IR-NEXT: s_and_b64 s[10:11], s[20:21], exec ; GCN-IR-NEXT: s_and_b64 s[10:11], s[18:19], exec
; GCN-IR-NEXT: s_cselect_b32 s11, 0, s13 ; GCN-IR-NEXT: s_cselect_b32 s11, 0, s13
; GCN-IR-NEXT: s_cselect_b32 s10, 0, s12 ; GCN-IR-NEXT: s_cselect_b32 s10, 0, s12
; GCN-IR-NEXT: s_or_b64 s[20:21], s[20:21], s[22:23] ; GCN-IR-NEXT: s_or_b64 s[18:19], s[18:19], s[22:23]
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[20:21] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[18:19]
; GCN-IR-NEXT: s_cbranch_vccz .LBB9_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB9_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s20, s16, 1 ; GCN-IR-NEXT: s_add_u32 s18, s16, 1
; GCN-IR-NEXT: s_addc_u32 s21, s17, 0 ; GCN-IR-NEXT: s_addc_u32 s19, s17, 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[20:21], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[18:19], 0
; GCN-IR-NEXT: s_sub_i32 s16, 63, s16 ; GCN-IR-NEXT: s_sub_i32 s16, 63, s16
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11]
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[12:13], s16 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[12:13], s16
; GCN-IR-NEXT: s_cbranch_vccz .LBB9_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB9_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[16:17], s[12:13], s20 ; GCN-IR-NEXT: s_lshr_b64 s[16:17], s[12:13], s18
; GCN-IR-NEXT: s_add_u32 s19, s6, -1 ; GCN-IR-NEXT: s_add_u32 s18, s6, -1
; GCN-IR-NEXT: s_addc_u32 s20, s7, -1 ; GCN-IR-NEXT: s_addc_u32 s19, s7, -1
; GCN-IR-NEXT: s_not_b64 s[8:9], s[14:15] ; GCN-IR-NEXT: s_not_b64 s[8:9], s[14:15]
; GCN-IR-NEXT: s_add_u32 s12, s8, s18 ; GCN-IR-NEXT: s_add_u32 s12, s8, s20
; GCN-IR-NEXT: s_addc_u32 s13, s9, 0 ; GCN-IR-NEXT: s_addc_u32 s13, s9, 0
; GCN-IR-NEXT: s_mov_b64 s[14:15], 0 ; GCN-IR-NEXT: s_mov_b64 s[14:15], 0
; GCN-IR-NEXT: s_mov_b32 s9, 0 ; GCN-IR-NEXT: s_mov_b32 s9, 0
; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[16:17], s[16:17], 1 ; GCN-IR-NEXT: s_lshl_b64 s[16:17], s[16:17], 1
; GCN-IR-NEXT: s_lshr_b32 s8, s11, 31 ; GCN-IR-NEXT: s_lshr_b32 s8, s11, 31
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[8:9] ; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[8:9]
; GCN-IR-NEXT: s_or_b64 s[10:11], s[14:15], s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[14:15], s[10:11]
; GCN-IR-NEXT: s_sub_u32 s8, s19, s16 ; GCN-IR-NEXT: s_sub_u32 s8, s18, s16
; GCN-IR-NEXT: s_subb_u32 s8, s20, s17 ; GCN-IR-NEXT: s_subb_u32 s8, s19, s17
; GCN-IR-NEXT: s_ashr_i32 s14, s8, 31 ; GCN-IR-NEXT: s_ashr_i32 s14, s8, 31
; GCN-IR-NEXT: s_mov_b32 s15, s14 ; GCN-IR-NEXT: s_mov_b32 s15, s14
; GCN-IR-NEXT: s_and_b32 s8, s14, 1 ; GCN-IR-NEXT: s_and_b32 s8, s14, 1
; GCN-IR-NEXT: s_and_b64 s[14:15], s[14:15], s[6:7] ; GCN-IR-NEXT: s_and_b64 s[14:15], s[14:15], s[6:7]
; GCN-IR-NEXT: s_sub_u32 s16, s16, s14 ; GCN-IR-NEXT: s_sub_u32 s16, s16, s14
; GCN-IR-NEXT: s_subb_u32 s17, s17, s15 ; GCN-IR-NEXT: s_subb_u32 s17, s17, s15
; GCN-IR-NEXT: s_add_u32 s12, s12, 1 ; GCN-IR-NEXT: s_add_u32 s12, s12, 1
; GCN-IR-NEXT: s_addc_u32 s13, s13, 0 ; GCN-IR-NEXT: s_addc_u32 s13, s13, 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[22:23], s[12:13], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[20:21], s[12:13], 0
; GCN-IR-NEXT: s_mov_b64 s[14:15], s[8:9] ; GCN-IR-NEXT: s_mov_b64 s[14:15], s[8:9]
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[22:23] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[20:21]
; GCN-IR-NEXT: s_cbranch_vccz .LBB9_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB9_3
; GCN-IR-NEXT: .LBB9_4: ; %Flow4 ; GCN-IR-NEXT: .LBB9_4: ; %Flow4
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[10:11], 1 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[10:11], 1
; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[6:7]
; GCN-IR-NEXT: .LBB9_5: ; %udiv-end ; GCN-IR-NEXT: .LBB9_5: ; %udiv-end
; GCN-IR-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x9
; GCN-IR-NEXT: s_xor_b64 s[0:1], s[4:5], s[2:3] ; GCN-IR-NEXT: s_xor_b64 s[0:1], s[4:5], s[2:3]
; GCN-IR-NEXT: s_xor_b64 s[2:3], s[10:11], s[0:1] ; GCN-IR-NEXT: s_xor_b64 s[2:3], s[10:11], s[0:1]
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; GCN-IR-NEXT: s_ashr_i32 s4, s3, 31 ; GCN-IR-NEXT: s_ashr_i32 s4, s3, 31
; GCN-IR-NEXT: s_mov_b32 s5, s4 ; GCN-IR-NEXT: s_mov_b32 s5, s4
; GCN-IR-NEXT: s_xor_b64 s[2:3], s[4:5], s[2:3] ; GCN-IR-NEXT: s_xor_b64 s[2:3], s[4:5], s[2:3]
; GCN-IR-NEXT: s_sub_u32 s2, s2, s4 ; GCN-IR-NEXT: s_sub_u32 s2, s2, s4
; GCN-IR-NEXT: s_subb_u32 s3, s3, s4 ; GCN-IR-NEXT: s_subb_u32 s3, s3, s4
; GCN-IR-NEXT: s_flbit_i32_b32 s10, s2 ; GCN-IR-NEXT: s_flbit_i32_b32 s10, s2
; GCN-IR-NEXT: s_add_i32 s10, s10, 32 ; GCN-IR-NEXT: s_add_i32 s10, s10, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s11, s3 ; GCN-IR-NEXT: s_flbit_i32_b32 s11, s3
; GCN-IR-NEXT: s_min_u32 s10, s10, s11 ; GCN-IR-NEXT: s_min_u32 s14, s10, s11
; GCN-IR-NEXT: s_add_u32 s12, s10, 0xffffffc5 ; GCN-IR-NEXT: s_add_u32 s10, s14, 0xffffffc5
; GCN-IR-NEXT: s_addc_u32 s13, 0, -1 ; GCN-IR-NEXT: s_addc_u32 s11, 0, -1
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[2:3], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[2:3], 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[14:15], s[12:13], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[12:13], s[10:11], 63
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[16:17], s[12:13], 63 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[16:17], s[10:11], 63
; GCN-IR-NEXT: s_or_b64 s[14:15], s[8:9], s[14:15] ; GCN-IR-NEXT: s_or_b64 s[12:13], s[8:9], s[12:13]
; GCN-IR-NEXT: s_and_b64 s[8:9], s[14:15], exec ; GCN-IR-NEXT: s_and_b64 s[8:9], s[12:13], exec
; GCN-IR-NEXT: s_cselect_b32 s8, 0, 24 ; GCN-IR-NEXT: s_cselect_b32 s8, 0, 24
; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17] ; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[16:17]
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[14:15] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[12:13]
; GCN-IR-NEXT: s_mov_b32 s9, 0 ; GCN-IR-NEXT: s_mov_b32 s9, 0
; GCN-IR-NEXT: s_cbranch_vccz .LBB10_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB10_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s14, s12, 1 ; GCN-IR-NEXT: s_add_u32 s12, s10, 1
; GCN-IR-NEXT: s_addc_u32 s15, s13, 0 ; GCN-IR-NEXT: s_addc_u32 s13, s11, 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[14:15], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[12:13], 0
; GCN-IR-NEXT: s_sub_i32 s11, 63, s12 ; GCN-IR-NEXT: s_sub_i32 s10, 63, s10
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[8:9] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[8:9]
; GCN-IR-NEXT: s_lshl_b64 s[8:9], 24, s11 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], 24, s10
; GCN-IR-NEXT: s_cbranch_vccz .LBB10_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB10_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[12:13], 24, s14 ; GCN-IR-NEXT: s_lshr_b64 s[12:13], 24, s12
; GCN-IR-NEXT: s_add_u32 s16, s2, -1 ; GCN-IR-NEXT: s_add_u32 s16, s2, -1
; GCN-IR-NEXT: s_addc_u32 s17, s3, -1 ; GCN-IR-NEXT: s_addc_u32 s17, s3, -1
; GCN-IR-NEXT: s_sub_u32 s10, 58, s10 ; GCN-IR-NEXT: s_sub_u32 s10, 58, s14
; GCN-IR-NEXT: s_subb_u32 s11, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s11, 0, 0
; GCN-IR-NEXT: s_mov_b64 s[14:15], 0 ; GCN-IR-NEXT: s_mov_b64 s[14:15], 0
; GCN-IR-NEXT: s_mov_b32 s7, 0 ; GCN-IR-NEXT: s_mov_b32 s7, 0
; GCN-IR-NEXT: .LBB10_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB10_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1 ; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1
; GCN-IR-NEXT: s_lshr_b32 s6, s9, 31 ; GCN-IR-NEXT: s_lshr_b32 s6, s9, 31
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1
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; GCN-NEXT: v_xor_b32_e32 v0, v1, v2 ; GCN-NEXT: v_xor_b32_e32 v0, v1, v2
; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v2, vcc ; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v2, vcc
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
; ;
; GCN-IR-LABEL: v_test_sdiv_k_num_i64: ; GCN-IR-LABEL: v_test_sdiv_k_num_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IR-NEXT: v_ashrrev_i32_e32 v2, 31, v1 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v1
; GCN-IR-NEXT: v_xor_b32_e32 v0, v2, v0 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v12, v0
; GCN-IR-NEXT: v_xor_b32_e32 v1, v2, v1 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v12, v1
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v12
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v12, vcc
; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v0 ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 32, v4 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 32, v2
; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v1 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
; GCN-IR-NEXT: v_min_u32_e32 v8, v4, v5 ; GCN-IR-NEXT: v_min_u32_e32 v10, v2, v3
; GCN-IR-NEXT: s_movk_i32 s6, 0xffc5 ; GCN-IR-NEXT: s_movk_i32 s6, 0xffc5
; GCN-IR-NEXT: v_add_i32_e32 v5, vcc, s6, v8 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, s6, v10
; GCN-IR-NEXT: v_addc_u32_e64 v6, s[6:7], 0, -1, vcc ; GCN-IR-NEXT: v_addc_u32_e64 v3, s[6:7], 0, -1, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[5:6] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[2:3]
; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[6:7], 63, v[5:6] ; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[6:7], 63, v[2:3]
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: v_cndmask_b32_e64 v7, 24, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v4, 24, 0, s[4:5]
; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1
; GCN-IR-NEXT: v_mov_b32_e32 v3, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v13, v12
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7] ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7]
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB11_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB11_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v5 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v2
; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v6, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v3, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v5 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[9:10] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[4:5], 24, v4 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], 24, v2
; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB11_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB11_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, -1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, -1, v0
; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, -1, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, -1, v1, vcc
; GCN-IR-NEXT: v_lshr_b64 v[10:11], 24, v9 ; GCN-IR-NEXT: v_lshr_b64 v[8:9], 24, v6
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, 58, v8 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 58, v10
; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], 0, 0, vcc ; GCN-IR-NEXT: v_subb_u32_e64 v7, s[4:5], 0, 0, vcc
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v13, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: .LBB11_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB11_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1 ; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6 ; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v14, v10 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v14, v8
; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v15, v11, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v15, v9, vcc
; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4 ; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2
; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v8 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v6
; GCN-IR-NEXT: v_or_b32_e32 v5, v13, v5 ; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3
; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10
; GCN-IR-NEXT: v_and_b32_e32 v13, v12, v1 ; GCN-IR-NEXT: v_and_b32_e32 v11, v10, v1
; GCN-IR-NEXT: v_and_b32_e32 v12, v12, v0 ; GCN-IR-NEXT: v_and_b32_e32 v10, v10, v0
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9] ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7]
; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v12 ; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v10
; GCN-IR-NEXT: v_subb_u32_e64 v11, s[4:5], v11, v13, s[4:5] ; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], v9, v11, s[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v13, v7 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v5
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v12, v6 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execnz .LBB11_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB11_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: .LBB11_5: ; %Flow4 ; GCN-IR-NEXT: .LBB11_5: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1
; GCN-IR-NEXT: v_or_b32_e32 v4, v7, v1 ; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v1
; GCN-IR-NEXT: v_or_b32_e32 v7, v6, v0 ; GCN-IR-NEXT: v_or_b32_e32 v4, v4, v0
; GCN-IR-NEXT: .LBB11_6: ; %Flow5 ; GCN-IR-NEXT: .LBB11_6: ; %Flow5
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_xor_b32_e32 v0, v7, v2 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v4, v12
; GCN-IR-NEXT: v_xor_b32_e32 v1, v4, v3 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v5, v13
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v12
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v13, vcc
; GCN-IR-NEXT: s_setpc_b64 s[30:31] ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = sdiv i64 24, %x %result = sdiv i64 24, %x
ret i64 %result ret i64 %result
} }
define i64 @v_test_sdiv_pow2_k_num_i64(i64 %x) { define i64 @v_test_sdiv_pow2_k_num_i64(i64 %x) {
; GCN-LABEL: v_test_sdiv_pow2_k_num_i64: ; GCN-LABEL: v_test_sdiv_pow2_k_num_i64:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_xor_b32_e32 v0, v1, v2 ; GCN-NEXT: v_xor_b32_e32 v0, v1, v2
; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v2, vcc ; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v2, vcc
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
; ;
; GCN-IR-LABEL: v_test_sdiv_pow2_k_num_i64: ; GCN-IR-LABEL: v_test_sdiv_pow2_k_num_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IR-NEXT: v_ashrrev_i32_e32 v2, 31, v1 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v1
; GCN-IR-NEXT: v_xor_b32_e32 v0, v2, v0 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v12, v0
; GCN-IR-NEXT: v_xor_b32_e32 v1, v2, v1 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v12, v1
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v12
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v12, vcc
; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v0 ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 32, v4 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 32, v2
; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v1 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
; GCN-IR-NEXT: v_min_u32_e32 v8, v4, v5 ; GCN-IR-NEXT: v_min_u32_e32 v10, v2, v3
; GCN-IR-NEXT: s_movk_i32 s6, 0xffd0 ; GCN-IR-NEXT: s_movk_i32 s6, 0xffd0
; GCN-IR-NEXT: v_add_i32_e32 v5, vcc, s6, v8 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, s6, v10
; GCN-IR-NEXT: v_addc_u32_e64 v6, s[6:7], 0, -1, vcc ; GCN-IR-NEXT: v_addc_u32_e64 v3, s[6:7], 0, -1, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[5:6] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[2:3]
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0x8000 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0x8000
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[5:6] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[2:3]
; GCN-IR-NEXT: v_cndmask_b32_e64 v7, v7, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[4:5]
; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1
; GCN-IR-NEXT: v_mov_b32_e32 v3, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v13, v12
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0x8000 ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0x8000
; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB12_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB12_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v5 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v2
; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v6, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v3, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v5 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[9:10] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[4:5], s[8:9], v4 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[8:9], v2
; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB12_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB12_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, -1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, -1, v0
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0x8000 ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0x8000
; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, -1, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, -1, v1, vcc
; GCN-IR-NEXT: v_lshr_b64 v[10:11], s[4:5], v9 ; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[4:5], v6
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, 47, v8 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 47, v10
; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], 0, 0, vcc ; GCN-IR-NEXT: v_subb_u32_e64 v7, s[4:5], 0, 0, vcc
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v13, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: .LBB12_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB12_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1 ; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6 ; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v14, v10 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v14, v8
; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v15, v11, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v15, v9, vcc
; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4 ; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2
; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v8 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v6
; GCN-IR-NEXT: v_or_b32_e32 v5, v13, v5 ; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3
; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10
; GCN-IR-NEXT: v_and_b32_e32 v13, v12, v1 ; GCN-IR-NEXT: v_and_b32_e32 v11, v10, v1
; GCN-IR-NEXT: v_and_b32_e32 v12, v12, v0 ; GCN-IR-NEXT: v_and_b32_e32 v10, v10, v0
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9] ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7]
; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v12 ; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v10
; GCN-IR-NEXT: v_subb_u32_e64 v11, s[4:5], v11, v13, s[4:5] ; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], v9, v11, s[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v13, v7 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v5
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v12, v6 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execnz .LBB12_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB12_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: .LBB12_5: ; %Flow4 ; GCN-IR-NEXT: .LBB12_5: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1
; GCN-IR-NEXT: v_or_b32_e32 v4, v7, v1 ; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v1
; GCN-IR-NEXT: v_or_b32_e32 v7, v6, v0 ; GCN-IR-NEXT: v_or_b32_e32 v4, v4, v0
; GCN-IR-NEXT: .LBB12_6: ; %Flow5 ; GCN-IR-NEXT: .LBB12_6: ; %Flow5
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_xor_b32_e32 v0, v7, v2 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v4, v12
; GCN-IR-NEXT: v_xor_b32_e32 v1, v4, v3 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v5, v13
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v12
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v13, vcc
; GCN-IR-NEXT: s_setpc_b64 s[30:31] ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = sdiv i64 32768, %x %result = sdiv i64 32768, %x
ret i64 %result ret i64 %result
} }
define i64 @v_test_sdiv_pow2_k_den_i64(i64 %x) { define i64 @v_test_sdiv_pow2_k_den_i64(i64 %x) {
; GCN-LABEL: v_test_sdiv_pow2_k_den_i64: ; GCN-LABEL: v_test_sdiv_pow2_k_den_i64:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v1 ; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v1
; GCN-NEXT: v_lshrrev_b32_e32 v2, 17, v2 ; GCN-NEXT: v_lshrrev_b32_e32 v2, 17, v2
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-NEXT: v_ashr_i64 v[0:1], v[0:1], 15 ; GCN-NEXT: v_ashr_i64 v[0:1], v[0:1], 15
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
; ;
; GCN-IR-LABEL: v_test_sdiv_pow2_k_den_i64: ; GCN-IR-LABEL: v_test_sdiv_pow2_k_den_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IR-NEXT: v_ashrrev_i32_e32 v2, 31, v1 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v1
; GCN-IR-NEXT: v_xor_b32_e32 v0, v2, v0 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v10, v0
; GCN-IR-NEXT: v_xor_b32_e32 v1, v2, v1 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v10, v1
; GCN-IR-NEXT: v_sub_i32_e32 v7, vcc, v0, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v0, v10
; GCN-IR-NEXT: v_subb_u32_e32 v8, vcc, v1, v2, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v5, vcc, v1, v10, vcc
; GCN-IR-NEXT: v_ffbh_u32_e32 v0, v7 ; GCN-IR-NEXT: v_ffbh_u32_e32 v0, v4
; GCN-IR-NEXT: v_add_i32_e64 v0, s[4:5], 32, v0 ; GCN-IR-NEXT: v_add_i32_e64 v0, s[4:5], 32, v0
; GCN-IR-NEXT: v_ffbh_u32_e32 v1, v8 ; GCN-IR-NEXT: v_ffbh_u32_e32 v1, v5
; GCN-IR-NEXT: v_min_u32_e32 v0, v0, v1 ; GCN-IR-NEXT: v_min_u32_e32 v8, v0, v1
; GCN-IR-NEXT: v_sub_i32_e64 v3, s[4:5], 48, v0 ; GCN-IR-NEXT: v_sub_i32_e64 v0, s[4:5], 48, v8
; GCN-IR-NEXT: v_subb_u32_e64 v4, s[4:5], 0, 0, s[4:5] ; GCN-IR-NEXT: v_subb_u32_e64 v1, s[4:5], 0, 0, s[4:5]
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[7:8] ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[3:4] ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[0:1]
; GCN-IR-NEXT: v_mov_b32_e32 v1, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v10
; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[3:4] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v8, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v5, 0, s[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v7, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[4:5]
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB13_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB13_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v3 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v0
; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v4, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v3, s[4:5], 63, v3 ; GCN-IR-NEXT: v_sub_i32_e64 v0, s[4:5], 63, v0
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[9:10] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[3:4], v[7:8], v3 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[4:5], v0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v2, 0
; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB13_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB13_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_lshr_b64 v[9:10], v[7:8], v9 ; GCN-IR-NEXT: v_lshr_b64 v[6:7], v[4:5], v6
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 0xffffffcf, v0 ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 0xffffffcf, v8
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
; GCN-IR-NEXT: v_addc_u32_e64 v8, s[4:5], 0, -1, vcc ; GCN-IR-NEXT: v_addc_u32_e64 v5, s[4:5], 0, -1, vcc
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff ; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff
; GCN-IR-NEXT: .LBB13_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB13_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[9:10], v[9:10], 1 ; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 31, v4 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1
; GCN-IR-NEXT: v_or_b32_e32 v0, v9, v0 ; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2
; GCN-IR-NEXT: v_sub_i32_e32 v5, vcc, s12, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s12, v6
; GCN-IR-NEXT: v_subb_u32_e32 v5, vcc, 0, v10, vcc ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v7 ; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_lshl_b64 v[3:4], v[3:4], 1 ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v4
; GCN-IR-NEXT: v_ashrrev_i32_e32 v9, 31, v5 ; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0
; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc ; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2
; GCN-IR-NEXT: v_and_b32_e32 v5, 1, v9 ; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_and_b32_e32 v9, 0x8000, v9 ; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[7:8] ; GCN-IR-NEXT: v_and_b32_e32 v8, 0x8000, v8
; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4 ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5]
; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3 ; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1
; GCN-IR-NEXT: v_sub_i32_e64 v9, s[4:5], v0, v9 ; GCN-IR-NEXT: v_sub_i32_e64 v6, s[4:5], v6, v8
; GCN-IR-NEXT: v_mov_b32_e32 v12, v6 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v3
; GCN-IR-NEXT: v_subbrev_u32_e64 v10, s[4:5], 0, v10, s[4:5] ; GCN-IR-NEXT: v_subbrev_u32_e64 v7, s[4:5], 0, v7, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v11, v5 ; GCN-IR-NEXT: v_mov_b32_e32 v8, v2
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execnz .LBB13_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB13_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: .LBB13_5: ; %Flow4 ; GCN-IR-NEXT: .LBB13_5: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[3:4], v[3:4], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v4 ; GCN-IR-NEXT: v_or_b32_e32 v3, v3, v1
; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3 ; GCN-IR-NEXT: v_or_b32_e32 v2, v2, v0
; GCN-IR-NEXT: .LBB13_6: ; %Flow5 ; GCN-IR-NEXT: .LBB13_6: ; %Flow5
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_xor_b32_e32 v0, v5, v2 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v2, v10
; GCN-IR-NEXT: v_xor_b32_e32 v3, v6, v1 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v3, v11
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v10
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v11, vcc
; GCN-IR-NEXT: s_setpc_b64 s[30:31] ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = sdiv i64 %x, 32768 %result = sdiv i64 %x, 32768
ret i64 %result ret i64 %result
} }
define amdgpu_kernel void @s_test_sdiv24_k_num_i64(ptr addrspace(1) %out, i64 %x) { define amdgpu_kernel void @s_test_sdiv24_k_num_i64(ptr addrspace(1) %out, i64 %x) {
; GCN-LABEL: s_test_sdiv24_k_num_i64: ; GCN-LABEL: s_test_sdiv24_k_num_i64:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
▲ Show 20 Lines • Show All 238 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir

Show All 13 Lines
machineFunctionInfo: machineFunctionInfo:
scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3 scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
stackPtrOffsetReg: $sgpr32 stackPtrOffsetReg: $sgpr32
body: | body: |
; CHECK-LABEL: name: expecting_non_empty_interval ; CHECK-LABEL: name: expecting_non_empty_interval
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: undef %5.sub1:vreg_64 = V_MOV_B32_e32 1786773504, implicit $exec ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1786773504, implicit $exec
; CHECK-NEXT: dead [[V_MUL_F32_e32_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e32 0, %5.sub1, implicit $mode, implicit $exec ; CHECK-NEXT: dead [[V_MUL_F32_e32_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e32 0, [[V_MOV_B32_e32_]], implicit $mode, implicit $exec
; CHECK-NEXT: undef %7.sub1:vreg_64 = V_MAC_F32_e32 0, undef %1:vgpr_32, undef %7.sub1, implicit $mode, implicit $exec ; CHECK-NEXT: undef %0.sub1:vreg_64 = V_MAC_F32_e32 0, undef %1:vgpr_32, undef %0.sub1, implicit $mode, implicit $exec
; CHECK-NEXT: SI_SPILL_V64_SAVE %7, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, align 4, addrspace 5)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1: ; CHECK-NEXT: bb.1:
; CHECK-NEXT: undef %6.sub1:vreg_64 = V_MOV_B32_e32 1786773504, implicit $exec ; CHECK-NEXT: S_NOP 0, implicit %0.sub1
; CHECK-NEXT: S_NOP 0, implicit %6.sub1 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1786773504, implicit $exec
; CHECK-NEXT: [[SI_SPILL_V64_RESTORE:%[0-9]+]]:vreg_64 = SI_SPILL_V64_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.0, align 4, addrspace 5) ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
; CHECK-NEXT: S_NOP 0, implicit [[SI_SPILL_V64_RESTORE]].sub1 ; CHECK-NEXT: S_NOP 0, implicit undef %0.sub0
; CHECK-NEXT: S_NOP 0, implicit undef %9.sub0:vreg_64
bb.0: bb.0:
successors: %bb.1 successors: %bb.1
undef %0.sub1:vreg_64 = V_MAC_F32_e32 0, undef %1:vgpr_32, undef %0.sub1, implicit $mode, implicit $exec undef %0.sub1:vreg_64 = V_MAC_F32_e32 0, undef %1:vgpr_32, undef %0.sub1, implicit $mode, implicit $exec
undef %2.sub1:vreg_64 = V_MOV_B32_e32 1786773504, implicit $exec undef %2.sub1:vreg_64 = V_MOV_B32_e32 1786773504, implicit $exec
dead %3:vgpr_32 = V_MUL_F32_e32 0, %2.sub1, implicit $mode, implicit $exec dead %3:vgpr_32 = V_MUL_F32_e32 0, %2.sub1, implicit $mode, implicit $exec
bb.1: bb.1:
Show All 13 Lines
machineFunctionInfo: machineFunctionInfo:
scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3 scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
stackPtrOffsetReg: $sgpr32 stackPtrOffsetReg: $sgpr32
body: | body: |
; CHECK-LABEL: name: rematerialize_empty_interval_has_reference ; CHECK-LABEL: name: rematerialize_empty_interval_has_reference
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: undef %1.sub2:vreg_128 = V_MOV_B32_e32 1786773504, implicit $exec ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1786773504, implicit $exec
; CHECK-NEXT: undef %2.sub2:vreg_96 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1: ; CHECK-NEXT: bb.1:
; CHECK-NEXT: S_NOP 0, implicit %1.sub2
; CHECK-NEXT: undef %2.sub2:vreg_128 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: S_NOP 0, implicit %2.sub2 ; CHECK-NEXT: S_NOP 0, implicit %2.sub2
; CHECK-NEXT: S_NOP 0, implicit undef %4.sub0:vreg_128 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
; CHECK-NEXT: S_NOP 0, implicit undef %2.sub0
bb.0: bb.0:
successors: %bb.1 successors: %bb.1
undef %0.sub2:vreg_128 = V_MOV_B32_e32 0, implicit $exec undef %0.sub2:vreg_128 = V_MOV_B32_e32 0, implicit $exec
undef %1.sub2:vreg_128 = V_MOV_B32_e32 1786773504, implicit $exec undef %1.sub2:vreg_128 = V_MOV_B32_e32 1786773504, implicit $exec
bb.1: bb.1:
S_NOP 0, implicit %1.sub2 S_NOP 0, implicit %1.sub2
S_NOP 0, implicit undef %0.sub0 S_NOP 0, implicit undef %0.sub0
S_NOP 0, implicit %0.sub2 S_NOP 0, implicit %0.sub2
... ...

llvm/test/CodeGen/AMDGPU/spill-vgpr.ll

Show First 20 Lines • Show All 131 Lines • ▼ Show 20 Lines
; GFX908: global_load_ ; GFX908: global_load_
; GFX900: buffer_store_dword v ; GFX900: buffer_store_dword v
; GFX900: buffer_load_dword v ; GFX900: buffer_load_dword v
; GFX908-NOT: buffer_ ; GFX908-NOT: buffer_
; GFX908-DAG: v_accvgpr_read_b32 ; GFX908-DAG: v_accvgpr_read_b32
; GFX900: NumVgprs: 256 ; GFX900: NumVgprs: 256
; GFX908: NumVgprs: 252 ; GFX908: NumVgprs: 252
; GFX900: ScratchSize: 1668 ; GFX900: ScratchSize: 132
; GFX908: ScratchSize: 0 ; GFX908: ScratchSize: 0
; GFX900: VGPRBlocks: 63 ; GFX900: VGPRBlocks: 63
; GFX908: VGPRBlocks: 62 ; GFX908: VGPRBlocks: 62
; GFX900: NumVGPRsForWavesPerEU: 256 ; GFX900: NumVGPRsForWavesPerEU: 256
; GFX908: NumVGPRsForWavesPerEU: 252 ; GFX908: NumVGPRsForWavesPerEU: 252
define amdgpu_kernel void @max_256_vgprs_spill_9x32_2bb(ptr addrspace(1) %p) #1 { define amdgpu_kernel void @max_256_vgprs_spill_9x32_2bb(ptr addrspace(1) %p) #1 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%p1 = getelementptr inbounds <32 x float>, ptr addrspace(1) %p, i32 %tid %p1 = getelementptr inbounds <32 x float>, ptr addrspace(1) %p, i32 %tid
▲ Show 20 Lines • Show All 76 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/srem64.ll

Show First 20 Lines • Show All 129 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: s_flbit_i32_b32 s10, s4 ; GCN-IR-NEXT: s_flbit_i32_b32 s10, s4
; GCN-IR-NEXT: s_or_b64 s[8:9], s[6:7], s[8:9] ; GCN-IR-NEXT: s_or_b64 s[8:9], s[6:7], s[8:9]
; GCN-IR-NEXT: s_flbit_i32_b32 s6, s2 ; GCN-IR-NEXT: s_flbit_i32_b32 s6, s2
; GCN-IR-NEXT: s_flbit_i32_b32 s11, s5 ; GCN-IR-NEXT: s_flbit_i32_b32 s11, s5
; GCN-IR-NEXT: s_add_i32 s10, s10, 32 ; GCN-IR-NEXT: s_add_i32 s10, s10, 32
; GCN-IR-NEXT: s_add_i32 s6, s6, 32 ; GCN-IR-NEXT: s_add_i32 s6, s6, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s7, s3 ; GCN-IR-NEXT: s_flbit_i32_b32 s7, s3
; GCN-IR-NEXT: s_min_u32 s10, s10, s11 ; GCN-IR-NEXT: s_min_u32 s10, s10, s11
; GCN-IR-NEXT: s_min_u32 s14, s6, s7 ; GCN-IR-NEXT: s_min_u32 s18, s6, s7
; GCN-IR-NEXT: s_sub_u32 s12, s10, s14 ; GCN-IR-NEXT: s_sub_u32 s12, s10, s18
; GCN-IR-NEXT: s_subb_u32 s13, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s13, 0, 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[16:17], s[12:13], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[14:15], s[12:13], 63
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[18:19], s[12:13], 63 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[16:17], s[12:13], 63
; GCN-IR-NEXT: s_or_b64 s[16:17], s[8:9], s[16:17] ; GCN-IR-NEXT: s_or_b64 s[14:15], s[8:9], s[14:15]
; GCN-IR-NEXT: s_and_b64 s[8:9], s[16:17], exec ; GCN-IR-NEXT: s_and_b64 s[8:9], s[14:15], exec
; GCN-IR-NEXT: s_cselect_b32 s9, 0, s3 ; GCN-IR-NEXT: s_cselect_b32 s9, 0, s3
; GCN-IR-NEXT: s_cselect_b32 s8, 0, s2 ; GCN-IR-NEXT: s_cselect_b32 s8, 0, s2
; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19] ; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17]
; GCN-IR-NEXT: s_mov_b64 s[6:7], 0 ; GCN-IR-NEXT: s_mov_b64 s[6:7], 0
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[16:17] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[14:15]
; GCN-IR-NEXT: s_mov_b32 s11, 0 ; GCN-IR-NEXT: s_mov_b32 s11, 0
; GCN-IR-NEXT: s_cbranch_vccz .LBB0_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s16, s12, 1 ; GCN-IR-NEXT: s_add_u32 s14, s12, 1
; GCN-IR-NEXT: s_addc_u32 s17, s13, 0 ; GCN-IR-NEXT: s_addc_u32 s15, s13, 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[16:17], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[14:15], 0
; GCN-IR-NEXT: s_sub_i32 s12, 63, s12 ; GCN-IR-NEXT: s_sub_i32 s12, 63, s12
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[8:9] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[8:9]
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[2:3], s12 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[2:3], s12
; GCN-IR-NEXT: s_cbranch_vccz .LBB0_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[12:13], s[2:3], s16 ; GCN-IR-NEXT: s_lshr_b64 s[12:13], s[2:3], s14
; GCN-IR-NEXT: s_add_u32 s16, s4, -1 ; GCN-IR-NEXT: s_add_u32 s16, s4, -1
; GCN-IR-NEXT: s_addc_u32 s17, s5, -1 ; GCN-IR-NEXT: s_addc_u32 s17, s5, -1
; GCN-IR-NEXT: s_not_b64 s[6:7], s[10:11] ; GCN-IR-NEXT: s_not_b64 s[6:7], s[10:11]
; GCN-IR-NEXT: s_add_u32 s10, s6, s14 ; GCN-IR-NEXT: s_add_u32 s10, s6, s18
; GCN-IR-NEXT: s_addc_u32 s11, s7, 0 ; GCN-IR-NEXT: s_addc_u32 s11, s7, 0
; GCN-IR-NEXT: s_mov_b64 s[14:15], 0 ; GCN-IR-NEXT: s_mov_b64 s[14:15], 0
; GCN-IR-NEXT: s_mov_b32 s7, 0 ; GCN-IR-NEXT: s_mov_b32 s7, 0
; GCN-IR-NEXT: .LBB0_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB0_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1 ; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1
; GCN-IR-NEXT: s_lshr_b32 s6, s9, 31 ; GCN-IR-NEXT: s_lshr_b32 s6, s9, 31
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1
▲ Show 20 Lines • Show All 160 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_xor_b32_e32 v1, v1, v6 ; GCN-NEXT: v_xor_b32_e32 v1, v1, v6
; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v6 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v6
; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v6, vcc ; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v6, vcc
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
; ;
; GCN-IR-LABEL: v_test_srem: ; GCN-IR-LABEL: v_test_srem:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IR-NEXT: v_ashrrev_i32_e32 v4, 31, v1 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v14, 31, v1
; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v4 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v14
; GCN-IR-NEXT: v_ashrrev_i32_e32 v6, 31, v3 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v4, 31, v3
; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v4 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v14
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v14
; GCN-IR-NEXT: v_xor_b32_e32 v2, v2, v6 ; GCN-IR-NEXT: v_xor_b32_e32 v2, v2, v4
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v14, vcc
; GCN-IR-NEXT: v_xor_b32_e32 v3, v3, v6 ; GCN-IR-NEXT: v_xor_b32_e32 v3, v3, v4
; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, v2, v6 ; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, v2, v4
; GCN-IR-NEXT: v_subb_u32_e32 v3, vcc, v3, v6, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v3, vcc, v3, v4, vcc
; GCN-IR-NEXT: v_ffbh_u32_e32 v6, v2 ; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v2
; GCN-IR-NEXT: v_add_i32_e64 v6, s[6:7], 32, v6 ; GCN-IR-NEXT: v_add_i32_e64 v4, s[6:7], 32, v4
; GCN-IR-NEXT: v_ffbh_u32_e32 v7, v3 ; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v3
; GCN-IR-NEXT: v_min_u32_e32 v10, v6, v7 ; GCN-IR-NEXT: v_min_u32_e32 v12, v4, v5
; GCN-IR-NEXT: v_ffbh_u32_e32 v6, v0 ; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v0
; GCN-IR-NEXT: v_add_i32_e64 v6, s[6:7], 32, v6 ; GCN-IR-NEXT: v_add_i32_e64 v4, s[6:7], 32, v4
; GCN-IR-NEXT: v_ffbh_u32_e32 v7, v1 ; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v1
; GCN-IR-NEXT: v_min_u32_e32 v11, v6, v7 ; GCN-IR-NEXT: v_min_u32_e32 v13, v4, v5
; GCN-IR-NEXT: v_sub_i32_e64 v7, s[6:7], v10, v11 ; GCN-IR-NEXT: v_sub_i32_e64 v4, s[6:7], v12, v13
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3] ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
; GCN-IR-NEXT: v_subb_u32_e64 v8, s[6:7], 0, 0, s[6:7] ; GCN-IR-NEXT: v_subb_u32_e64 v5, s[6:7], 0, 0, s[6:7]
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[6:7], 63, v[7:8] ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[6:7], 63, v[4:5]
; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[7:8] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
; GCN-IR-NEXT: v_mov_b32_e32 v5, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v15, v14
; GCN-IR-NEXT: v_cndmask_b32_e64 v9, v1, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v7, v1, 0, s[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v0, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v0, 0, s[4:5]
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB1_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v7 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v8, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v6, s[4:5], 63, v7 ; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v4
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[12:13] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[0:1], v6 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB1_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_add_i32_e32 v16, vcc, -1, v2 ; GCN-IR-NEXT: v_add_i32_e32 v16, vcc, -1, v2
; GCN-IR-NEXT: v_addc_u32_e32 v17, vcc, -1, v3, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v17, vcc, -1, v3, vcc
; GCN-IR-NEXT: v_not_b32_e32 v9, v10 ; GCN-IR-NEXT: v_not_b32_e32 v7, v12
; GCN-IR-NEXT: v_lshr_b64 v[12:13], v[0:1], v12 ; GCN-IR-NEXT: v_lshr_b64 v[10:11], v[0:1], v8
; GCN-IR-NEXT: v_not_b32_e32 v8, 0 ; GCN-IR-NEXT: v_not_b32_e32 v6, 0
; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, v9, v11 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, v7, v13
; GCN-IR-NEXT: v_mov_b32_e32 v14, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v8, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v6, vcc
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v15, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v13, 0
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: .LBB1_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB1_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[12:13], v[12:13], 1 ; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v8, 31, v7 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5
; GCN-IR-NEXT: v_or_b32_e32 v12, v12, v8 ; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, v16, v12 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v16, v10
; GCN-IR-NEXT: v_subb_u32_e32 v8, vcc, v17, v13, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v17, v11, vcc
; GCN-IR-NEXT: v_or_b32_e32 v6, v14, v6 ; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4
; GCN-IR-NEXT: v_ashrrev_i32_e32 v14, 31, v8 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6
; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v10 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v8
; GCN-IR-NEXT: v_or_b32_e32 v7, v15, v7 ; GCN-IR-NEXT: v_or_b32_e32 v5, v13, v5
; GCN-IR-NEXT: v_and_b32_e32 v8, 1, v14 ; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12
; GCN-IR-NEXT: v_and_b32_e32 v15, v14, v3 ; GCN-IR-NEXT: v_and_b32_e32 v13, v12, v3
; GCN-IR-NEXT: v_and_b32_e32 v14, v14, v2 ; GCN-IR-NEXT: v_and_b32_e32 v12, v12, v2
; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11] ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9]
; GCN-IR-NEXT: v_sub_i32_e64 v12, s[4:5], v12, v14 ; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v12
; GCN-IR-NEXT: v_subb_u32_e64 v13, s[4:5], v13, v15, s[4:5] ; GCN-IR-NEXT: v_subb_u32_e64 v11, s[4:5], v11, v13, s[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v15, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v13, v7
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v14, v8 ; GCN-IR-NEXT: v_mov_b32_e32 v12, v6
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execnz .LBB1_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB1_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: .LBB1_5: ; %Flow4 ; GCN-IR-NEXT: .LBB1_5: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
; GCN-IR-NEXT: v_or_b32_e32 v9, v9, v7 ; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v5
; GCN-IR-NEXT: v_or_b32_e32 v6, v8, v6 ; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v4
; GCN-IR-NEXT: .LBB1_6: ; %Flow5 ; GCN-IR-NEXT: .LBB1_6: ; %Flow5
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_mul_lo_u32 v7, v2, v9 ; GCN-IR-NEXT: v_mul_lo_u32 v4, v2, v7
; GCN-IR-NEXT: v_mul_hi_u32 v8, v2, v6 ; GCN-IR-NEXT: v_mul_hi_u32 v5, v2, v6
; GCN-IR-NEXT: v_mul_lo_u32 v3, v3, v6 ; GCN-IR-NEXT: v_mul_lo_u32 v3, v3, v6
; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, v6 ; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, v6
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, v8, v7 ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v7, v3 ; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v4 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v14
; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v5 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v15
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v14
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v15, vcc
; GCN-IR-NEXT: s_setpc_b64 s[30:31] ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = srem i64 %x, %y %result = srem i64 %x, %y
ret i64 %result ret i64 %result
} }
define amdgpu_kernel void @s_test_srem23_64(ptr addrspace(1) %out, i64 %x, i64 %y) { define amdgpu_kernel void @s_test_srem23_64(ptr addrspace(1) %out, i64 %x, i64 %y) {
; GCN-LABEL: s_test_srem23_64: ; GCN-LABEL: s_test_srem23_64:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
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; GCN-IR-NEXT: s_or_b64 s[10:11], s[6:7], s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[6:7], s[10:11]
; GCN-IR-NEXT: s_flbit_i32_b32 s6, s8 ; GCN-IR-NEXT: s_flbit_i32_b32 s6, s8
; GCN-IR-NEXT: s_add_i32 s6, s6, 32 ; GCN-IR-NEXT: s_add_i32 s6, s6, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s7, s9 ; GCN-IR-NEXT: s_flbit_i32_b32 s7, s9
; GCN-IR-NEXT: s_min_u32 s12, s6, s7 ; GCN-IR-NEXT: s_min_u32 s12, s6, s7
; GCN-IR-NEXT: s_flbit_i32_b32 s6, s2 ; GCN-IR-NEXT: s_flbit_i32_b32 s6, s2
; GCN-IR-NEXT: s_add_i32 s6, s6, 32 ; GCN-IR-NEXT: s_add_i32 s6, s6, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s7, s3 ; GCN-IR-NEXT: s_flbit_i32_b32 s7, s3
; GCN-IR-NEXT: s_min_u32 s16, s6, s7 ; GCN-IR-NEXT: s_min_u32 s20, s6, s7
; GCN-IR-NEXT: s_sub_u32 s14, s12, s16 ; GCN-IR-NEXT: s_sub_u32 s14, s12, s20
; GCN-IR-NEXT: s_subb_u32 s15, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s15, 0, 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[18:19], s[14:15], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[16:17], s[14:15], 63
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[20:21], s[14:15], 63 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[18:19], s[14:15], 63
; GCN-IR-NEXT: s_or_b64 s[18:19], s[10:11], s[18:19] ; GCN-IR-NEXT: s_or_b64 s[16:17], s[10:11], s[16:17]
; GCN-IR-NEXT: s_and_b64 s[10:11], s[18:19], exec ; GCN-IR-NEXT: s_and_b64 s[10:11], s[16:17], exec
; GCN-IR-NEXT: s_cselect_b32 s11, 0, s3 ; GCN-IR-NEXT: s_cselect_b32 s11, 0, s3
; GCN-IR-NEXT: s_cselect_b32 s10, 0, s2 ; GCN-IR-NEXT: s_cselect_b32 s10, 0, s2
; GCN-IR-NEXT: s_or_b64 s[18:19], s[18:19], s[20:21] ; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19]
; GCN-IR-NEXT: s_mov_b64 s[6:7], 0 ; GCN-IR-NEXT: s_mov_b64 s[6:7], 0
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[18:19] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[16:17]
; GCN-IR-NEXT: s_cbranch_vccz .LBB8_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB8_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s18, s14, 1 ; GCN-IR-NEXT: s_add_u32 s16, s14, 1
; GCN-IR-NEXT: s_addc_u32 s19, s15, 0 ; GCN-IR-NEXT: s_addc_u32 s17, s15, 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[18:19], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[16:17], 0
; GCN-IR-NEXT: s_sub_i32 s14, 63, s14 ; GCN-IR-NEXT: s_sub_i32 s14, 63, s14
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11]
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[2:3], s14 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[2:3], s14
; GCN-IR-NEXT: s_cbranch_vccz .LBB8_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB8_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[14:15], s[2:3], s18 ; GCN-IR-NEXT: s_lshr_b64 s[14:15], s[2:3], s16
; GCN-IR-NEXT: s_add_u32 s18, s8, -1 ; GCN-IR-NEXT: s_add_u32 s18, s8, -1
; GCN-IR-NEXT: s_addc_u32 s19, s9, -1 ; GCN-IR-NEXT: s_addc_u32 s19, s9, -1
; GCN-IR-NEXT: s_not_b64 s[6:7], s[12:13] ; GCN-IR-NEXT: s_not_b64 s[6:7], s[12:13]
; GCN-IR-NEXT: s_add_u32 s12, s6, s16 ; GCN-IR-NEXT: s_add_u32 s12, s6, s20
; GCN-IR-NEXT: s_addc_u32 s13, s7, 0 ; GCN-IR-NEXT: s_addc_u32 s13, s7, 0
; GCN-IR-NEXT: s_mov_b64 s[16:17], 0 ; GCN-IR-NEXT: s_mov_b64 s[16:17], 0
; GCN-IR-NEXT: s_mov_b32 s7, 0 ; GCN-IR-NEXT: s_mov_b32 s7, 0
; GCN-IR-NEXT: .LBB8_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB8_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[14:15], s[14:15], 1 ; GCN-IR-NEXT: s_lshl_b64 s[14:15], s[14:15], 1
; GCN-IR-NEXT: s_lshr_b32 s6, s11, 31 ; GCN-IR-NEXT: s_lshr_b32 s6, s11, 31
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
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; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[10:11]
; GCN-IR-NEXT: s_flbit_i32_b32 s8, s6 ; GCN-IR-NEXT: s_flbit_i32_b32 s8, s6
; GCN-IR-NEXT: s_add_i32 s8, s8, 32 ; GCN-IR-NEXT: s_add_i32 s8, s8, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s9, s7 ; GCN-IR-NEXT: s_flbit_i32_b32 s9, s7
; GCN-IR-NEXT: s_min_u32 s12, s8, s9 ; GCN-IR-NEXT: s_min_u32 s12, s8, s9
; GCN-IR-NEXT: s_flbit_i32_b32 s8, s4 ; GCN-IR-NEXT: s_flbit_i32_b32 s8, s4
; GCN-IR-NEXT: s_add_i32 s8, s8, 32 ; GCN-IR-NEXT: s_add_i32 s8, s8, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s9, s5 ; GCN-IR-NEXT: s_flbit_i32_b32 s9, s5
; GCN-IR-NEXT: s_min_u32 s16, s8, s9 ; GCN-IR-NEXT: s_min_u32 s20, s8, s9
; GCN-IR-NEXT: s_sub_u32 s14, s12, s16 ; GCN-IR-NEXT: s_sub_u32 s14, s12, s20
; GCN-IR-NEXT: s_subb_u32 s15, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s15, 0, 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[18:19], s[14:15], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[16:17], s[14:15], 63
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[20:21], s[14:15], 63 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[18:19], s[14:15], 63
; GCN-IR-NEXT: s_or_b64 s[18:19], s[10:11], s[18:19] ; GCN-IR-NEXT: s_or_b64 s[16:17], s[10:11], s[16:17]
; GCN-IR-NEXT: s_and_b64 s[10:11], s[18:19], exec ; GCN-IR-NEXT: s_and_b64 s[10:11], s[16:17], exec
; GCN-IR-NEXT: s_cselect_b32 s11, 0, s5 ; GCN-IR-NEXT: s_cselect_b32 s11, 0, s5
; GCN-IR-NEXT: s_cselect_b32 s10, 0, s4 ; GCN-IR-NEXT: s_cselect_b32 s10, 0, s4
; GCN-IR-NEXT: s_or_b64 s[18:19], s[18:19], s[20:21] ; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19]
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[18:19] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[16:17]
; GCN-IR-NEXT: s_cbranch_vccz .LBB9_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB9_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s18, s14, 1 ; GCN-IR-NEXT: s_add_u32 s16, s14, 1
; GCN-IR-NEXT: s_addc_u32 s19, s15, 0 ; GCN-IR-NEXT: s_addc_u32 s17, s15, 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[18:19], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[16:17], 0
; GCN-IR-NEXT: s_sub_i32 s14, 63, s14 ; GCN-IR-NEXT: s_sub_i32 s14, 63, s14
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11]
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[4:5], s14 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[4:5], s14
; GCN-IR-NEXT: s_cbranch_vccz .LBB9_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB9_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[14:15], s[4:5], s18 ; GCN-IR-NEXT: s_lshr_b64 s[14:15], s[4:5], s16
; GCN-IR-NEXT: s_add_u32 s18, s6, -1 ; GCN-IR-NEXT: s_add_u32 s18, s6, -1
; GCN-IR-NEXT: s_addc_u32 s19, s7, -1 ; GCN-IR-NEXT: s_addc_u32 s19, s7, -1
; GCN-IR-NEXT: s_not_b64 s[8:9], s[12:13] ; GCN-IR-NEXT: s_not_b64 s[8:9], s[12:13]
; GCN-IR-NEXT: s_add_u32 s12, s8, s16 ; GCN-IR-NEXT: s_add_u32 s12, s8, s20
; GCN-IR-NEXT: s_addc_u32 s13, s9, 0 ; GCN-IR-NEXT: s_addc_u32 s13, s9, 0
; GCN-IR-NEXT: s_mov_b64 s[16:17], 0 ; GCN-IR-NEXT: s_mov_b64 s[16:17], 0
; GCN-IR-NEXT: s_mov_b32 s9, 0 ; GCN-IR-NEXT: s_mov_b32 s9, 0
; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[14:15], s[14:15], 1 ; GCN-IR-NEXT: s_lshl_b64 s[14:15], s[14:15], 1
; GCN-IR-NEXT: s_lshr_b32 s8, s11, 31 ; GCN-IR-NEXT: s_lshr_b32 s8, s11, 31
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
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; GCN-IR-NEXT: s_ashr_i32 s8, s3, 31 ; GCN-IR-NEXT: s_ashr_i32 s8, s3, 31
; GCN-IR-NEXT: s_mov_b32 s9, s8 ; GCN-IR-NEXT: s_mov_b32 s9, s8
; GCN-IR-NEXT: s_xor_b64 s[2:3], s[2:3], s[8:9] ; GCN-IR-NEXT: s_xor_b64 s[2:3], s[2:3], s[8:9]
; GCN-IR-NEXT: s_sub_u32 s4, s2, s8 ; GCN-IR-NEXT: s_sub_u32 s4, s2, s8
; GCN-IR-NEXT: s_subb_u32 s5, s3, s8 ; GCN-IR-NEXT: s_subb_u32 s5, s3, s8
; GCN-IR-NEXT: s_flbit_i32_b32 s2, s4 ; GCN-IR-NEXT: s_flbit_i32_b32 s2, s4
; GCN-IR-NEXT: s_add_i32 s2, s2, 32 ; GCN-IR-NEXT: s_add_i32 s2, s2, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s3, s5 ; GCN-IR-NEXT: s_flbit_i32_b32 s3, s5
; GCN-IR-NEXT: s_min_u32 s8, s2, s3 ; GCN-IR-NEXT: s_min_u32 s12, s2, s3
; GCN-IR-NEXT: s_add_u32 s2, s8, 0xffffffc5 ; GCN-IR-NEXT: s_add_u32 s2, s12, 0xffffffc5
; GCN-IR-NEXT: s_addc_u32 s3, 0, -1 ; GCN-IR-NEXT: s_addc_u32 s3, 0, -1
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[4:5], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[4:5], 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[12:13], s[2:3], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[10:11], s[2:3], 63
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[14:15], s[2:3], 63 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[14:15], s[2:3], 63
; GCN-IR-NEXT: s_or_b64 s[12:13], s[10:11], s[12:13] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[10:11]
; GCN-IR-NEXT: s_and_b64 s[10:11], s[12:13], exec ; GCN-IR-NEXT: s_and_b64 s[8:9], s[10:11], exec
; GCN-IR-NEXT: s_cselect_b32 s10, 0, 24 ; GCN-IR-NEXT: s_cselect_b32 s8, 0, 24
; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[14:15] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[14:15]
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[12:13] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11]
; GCN-IR-NEXT: s_mov_b32 s11, 0 ; GCN-IR-NEXT: s_mov_b32 s9, 0
; GCN-IR-NEXT: s_cbranch_vccz .LBB10_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB10_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s10, s2, 1 ; GCN-IR-NEXT: s_add_u32 s8, s2, 1
; GCN-IR-NEXT: s_addc_u32 s11, s3, 0 ; GCN-IR-NEXT: s_addc_u32 s9, s3, 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[10:11], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[8:9], 0
; GCN-IR-NEXT: s_sub_i32 s2, 63, s2 ; GCN-IR-NEXT: s_sub_i32 s2, 63, s2
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[12:13] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11]
; GCN-IR-NEXT: s_lshl_b64 s[2:3], 24, s2 ; GCN-IR-NEXT: s_lshl_b64 s[2:3], 24, s2
; GCN-IR-NEXT: s_cbranch_vccz .LBB10_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB10_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[10:11], 24, s10 ; GCN-IR-NEXT: s_lshr_b64 s[10:11], 24, s8
; GCN-IR-NEXT: s_add_u32 s14, s4, -1 ; GCN-IR-NEXT: s_add_u32 s14, s4, -1
; GCN-IR-NEXT: s_addc_u32 s15, s5, -1 ; GCN-IR-NEXT: s_addc_u32 s15, s5, -1
; GCN-IR-NEXT: s_sub_u32 s8, 58, s8 ; GCN-IR-NEXT: s_sub_u32 s8, 58, s12
; GCN-IR-NEXT: s_subb_u32 s9, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s9, 0, 0
; GCN-IR-NEXT: s_mov_b64 s[12:13], 0 ; GCN-IR-NEXT: s_mov_b64 s[12:13], 0
; GCN-IR-NEXT: s_mov_b32 s7, 0 ; GCN-IR-NEXT: s_mov_b32 s7, 0
; GCN-IR-NEXT: .LBB10_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB10_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
; GCN-IR-NEXT: s_lshr_b32 s6, s3, 31 ; GCN-IR-NEXT: s_lshr_b32 s6, s3, 31
; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 ; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
Show All 10 Lines
; GCN-IR-NEXT: s_add_u32 s8, s8, 1 ; GCN-IR-NEXT: s_add_u32 s8, s8, 1
; GCN-IR-NEXT: s_addc_u32 s9, s9, 0 ; GCN-IR-NEXT: s_addc_u32 s9, s9, 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[16:17], s[8:9], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[16:17], s[8:9], 0
; GCN-IR-NEXT: s_mov_b64 s[12:13], s[6:7] ; GCN-IR-NEXT: s_mov_b64 s[12:13], s[6:7]
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[16:17] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[16:17]
; GCN-IR-NEXT: s_cbranch_vccz .LBB10_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB10_3
; GCN-IR-NEXT: .LBB10_4: ; %Flow6 ; GCN-IR-NEXT: .LBB10_4: ; %Flow6
; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[2:3], 1 ; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
; GCN-IR-NEXT: s_or_b64 s[10:11], s[6:7], s[2:3] ; GCN-IR-NEXT: s_or_b64 s[8:9], s[6:7], s[2:3]
; GCN-IR-NEXT: .LBB10_5: ; %udiv-end ; GCN-IR-NEXT: .LBB10_5: ; %udiv-end
; GCN-IR-NEXT: v_mov_b32_e32 v0, s10 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s8
; GCN-IR-NEXT: v_mul_hi_u32 v0, s4, v0 ; GCN-IR-NEXT: v_mul_hi_u32 v0, s4, v0
; GCN-IR-NEXT: s_mul_i32 s6, s4, s11 ; GCN-IR-NEXT: s_mul_i32 s6, s4, s9
; GCN-IR-NEXT: s_mul_i32 s5, s5, s10 ; GCN-IR-NEXT: s_mul_i32 s5, s5, s8
; GCN-IR-NEXT: s_mul_i32 s4, s4, s10 ; GCN-IR-NEXT: s_mul_i32 s4, s4, s8
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s6, v0 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s6, v0
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, s5, v0 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, s5, v0
; GCN-IR-NEXT: v_sub_i32_e64 v0, vcc, 24, s4 ; GCN-IR-NEXT: v_sub_i32_e64 v0, vcc, 24, s4
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_mov_b32 s2, -1
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; GCN-IR-NEXT: s_endpgm ; GCN-IR-NEXT: s_endpgm
▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_ashrrev_i32_e32 v2, 31, v1 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v2, 31, v1
; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v2 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v2
; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v2 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v2
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0 ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0
; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 32, v2 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 32, v2
; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
; GCN-IR-NEXT: v_min_u32_e32 v6, v2, v3 ; GCN-IR-NEXT: v_min_u32_e32 v10, v2, v3
; GCN-IR-NEXT: s_movk_i32 s6, 0xffc5 ; GCN-IR-NEXT: s_movk_i32 s6, 0xffc5
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, s6, v6 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, s6, v10
; GCN-IR-NEXT: v_addc_u32_e64 v5, s[6:7], 0, -1, vcc ; GCN-IR-NEXT: v_addc_u32_e64 v3, s[6:7], 0, -1, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[4:5] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[2:3]
; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[6:7], 63, v[4:5] ; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[6:7], 63, v[2:3]
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: v_cndmask_b32_e64 v3, 24, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v4, 24, 0, s[4:5]
; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1
; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7] ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7]
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB11_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB11_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v4 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v2
; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v5, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v3, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[7:8] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[2:3], 24, v2 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], 24, v2
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB11_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB11_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc
; GCN-IR-NEXT: v_lshr_b64 v[8:9], 24, v7 ; GCN-IR-NEXT: v_lshr_b64 v[8:9], 24, v6
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 58, v6 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 58, v10
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_subb_u32_e64 v7, s[4:5], 0, 0, vcc ; GCN-IR-NEXT: v_subb_u32_e64 v7, s[4:5], 0, 0, vcc
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: .LBB11_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB11_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 ; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
Show All 17 Lines
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v10, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execnz .LBB11_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB11_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: .LBB11_5: ; %Flow4 ; GCN-IR-NEXT: .LBB11_5: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v7 ; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3
; GCN-IR-NEXT: v_or_b32_e32 v3, v4, v6 ; GCN-IR-NEXT: v_or_b32_e32 v4, v4, v2
; GCN-IR-NEXT: .LBB11_6: ; %Flow5 ; GCN-IR-NEXT: .LBB11_6: ; %Flow5
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_mul_lo_u32 v2, v0, v2 ; GCN-IR-NEXT: v_mul_lo_u32 v2, v0, v5
; GCN-IR-NEXT: v_mul_hi_u32 v4, v0, v3 ; GCN-IR-NEXT: v_mul_hi_u32 v3, v0, v4
; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v3 ; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v4
; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, v3 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, v4
; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v4, v2 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 24, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 24, v0
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: s_setpc_b64 s[30:31] ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = srem i64 24, %x %result = srem i64 24, %x
ret i64 %result ret i64 %result
} }
▲ Show 20 Lines • Show All 102 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_ashrrev_i32_e32 v2, 31, v1 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v2, 31, v1
; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v2 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v2
; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v2 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v2
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0 ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0
; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 32, v2 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 32, v2
; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
; GCN-IR-NEXT: v_min_u32_e32 v6, v2, v3 ; GCN-IR-NEXT: v_min_u32_e32 v10, v2, v3
; GCN-IR-NEXT: s_movk_i32 s6, 0xffd0 ; GCN-IR-NEXT: s_movk_i32 s6, 0xffd0
; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, s6, v6 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, s6, v10
; GCN-IR-NEXT: v_addc_u32_e64 v4, s[6:7], 0, -1, vcc ; GCN-IR-NEXT: v_addc_u32_e64 v3, s[6:7], 0, -1, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[3:4] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[2:3]
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0x8000 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0x8000
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[3:4] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[2:3]
; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v5, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[4:5]
; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1
; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0x8000 ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0x8000
; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB12_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB12_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v3 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v2
; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v4, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v3, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v3 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[7:8] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[8:9], v2 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[8:9], v2
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB12_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB12_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0x8000 ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0x8000
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc
; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[4:5], v7 ; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[4:5], v6
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 47, v6 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 47, v10
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_subb_u32_e64 v7, s[4:5], 0, 0, vcc ; GCN-IR-NEXT: v_subb_u32_e64 v7, s[4:5], 0, 0, vcc
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: .LBB12_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB12_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 ; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
Show All 17 Lines
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v10, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execnz .LBB12_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB12_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: .LBB12_5: ; %Flow4 ; GCN-IR-NEXT: .LBB12_5: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v7 ; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3
; GCN-IR-NEXT: v_or_b32_e32 v5, v4, v6 ; GCN-IR-NEXT: v_or_b32_e32 v4, v4, v2
; GCN-IR-NEXT: .LBB12_6: ; %Flow5 ; GCN-IR-NEXT: .LBB12_6: ; %Flow5
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_mul_lo_u32 v2, v0, v2 ; GCN-IR-NEXT: v_mul_lo_u32 v2, v0, v5
; GCN-IR-NEXT: v_mul_hi_u32 v3, v0, v5 ; GCN-IR-NEXT: v_mul_hi_u32 v3, v0, v4
; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v5 ; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v4
; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, v5 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, v4
; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 0x8000, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 0x8000, v0
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: s_setpc_b64 s[30:31] ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = srem i64 32768, %x %result = srem i64 32768, %x
ret i64 %result ret i64 %result
} }
Show All 9 Lines
; GCN-NEXT: v_and_b32_e32 v2, 0xffff8000, v2 ; GCN-NEXT: v_and_b32_e32 v2, 0xffff8000, v2
; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc ; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
; ;
; GCN-IR-LABEL: v_test_srem_pow2_k_den_i64: ; GCN-IR-LABEL: v_test_srem_pow2_k_den_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IR-NEXT: v_ashrrev_i32_e32 v2, 31, v1 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v1
; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v2 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v12
; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v2 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v12
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v12
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v12, vcc
; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v0 ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0
; GCN-IR-NEXT: v_add_i32_e64 v3, s[4:5], 32, v3 ; GCN-IR-NEXT: v_add_i32_e64 v2, s[4:5], 32, v2
; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v1 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
; GCN-IR-NEXT: v_min_u32_e32 v8, v3, v4 ; GCN-IR-NEXT: v_min_u32_e32 v10, v2, v3
; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 48, v8 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 48, v10
; GCN-IR-NEXT: v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5] ; GCN-IR-NEXT: v_subb_u32_e64 v3, s[4:5], 0, 0, s[4:5]
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[4:5] ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[2:3]
; GCN-IR-NEXT: v_mov_b32_e32 v3, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v13, v12
; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[2:3]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
; GCN-IR-NEXT: v_cndmask_b32_e64 v7, v1, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v1, 0, s[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v0, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v0, 0, s[4:5]
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB13_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB13_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v4 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v2
; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v5, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v3, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v4 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[9:10] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2
; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB13_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB13_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_lshr_b64 v[10:11], v[0:1], v9 ; GCN-IR-NEXT: v_lshr_b64 v[8:9], v[0:1], v6
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 0xffffffcf, v8 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 0xffffffcf, v10
; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_addc_u32_e64 v9, s[4:5], 0, -1, vcc ; GCN-IR-NEXT: v_addc_u32_e64 v7, s[4:5], 0, -1, vcc
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v13, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff ; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff
; GCN-IR-NEXT: .LBB13_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB13_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1 ; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6 ; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, s12, v10 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s12, v8
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, 0, v11, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v9, vcc
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v8 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v6
; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4 ; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2
; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10
; GCN-IR-NEXT: v_and_b32_e32 v12, 0x8000, v12 ; GCN-IR-NEXT: v_and_b32_e32 v10, 0x8000, v10
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9] ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7]
; GCN-IR-NEXT: v_or_b32_e32 v5, v13, v5 ; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3
; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v12 ; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v10
; GCN-IR-NEXT: v_mov_b32_e32 v13, v7 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v5
; GCN-IR-NEXT: v_subbrev_u32_e64 v11, s[4:5], 0, v11, s[4:5] ; GCN-IR-NEXT: v_subbrev_u32_e64 v9, s[4:5], 0, v9, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v12, v6 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execnz .LBB13_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB13_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: .LBB13_5: ; %Flow4 ; GCN-IR-NEXT: .LBB13_5: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v5 ; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3
; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v4 ; GCN-IR-NEXT: v_or_b32_e32 v4, v4, v2
; GCN-IR-NEXT: .LBB13_6: ; %Flow5 ; GCN-IR-NEXT: .LBB13_6: ; %Flow5
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[6:7], 15 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[4:5], 15
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc
; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v2
; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v3
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v12
; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v13
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v12
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v13, vcc
; GCN-IR-NEXT: s_setpc_b64 s[30:31] ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = srem i64 %x, 32768 %result = srem i64 %x, 32768
ret i64 %result ret i64 %result
} }
define amdgpu_kernel void @s_test_srem24_k_num_i64(ptr addrspace(1) %out, i64 %x) { define amdgpu_kernel void @s_test_srem24_k_num_i64(ptr addrspace(1) %out, i64 %x) {
; GCN-LABEL: s_test_srem24_k_num_i64: ; GCN-LABEL: s_test_srem24_k_num_i64:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
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llvm/test/CodeGen/AMDGPU/udiv64.ll

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; GCN-IR-NEXT: s_flbit_i32_b32 s10, s4 ; GCN-IR-NEXT: s_flbit_i32_b32 s10, s4
; GCN-IR-NEXT: s_or_b64 s[8:9], s[6:7], s[8:9] ; GCN-IR-NEXT: s_or_b64 s[8:9], s[6:7], s[8:9]
; GCN-IR-NEXT: s_flbit_i32_b32 s6, s2 ; GCN-IR-NEXT: s_flbit_i32_b32 s6, s2
; GCN-IR-NEXT: s_flbit_i32_b32 s11, s5 ; GCN-IR-NEXT: s_flbit_i32_b32 s11, s5
; GCN-IR-NEXT: s_add_i32 s10, s10, 32 ; GCN-IR-NEXT: s_add_i32 s10, s10, 32
; GCN-IR-NEXT: s_add_i32 s6, s6, 32 ; GCN-IR-NEXT: s_add_i32 s6, s6, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s7, s3 ; GCN-IR-NEXT: s_flbit_i32_b32 s7, s3
; GCN-IR-NEXT: s_min_u32 s10, s10, s11 ; GCN-IR-NEXT: s_min_u32 s10, s10, s11
; GCN-IR-NEXT: s_min_u32 s14, s6, s7 ; GCN-IR-NEXT: s_min_u32 s16, s6, s7
; GCN-IR-NEXT: s_sub_u32 s12, s10, s14 ; GCN-IR-NEXT: s_sub_u32 s12, s10, s16
; GCN-IR-NEXT: s_subb_u32 s13, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s13, 0, 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[16:17], s[12:13], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[14:15], s[12:13], 63
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[18:19], s[12:13], 63 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[18:19], s[12:13], 63
; GCN-IR-NEXT: s_or_b64 s[16:17], s[8:9], s[16:17] ; GCN-IR-NEXT: s_or_b64 s[14:15], s[8:9], s[14:15]
; GCN-IR-NEXT: s_and_b64 s[8:9], s[16:17], exec ; GCN-IR-NEXT: s_and_b64 s[8:9], s[14:15], exec
; GCN-IR-NEXT: s_cselect_b32 s9, 0, s3 ; GCN-IR-NEXT: s_cselect_b32 s9, 0, s3
; GCN-IR-NEXT: s_cselect_b32 s8, 0, s2 ; GCN-IR-NEXT: s_cselect_b32 s8, 0, s2
; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19] ; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[18:19]
; GCN-IR-NEXT: s_mov_b64 s[6:7], 0 ; GCN-IR-NEXT: s_mov_b64 s[6:7], 0
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[16:17] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[14:15]
; GCN-IR-NEXT: s_mov_b32 s11, 0 ; GCN-IR-NEXT: s_mov_b32 s11, 0
; GCN-IR-NEXT: s_cbranch_vccz .LBB0_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s16, s12, 1 ; GCN-IR-NEXT: s_add_u32 s14, s12, 1
; GCN-IR-NEXT: s_addc_u32 s17, s13, 0 ; GCN-IR-NEXT: s_addc_u32 s15, s13, 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[16:17], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[14:15], 0
; GCN-IR-NEXT: s_sub_i32 s12, 63, s12 ; GCN-IR-NEXT: s_sub_i32 s12, 63, s12
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[8:9] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[8:9]
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[2:3], s12 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[2:3], s12
; GCN-IR-NEXT: s_cbranch_vccz .LBB0_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[12:13], s[2:3], s16 ; GCN-IR-NEXT: s_lshr_b64 s[12:13], s[2:3], s14
; GCN-IR-NEXT: s_add_u32 s15, s4, -1 ; GCN-IR-NEXT: s_add_u32 s14, s4, -1
; GCN-IR-NEXT: s_addc_u32 s16, s5, -1 ; GCN-IR-NEXT: s_addc_u32 s15, s5, -1
; GCN-IR-NEXT: s_not_b64 s[2:3], s[10:11] ; GCN-IR-NEXT: s_not_b64 s[2:3], s[10:11]
; GCN-IR-NEXT: s_add_u32 s2, s2, s14 ; GCN-IR-NEXT: s_add_u32 s2, s2, s16
; GCN-IR-NEXT: s_addc_u32 s3, s3, 0 ; GCN-IR-NEXT: s_addc_u32 s3, s3, 0
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: s_mov_b32 s7, 0 ; GCN-IR-NEXT: s_mov_b32 s7, 0
; GCN-IR-NEXT: .LBB0_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB0_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1 ; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1
; GCN-IR-NEXT: s_lshr_b32 s6, s9, 31 ; GCN-IR-NEXT: s_lshr_b32 s6, s9, 31
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1
; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[6:7]
; GCN-IR-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9] ; GCN-IR-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9]
; GCN-IR-NEXT: s_sub_u32 s6, s15, s12 ; GCN-IR-NEXT: s_sub_u32 s6, s14, s12
; GCN-IR-NEXT: s_subb_u32 s6, s16, s13 ; GCN-IR-NEXT: s_subb_u32 s6, s15, s13
; GCN-IR-NEXT: s_ashr_i32 s10, s6, 31 ; GCN-IR-NEXT: s_ashr_i32 s10, s6, 31
; GCN-IR-NEXT: s_mov_b32 s11, s10 ; GCN-IR-NEXT: s_mov_b32 s11, s10
; GCN-IR-NEXT: s_and_b32 s6, s10, 1 ; GCN-IR-NEXT: s_and_b32 s6, s10, 1
; GCN-IR-NEXT: s_and_b64 s[10:11], s[10:11], s[4:5] ; GCN-IR-NEXT: s_and_b64 s[10:11], s[10:11], s[4:5]
; GCN-IR-NEXT: s_sub_u32 s12, s12, s10 ; GCN-IR-NEXT: s_sub_u32 s12, s12, s10
; GCN-IR-NEXT: s_subb_u32 s13, s13, s11 ; GCN-IR-NEXT: s_subb_u32 s13, s13, s11
; GCN-IR-NEXT: s_add_u32 s2, s2, 1 ; GCN-IR-NEXT: s_add_u32 s2, s2, 1
; GCN-IR-NEXT: s_addc_u32 s3, s3, 0 ; GCN-IR-NEXT: s_addc_u32 s3, s3, 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[18:19], s[2:3], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[16:17], s[2:3], 0
; GCN-IR-NEXT: s_mov_b64 s[10:11], s[6:7] ; GCN-IR-NEXT: s_mov_b64 s[10:11], s[6:7]
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[18:19] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[16:17]
; GCN-IR-NEXT: s_cbranch_vccz .LBB0_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_3
; GCN-IR-NEXT: .LBB0_4: ; %Flow7 ; GCN-IR-NEXT: .LBB0_4: ; %Flow7
; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[8:9], 1 ; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[8:9], 1
; GCN-IR-NEXT: s_or_b64 s[8:9], s[6:7], s[2:3] ; GCN-IR-NEXT: s_or_b64 s[8:9], s[6:7], s[2:3]
; GCN-IR-NEXT: .LBB0_5: ; %udiv-end ; GCN-IR-NEXT: .LBB0_5: ; %udiv-end
; GCN-IR-NEXT: v_mov_b32_e32 v0, s8 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s8
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_mov_b32 s2, -1
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; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
; ;
; GCN-IR-LABEL: v_test_udiv_i64: ; GCN-IR-LABEL: v_test_udiv_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v2 ; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v2
; GCN-IR-NEXT: v_add_i32_e64 v4, s[6:7], 32, v4 ; GCN-IR-NEXT: v_add_i32_e64 v4, s[6:7], 32, v4
; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v3 ; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v3
; GCN-IR-NEXT: v_min_u32_e32 v8, v4, v5 ; GCN-IR-NEXT: v_min_u32_e32 v10, v4, v5
; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v0 ; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v0
; GCN-IR-NEXT: v_add_i32_e64 v4, s[6:7], 32, v4 ; GCN-IR-NEXT: v_add_i32_e64 v4, s[6:7], 32, v4
; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v1 ; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v1
; GCN-IR-NEXT: v_min_u32_e32 v9, v4, v5 ; GCN-IR-NEXT: v_min_u32_e32 v11, v4, v5
; GCN-IR-NEXT: v_sub_i32_e64 v6, s[6:7], v8, v9 ; GCN-IR-NEXT: v_sub_i32_e64 v6, s[6:7], v10, v11
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3] ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
; GCN-IR-NEXT: v_subb_u32_e64 v7, s[6:7], 0, 0, s[6:7] ; GCN-IR-NEXT: v_subb_u32_e64 v7, s[6:7], 0, 0, s[6:7]
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[6:7], 63, v[6:7] ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[6:7], 63, v[6:7]
; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[6:7] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[6:7]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v1, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v1, 0, s[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v0, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v0, 0, s[4:5]
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB1_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v6 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v6
; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v7, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v6 ; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v6
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4
; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB1_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v2 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v2
; GCN-IR-NEXT: v_lshr_b64 v[10:11], v[0:1], v10 ; GCN-IR-NEXT: v_lshr_b64 v[8:9], v[0:1], v8
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v3, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v3, vcc
; GCN-IR-NEXT: v_not_b32_e32 v0, v8 ; GCN-IR-NEXT: v_not_b32_e32 v0, v10
; GCN-IR-NEXT: v_not_b32_e32 v1, 0 ; GCN-IR-NEXT: v_not_b32_e32 v1, 0
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v9 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v11
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: .LBB1_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB1_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1 ; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5
; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6 ; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v6
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v12, v10 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v12, v8
; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v13, v11, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v13, v9, vcc
; GCN-IR-NEXT: v_or_b32_e32 v4, v8, v4 ; GCN-IR-NEXT: v_or_b32_e32 v4, v10, v4
; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v6 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v6
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
; GCN-IR-NEXT: v_or_b32_e32 v5, v9, v5 ; GCN-IR-NEXT: v_or_b32_e32 v5, v11, v5
; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v8 ; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v10
; GCN-IR-NEXT: v_and_b32_e32 v9, v8, v3 ; GCN-IR-NEXT: v_and_b32_e32 v11, v10, v3
; GCN-IR-NEXT: v_and_b32_e32 v8, v8, v2 ; GCN-IR-NEXT: v_and_b32_e32 v10, v10, v2
; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v8 ; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v10
; GCN-IR-NEXT: v_subb_u32_e64 v11, s[4:5], v11, v9, s[4:5] ; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], v9, v11, s[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v9, v7 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v7
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v8, v6 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v6
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execnz .LBB1_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB1_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: .LBB1_5: ; %Flow4 ; GCN-IR-NEXT: .LBB1_5: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[4:5], 1
; GCN-IR-NEXT: v_or_b32_e32 v4, v7, v1 ; GCN-IR-NEXT: v_or_b32_e32 v4, v7, v1
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; GCN-IR-NEXT: s_or_b64 s[6:7], s[4:5], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[6:7], s[4:5], s[6:7]
; GCN-IR-NEXT: s_flbit_i32_b32 s4, s2 ; GCN-IR-NEXT: s_flbit_i32_b32 s4, s2
; GCN-IR-NEXT: s_add_i32 s4, s4, 32 ; GCN-IR-NEXT: s_add_i32 s4, s4, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s5, s3 ; GCN-IR-NEXT: s_flbit_i32_b32 s5, s3
; GCN-IR-NEXT: s_min_u32 s10, s4, s5 ; GCN-IR-NEXT: s_min_u32 s10, s4, s5
; GCN-IR-NEXT: s_flbit_i32_b32 s4, s8 ; GCN-IR-NEXT: s_flbit_i32_b32 s4, s8
; GCN-IR-NEXT: s_add_i32 s4, s4, 32 ; GCN-IR-NEXT: s_add_i32 s4, s4, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s5, s9 ; GCN-IR-NEXT: s_flbit_i32_b32 s5, s9
; GCN-IR-NEXT: s_min_u32 s14, s4, s5 ; GCN-IR-NEXT: s_min_u32 s16, s4, s5
; GCN-IR-NEXT: s_sub_u32 s12, s10, s14 ; GCN-IR-NEXT: s_sub_u32 s12, s10, s16
; GCN-IR-NEXT: s_subb_u32 s13, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s13, 0, 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[16:17], s[12:13], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[14:15], s[12:13], 63
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[18:19], s[12:13], 63 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[18:19], s[12:13], 63
; GCN-IR-NEXT: s_or_b64 s[16:17], s[6:7], s[16:17] ; GCN-IR-NEXT: s_or_b64 s[14:15], s[6:7], s[14:15]
; GCN-IR-NEXT: s_and_b64 s[6:7], s[16:17], exec ; GCN-IR-NEXT: s_and_b64 s[6:7], s[14:15], exec
; GCN-IR-NEXT: s_cselect_b32 s7, 0, s9 ; GCN-IR-NEXT: s_cselect_b32 s7, 0, s9
; GCN-IR-NEXT: s_cselect_b32 s6, 0, s8 ; GCN-IR-NEXT: s_cselect_b32 s6, 0, s8
; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19] ; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[18:19]
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0 ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[16:17] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[14:15]
; GCN-IR-NEXT: s_cbranch_vccz .LBB7_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB7_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s16, s12, 1 ; GCN-IR-NEXT: s_add_u32 s14, s12, 1
; GCN-IR-NEXT: s_addc_u32 s17, s13, 0 ; GCN-IR-NEXT: s_addc_u32 s15, s13, 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[16:17], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[14:15], 0
; GCN-IR-NEXT: s_sub_i32 s12, 63, s12 ; GCN-IR-NEXT: s_sub_i32 s12, 63, s12
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[6:7] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[6:7]
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[8:9], s12 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[8:9], s12
; GCN-IR-NEXT: s_cbranch_vccz .LBB7_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB7_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[12:13], s[8:9], s16 ; GCN-IR-NEXT: s_lshr_b64 s[12:13], s[8:9], s14
; GCN-IR-NEXT: s_add_u32 s15, s2, -1 ; GCN-IR-NEXT: s_add_u32 s14, s2, -1
; GCN-IR-NEXT: s_addc_u32 s16, s3, -1 ; GCN-IR-NEXT: s_addc_u32 s15, s3, -1
; GCN-IR-NEXT: s_not_b64 s[4:5], s[10:11] ; GCN-IR-NEXT: s_not_b64 s[4:5], s[10:11]
; GCN-IR-NEXT: s_add_u32 s8, s4, s14 ; GCN-IR-NEXT: s_add_u32 s8, s4, s16
; GCN-IR-NEXT: s_addc_u32 s9, s5, 0 ; GCN-IR-NEXT: s_addc_u32 s9, s5, 0
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: s_mov_b32 s5, 0 ; GCN-IR-NEXT: s_mov_b32 s5, 0
; GCN-IR-NEXT: .LBB7_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB7_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1 ; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1
; GCN-IR-NEXT: s_lshr_b32 s4, s7, 31 ; GCN-IR-NEXT: s_lshr_b32 s4, s7, 31
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[4:5] ; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[4:5]
; GCN-IR-NEXT: s_or_b64 s[6:7], s[10:11], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[6:7], s[10:11], s[6:7]
; GCN-IR-NEXT: s_sub_u32 s4, s15, s12 ; GCN-IR-NEXT: s_sub_u32 s4, s14, s12
; GCN-IR-NEXT: s_subb_u32 s4, s16, s13 ; GCN-IR-NEXT: s_subb_u32 s4, s15, s13
; GCN-IR-NEXT: s_ashr_i32 s10, s4, 31 ; GCN-IR-NEXT: s_ashr_i32 s10, s4, 31
; GCN-IR-NEXT: s_mov_b32 s11, s10 ; GCN-IR-NEXT: s_mov_b32 s11, s10
; GCN-IR-NEXT: s_and_b32 s4, s10, 1 ; GCN-IR-NEXT: s_and_b32 s4, s10, 1
; GCN-IR-NEXT: s_and_b64 s[10:11], s[10:11], s[2:3] ; GCN-IR-NEXT: s_and_b64 s[10:11], s[10:11], s[2:3]
; GCN-IR-NEXT: s_sub_u32 s12, s12, s10 ; GCN-IR-NEXT: s_sub_u32 s12, s12, s10
; GCN-IR-NEXT: s_subb_u32 s13, s13, s11 ; GCN-IR-NEXT: s_subb_u32 s13, s13, s11
; GCN-IR-NEXT: s_add_u32 s8, s8, 1 ; GCN-IR-NEXT: s_add_u32 s8, s8, 1
; GCN-IR-NEXT: s_addc_u32 s9, s9, 0 ; GCN-IR-NEXT: s_addc_u32 s9, s9, 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[18:19], s[8:9], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[16:17], s[8:9], 0
; GCN-IR-NEXT: s_mov_b64 s[10:11], s[4:5] ; GCN-IR-NEXT: s_mov_b64 s[10:11], s[4:5]
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[18:19] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[16:17]
; GCN-IR-NEXT: s_cbranch_vccz .LBB7_3 ; GCN-IR-NEXT: s_cbranch_vccz .LBB7_3
; GCN-IR-NEXT: .LBB7_4: ; %Flow4 ; GCN-IR-NEXT: .LBB7_4: ; %Flow4
; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[6:7], 1 ; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[6:7], 1
; GCN-IR-NEXT: s_or_b64 s[6:7], s[4:5], s[2:3] ; GCN-IR-NEXT: s_or_b64 s[6:7], s[4:5], s[2:3]
; GCN-IR-NEXT: .LBB7_5: ; %udiv-end ; GCN-IR-NEXT: .LBB7_5: ; %udiv-end
; GCN-IR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_mov_b32 s2, -1
▲ Show 20 Lines • Show All 119 Lines • ▼ Show 20 Lines
; GCN-IR-LABEL: s_test_udiv_k_num_i64: ; GCN-IR-LABEL: s_test_udiv_k_num_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0 ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_flbit_i32_b32 s8, s2 ; GCN-IR-NEXT: s_flbit_i32_b32 s8, s2
; GCN-IR-NEXT: s_flbit_i32_b32 s9, s3 ; GCN-IR-NEXT: s_flbit_i32_b32 s9, s3
; GCN-IR-NEXT: s_add_i32 s8, s8, 32 ; GCN-IR-NEXT: s_add_i32 s8, s8, 32
; GCN-IR-NEXT: s_min_u32 s8, s8, s9 ; GCN-IR-NEXT: s_min_u32 s12, s8, s9
; GCN-IR-NEXT: s_add_u32 s10, s8, 0xffffffc5 ; GCN-IR-NEXT: s_add_u32 s8, s12, 0xffffffc5
; GCN-IR-NEXT: s_addc_u32 s11, 0, -1 ; GCN-IR-NEXT: s_addc_u32 s9, 0, -1
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[2:3], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[2:3], 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[12:13], s[10:11], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[10:11], s[8:9], 63
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[14:15], s[10:11], 63 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[14:15], s[8:9], 63
; GCN-IR-NEXT: s_or_b64 s[12:13], s[6:7], s[12:13] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[6:7], s[10:11]
; GCN-IR-NEXT: s_and_b64 s[6:7], s[12:13], exec ; GCN-IR-NEXT: s_and_b64 s[6:7], s[10:11], exec
; GCN-IR-NEXT: s_cselect_b32 s6, 0, 24 ; GCN-IR-NEXT: s_cselect_b32 s6, 0, 24
; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[14:15] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[14:15]
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[12:13] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11]
; GCN-IR-NEXT: s_mov_b32 s7, 0 ; GCN-IR-NEXT: s_mov_b32 s7, 0
; GCN-IR-NEXT: s_cbranch_vccz .LBB8_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB8_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s12, s10, 1 ; GCN-IR-NEXT: s_add_u32 s10, s8, 1
; GCN-IR-NEXT: s_addc_u32 s13, s11, 0 ; GCN-IR-NEXT: s_addc_u32 s11, s9, 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[12:13], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[10:11], 0
; GCN-IR-NEXT: s_sub_i32 s9, 63, s10 ; GCN-IR-NEXT: s_sub_i32 s8, 63, s8
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[6:7] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[6:7]
; GCN-IR-NEXT: s_lshl_b64 s[6:7], 24, s9 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], 24, s8
; GCN-IR-NEXT: s_cbranch_vccz .LBB8_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB8_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[10:11], 24, s12 ; GCN-IR-NEXT: s_lshr_b64 s[10:11], 24, s10
; GCN-IR-NEXT: s_add_u32 s14, s2, -1 ; GCN-IR-NEXT: s_add_u32 s14, s2, -1
; GCN-IR-NEXT: s_addc_u32 s15, s3, -1 ; GCN-IR-NEXT: s_addc_u32 s15, s3, -1
; GCN-IR-NEXT: s_sub_u32 s8, 58, s8 ; GCN-IR-NEXT: s_sub_u32 s8, 58, s12
; GCN-IR-NEXT: s_subb_u32 s9, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s9, 0, 0
; GCN-IR-NEXT: s_mov_b64 s[12:13], 0 ; GCN-IR-NEXT: s_mov_b64 s[12:13], 0
; GCN-IR-NEXT: s_mov_b32 s5, 0 ; GCN-IR-NEXT: s_mov_b32 s5, 0
; GCN-IR-NEXT: .LBB8_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB8_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
; GCN-IR-NEXT: s_lshr_b32 s4, s7, 31 ; GCN-IR-NEXT: s_lshr_b32 s4, s7, 31
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
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; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
; ;
; GCN-IR-LABEL: v_test_udiv_pow2_k_num_i64: ; GCN-IR-LABEL: v_test_udiv_pow2_k_num_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0 ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0
; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 32, v2 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 32, v2
; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
; GCN-IR-NEXT: v_min_u32_e32 v6, v2, v3 ; GCN-IR-NEXT: v_min_u32_e32 v10, v2, v3
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 0xffffffd0, v6 ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 0xffffffd0, v10
; GCN-IR-NEXT: v_addc_u32_e64 v5, s[6:7], 0, -1, vcc ; GCN-IR-NEXT: v_addc_u32_e64 v5, s[6:7], 0, -1, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[4:5] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0x8000 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0x8000
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v3, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v3, 0, s[4:5]
; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1
; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v2, 0
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0x8000 ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0x8000
; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB9_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB9_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v4 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v4
; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v5, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[7:8] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[8:9], v2 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[8:9], v2
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB9_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB9_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0x8000 ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0x8000
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc
; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[4:5], v7 ; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[4:5], v6
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 47, v6 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 47, v10
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_subb_u32_e64 v7, s[4:5], 0, 0, vcc ; GCN-IR-NEXT: v_subb_u32_e64 v7, s[4:5], 0, 0, vcc
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 ; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
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; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
; ;
; GCN-IR-LABEL: v_test_udiv_pow2_k_den_i64: ; GCN-IR-LABEL: v_test_udiv_pow2_k_den_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0 ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0
; GCN-IR-NEXT: v_add_i32_e64 v2, s[4:5], 32, v2 ; GCN-IR-NEXT: v_add_i32_e64 v2, s[4:5], 32, v2
; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
; GCN-IR-NEXT: v_min_u32_e32 v6, v2, v3 ; GCN-IR-NEXT: v_min_u32_e32 v8, v2, v3
; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 48, v6 ; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 48, v8
; GCN-IR-NEXT: v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5] ; GCN-IR-NEXT: v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5]
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[4:5] ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[4:5]
; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v1, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v1, 0, s[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5]
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB10_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB10_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v4 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v4
; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v5, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[7:8] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB10_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB10_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_lshr_b64 v[7:8], v[0:1], v7 ; GCN-IR-NEXT: v_lshr_b64 v[6:7], v[0:1], v6
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffcf, v6 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffcf, v8
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
; GCN-IR-NEXT: v_addc_u32_e64 v1, s[4:5], 0, -1, vcc ; GCN-IR-NEXT: v_addc_u32_e64 v1, s[4:5], 0, -1, vcc
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff ; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff
; GCN-IR-NEXT: .LBB10_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB10_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1 ; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
; GCN-IR-NEXT: v_or_b32_e32 v6, v7, v4 ; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v4
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s12, v6 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s12, v6
; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v8, vcc
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_ashrrev_i32_e32 v7, 31, v4 ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
; GCN-IR-NEXT: v_or_b32_e32 v2, v8, v2
; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v4
; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v7 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v8
; GCN-IR-NEXT: v_and_b32_e32 v7, 0x8000, v7 ; GCN-IR-NEXT: v_and_b32_e32 v8, 0x8000, v8
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
; GCN-IR-NEXT: v_or_b32_e32 v3, v10, v3 ; GCN-IR-NEXT: v_or_b32_e32 v3, v9, v3
; GCN-IR-NEXT: v_or_b32_e32 v2, v9, v2 ; GCN-IR-NEXT: v_sub_i32_e64 v6, s[4:5], v6, v8
; GCN-IR-NEXT: v_sub_i32_e64 v7, s[4:5], v6, v7 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v5
; GCN-IR-NEXT: v_mov_b32_e32 v10, v5 ; GCN-IR-NEXT: v_subbrev_u32_e64 v7, s[4:5], 0, v7, s[4:5]
; GCN-IR-NEXT: v_subbrev_u32_e64 v8, s[4:5], 0, v8, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v9, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v8, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execnz .LBB10_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB10_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: .LBB10_5: ; %Flow4 ; GCN-IR-NEXT: .LBB10_5: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1
; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v1 ; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v1
▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 Lines
; ;
; GCN-IR-LABEL: s_test_udiv_k_den_i64: ; GCN-IR-LABEL: s_test_udiv_k_den_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_flbit_i32_b32 s6, s2 ; GCN-IR-NEXT: s_flbit_i32_b32 s6, s2
; GCN-IR-NEXT: s_flbit_i32_b32 s7, s3 ; GCN-IR-NEXT: s_flbit_i32_b32 s7, s3
; GCN-IR-NEXT: s_add_i32 s6, s6, 32 ; GCN-IR-NEXT: s_add_i32 s6, s6, 32
; GCN-IR-NEXT: s_min_u32 s10, s6, s7 ; GCN-IR-NEXT: s_min_u32 s12, s6, s7
; GCN-IR-NEXT: s_sub_u32 s8, 59, s10 ; GCN-IR-NEXT: s_sub_u32 s8, 59, s12
; GCN-IR-NEXT: s_subb_u32 s9, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s9, 0, 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], s[2:3], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], s[2:3], 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[6:7], s[8:9], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[6:7], s[8:9], 63
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[8:9], 63 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[8:9], 63
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
; GCN-IR-NEXT: s_and_b64 s[6:7], s[4:5], exec ; GCN-IR-NEXT: s_and_b64 s[6:7], s[4:5], exec
; GCN-IR-NEXT: s_cselect_b32 s7, 0, s3 ; GCN-IR-NEXT: s_cselect_b32 s7, 0, s3
; GCN-IR-NEXT: s_cselect_b32 s6, 0, s2 ; GCN-IR-NEXT: s_cselect_b32 s6, 0, s2
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[12:13] ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[10:11]
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[4:5] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[4:5]
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0 ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0
; GCN-IR-NEXT: s_cbranch_vccz .LBB11_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB11_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s12, s8, 1 ; GCN-IR-NEXT: s_add_u32 s10, s8, 1
; GCN-IR-NEXT: s_addc_u32 s13, s9, 0 ; GCN-IR-NEXT: s_addc_u32 s11, s9, 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[12:13], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[10:11], 0
; GCN-IR-NEXT: s_sub_i32 s8, 63, s8 ; GCN-IR-NEXT: s_sub_i32 s8, 63, s8
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[6:7] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[6:7]
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[2:3], s8 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[2:3], s8
; GCN-IR-NEXT: s_cbranch_vccz .LBB11_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB11_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[8:9], s[2:3], s12 ; GCN-IR-NEXT: s_lshr_b64 s[8:9], s[2:3], s10
; GCN-IR-NEXT: s_add_u32 s2, s10, 0xffffffc4 ; GCN-IR-NEXT: s_add_u32 s2, s12, 0xffffffc4
; GCN-IR-NEXT: s_addc_u32 s3, 0, -1 ; GCN-IR-NEXT: s_addc_u32 s3, 0, -1
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: s_mov_b32 s5, 0 ; GCN-IR-NEXT: s_mov_b32 s5, 0
; GCN-IR-NEXT: .LBB11_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB11_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1
; GCN-IR-NEXT: s_lshr_b32 s4, s7, 31 ; GCN-IR-NEXT: s_lshr_b32 s4, s7, 31
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
▲ Show 20 Lines • Show All 126 Lines • ▼ Show 20 Lines
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
; ;
; GCN-IR-LABEL: v_test_udiv_k_den_i64: ; GCN-IR-LABEL: v_test_udiv_k_den_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0 ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0
; GCN-IR-NEXT: v_add_i32_e64 v2, s[4:5], 32, v2 ; GCN-IR-NEXT: v_add_i32_e64 v2, s[4:5], 32, v2
; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
; GCN-IR-NEXT: v_min_u32_e32 v6, v2, v3 ; GCN-IR-NEXT: v_min_u32_e32 v8, v2, v3
; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 59, v6 ; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 59, v8
; GCN-IR-NEXT: v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5] ; GCN-IR-NEXT: v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5]
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[4:5] ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[4:5]
; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v1, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v1, 0, s[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5]
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB12_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB12_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v4 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v4
; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v5, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[7:8] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB12_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB12_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_lshr_b64 v[7:8], v[0:1], v7 ; GCN-IR-NEXT: v_lshr_b64 v[6:7], v[0:1], v6
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc4, v6 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc4, v8
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
; GCN-IR-NEXT: v_addc_u32_e64 v1, s[4:5], 0, -1, vcc ; GCN-IR-NEXT: v_addc_u32_e64 v1, s[4:5], 0, -1, vcc
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: .LBB12_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB12_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1 ; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
; GCN-IR-NEXT: v_or_b32_e32 v6, v7, v4 ; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v4
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 23, v6 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 23, v6
; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v8, vcc
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_ashrrev_i32_e32 v7, 31, v4 ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 1, v0
; GCN-IR-NEXT: v_or_b32_e32 v2, v8, v2
; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v4
; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v7 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v8
; GCN-IR-NEXT: v_and_b32_e32 v7, 24, v7 ; GCN-IR-NEXT: v_and_b32_e32 v8, 24, v8
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
; GCN-IR-NEXT: v_or_b32_e32 v3, v10, v3 ; GCN-IR-NEXT: v_or_b32_e32 v3, v9, v3
; GCN-IR-NEXT: v_or_b32_e32 v2, v9, v2 ; GCN-IR-NEXT: v_sub_i32_e64 v6, s[4:5], v6, v8
; GCN-IR-NEXT: v_sub_i32_e64 v7, s[4:5], v6, v7 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v5
; GCN-IR-NEXT: v_mov_b32_e32 v10, v5 ; GCN-IR-NEXT: v_subbrev_u32_e64 v7, s[4:5], 0, v7, s[4:5]
; GCN-IR-NEXT: v_subbrev_u32_e64 v8, s[4:5], 0, v8, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v9, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v8, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execnz .LBB12_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB12_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: .LBB12_5: ; %Flow4 ; GCN-IR-NEXT: .LBB12_5: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1
; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v1 ; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v1
▲ Show 20 Lines • Show All 213 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/urem64.ll

Show First 20 Lines • Show All 129 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: s_flbit_i32_b32 s10, s4 ; GCN-IR-NEXT: s_flbit_i32_b32 s10, s4
; GCN-IR-NEXT: s_or_b64 s[8:9], s[6:7], s[8:9] ; GCN-IR-NEXT: s_or_b64 s[8:9], s[6:7], s[8:9]
; GCN-IR-NEXT: s_flbit_i32_b32 s6, s2 ; GCN-IR-NEXT: s_flbit_i32_b32 s6, s2
; GCN-IR-NEXT: s_flbit_i32_b32 s11, s5 ; GCN-IR-NEXT: s_flbit_i32_b32 s11, s5
; GCN-IR-NEXT: s_add_i32 s10, s10, 32 ; GCN-IR-NEXT: s_add_i32 s10, s10, 32
; GCN-IR-NEXT: s_add_i32 s6, s6, 32 ; GCN-IR-NEXT: s_add_i32 s6, s6, 32
; GCN-IR-NEXT: s_flbit_i32_b32 s7, s3 ; GCN-IR-NEXT: s_flbit_i32_b32 s7, s3
; GCN-IR-NEXT: s_min_u32 s10, s10, s11 ; GCN-IR-NEXT: s_min_u32 s10, s10, s11
; GCN-IR-NEXT: s_min_u32 s14, s6, s7 ; GCN-IR-NEXT: s_min_u32 s18, s6, s7
; GCN-IR-NEXT: s_sub_u32 s12, s10, s14 ; GCN-IR-NEXT: s_sub_u32 s12, s10, s18
; GCN-IR-NEXT: s_subb_u32 s13, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s13, 0, 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[16:17], s[12:13], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[14:15], s[12:13], 63
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[18:19], s[12:13], 63 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[16:17], s[12:13], 63
; GCN-IR-NEXT: s_or_b64 s[16:17], s[8:9], s[16:17] ; GCN-IR-NEXT: s_or_b64 s[14:15], s[8:9], s[14:15]
; GCN-IR-NEXT: s_and_b64 s[8:9], s[16:17], exec ; GCN-IR-NEXT: s_and_b64 s[8:9], s[14:15], exec
; GCN-IR-NEXT: s_cselect_b32 s9, 0, s3 ; GCN-IR-NEXT: s_cselect_b32 s9, 0, s3
; GCN-IR-NEXT: s_cselect_b32 s8, 0, s2 ; GCN-IR-NEXT: s_cselect_b32 s8, 0, s2
; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19] ; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17]
; GCN-IR-NEXT: s_mov_b64 s[6:7], 0 ; GCN-IR-NEXT: s_mov_b64 s[6:7], 0
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[16:17] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[14:15]
; GCN-IR-NEXT: s_mov_b32 s11, 0 ; GCN-IR-NEXT: s_mov_b32 s11, 0
; GCN-IR-NEXT: s_cbranch_vccz .LBB0_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s16, s12, 1 ; GCN-IR-NEXT: s_add_u32 s14, s12, 1
; GCN-IR-NEXT: s_addc_u32 s17, s13, 0 ; GCN-IR-NEXT: s_addc_u32 s15, s13, 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[16:17], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[14:15], 0
; GCN-IR-NEXT: s_sub_i32 s12, 63, s12 ; GCN-IR-NEXT: s_sub_i32 s12, 63, s12
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[8:9] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[8:9]
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[2:3], s12 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[2:3], s12
; GCN-IR-NEXT: s_cbranch_vccz .LBB0_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[12:13], s[2:3], s16 ; GCN-IR-NEXT: s_lshr_b64 s[12:13], s[2:3], s14
; GCN-IR-NEXT: s_add_u32 s16, s4, -1 ; GCN-IR-NEXT: s_add_u32 s16, s4, -1
; GCN-IR-NEXT: s_addc_u32 s17, s5, -1 ; GCN-IR-NEXT: s_addc_u32 s17, s5, -1
; GCN-IR-NEXT: s_not_b64 s[6:7], s[10:11] ; GCN-IR-NEXT: s_not_b64 s[6:7], s[10:11]
; GCN-IR-NEXT: s_add_u32 s10, s6, s14 ; GCN-IR-NEXT: s_add_u32 s10, s6, s18
; GCN-IR-NEXT: s_addc_u32 s11, s7, 0 ; GCN-IR-NEXT: s_addc_u32 s11, s7, 0
; GCN-IR-NEXT: s_mov_b64 s[14:15], 0 ; GCN-IR-NEXT: s_mov_b64 s[14:15], 0
; GCN-IR-NEXT: s_mov_b32 s7, 0 ; GCN-IR-NEXT: s_mov_b32 s7, 0
; GCN-IR-NEXT: .LBB0_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB0_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1 ; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1
; GCN-IR-NEXT: s_lshr_b32 s6, s9, 31 ; GCN-IR-NEXT: s_lshr_b32 s6, s9, 31
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1
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; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
; ;
; GCN-IR-LABEL: v_test_urem_i64: ; GCN-IR-LABEL: v_test_urem_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v2 ; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v2
; GCN-IR-NEXT: v_add_i32_e64 v4, s[6:7], 32, v4 ; GCN-IR-NEXT: v_add_i32_e64 v4, s[6:7], 32, v4
; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v3 ; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v3
; GCN-IR-NEXT: v_min_u32_e32 v8, v4, v5 ; GCN-IR-NEXT: v_min_u32_e32 v12, v4, v5
; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v0 ; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v0
; GCN-IR-NEXT: v_add_i32_e64 v4, s[6:7], 32, v4 ; GCN-IR-NEXT: v_add_i32_e64 v4, s[6:7], 32, v4
; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v1 ; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v1
; GCN-IR-NEXT: v_min_u32_e32 v9, v4, v5 ; GCN-IR-NEXT: v_min_u32_e32 v13, v4, v5
; GCN-IR-NEXT: v_sub_i32_e64 v5, s[6:7], v8, v9 ; GCN-IR-NEXT: v_sub_i32_e64 v4, s[6:7], v12, v13
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3] ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
; GCN-IR-NEXT: v_subb_u32_e64 v6, s[6:7], 0, 0, s[6:7] ; GCN-IR-NEXT: v_subb_u32_e64 v5, s[6:7], 0, 0, s[6:7]
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[6:7], 63, v[5:6] ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[6:7], 63, v[4:5]
; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[5:6] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
; GCN-IR-NEXT: v_cndmask_b32_e64 v7, v1, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v7, v1, 0, s[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v0, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v0, 0, s[4:5]
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB1_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v5 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4
; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v6, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v5 ; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v4
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4
; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB1_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, -1, v2 ; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, -1, v2
; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, -1, v3, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, -1, v3, vcc
; GCN-IR-NEXT: v_not_b32_e32 v7, v8 ; GCN-IR-NEXT: v_not_b32_e32 v7, v12
; GCN-IR-NEXT: v_lshr_b64 v[10:11], v[0:1], v10 ; GCN-IR-NEXT: v_lshr_b64 v[10:11], v[0:1], v8
; GCN-IR-NEXT: v_not_b32_e32 v6, 0 ; GCN-IR-NEXT: v_not_b32_e32 v6, 0
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, v7, v9 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, v7, v13
; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v6, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v6, vcc
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v13, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v13, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: .LBB1_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB1_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1 ; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1
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; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execnz .LBB1_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB1_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: .LBB1_5: ; %Flow4 ; GCN-IR-NEXT: .LBB1_5: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v5 ; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v5
; GCN-IR-NEXT: v_or_b32_e32 v4, v6, v4 ; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v4
; GCN-IR-NEXT: .LBB1_6: ; %Flow5 ; GCN-IR-NEXT: .LBB1_6: ; %Flow5
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_mul_lo_u32 v5, v2, v7 ; GCN-IR-NEXT: v_mul_lo_u32 v4, v2, v7
; GCN-IR-NEXT: v_mul_hi_u32 v6, v2, v4 ; GCN-IR-NEXT: v_mul_hi_u32 v5, v2, v6
; GCN-IR-NEXT: v_mul_lo_u32 v3, v3, v4 ; GCN-IR-NEXT: v_mul_lo_u32 v3, v3, v6
; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, v4 ; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, v6
; GCN-IR-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v5, v3 ; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v4, v3
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
; GCN-IR-NEXT: s_setpc_b64 s[30:31] ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = urem i64 %x, %y %result = urem i64 %x, %y
ret i64 %result ret i64 %result
} }
define amdgpu_kernel void @s_test_urem31_i64(ptr addrspace(1) %out, i64 %x, i64 %y) { define amdgpu_kernel void @s_test_urem31_i64(ptr addrspace(1) %out, i64 %x, i64 %y) {
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; GCN-IR-LABEL: s_test_urem_k_num_i64: ; GCN-IR-LABEL: s_test_urem_k_num_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0 ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_flbit_i32_b32 s8, s2 ; GCN-IR-NEXT: s_flbit_i32_b32 s8, s2
; GCN-IR-NEXT: s_flbit_i32_b32 s9, s3 ; GCN-IR-NEXT: s_flbit_i32_b32 s9, s3
; GCN-IR-NEXT: s_add_i32 s8, s8, 32 ; GCN-IR-NEXT: s_add_i32 s8, s8, 32
; GCN-IR-NEXT: s_min_u32 s8, s8, s9 ; GCN-IR-NEXT: s_min_u32 s12, s8, s9
; GCN-IR-NEXT: s_add_u32 s10, s8, 0xffffffc5 ; GCN-IR-NEXT: s_add_u32 s8, s12, 0xffffffc5
; GCN-IR-NEXT: s_addc_u32 s11, 0, -1 ; GCN-IR-NEXT: s_addc_u32 s9, 0, -1
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[2:3], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[2:3], 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[12:13], s[10:11], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[10:11], s[8:9], 63
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[14:15], s[10:11], 63 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[14:15], s[8:9], 63
; GCN-IR-NEXT: s_or_b64 s[12:13], s[6:7], s[12:13] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[6:7], s[10:11]
; GCN-IR-NEXT: s_and_b64 s[6:7], s[12:13], exec ; GCN-IR-NEXT: s_and_b64 s[6:7], s[10:11], exec
; GCN-IR-NEXT: s_cselect_b32 s6, 0, 24 ; GCN-IR-NEXT: s_cselect_b32 s6, 0, 24
; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[14:15] ; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[14:15]
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[12:13] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11]
; GCN-IR-NEXT: s_mov_b32 s7, 0 ; GCN-IR-NEXT: s_mov_b32 s7, 0
; GCN-IR-NEXT: s_cbranch_vccz .LBB6_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB6_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s12, s10, 1 ; GCN-IR-NEXT: s_add_u32 s10, s8, 1
; GCN-IR-NEXT: s_addc_u32 s13, s11, 0 ; GCN-IR-NEXT: s_addc_u32 s11, s9, 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[12:13], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[10:11], 0
; GCN-IR-NEXT: s_sub_i32 s9, 63, s10 ; GCN-IR-NEXT: s_sub_i32 s8, 63, s8
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[6:7] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[6:7]
; GCN-IR-NEXT: s_lshl_b64 s[6:7], 24, s9 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], 24, s8
; GCN-IR-NEXT: s_cbranch_vccz .LBB6_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB6_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[10:11], 24, s12 ; GCN-IR-NEXT: s_lshr_b64 s[10:11], 24, s10
; GCN-IR-NEXT: s_add_u32 s14, s2, -1 ; GCN-IR-NEXT: s_add_u32 s14, s2, -1
; GCN-IR-NEXT: s_addc_u32 s15, s3, -1 ; GCN-IR-NEXT: s_addc_u32 s15, s3, -1
; GCN-IR-NEXT: s_sub_u32 s8, 58, s8 ; GCN-IR-NEXT: s_sub_u32 s8, 58, s12
; GCN-IR-NEXT: s_subb_u32 s9, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s9, 0, 0
; GCN-IR-NEXT: s_mov_b64 s[12:13], 0 ; GCN-IR-NEXT: s_mov_b64 s[12:13], 0
; GCN-IR-NEXT: s_mov_b32 s5, 0 ; GCN-IR-NEXT: s_mov_b32 s5, 0
; GCN-IR-NEXT: .LBB6_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB6_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
; GCN-IR-NEXT: s_lshr_b32 s4, s7, 31 ; GCN-IR-NEXT: s_lshr_b32 s4, s7, 31
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
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; ;
; GCN-IR-LABEL: s_test_urem_k_den_i64: ; GCN-IR-LABEL: s_test_urem_k_den_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
; GCN-IR-NEXT: s_flbit_i32_b32 s6, s2 ; GCN-IR-NEXT: s_flbit_i32_b32 s6, s2
; GCN-IR-NEXT: s_flbit_i32_b32 s7, s3 ; GCN-IR-NEXT: s_flbit_i32_b32 s7, s3
; GCN-IR-NEXT: s_add_i32 s6, s6, 32 ; GCN-IR-NEXT: s_add_i32 s6, s6, 32
; GCN-IR-NEXT: s_min_u32 s8, s6, s7 ; GCN-IR-NEXT: s_min_u32 s12, s6, s7
; GCN-IR-NEXT: s_sub_u32 s10, 59, s8 ; GCN-IR-NEXT: s_sub_u32 s8, 59, s12
; GCN-IR-NEXT: s_subb_u32 s11, 0, 0 ; GCN-IR-NEXT: s_subb_u32 s9, 0, 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], s[2:3], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], s[2:3], 0
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[6:7], s[10:11], 63 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[6:7], s[8:9], 63
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[10:11], 63 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[8:9], 63
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
; GCN-IR-NEXT: s_and_b64 s[6:7], s[4:5], exec ; GCN-IR-NEXT: s_and_b64 s[6:7], s[4:5], exec
; GCN-IR-NEXT: s_cselect_b32 s7, 0, s3 ; GCN-IR-NEXT: s_cselect_b32 s7, 0, s3
; GCN-IR-NEXT: s_cselect_b32 s6, 0, s2 ; GCN-IR-NEXT: s_cselect_b32 s6, 0, s2
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[12:13] ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[10:11]
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[4:5] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[4:5]
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0 ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0
; GCN-IR-NEXT: s_cbranch_vccz .LBB7_5 ; GCN-IR-NEXT: s_cbranch_vccz .LBB7_5
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: s_add_u32 s12, s10, 1 ; GCN-IR-NEXT: s_add_u32 s10, s8, 1
; GCN-IR-NEXT: s_addc_u32 s13, s11, 0 ; GCN-IR-NEXT: s_addc_u32 s11, s9, 0
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[12:13], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[10:11], 0
; GCN-IR-NEXT: s_sub_i32 s9, 63, s10 ; GCN-IR-NEXT: s_sub_i32 s8, 63, s8
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[6:7] ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[6:7]
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[2:3], s9 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[2:3], s8
; GCN-IR-NEXT: s_cbranch_vccz .LBB7_4 ; GCN-IR-NEXT: s_cbranch_vccz .LBB7_4
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: s_lshr_b64 s[10:11], s[2:3], s12 ; GCN-IR-NEXT: s_lshr_b64 s[10:11], s[2:3], s10
; GCN-IR-NEXT: s_add_u32 s8, s8, 0xffffffc4 ; GCN-IR-NEXT: s_add_u32 s8, s12, 0xffffffc4
; GCN-IR-NEXT: s_addc_u32 s9, 0, -1 ; GCN-IR-NEXT: s_addc_u32 s9, 0, -1
; GCN-IR-NEXT: s_mov_b64 s[12:13], 0 ; GCN-IR-NEXT: s_mov_b64 s[12:13], 0
; GCN-IR-NEXT: s_mov_b32 s5, 0 ; GCN-IR-NEXT: s_mov_b32 s5, 0
; GCN-IR-NEXT: .LBB7_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB7_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
; GCN-IR-NEXT: s_lshr_b32 s4, s7, 31 ; GCN-IR-NEXT: s_lshr_b32 s4, s7, 31
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
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; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
; ;
; GCN-IR-LABEL: v_test_urem_pow2_k_num_i64: ; GCN-IR-LABEL: v_test_urem_pow2_k_num_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0 ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0
; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 32, v2 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 32, v2
; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
; GCN-IR-NEXT: v_min_u32_e32 v6, v2, v3 ; GCN-IR-NEXT: v_min_u32_e32 v10, v2, v3
; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, 0xffffffd0, v6 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 0xffffffd0, v10
; GCN-IR-NEXT: v_addc_u32_e64 v4, s[6:7], 0, -1, vcc ; GCN-IR-NEXT: v_addc_u32_e64 v3, s[6:7], 0, -1, vcc
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[3:4] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[2:3]
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0x8000 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0x8000
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[3:4] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[2:3]
; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v5, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[4:5]
; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1
; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0x8000 ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0x8000
; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB8_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB8_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v3 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v2
; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v4, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v3, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v3 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[7:8] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[8:9], v2 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[8:9], v2
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB8_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB8_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0x8000 ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0x8000
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc
; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[4:5], v7 ; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[4:5], v6
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 47, v6 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 47, v10
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_subb_u32_e64 v7, s[4:5], 0, 0, vcc ; GCN-IR-NEXT: v_subb_u32_e64 v7, s[4:5], 0, 0, vcc
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: .LBB8_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB8_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 ; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
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; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
; GCN-IR-NEXT: v_mov_b32_e32 v10, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: s_cbranch_execnz .LBB8_3 ; GCN-IR-NEXT: s_cbranch_execnz .LBB8_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: .LBB8_5: ; %Flow4 ; GCN-IR-NEXT: .LBB8_5: ; %Flow4
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v7 ; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3
; GCN-IR-NEXT: v_or_b32_e32 v5, v4, v6 ; GCN-IR-NEXT: v_or_b32_e32 v4, v4, v2
; GCN-IR-NEXT: .LBB8_6: ; %Flow5 ; GCN-IR-NEXT: .LBB8_6: ; %Flow5
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
; GCN-IR-NEXT: v_mul_lo_u32 v2, v0, v2 ; GCN-IR-NEXT: v_mul_lo_u32 v2, v0, v5
; GCN-IR-NEXT: v_mul_hi_u32 v3, v0, v5 ; GCN-IR-NEXT: v_mul_hi_u32 v3, v0, v4
; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v5 ; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v4
; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, v5 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, v4
; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1
; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 0x8000, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 0x8000, v0
; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc
; GCN-IR-NEXT: s_setpc_b64 s[30:31] ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
%result = urem i64 32768, %x %result = urem i64 32768, %x
ret i64 %result ret i64 %result
} }
define i64 @v_test_urem_pow2_k_den_i64(i64 %x) { define i64 @v_test_urem_pow2_k_den_i64(i64 %x) {
; GCN-LABEL: v_test_urem_pow2_k_den_i64: ; GCN-LABEL: v_test_urem_pow2_k_den_i64:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_and_b32_e32 v0, 0x7fff, v0 ; GCN-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
; ;
; GCN-IR-LABEL: v_test_urem_pow2_k_den_i64: ; GCN-IR-LABEL: v_test_urem_pow2_k_den_i64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0 ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0
; GCN-IR-NEXT: v_add_i32_e64 v2, s[4:5], 32, v2 ; GCN-IR-NEXT: v_add_i32_e64 v2, s[4:5], 32, v2
; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
; GCN-IR-NEXT: v_min_u32_e32 v6, v2, v3 ; GCN-IR-NEXT: v_min_u32_e32 v10, v2, v3
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 48, v6 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 48, v10
; GCN-IR-NEXT: v_subb_u32_e64 v3, s[4:5], 0, 0, s[4:5] ; GCN-IR-NEXT: v_subb_u32_e64 v3, s[4:5], 0, 0, s[4:5]
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[2:3] ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[2:3]
; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[2:3] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[2:3]
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v1, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v1, 0, s[4:5]
; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v0, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v0, 0, s[4:5]
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB9_6 ; GCN-IR-NEXT: s_cbranch_execz .LBB9_6
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v2 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v2
; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v3, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v3, vcc
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[7:8] ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz .LBB9_5 ; GCN-IR-NEXT: s_cbranch_execz .LBB9_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_lshr_b64 v[8:9], v[0:1], v7 ; GCN-IR-NEXT: v_lshr_b64 v[8:9], v[0:1], v6
; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 0xffffffcf, v6 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 0xffffffcf, v10
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_addc_u32_e64 v7, s[4:5], 0, -1, vcc ; GCN-IR-NEXT: v_addc_u32_e64 v7, s[4:5], 0, -1, vcc
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff ; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff
; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while ; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
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