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Differential D152807

[AMDGPU][GFX11] Add test coverage for 16-bit conversions, part 6.
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Authored by kosarev on Jun 13 2023, 5:36 AM.

Details

Reviewers
arsenm
Joe_Nash
rampitec
foad
Commits
rGc2887096f30d: [AMDGPU][GFX11] Add test coverage for 16-bit conversions, part 6.

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Event Timeline

kosarev created this revision.Jun 13 2023, 5:36 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 13 2023, 5:36 AM
Herald added subscribers: StephenFan, kerbowa, tpr and 4 others. · View Herald Transcript
kosarev requested review of this revision.Jun 13 2023, 5:36 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 13 2023, 5:36 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
Harbormaster completed remote builds in B238467: Diff 530874.Jun 13 2023, 5:37 AM
kosarev updated this revision to Diff 530962.Jun 13 2023, 10:03 AM

Removed unused prefixes.

Harbormaster completed remote builds in B238536: Diff 530962.Jun 13 2023, 10:06 AM
kosarev updated this revision to Diff 531282.Jun 14 2023, 5:40 AM

Removed converted manual tests. Rebased on top of
https://reviews.llvm.org/rG1f615b502c6897e291b4ac79bb28e4f2644d6ab5.

Joe_Nash accepted this revision.Jun 14 2023, 6:41 AM
This revision is now accepted and ready to land.Jun 14 2023, 6:41 AM
Harbormaster completed remote builds in B238768: Diff 531282.Jun 14 2023, 6:44 AM
This revision was landed with ongoing or failed builds.Jun 15 2023, 2:39 AM
Closed by commit rGc2887096f30d: [AMDGPU][GFX11] Add test coverage for 16-bit conversions, part 6. (authored by kosarev). · Explain Why
This revision was automatically updated to reflect the committed changes.
kosarev added a commit: rGc2887096f30d: [AMDGPU][GFX11] Add test coverage for 16-bit conversions, part 6..

Revision Contents

PathSize
llvm/
test/
CodeGen/
AMDGPU/
934 lines
934 lines
755 lines
306 lines

Diff 531665

llvm/test/CodeGen/AMDGPU/llvm.log.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -global-isel=0 -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI,GCN-SDAG,SI-SDAG %s ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GFX689,SI,GFX689-SDAG,SI-SDAG %s
; RUN: llc -global-isel=1 -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI,GCN-GISEL,SI-GISEL %s ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GFX689,SI,GFX689-GISEL,SI-GISEL %s
; RUN: llc -global-isel=0 -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI,GCN-SDAG,VI-SDAG %s ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GFX689,VI,GFX689-SDAG,VI-SDAG %s
; RUN: llc -global-isel=1 -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI,GCN-GISEL,VI-GISEL %s ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GFX689,VI,GFX689-GISEL,VI-GISEL %s
; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-SDAG,GFX900-SDAG %s ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX689,GFX900,GFX689-SDAG,GFX900-SDAG %s
; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-GISEL,GFX900-GISEL %s ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX689,GFX900,GFX689-GISEL,GFX900-GISEL %s
; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-SDAG %s
; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s ; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
define amdgpu_kernel void @s_log_f32(ptr addrspace(1) %out, float %in) { define amdgpu_kernel void @s_log_f32(ptr addrspace(1) %out, float %in) {
; SI-LABEL: s_log_f32: ; SI-LABEL: s_log_f32:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dword s2, s[0:1], 0xb ; SI-NEXT: s_load_dword s2, s[0:1], 0xb
Show All 35 Lines
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-GISEL-NEXT: v_log_f32_e32 v0, s2 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, s2
; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[0:1] ; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[0:1]
; GFX900-GISEL-NEXT: s_endpgm ; GFX900-GISEL-NEXT: s_endpgm
; ;
; GFX1100-SDAG-LABEL: s_log_f32:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_clause 0x1
; GFX1100-SDAG-NEXT: s_load_b32 s2, s[0:1], 0x2c
; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, s2
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mul_f32 v0, 0x3f317218, v0
; GFX1100-SDAG-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX1100-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX1100-SDAG-NEXT: s_endpgm
;
; GFX1100-GISEL-LABEL: s_log_f32:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_clause 0x1
; GFX1100-GISEL-NEXT: s_load_b32 s2, s[0:1], 0x2c
; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
; GFX1100-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, s2
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX1100-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log_f32: ; R600-LABEL: s_log_f32:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[] ; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4: ; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: LOG_IEEE * T0.X, KC0[2].Z, ; R600-NEXT: LOG_IEEE * T0.X, KC0[2].Z,
▲ Show 20 Lines • Show All 97 Lines • ▼ Show 20 Lines
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-GISEL-NEXT: v_log_f32_e32 v0, s2 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, s2
; GFX900-GISEL-NEXT: v_log_f32_e32 v1, s3 ; GFX900-GISEL-NEXT: v_log_f32_e32 v1, s3
; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317218, v1 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317218, v1
; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX900-GISEL-NEXT: s_endpgm ; GFX900-GISEL-NEXT: s_endpgm
; ;
; GFX1100-SDAG-LABEL: s_log_v2f32:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, s3
; GFX1100-SDAG-NEXT: v_log_f32_e32 v2, s2
; GFX1100-SDAG-NEXT: v_mov_b32_e32 v3, 0
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_dual_mul_f32 v1, 0x3f317218, v0 :: v_dual_mul_f32 v0, 0x3f317218, v2
; GFX1100-SDAG-NEXT: global_store_b64 v3, v[0:1], s[0:1]
; GFX1100-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX1100-SDAG-NEXT: s_endpgm
;
; GFX1100-GISEL-LABEL: s_log_v2f32:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
; GFX1100-GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, s2
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, s3
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_dual_mul_f32 v0, 0x3f317218, v0 :: v_dual_mul_f32 v1, 0x3f317218, v1
; GFX1100-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1100-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log_v2f32: ; R600-LABEL: s_log_v2f32:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: ALU 6, @4, KC0[CB0:0-32], KC1[] ; R600-NEXT: ALU 6, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4: ; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: LOG_IEEE * T0.X, KC0[3].X, ; R600-NEXT: LOG_IEEE * T0.X, KC0[3].X,
▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
; GFX900-GISEL-NEXT: v_log_f32_e32 v1, s5 ; GFX900-GISEL-NEXT: v_log_f32_e32 v1, s5
; GFX900-GISEL-NEXT: v_log_f32_e32 v2, s6 ; GFX900-GISEL-NEXT: v_log_f32_e32 v2, s6
; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317218, v1 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317218, v1
; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317218, v2 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317218, v2
; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1] ; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
; GFX900-GISEL-NEXT: s_endpgm ; GFX900-GISEL-NEXT: s_endpgm
; ;
; GFX1100-SDAG-LABEL: s_log_v3f32:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_clause 0x1
; GFX1100-SDAG-NEXT: s_load_b128 s[4:7], s[0:1], 0x34
; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, s6
; GFX1100-SDAG-NEXT: v_log_f32_e32 v1, s5
; GFX1100-SDAG-NEXT: v_log_f32_e32 v3, s4
; GFX1100-SDAG-NEXT: v_mov_b32_e32 v4, 0
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_dual_mul_f32 v2, 0x3f317218, v0 :: v_dual_mul_f32 v1, 0x3f317218, v1
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v3
; GFX1100-SDAG-NEXT: global_store_b96 v4, v[0:2], s[0:1]
; GFX1100-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX1100-SDAG-NEXT: s_endpgm
;
; GFX1100-GISEL-LABEL: s_log_v3f32:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_clause 0x1
; GFX1100-GISEL-NEXT: s_load_b128 s[4:7], s[0:1], 0x34
; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
; GFX1100-GISEL-NEXT: v_mov_b32_e32 v3, 0
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, s4
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, s5
; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, s6
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_dual_mul_f32 v0, 0x3f317218, v0 :: v_dual_mul_f32 v1, 0x3f317218, v1
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317218, v2
; GFX1100-GISEL-NEXT: global_store_b96 v3, v[0:2], s[0:1]
; GFX1100-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log_v3f32: ; R600-LABEL: s_log_v3f32:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: ALU 13, @4, KC0[CB0:0-32], KC1[] ; R600-NEXT: ALU 13, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.X, T2.X, 0 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.X, T2.X, 0
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: ALU clause starting at 4: ; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: LOG_IEEE * T0.X, KC0[3].Z, ; R600-NEXT: LOG_IEEE * T0.X, KC0[3].Z,
▲ Show 20 Lines • Show All 150 Lines • ▼ Show 20 Lines
; GFX900-GISEL-NEXT: v_log_f32_e32 v3, s7 ; GFX900-GISEL-NEXT: v_log_f32_e32 v3, s7
; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317218, v1 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317218, v1
; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317218, v2 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317218, v2
; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, 0x3f317218, v3 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, 0x3f317218, v3
; GFX900-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] ; GFX900-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
; GFX900-GISEL-NEXT: s_endpgm ; GFX900-GISEL-NEXT: s_endpgm
; ;
; GFX1100-SDAG-LABEL: s_log_v4f32:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_clause 0x1
; GFX1100-SDAG-NEXT: s_load_b128 s[4:7], s[0:1], 0x34
; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, s7
; GFX1100-SDAG-NEXT: v_log_f32_e32 v1, s6
; GFX1100-SDAG-NEXT: v_log_f32_e32 v4, s5
; GFX1100-SDAG-NEXT: v_log_f32_e32 v5, s4
; GFX1100-SDAG-NEXT: v_dual_mov_b32 v6, 0 :: v_dual_mul_f32 v3, 0x3f317218, v0
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_dual_mul_f32 v2, 0x3f317218, v1 :: v_dual_mul_f32 v1, 0x3f317218, v4
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v5
; GFX1100-SDAG-NEXT: global_store_b128 v6, v[0:3], s[0:1]
; GFX1100-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX1100-SDAG-NEXT: s_endpgm
;
; GFX1100-GISEL-LABEL: s_log_v4f32:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_clause 0x1
; GFX1100-GISEL-NEXT: s_load_b128 s[4:7], s[0:1], 0x34
; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
; GFX1100-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, s4
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, s5
; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, s6
; GFX1100-GISEL-NEXT: v_log_f32_e32 v3, s7
; GFX1100-GISEL-NEXT: s_delay_alu instid0(TRANS32_DEP_3)
; GFX1100-GISEL-NEXT: v_dual_mul_f32 v0, 0x3f317218, v0 :: v_dual_mul_f32 v1, 0x3f317218, v1
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_dual_mul_f32 v2, 0x3f317218, v2 :: v_dual_mul_f32 v3, 0x3f317218, v3
; GFX1100-GISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX1100-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log_v4f32: ; R600-LABEL: s_log_v4f32:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[] ; R600-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4: ; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: LOG_IEEE * T0.X, KC0[4].X, ; R600-NEXT: LOG_IEEE * T0.X, KC0[4].X,
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; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, ; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%result = call <4 x float> @llvm.log.v4f32(<4 x float> %in) %result = call <4 x float> @llvm.log.v4f32(<4 x float> %in)
store <4 x float> %result, ptr addrspace(1) %out store <4 x float> %result, ptr addrspace(1) %out
ret void ret void
} }
define float @v_log_f32(float %in) { define float @v_log_f32(float %in) {
; GCN-LABEL: v_log_f32: ; GFX689-LABEL: v_log_f32:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log_f32:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_f32: ; R600-LABEL: v_log_f32:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f32: ; CM-LABEL: v_log_f32:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call float @llvm.log.f32(float %in) %result = call float @llvm.log.f32(float %in)
ret float %result ret float %result
} }
define float @v_log_fabs_f32(float %in) { define float @v_log_fabs_f32(float %in) {
; GCN-LABEL: v_log_fabs_f32: ; GFX689-LABEL: v_log_fabs_f32:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e64 v0, |v0| ; GFX689-NEXT: v_log_f32_e64 v0, |v0|
; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log_fabs_f32:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e64 v0, |v0|
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_fabs_f32: ; R600-LABEL: v_log_fabs_f32:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_fabs_f32: ; CM-LABEL: v_log_fabs_f32:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%fabs = call float @llvm.fabs.f32(float %in) %fabs = call float @llvm.fabs.f32(float %in)
%result = call float @llvm.log.f32(float %fabs) %result = call float @llvm.log.f32(float %fabs)
ret float %result ret float %result
} }
define float @v_log_fneg_fabs_f32(float %in) { define float @v_log_fneg_fabs_f32(float %in) {
; GCN-LABEL: v_log_fneg_fabs_f32: ; GFX689-LABEL: v_log_fneg_fabs_f32:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e64 v0, -|v0| ; GFX689-NEXT: v_log_f32_e64 v0, -|v0|
; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log_fneg_fabs_f32:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e64 v0, -|v0|
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_fneg_fabs_f32: ; R600-LABEL: v_log_fneg_fabs_f32:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_fneg_fabs_f32: ; CM-LABEL: v_log_fneg_fabs_f32:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%fabs = call float @llvm.fabs.f32(float %in) %fabs = call float @llvm.fabs.f32(float %in)
%fneg.fabs = fneg float %fabs %fneg.fabs = fneg float %fabs
%result = call float @llvm.log.f32(float %fneg.fabs) %result = call float @llvm.log.f32(float %fneg.fabs)
ret float %result ret float %result
} }
define float @v_log_fneg_f32(float %in) { define float @v_log_fneg_f32(float %in) {
; GCN-LABEL: v_log_fneg_f32: ; GFX689-LABEL: v_log_fneg_f32:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e64 v0, -v0 ; GFX689-NEXT: v_log_f32_e64 v0, -v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log_fneg_f32:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e64 v0, -v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_fneg_f32: ; R600-LABEL: v_log_fneg_f32:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_fneg_f32: ; CM-LABEL: v_log_fneg_f32:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%fneg = fneg float %in %fneg = fneg float %in
%result = call float @llvm.log.f32(float %fneg) %result = call float @llvm.log.f32(float %fneg)
ret float %result ret float %result
} }
define float @v_log_f32_fast(float %in) { define float @v_log_f32_fast(float %in) {
; GCN-LABEL: v_log_f32_fast: ; GFX689-LABEL: v_log_f32_fast:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log_f32_fast:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_f32_fast: ; R600-LABEL: v_log_f32_fast:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f32_fast: ; CM-LABEL: v_log_f32_fast:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call fast float @llvm.log.f32(float %in) %result = call fast float @llvm.log.f32(float %in)
ret float %result ret float %result
} }
define float @v_log_f32_unsafe_math_attr(float %in) "unsafe-fp-math"="true" { define float @v_log_f32_unsafe_math_attr(float %in) "unsafe-fp-math"="true" {
; GCN-LABEL: v_log_f32_unsafe_math_attr: ; GFX689-LABEL: v_log_f32_unsafe_math_attr:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log_f32_unsafe_math_attr:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_f32_unsafe_math_attr: ; R600-LABEL: v_log_f32_unsafe_math_attr:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f32_unsafe_math_attr: ; CM-LABEL: v_log_f32_unsafe_math_attr:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call float @llvm.log.f32(float %in) %result = call float @llvm.log.f32(float %in)
ret float %result ret float %result
} }
define float @v_log_f32_approx_fn_attr(float %in) "approx-func-fp-math"="true" { define float @v_log_f32_approx_fn_attr(float %in) "approx-func-fp-math"="true" {
; GCN-LABEL: v_log_f32_approx_fn_attr: ; GFX689-LABEL: v_log_f32_approx_fn_attr:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log_f32_approx_fn_attr:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_f32_approx_fn_attr: ; R600-LABEL: v_log_f32_approx_fn_attr:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f32_approx_fn_attr: ; CM-LABEL: v_log_f32_approx_fn_attr:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call float @llvm.log.f32(float %in) %result = call float @llvm.log.f32(float %in)
ret float %result ret float %result
} }
define float @v_log_f32_ninf(float %in) { define float @v_log_f32_ninf(float %in) {
; GCN-LABEL: v_log_f32_ninf: ; GFX689-LABEL: v_log_f32_ninf:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log_f32_ninf:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_f32_ninf: ; R600-LABEL: v_log_f32_ninf:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f32_ninf: ; CM-LABEL: v_log_f32_ninf:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call ninf float @llvm.log.f32(float %in) %result = call ninf float @llvm.log.f32(float %in)
ret float %result ret float %result
} }
define float @v_log_f32_afn(float %in) { define float @v_log_f32_afn(float %in) {
; GCN-LABEL: v_log_f32_afn: ; GFX689-LABEL: v_log_f32_afn:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log_f32_afn:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_f32_afn: ; R600-LABEL: v_log_f32_afn:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f32_afn: ; CM-LABEL: v_log_f32_afn:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call afn float @llvm.log.f32(float %in) %result = call afn float @llvm.log.f32(float %in)
ret float %result ret float %result
} }
define float @v_log_f32_afn_daz(float %in) #0 { define float @v_log_f32_afn_daz(float %in) #0 {
; GCN-LABEL: v_log_f32_afn_daz: ; GFX689-LABEL: v_log_f32_afn_daz:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log_f32_afn_daz:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_f32_afn_daz: ; R600-LABEL: v_log_f32_afn_daz:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f32_afn_daz: ; CM-LABEL: v_log_f32_afn_daz:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call afn float @llvm.log.f32(float %in) %result = call afn float @llvm.log.f32(float %in)
ret float %result ret float %result
} }
define float @v_log_f32_afn_dynamic(float %in) #1 { define float @v_log_f32_afn_dynamic(float %in) #1 {
; GCN-LABEL: v_log_f32_afn_dynamic: ; GFX689-LABEL: v_log_f32_afn_dynamic:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log_f32_afn_dynamic:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_f32_afn_dynamic: ; R600-LABEL: v_log_f32_afn_dynamic:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f32_afn_dynamic: ; CM-LABEL: v_log_f32_afn_dynamic:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call afn float @llvm.log.f32(float %in) %result = call afn float @llvm.log.f32(float %in)
ret float %result ret float %result
} }
define float @v_fabs_log_f32_afn(float %in) { define float @v_fabs_log_f32_afn(float %in) {
; GCN-LABEL: v_fabs_log_f32_afn: ; GFX689-LABEL: v_fabs_log_f32_afn:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e64 v0, |v0| ; GFX689-NEXT: v_log_f32_e64 v0, |v0|
; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_fabs_log_f32_afn:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e64 v0, |v0|
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_fabs_log_f32_afn: ; R600-LABEL: v_fabs_log_f32_afn:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_fabs_log_f32_afn: ; CM-LABEL: v_fabs_log_f32_afn:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%fabs = call float @llvm.fabs.f32(float %in) %fabs = call float @llvm.fabs.f32(float %in)
%result = call afn float @llvm.log.f32(float %fabs) %result = call afn float @llvm.log.f32(float %fabs)
ret float %result ret float %result
} }
define float @v_log_f32_daz(float %in) #0 { define float @v_log_f32_daz(float %in) #0 {
; GCN-LABEL: v_log_f32_daz: ; GFX689-LABEL: v_log_f32_daz:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log_f32_daz:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_f32_daz: ; R600-LABEL: v_log_f32_daz:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f32_daz: ; CM-LABEL: v_log_f32_daz:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call float @llvm.log.f32(float %in) %result = call float @llvm.log.f32(float %in)
ret float %result ret float %result
} }
define float @v_log_f32_nnan(float %in) { define float @v_log_f32_nnan(float %in) {
; GCN-LABEL: v_log_f32_nnan: ; GFX689-LABEL: v_log_f32_nnan:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log_f32_nnan:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_f32_nnan: ; R600-LABEL: v_log_f32_nnan:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f32_nnan: ; CM-LABEL: v_log_f32_nnan:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call nnan float @llvm.log.f32(float %in) %result = call nnan float @llvm.log.f32(float %in)
ret float %result ret float %result
} }
define float @v_log_f32_nnan_daz(float %in) #0 { define float @v_log_f32_nnan_daz(float %in) #0 {
; GCN-LABEL: v_log_f32_nnan_daz: ; GFX689-LABEL: v_log_f32_nnan_daz:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log_f32_nnan_daz:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_f32_nnan_daz: ; R600-LABEL: v_log_f32_nnan_daz:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f32_nnan_daz: ; CM-LABEL: v_log_f32_nnan_daz:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call nnan float @llvm.log.f32(float %in) %result = call nnan float @llvm.log.f32(float %in)
ret float %result ret float %result
} }
define float @v_log_f32_nnan_dynamic(float %in) #1 { define float @v_log_f32_nnan_dynamic(float %in) #1 {
; GCN-LABEL: v_log_f32_nnan_dynamic: ; GFX689-LABEL: v_log_f32_nnan_dynamic:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log_f32_nnan_dynamic:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_f32_nnan_dynamic: ; R600-LABEL: v_log_f32_nnan_dynamic:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f32_nnan_dynamic: ; CM-LABEL: v_log_f32_nnan_dynamic:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call nnan float @llvm.log.f32(float %in) %result = call nnan float @llvm.log.f32(float %in)
ret float %result ret float %result
} }
define float @v_log_f32_ninf_daz(float %in) #0 { define float @v_log_f32_ninf_daz(float %in) #0 {
; GCN-LABEL: v_log_f32_ninf_daz: ; GFX689-LABEL: v_log_f32_ninf_daz:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log_f32_ninf_daz:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_f32_ninf_daz: ; R600-LABEL: v_log_f32_ninf_daz:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f32_ninf_daz: ; CM-LABEL: v_log_f32_ninf_daz:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call ninf float @llvm.log.f32(float %in) %result = call ninf float @llvm.log.f32(float %in)
ret float %result ret float %result
} }
define float @v_log_f32_ninf_dynamic(float %in) #1 { define float @v_log_f32_ninf_dynamic(float %in) #1 {
; GCN-LABEL: v_log_f32_ninf_dynamic: ; GFX689-LABEL: v_log_f32_ninf_dynamic:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log_f32_ninf_dynamic:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_f32_ninf_dynamic: ; R600-LABEL: v_log_f32_ninf_dynamic:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f32_ninf_dynamic: ; CM-LABEL: v_log_f32_ninf_dynamic:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call ninf float @llvm.log.f32(float %in) %result = call ninf float @llvm.log.f32(float %in)
ret float %result ret float %result
} }
define float @v_log_f32_nnan_ninf(float %in) { define float @v_log_f32_nnan_ninf(float %in) {
; GCN-LABEL: v_log_f32_nnan_ninf: ; GFX689-LABEL: v_log_f32_nnan_ninf:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log_f32_nnan_ninf:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_f32_nnan_ninf: ; R600-LABEL: v_log_f32_nnan_ninf:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f32_nnan_ninf: ; CM-LABEL: v_log_f32_nnan_ninf:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call nnan ninf float @llvm.log.f32(float %in) %result = call nnan ninf float @llvm.log.f32(float %in)
ret float %result ret float %result
} }
define float @v_log_f32_nnan_ninf_daz(float %in) #0 { define float @v_log_f32_nnan_ninf_daz(float %in) #0 {
; GCN-LABEL: v_log_f32_nnan_ninf_daz: ; GFX689-LABEL: v_log_f32_nnan_ninf_daz:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log_f32_nnan_ninf_daz:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_f32_nnan_ninf_daz: ; R600-LABEL: v_log_f32_nnan_ninf_daz:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f32_nnan_ninf_daz: ; CM-LABEL: v_log_f32_nnan_ninf_daz:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call nnan ninf float @llvm.log.f32(float %in) %result = call nnan ninf float @llvm.log.f32(float %in)
ret float %result ret float %result
} }
define float @v_log_f32_nnan_ninf_dynamic(float %in) #1 { define float @v_log_f32_nnan_ninf_dynamic(float %in) #1 {
; GCN-LABEL: v_log_f32_nnan_ninf_dynamic: ; GFX689-LABEL: v_log_f32_nnan_ninf_dynamic:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log_f32_nnan_ninf_dynamic:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_f32_nnan_ninf_dynamic: ; R600-LABEL: v_log_f32_nnan_ninf_dynamic:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f32_nnan_ninf_dynamic: ; CM-LABEL: v_log_f32_nnan_ninf_dynamic:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call nnan ninf float @llvm.log.f32(float %in) %result = call nnan ninf float @llvm.log.f32(float %in)
ret float %result ret float %result
} }
define float @v_log_f32_fast_daz(float %in) #0 { define float @v_log_f32_fast_daz(float %in) #0 {
; GCN-LABEL: v_log_f32_fast_daz: ; GFX689-LABEL: v_log_f32_fast_daz:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log_f32_fast_daz:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_f32_fast_daz: ; R600-LABEL: v_log_f32_fast_daz:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f32_fast_daz: ; CM-LABEL: v_log_f32_fast_daz:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call fast float @llvm.log.f32(float %in) %result = call fast float @llvm.log.f32(float %in)
ret float %result ret float %result
} }
define float @v_log_f32_dynamic_mode(float %in) #1 { define float @v_log_f32_dynamic_mode(float %in) #1 {
; GCN-LABEL: v_log_f32_dynamic_mode: ; GFX689-LABEL: v_log_f32_dynamic_mode:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log_f32_dynamic_mode:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_f32_dynamic_mode: ; R600-LABEL: v_log_f32_dynamic_mode:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f32_dynamic_mode: ; CM-LABEL: v_log_f32_dynamic_mode:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call float @llvm.log.f32(float %in) %result = call float @llvm.log.f32(float %in)
ret float %result ret float %result
} }
define float @v_log_f32_undef() { define float @v_log_f32_undef() {
; GCN-LABEL: v_log_f32_undef: ; GFX689-LABEL: v_log_f32_undef:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, s4 ; GFX689-NEXT: v_log_f32_e32 v0, s4
; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log_f32_undef:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, s0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_f32_undef: ; R600-LABEL: v_log_f32_undef:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f32_undef: ; CM-LABEL: v_log_f32_undef:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call float @llvm.log.f32(float undef) %result = call float @llvm.log.f32(float undef)
ret float %result ret float %result
} }
define float @v_log_f32_0() { define float @v_log_f32_0() {
; GCN-SDAG-LABEL: v_log_f32_0: ; GFX689-SDAG-LABEL: v_log_f32_0:
; GCN-SDAG: ; %bb.0: ; GFX689-SDAG: ; %bb.0:
; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-SDAG-NEXT: v_log_f32_e32 v0, 0 ; GFX689-SDAG-NEXT: v_log_f32_e32 v0, 0
; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX689-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] ; GFX689-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GCN-GISEL-LABEL: v_log_f32_0: ; GFX689-GISEL-LABEL: v_log_f32_0:
; GCN-GISEL: ; %bb.0: ; GFX689-GISEL: ; %bb.0:
; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-GISEL-NEXT: v_mov_b32_e32 v0, 0x3f317218 ; GFX689-GISEL-NEXT: v_mov_b32_e32 v0, 0x3f317218
; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0xff800000, v0 ; GFX689-GISEL-NEXT: v_mul_f32_e32 v0, 0xff800000, v0
; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX689-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-LABEL: v_log_f32_0:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, 0
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-LABEL: v_log_f32_0:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-GISEL-NEXT: v_mov_b32_e32 v0, 0x3f317218
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, 0xff800000, v0
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_f32_0: ; R600-LABEL: v_log_f32_0:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f32_0: ; CM-LABEL: v_log_f32_0:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call float @llvm.log.f32(float 0.0) %result = call float @llvm.log.f32(float 0.0)
ret float %result ret float %result
} }
define float @v_log_f32_from_fpext_f16(i16 %src.i) { define float @v_log_f32_from_fpext_f16(i16 %src.i) {
; GCN-LABEL: v_log_f32_from_fpext_f16: ; GFX689-LABEL: v_log_f32_from_fpext_f16:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX689-NEXT: v_cvt_f32_f16_e32 v0, v0
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log_f32_from_fpext_f16:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_f32_from_fpext_f16: ; R600-LABEL: v_log_f32_from_fpext_f16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f32_from_fpext_f16: ; CM-LABEL: v_log_f32_from_fpext_f16:
; CM: ; %bb.0: ; CM: ; %bb.0:
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; GFX900: ; %bb.0: ; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_add_f16_e32 v0, v0, v1 ; GFX900-NEXT: v_add_f16_e32 v0, v0, v1
; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX900-NEXT: v_log_f32_e32 v0, v0 ; GFX900-NEXT: v_log_f32_e32 v0, v0
; GFX900-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX900-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX900-NEXT: s_setpc_b64 s[30:31] ; GFX900-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log_f32_from_fpext_math_f16:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_add_f16_e32 v0, v0, v1
; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log_f32_from_fpext_math_f16: ; R600-LABEL: v_log_f32_from_fpext_math_f16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f32_from_fpext_math_f16: ; CM-LABEL: v_log_f32_from_fpext_math_f16:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%src0 = bitcast i16 %src0.i to half %src0 = bitcast i16 %src0.i to half
%src1 = bitcast i16 %src1.i to half %src1 = bitcast i16 %src1.i to half
%fadd = fadd half %src0, %src1 %fadd = fadd half %src0, %src1
%fpext = fpext half %fadd to float %fpext = fpext half %fadd to float
%result = call float @llvm.log.f32(float %fpext) %result = call float @llvm.log.f32(float %fpext)
ret float %result ret float %result
} }
define float @v_log_f32_from_fpext_bf16(bfloat %src) { define float @v_log_f32_from_fpext_bf16(bfloat %src) {
; GCN-SDAG-LABEL: v_log_f32_from_fpext_bf16: ; GFX689-SDAG-LABEL: v_log_f32_from_fpext_bf16:
; GCN-SDAG: ; %bb.0: ; GFX689-SDAG: ; %bb.0:
; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 ; GFX689-SDAG-NEXT: v_log_f32_e32 v0, v0
; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX689-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] ; GFX689-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GCN-GISEL-LABEL: v_log_f32_from_fpext_bf16: ; GFX689-GISEL-LABEL: v_log_f32_from_fpext_bf16:
; GCN-GISEL: ; %bb.0: ; GFX689-GISEL: ; %bb.0:
; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX689-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX689-GISEL-NEXT: v_log_f32_e32 v0, v0
; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0 ; GFX689-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX689-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-LABEL: v_log_f32_from_fpext_bf16:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-LABEL: v_log_f32_from_fpext_bf16:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log_f32_from_fpext_bf16: ; R600-LABEL: v_log_f32_from_fpext_bf16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f32_from_fpext_bf16: ; CM-LABEL: v_log_f32_from_fpext_bf16:
; CM: ; %bb.0: ; CM: ; %bb.0:
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; ;
; GFX900-LABEL: v_log_f16: ; GFX900-LABEL: v_log_f16:
; GFX900: ; %bb.0: ; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_log_f16_e32 v0, v0 ; GFX900-NEXT: v_log_f16_e32 v0, v0
; GFX900-NEXT: v_mul_f16_e32 v0, 0x398c, v0 ; GFX900-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX900-NEXT: s_setpc_b64 s[30:31] ; GFX900-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log_f16:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f16_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log_f16: ; R600-LABEL: v_log_f16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f16: ; CM-LABEL: v_log_f16:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
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; ;
; GFX900-LABEL: v_log_fabs_f16: ; GFX900-LABEL: v_log_fabs_f16:
; GFX900: ; %bb.0: ; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_log_f16_e64 v0, |v0| ; GFX900-NEXT: v_log_f16_e64 v0, |v0|
; GFX900-NEXT: v_mul_f16_e32 v0, 0x398c, v0 ; GFX900-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX900-NEXT: s_setpc_b64 s[30:31] ; GFX900-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log_fabs_f16:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f16_e64 v0, |v0|
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log_fabs_f16: ; R600-LABEL: v_log_fabs_f16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_fabs_f16: ; CM-LABEL: v_log_fabs_f16:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
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; ;
; GFX900-LABEL: v_log_fneg_fabs_f16: ; GFX900-LABEL: v_log_fneg_fabs_f16:
; GFX900: ; %bb.0: ; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_log_f16_e64 v0, -|v0| ; GFX900-NEXT: v_log_f16_e64 v0, -|v0|
; GFX900-NEXT: v_mul_f16_e32 v0, 0x398c, v0 ; GFX900-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX900-NEXT: s_setpc_b64 s[30:31] ; GFX900-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log_fneg_fabs_f16:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f16_e64 v0, -|v0|
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log_fneg_fabs_f16: ; R600-LABEL: v_log_fneg_fabs_f16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_fneg_fabs_f16: ; CM-LABEL: v_log_fneg_fabs_f16:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
Show All 32 Lines
; ;
; GFX900-LABEL: v_log_fneg_f16: ; GFX900-LABEL: v_log_fneg_f16:
; GFX900: ; %bb.0: ; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_log_f16_e64 v0, -v0 ; GFX900-NEXT: v_log_f16_e64 v0, -v0
; GFX900-NEXT: v_mul_f16_e32 v0, 0x398c, v0 ; GFX900-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX900-NEXT: s_setpc_b64 s[30:31] ; GFX900-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log_fneg_f16:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f16_e64 v0, -v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log_fneg_f16: ; R600-LABEL: v_log_fneg_f16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_fneg_f16: ; CM-LABEL: v_log_fneg_f16:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
Show All 31 Lines
; ;
; GFX900-LABEL: v_log_f16_fast: ; GFX900-LABEL: v_log_f16_fast:
; GFX900: ; %bb.0: ; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_log_f16_e32 v0, v0 ; GFX900-NEXT: v_log_f16_e32 v0, v0
; GFX900-NEXT: v_mul_f16_e32 v0, 0x398c, v0 ; GFX900-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX900-NEXT: s_setpc_b64 s[30:31] ; GFX900-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log_f16_fast:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f16_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log_f16_fast: ; R600-LABEL: v_log_f16_fast:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_f16_fast: ; CM-LABEL: v_log_f16_fast:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_log_f16_e32 v1, v0 ; GFX900-NEXT: v_log_f16_e32 v1, v0
; GFX900-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX900-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX900-NEXT: v_mul_f16_e32 v1, 0x398c, v1 ; GFX900-NEXT: v_mul_f16_e32 v1, 0x398c, v1
; GFX900-NEXT: v_mul_f16_e32 v0, 0x398c, v0 ; GFX900-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX900-NEXT: v_pack_b32_f16 v0, v1, v0 ; GFX900-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX900-NEXT: s_setpc_b64 s[30:31] ; GFX900-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log_v2f16:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-NEXT: v_log_f16_e32 v0, v0
; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1100-NEXT: v_log_f16_e32 v1, v1
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-NEXT: v_mul_f16_e32 v1, 0x398c, v1
; GFX1100-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log_v2f16: ; R600-LABEL: v_log_v2f16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_v2f16: ; CM-LABEL: v_log_v2f16:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
; GFX900-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0 ; GFX900-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
; GFX900-GISEL-NEXT: v_log_f16_e32 v1, v0 ; GFX900-GISEL-NEXT: v_log_f16_e32 v1, v0
; GFX900-GISEL-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX900-GISEL-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX900-GISEL-NEXT: v_mul_f16_e32 v1, 0x398c, v1 ; GFX900-GISEL-NEXT: v_mul_f16_e32 v1, 0x398c, v1
; GFX900-GISEL-NEXT: v_mul_f16_e32 v0, 0x398c, v0 ; GFX900-GISEL-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v0 ; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-SDAG-LABEL: v_log_fabs_v2f16:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-SDAG-NEXT: v_log_f16_e64 v0, |v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_log_f16_e64 v1, |v1|
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-SDAG-NEXT: v_mul_f16_e32 v1, 0x398c, v1
; GFX1100-SDAG-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-LABEL: v_log_fabs_v2f16:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-GISEL-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-NEXT: v_log_f16_e32 v1, v1
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-GISEL-NEXT: v_mul_f16_e32 v1, 0x398c, v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log_fabs_v2f16: ; R600-LABEL: v_log_fabs_v2f16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_fabs_v2f16: ; CM-LABEL: v_log_fabs_v2f16:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines
; GFX900-GISEL-NEXT: v_or_b32_e32 v0, 0x80008000, v0 ; GFX900-GISEL-NEXT: v_or_b32_e32 v0, 0x80008000, v0
; GFX900-GISEL-NEXT: v_log_f16_e32 v1, v0 ; GFX900-GISEL-NEXT: v_log_f16_e32 v1, v0
; GFX900-GISEL-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX900-GISEL-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX900-GISEL-NEXT: v_mul_f16_e32 v1, 0x398c, v1 ; GFX900-GISEL-NEXT: v_mul_f16_e32 v1, 0x398c, v1
; GFX900-GISEL-NEXT: v_mul_f16_e32 v0, 0x398c, v0 ; GFX900-GISEL-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v0 ; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-SDAG-LABEL: v_log_fneg_fabs_v2f16:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-SDAG-NEXT: v_log_f16_e64 v0, -|v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_log_f16_e64 v1, -|v1|
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-SDAG-NEXT: v_mul_f16_e32 v1, 0x398c, v1
; GFX1100-SDAG-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-LABEL: v_log_fneg_fabs_v2f16:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-GISEL-NEXT: v_or_b32_e32 v0, 0x80008000, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-GISEL-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-NEXT: v_log_f16_e32 v1, v1
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-GISEL-NEXT: v_mul_f16_e32 v1, 0x398c, v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log_fneg_fabs_v2f16: ; R600-LABEL: v_log_fneg_fabs_v2f16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_fneg_fabs_v2f16: ; CM-LABEL: v_log_fneg_fabs_v2f16:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
; GFX900-GISEL-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 ; GFX900-GISEL-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
; GFX900-GISEL-NEXT: v_log_f16_e32 v1, v0 ; GFX900-GISEL-NEXT: v_log_f16_e32 v1, v0
; GFX900-GISEL-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX900-GISEL-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX900-GISEL-NEXT: v_mul_f16_e32 v1, 0x398c, v1 ; GFX900-GISEL-NEXT: v_mul_f16_e32 v1, 0x398c, v1
; GFX900-GISEL-NEXT: v_mul_f16_e32 v0, 0x398c, v0 ; GFX900-GISEL-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v0 ; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-SDAG-LABEL: v_log_fneg_v2f16:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-SDAG-NEXT: v_log_f16_e64 v0, -v0
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_log_f16_e64 v1, -v1
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-SDAG-NEXT: v_mul_f16_e32 v1, 0x398c, v1
; GFX1100-SDAG-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-LABEL: v_log_fneg_v2f16:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-GISEL-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-GISEL-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-NEXT: v_log_f16_e32 v1, v1
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-GISEL-NEXT: v_mul_f16_e32 v1, 0x398c, v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log_fneg_v2f16: ; R600-LABEL: v_log_fneg_v2f16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_fneg_v2f16: ; CM-LABEL: v_log_fneg_v2f16:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_log_f16_e32 v1, v0 ; GFX900-NEXT: v_log_f16_e32 v1, v0
; GFX900-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX900-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX900-NEXT: v_mul_f16_e32 v1, 0x398c, v1 ; GFX900-NEXT: v_mul_f16_e32 v1, 0x398c, v1
; GFX900-NEXT: v_mul_f16_e32 v0, 0x398c, v0 ; GFX900-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX900-NEXT: v_pack_b32_f16 v0, v1, v0 ; GFX900-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX900-NEXT: s_setpc_b64 s[30:31] ; GFX900-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log_v2f16_fast:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-NEXT: v_log_f16_e32 v0, v0
; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1100-NEXT: v_log_f16_e32 v1, v1
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f16_e32 v0, 0x398c, v0
; GFX1100-NEXT: v_mul_f16_e32 v1, 0x398c, v1
; GFX1100-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log_v2f16_fast: ; R600-LABEL: v_log_v2f16_fast:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log_v2f16_fast: ; CM-LABEL: v_log_v2f16_fast:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
Show All 18 Lines

llvm/test/CodeGen/AMDGPU/llvm.log10.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -global-isel=0 -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI,GCN-SDAG,SI-SDAG %s ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GFX689,SI,GFX689-SDAG,SI-SDAG %s
; RUN: llc -global-isel=1 -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI,GCN-GISEL,SI-GISEL %s ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GFX689,SI,GFX689-GISEL,SI-GISEL %s
; RUN: llc -global-isel=0 -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI,GCN-SDAG,VI-SDAG %s ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GFX689,VI,GFX689-SDAG,VI-SDAG %s
; RUN: llc -global-isel=1 -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI,GCN-GISEL,VI-GISEL %s ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GFX689,VI,GFX689-GISEL,VI-GISEL %s
; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-SDAG,GFX900-SDAG %s ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX689,GFX900,GFX689-SDAG,GFX900-SDAG %s
; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-GISEL,GFX900-GISEL %s ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX689,GFX900,GFX689-GISEL,GFX900-GISEL %s
; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-SDAG %s
; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s ; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
define amdgpu_kernel void @s_log10_f32(ptr addrspace(1) %out, float %in) { define amdgpu_kernel void @s_log10_f32(ptr addrspace(1) %out, float %in) {
; SI-LABEL: s_log10_f32: ; SI-LABEL: s_log10_f32:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dword s2, s[0:1], 0xb ; SI-NEXT: s_load_dword s2, s[0:1], 0xb
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; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-GISEL-NEXT: v_log_f32_e32 v0, s2 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, s2
; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[0:1] ; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[0:1]
; GFX900-GISEL-NEXT: s_endpgm ; GFX900-GISEL-NEXT: s_endpgm
; ;
; GFX1100-SDAG-LABEL: s_log10_f32:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_clause 0x1
; GFX1100-SDAG-NEXT: s_load_b32 s2, s[0:1], 0x2c
; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, s2
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mul_f32 v0, 0x3e9a209b, v0
; GFX1100-SDAG-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX1100-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX1100-SDAG-NEXT: s_endpgm
;
; GFX1100-GISEL-LABEL: s_log10_f32:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_clause 0x1
; GFX1100-GISEL-NEXT: s_load_b32 s2, s[0:1], 0x2c
; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
; GFX1100-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, s2
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX1100-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log10_f32: ; R600-LABEL: s_log10_f32:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[] ; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4: ; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: LOG_IEEE * T0.X, KC0[2].Z, ; R600-NEXT: LOG_IEEE * T0.X, KC0[2].Z,
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; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-GISEL-NEXT: v_log_f32_e32 v0, s2 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, s2
; GFX900-GISEL-NEXT: v_log_f32_e32 v1, s3 ; GFX900-GISEL-NEXT: v_log_f32_e32 v1, s3
; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v1 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v1
; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX900-GISEL-NEXT: s_endpgm ; GFX900-GISEL-NEXT: s_endpgm
; ;
; GFX1100-SDAG-LABEL: s_log10_v2f32:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, s3
; GFX1100-SDAG-NEXT: v_log_f32_e32 v2, s2
; GFX1100-SDAG-NEXT: v_mov_b32_e32 v3, 0
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_dual_mul_f32 v1, 0x3e9a209b, v0 :: v_dual_mul_f32 v0, 0x3e9a209b, v2
; GFX1100-SDAG-NEXT: global_store_b64 v3, v[0:1], s[0:1]
; GFX1100-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX1100-SDAG-NEXT: s_endpgm
;
; GFX1100-GISEL-LABEL: s_log10_v2f32:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
; GFX1100-GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, s2
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, s3
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_dual_mul_f32 v0, 0x3e9a209b, v0 :: v_dual_mul_f32 v1, 0x3e9a209b, v1
; GFX1100-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1100-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log10_v2f32: ; R600-LABEL: s_log10_v2f32:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: ALU 6, @4, KC0[CB0:0-32], KC1[] ; R600-NEXT: ALU 6, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4: ; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: LOG_IEEE * T0.X, KC0[3].X, ; R600-NEXT: LOG_IEEE * T0.X, KC0[3].X,
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; GFX900-GISEL-NEXT: v_log_f32_e32 v1, s5 ; GFX900-GISEL-NEXT: v_log_f32_e32 v1, s5
; GFX900-GISEL-NEXT: v_log_f32_e32 v2, s6 ; GFX900-GISEL-NEXT: v_log_f32_e32 v2, s6
; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v1 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v1
; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209b, v2 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209b, v2
; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1] ; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
; GFX900-GISEL-NEXT: s_endpgm ; GFX900-GISEL-NEXT: s_endpgm
; ;
; GFX1100-SDAG-LABEL: s_log10_v3f32:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_clause 0x1
; GFX1100-SDAG-NEXT: s_load_b128 s[4:7], s[0:1], 0x34
; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, s6
; GFX1100-SDAG-NEXT: v_log_f32_e32 v1, s5
; GFX1100-SDAG-NEXT: v_log_f32_e32 v3, s4
; GFX1100-SDAG-NEXT: v_mov_b32_e32 v4, 0
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_dual_mul_f32 v2, 0x3e9a209b, v0 :: v_dual_mul_f32 v1, 0x3e9a209b, v1
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v3
; GFX1100-SDAG-NEXT: global_store_b96 v4, v[0:2], s[0:1]
; GFX1100-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX1100-SDAG-NEXT: s_endpgm
;
; GFX1100-GISEL-LABEL: s_log10_v3f32:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_clause 0x1
; GFX1100-GISEL-NEXT: s_load_b128 s[4:7], s[0:1], 0x34
; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
; GFX1100-GISEL-NEXT: v_mov_b32_e32 v3, 0
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, s4
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, s5
; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, s6
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_dual_mul_f32 v0, 0x3e9a209b, v0 :: v_dual_mul_f32 v1, 0x3e9a209b, v1
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209b, v2
; GFX1100-GISEL-NEXT: global_store_b96 v3, v[0:2], s[0:1]
; GFX1100-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log10_v3f32: ; R600-LABEL: s_log10_v3f32:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: ALU 13, @4, KC0[CB0:0-32], KC1[] ; R600-NEXT: ALU 13, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.X, T2.X, 0 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.X, T2.X, 0
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: ALU clause starting at 4: ; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: LOG_IEEE * T0.X, KC0[3].Z, ; R600-NEXT: LOG_IEEE * T0.X, KC0[3].Z,
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; GFX900-GISEL-NEXT: v_log_f32_e32 v3, s7 ; GFX900-GISEL-NEXT: v_log_f32_e32 v3, s7
; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v1 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v1
; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209b, v2 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209b, v2
; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, 0x3e9a209b, v3 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, 0x3e9a209b, v3
; GFX900-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] ; GFX900-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
; GFX900-GISEL-NEXT: s_endpgm ; GFX900-GISEL-NEXT: s_endpgm
; ;
; GFX1100-SDAG-LABEL: s_log10_v4f32:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_clause 0x1
; GFX1100-SDAG-NEXT: s_load_b128 s[4:7], s[0:1], 0x34
; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, s7
; GFX1100-SDAG-NEXT: v_log_f32_e32 v1, s6
; GFX1100-SDAG-NEXT: v_log_f32_e32 v4, s5
; GFX1100-SDAG-NEXT: v_log_f32_e32 v5, s4
; GFX1100-SDAG-NEXT: v_dual_mov_b32 v6, 0 :: v_dual_mul_f32 v3, 0x3e9a209b, v0
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_dual_mul_f32 v2, 0x3e9a209b, v1 :: v_dual_mul_f32 v1, 0x3e9a209b, v4
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v5
; GFX1100-SDAG-NEXT: global_store_b128 v6, v[0:3], s[0:1]
; GFX1100-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX1100-SDAG-NEXT: s_endpgm
;
; GFX1100-GISEL-LABEL: s_log10_v4f32:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_clause 0x1
; GFX1100-GISEL-NEXT: s_load_b128 s[4:7], s[0:1], 0x34
; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
; GFX1100-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, s4
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, s5
; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, s6
; GFX1100-GISEL-NEXT: v_log_f32_e32 v3, s7
; GFX1100-GISEL-NEXT: s_delay_alu instid0(TRANS32_DEP_3)
; GFX1100-GISEL-NEXT: v_dual_mul_f32 v0, 0x3e9a209b, v0 :: v_dual_mul_f32 v1, 0x3e9a209b, v1
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_dual_mul_f32 v2, 0x3e9a209b, v2 :: v_dual_mul_f32 v3, 0x3e9a209b, v3
; GFX1100-GISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX1100-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log10_v4f32: ; R600-LABEL: s_log10_v4f32:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[] ; R600-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4: ; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: LOG_IEEE * T0.X, KC0[4].X, ; R600-NEXT: LOG_IEEE * T0.X, KC0[4].X,
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; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, ; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00) ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%result = call <4 x float> @llvm.log10.v4f32(<4 x float> %in) %result = call <4 x float> @llvm.log10.v4f32(<4 x float> %in)
store <4 x float> %result, ptr addrspace(1) %out store <4 x float> %result, ptr addrspace(1) %out
ret void ret void
} }
define float @v_log10_f32(float %in) { define float @v_log10_f32(float %in) {
; GCN-LABEL: v_log10_f32: ; GFX689-LABEL: v_log10_f32:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log10_f32:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_f32: ; R600-LABEL: v_log10_f32:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f32: ; CM-LABEL: v_log10_f32:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call float @llvm.log10.f32(float %in) %result = call float @llvm.log10.f32(float %in)
ret float %result ret float %result
} }
define float @v_log10_fabs_f32(float %in) { define float @v_log10_fabs_f32(float %in) {
; GCN-LABEL: v_log10_fabs_f32: ; GFX689-LABEL: v_log10_fabs_f32:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e64 v0, |v0| ; GFX689-NEXT: v_log_f32_e64 v0, |v0|
; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log10_fabs_f32:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e64 v0, |v0|
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_fabs_f32: ; R600-LABEL: v_log10_fabs_f32:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_fabs_f32: ; CM-LABEL: v_log10_fabs_f32:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%fabs = call float @llvm.fabs.f32(float %in) %fabs = call float @llvm.fabs.f32(float %in)
%result = call float @llvm.log10.f32(float %fabs) %result = call float @llvm.log10.f32(float %fabs)
ret float %result ret float %result
} }
define float @v_log10_fneg_fabs_f32(float %in) { define float @v_log10_fneg_fabs_f32(float %in) {
; GCN-LABEL: v_log10_fneg_fabs_f32: ; GFX689-LABEL: v_log10_fneg_fabs_f32:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e64 v0, -|v0| ; GFX689-NEXT: v_log_f32_e64 v0, -|v0|
; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log10_fneg_fabs_f32:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e64 v0, -|v0|
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_fneg_fabs_f32: ; R600-LABEL: v_log10_fneg_fabs_f32:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_fneg_fabs_f32: ; CM-LABEL: v_log10_fneg_fabs_f32:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%fabs = call float @llvm.fabs.f32(float %in) %fabs = call float @llvm.fabs.f32(float %in)
%fneg.fabs = fneg float %fabs %fneg.fabs = fneg float %fabs
%result = call float @llvm.log10.f32(float %fneg.fabs) %result = call float @llvm.log10.f32(float %fneg.fabs)
ret float %result ret float %result
} }
define float @v_log10_fneg_f32(float %in) { define float @v_log10_fneg_f32(float %in) {
; GCN-LABEL: v_log10_fneg_f32: ; GFX689-LABEL: v_log10_fneg_f32:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e64 v0, -v0 ; GFX689-NEXT: v_log_f32_e64 v0, -v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log10_fneg_f32:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e64 v0, -v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_fneg_f32: ; R600-LABEL: v_log10_fneg_f32:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_fneg_f32: ; CM-LABEL: v_log10_fneg_f32:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%fneg = fneg float %in %fneg = fneg float %in
%result = call float @llvm.log10.f32(float %fneg) %result = call float @llvm.log10.f32(float %fneg)
ret float %result ret float %result
} }
define float @v_log10_f32_fast(float %in) { define float @v_log10_f32_fast(float %in) {
; GCN-LABEL: v_log10_f32_fast: ; GFX689-LABEL: v_log10_f32_fast:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log10_f32_fast:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_f32_fast: ; R600-LABEL: v_log10_f32_fast:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f32_fast: ; CM-LABEL: v_log10_f32_fast:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call fast float @llvm.log10.f32(float %in) %result = call fast float @llvm.log10.f32(float %in)
ret float %result ret float %result
} }
define float @v_log10_f32_unsafe_math_attr(float %in) "unsafe-fp-math"="true" { define float @v_log10_f32_unsafe_math_attr(float %in) "unsafe-fp-math"="true" {
; GCN-LABEL: v_log10_f32_unsafe_math_attr: ; GFX689-LABEL: v_log10_f32_unsafe_math_attr:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log10_f32_unsafe_math_attr:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_f32_unsafe_math_attr: ; R600-LABEL: v_log10_f32_unsafe_math_attr:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f32_unsafe_math_attr: ; CM-LABEL: v_log10_f32_unsafe_math_attr:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call float @llvm.log10.f32(float %in) %result = call float @llvm.log10.f32(float %in)
ret float %result ret float %result
} }
define float @v_log10_f32_approx_fn_attr(float %in) "approx-func-fp-math"="true" { define float @v_log10_f32_approx_fn_attr(float %in) "approx-func-fp-math"="true" {
; GCN-LABEL: v_log10_f32_approx_fn_attr: ; GFX689-LABEL: v_log10_f32_approx_fn_attr:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log10_f32_approx_fn_attr:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_f32_approx_fn_attr: ; R600-LABEL: v_log10_f32_approx_fn_attr:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f32_approx_fn_attr: ; CM-LABEL: v_log10_f32_approx_fn_attr:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call float @llvm.log10.f32(float %in) %result = call float @llvm.log10.f32(float %in)
ret float %result ret float %result
} }
define float @v_log10_f32_ninf(float %in) { define float @v_log10_f32_ninf(float %in) {
; GCN-LABEL: v_log10_f32_ninf: ; GFX689-LABEL: v_log10_f32_ninf:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log10_f32_ninf:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_f32_ninf: ; R600-LABEL: v_log10_f32_ninf:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f32_ninf: ; CM-LABEL: v_log10_f32_ninf:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call ninf float @llvm.log10.f32(float %in) %result = call ninf float @llvm.log10.f32(float %in)
ret float %result ret float %result
} }
define float @v_log10_f32_afn(float %in) { define float @v_log10_f32_afn(float %in) {
; GCN-LABEL: v_log10_f32_afn: ; GFX689-LABEL: v_log10_f32_afn:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log10_f32_afn:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_f32_afn: ; R600-LABEL: v_log10_f32_afn:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f32_afn: ; CM-LABEL: v_log10_f32_afn:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call afn float @llvm.log10.f32(float %in) %result = call afn float @llvm.log10.f32(float %in)
ret float %result ret float %result
} }
define float @v_log10_f32_afn_daz(float %in) #0 { define float @v_log10_f32_afn_daz(float %in) #0 {
; GCN-LABEL: v_log10_f32_afn_daz: ; GFX689-LABEL: v_log10_f32_afn_daz:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log10_f32_afn_daz:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_f32_afn_daz: ; R600-LABEL: v_log10_f32_afn_daz:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f32_afn_daz: ; CM-LABEL: v_log10_f32_afn_daz:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call afn float @llvm.log10.f32(float %in) %result = call afn float @llvm.log10.f32(float %in)
ret float %result ret float %result
} }
define float @v_log10_f32_afn_dynamic(float %in) #1 { define float @v_log10_f32_afn_dynamic(float %in) #1 {
; GCN-LABEL: v_log10_f32_afn_dynamic: ; GFX689-LABEL: v_log10_f32_afn_dynamic:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log10_f32_afn_dynamic:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_f32_afn_dynamic: ; R600-LABEL: v_log10_f32_afn_dynamic:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f32_afn_dynamic: ; CM-LABEL: v_log10_f32_afn_dynamic:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call afn float @llvm.log10.f32(float %in) %result = call afn float @llvm.log10.f32(float %in)
ret float %result ret float %result
} }
define float @v_fabs_log10_f32_afn(float %in) { define float @v_fabs_log10_f32_afn(float %in) {
; GCN-LABEL: v_fabs_log10_f32_afn: ; GFX689-LABEL: v_fabs_log10_f32_afn:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e64 v0, |v0| ; GFX689-NEXT: v_log_f32_e64 v0, |v0|
; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_fabs_log10_f32_afn:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e64 v0, |v0|
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_fabs_log10_f32_afn: ; R600-LABEL: v_fabs_log10_f32_afn:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_fabs_log10_f32_afn: ; CM-LABEL: v_fabs_log10_f32_afn:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%fabs = call float @llvm.fabs.f32(float %in) %fabs = call float @llvm.fabs.f32(float %in)
%result = call afn float @llvm.log10.f32(float %fabs) %result = call afn float @llvm.log10.f32(float %fabs)
ret float %result ret float %result
} }
define float @v_log10_f32_daz(float %in) #0 { define float @v_log10_f32_daz(float %in) #0 {
; GCN-LABEL: v_log10_f32_daz: ; GFX689-LABEL: v_log10_f32_daz:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log10_f32_daz:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_f32_daz: ; R600-LABEL: v_log10_f32_daz:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f32_daz: ; CM-LABEL: v_log10_f32_daz:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call float @llvm.log10.f32(float %in) %result = call float @llvm.log10.f32(float %in)
ret float %result ret float %result
} }
define float @v_log10_f32_nnan(float %in) { define float @v_log10_f32_nnan(float %in) {
; GCN-LABEL: v_log10_f32_nnan: ; GFX689-LABEL: v_log10_f32_nnan:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log10_f32_nnan:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_f32_nnan: ; R600-LABEL: v_log10_f32_nnan:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f32_nnan: ; CM-LABEL: v_log10_f32_nnan:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call nnan float @llvm.log10.f32(float %in) %result = call nnan float @llvm.log10.f32(float %in)
ret float %result ret float %result
} }
define float @v_log10_f32_nnan_daz(float %in) #0 { define float @v_log10_f32_nnan_daz(float %in) #0 {
; GCN-LABEL: v_log10_f32_nnan_daz: ; GFX689-LABEL: v_log10_f32_nnan_daz:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log10_f32_nnan_daz:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_f32_nnan_daz: ; R600-LABEL: v_log10_f32_nnan_daz:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f32_nnan_daz: ; CM-LABEL: v_log10_f32_nnan_daz:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call nnan float @llvm.log10.f32(float %in) %result = call nnan float @llvm.log10.f32(float %in)
ret float %result ret float %result
} }
define float @v_log10_f32_nnan_dynamic(float %in) #1 { define float @v_log10_f32_nnan_dynamic(float %in) #1 {
; GCN-LABEL: v_log10_f32_nnan_dynamic: ; GFX689-LABEL: v_log10_f32_nnan_dynamic:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log10_f32_nnan_dynamic:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_f32_nnan_dynamic: ; R600-LABEL: v_log10_f32_nnan_dynamic:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f32_nnan_dynamic: ; CM-LABEL: v_log10_f32_nnan_dynamic:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call nnan float @llvm.log10.f32(float %in) %result = call nnan float @llvm.log10.f32(float %in)
ret float %result ret float %result
} }
define float @v_log10_f32_ninf_daz(float %in) #0 { define float @v_log10_f32_ninf_daz(float %in) #0 {
; GCN-LABEL: v_log10_f32_ninf_daz: ; GFX689-LABEL: v_log10_f32_ninf_daz:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log10_f32_ninf_daz:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_f32_ninf_daz: ; R600-LABEL: v_log10_f32_ninf_daz:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f32_ninf_daz: ; CM-LABEL: v_log10_f32_ninf_daz:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call ninf float @llvm.log10.f32(float %in) %result = call ninf float @llvm.log10.f32(float %in)
ret float %result ret float %result
} }
define float @v_log10_f32_ninf_dynamic(float %in) #1 { define float @v_log10_f32_ninf_dynamic(float %in) #1 {
; GCN-LABEL: v_log10_f32_ninf_dynamic: ; GFX689-LABEL: v_log10_f32_ninf_dynamic:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log10_f32_ninf_dynamic:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_f32_ninf_dynamic: ; R600-LABEL: v_log10_f32_ninf_dynamic:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f32_ninf_dynamic: ; CM-LABEL: v_log10_f32_ninf_dynamic:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call ninf float @llvm.log10.f32(float %in) %result = call ninf float @llvm.log10.f32(float %in)
ret float %result ret float %result
} }
define float @v_log10_f32_nnan_ninf(float %in) { define float @v_log10_f32_nnan_ninf(float %in) {
; GCN-LABEL: v_log10_f32_nnan_ninf: ; GFX689-LABEL: v_log10_f32_nnan_ninf:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log10_f32_nnan_ninf:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_f32_nnan_ninf: ; R600-LABEL: v_log10_f32_nnan_ninf:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f32_nnan_ninf: ; CM-LABEL: v_log10_f32_nnan_ninf:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call nnan ninf float @llvm.log10.f32(float %in) %result = call nnan ninf float @llvm.log10.f32(float %in)
ret float %result ret float %result
} }
define float @v_log10_f32_nnan_ninf_daz(float %in) #0 { define float @v_log10_f32_nnan_ninf_daz(float %in) #0 {
; GCN-LABEL: v_log10_f32_nnan_ninf_daz: ; GFX689-LABEL: v_log10_f32_nnan_ninf_daz:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log10_f32_nnan_ninf_daz:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_f32_nnan_ninf_daz: ; R600-LABEL: v_log10_f32_nnan_ninf_daz:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f32_nnan_ninf_daz: ; CM-LABEL: v_log10_f32_nnan_ninf_daz:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call nnan ninf float @llvm.log10.f32(float %in) %result = call nnan ninf float @llvm.log10.f32(float %in)
ret float %result ret float %result
} }
define float @v_log10_f32_nnan_ninf_dynamic(float %in) #1 { define float @v_log10_f32_nnan_ninf_dynamic(float %in) #1 {
; GCN-LABEL: v_log10_f32_nnan_ninf_dynamic: ; GFX689-LABEL: v_log10_f32_nnan_ninf_dynamic:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log10_f32_nnan_ninf_dynamic:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_f32_nnan_ninf_dynamic: ; R600-LABEL: v_log10_f32_nnan_ninf_dynamic:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f32_nnan_ninf_dynamic: ; CM-LABEL: v_log10_f32_nnan_ninf_dynamic:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call nnan ninf float @llvm.log10.f32(float %in) %result = call nnan ninf float @llvm.log10.f32(float %in)
ret float %result ret float %result
} }
define float @v_log10_f32_fast_daz(float %in) #0 { define float @v_log10_f32_fast_daz(float %in) #0 {
; GCN-LABEL: v_log10_f32_fast_daz: ; GFX689-LABEL: v_log10_f32_fast_daz:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log10_f32_fast_daz:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_f32_fast_daz: ; R600-LABEL: v_log10_f32_fast_daz:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f32_fast_daz: ; CM-LABEL: v_log10_f32_fast_daz:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call fast float @llvm.log10.f32(float %in) %result = call fast float @llvm.log10.f32(float %in)
ret float %result ret float %result
} }
define float @v_log10_f32_dynamic_mode(float %in) #1 { define float @v_log10_f32_dynamic_mode(float %in) #1 {
; GCN-LABEL: v_log10_f32_dynamic_mode: ; GFX689-LABEL: v_log10_f32_dynamic_mode:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log10_f32_dynamic_mode:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_f32_dynamic_mode: ; R600-LABEL: v_log10_f32_dynamic_mode:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f32_dynamic_mode: ; CM-LABEL: v_log10_f32_dynamic_mode:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call float @llvm.log10.f32(float %in) %result = call float @llvm.log10.f32(float %in)
ret float %result ret float %result
} }
define float @v_log10_f32_undef() { define float @v_log10_f32_undef() {
; GCN-LABEL: v_log10_f32_undef: ; GFX689-LABEL: v_log10_f32_undef:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, s4 ; GFX689-NEXT: v_log_f32_e32 v0, s4
; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log10_f32_undef:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, s0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_f32_undef: ; R600-LABEL: v_log10_f32_undef:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f32_undef: ; CM-LABEL: v_log10_f32_undef:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call float @llvm.log10.f32(float undef) %result = call float @llvm.log10.f32(float undef)
ret float %result ret float %result
} }
define float @v_log10_f32_0() { define float @v_log10_f32_0() {
; GCN-SDAG-LABEL: v_log10_f32_0: ; GFX689-SDAG-LABEL: v_log10_f32_0:
; GCN-SDAG: ; %bb.0: ; GFX689-SDAG: ; %bb.0:
; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-SDAG-NEXT: v_log_f32_e32 v0, 0 ; GFX689-SDAG-NEXT: v_log_f32_e32 v0, 0
; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX689-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] ; GFX689-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GCN-GISEL-LABEL: v_log10_f32_0: ; GFX689-GISEL-LABEL: v_log10_f32_0:
; GCN-GISEL: ; %bb.0: ; GFX689-GISEL: ; %bb.0:
; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-GISEL-NEXT: v_mov_b32_e32 v0, 0x3e9a209b ; GFX689-GISEL-NEXT: v_mov_b32_e32 v0, 0x3e9a209b
; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0xff800000, v0 ; GFX689-GISEL-NEXT: v_mul_f32_e32 v0, 0xff800000, v0
; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX689-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-LABEL: v_log10_f32_0:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, 0
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-LABEL: v_log10_f32_0:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-GISEL-NEXT: v_mov_b32_e32 v0, 0x3e9a209b
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, 0xff800000, v0
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_f32_0: ; R600-LABEL: v_log10_f32_0:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f32_0: ; CM-LABEL: v_log10_f32_0:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call float @llvm.log10.f32(float 0.0) %result = call float @llvm.log10.f32(float 0.0)
ret float %result ret float %result
} }
define float @v_log10_f32_from_fpext_f16(i16 %src.i) { define float @v_log10_f32_from_fpext_f16(i16 %src.i) {
; GCN-LABEL: v_log10_f32_from_fpext_f16: ; GFX689-LABEL: v_log10_f32_from_fpext_f16:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX689-NEXT: v_cvt_f32_f16_e32 v0, v0
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX689-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log10_f32_from_fpext_f16:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_f32_from_fpext_f16: ; R600-LABEL: v_log10_f32_from_fpext_f16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f32_from_fpext_f16: ; CM-LABEL: v_log10_f32_from_fpext_f16:
; CM: ; %bb.0: ; CM: ; %bb.0:
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; GFX900: ; %bb.0: ; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_add_f16_e32 v0, v0, v1 ; GFX900-NEXT: v_add_f16_e32 v0, v0, v1
; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX900-NEXT: v_log_f32_e32 v0, v0 ; GFX900-NEXT: v_log_f32_e32 v0, v0
; GFX900-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX900-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX900-NEXT: s_setpc_b64 s[30:31] ; GFX900-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log10_f32_from_fpext_math_f16:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_add_f16_e32 v0, v0, v1
; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log10_f32_from_fpext_math_f16: ; R600-LABEL: v_log10_f32_from_fpext_math_f16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f32_from_fpext_math_f16: ; CM-LABEL: v_log10_f32_from_fpext_math_f16:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%src0 = bitcast i16 %src0.i to half %src0 = bitcast i16 %src0.i to half
%src1 = bitcast i16 %src1.i to half %src1 = bitcast i16 %src1.i to half
%fadd = fadd half %src0, %src1 %fadd = fadd half %src0, %src1
%fpext = fpext half %fadd to float %fpext = fpext half %fadd to float
%result = call float @llvm.log10.f32(float %fpext) %result = call float @llvm.log10.f32(float %fpext)
ret float %result ret float %result
} }
define float @v_log10_f32_from_fpext_bf16(bfloat %src) { define float @v_log10_f32_from_fpext_bf16(bfloat %src) {
; GCN-SDAG-LABEL: v_log10_f32_from_fpext_bf16: ; GFX689-SDAG-LABEL: v_log10_f32_from_fpext_bf16:
; GCN-SDAG: ; %bb.0: ; GFX689-SDAG: ; %bb.0:
; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 ; GFX689-SDAG-NEXT: v_log_f32_e32 v0, v0
; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX689-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] ; GFX689-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GCN-GISEL-LABEL: v_log10_f32_from_fpext_bf16: ; GFX689-GISEL-LABEL: v_log10_f32_from_fpext_bf16:
; GCN-GISEL: ; %bb.0: ; GFX689-GISEL: ; %bb.0:
; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX689-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX689-GISEL-NEXT: v_log_f32_e32 v0, v0
; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0 ; GFX689-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX689-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-LABEL: v_log10_f32_from_fpext_bf16:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-LABEL: v_log10_f32_from_fpext_bf16:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log10_f32_from_fpext_bf16: ; R600-LABEL: v_log10_f32_from_fpext_bf16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f32_from_fpext_bf16: ; CM-LABEL: v_log10_f32_from_fpext_bf16:
; CM: ; %bb.0: ; CM: ; %bb.0:
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; ;
; GFX900-LABEL: v_log10_f16: ; GFX900-LABEL: v_log10_f16:
; GFX900: ; %bb.0: ; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_log_f16_e32 v0, v0 ; GFX900-NEXT: v_log_f16_e32 v0, v0
; GFX900-NEXT: v_mul_f16_e32 v0, 0x34d1, v0 ; GFX900-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX900-NEXT: s_setpc_b64 s[30:31] ; GFX900-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log10_f16:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f16_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log10_f16: ; R600-LABEL: v_log10_f16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f16: ; CM-LABEL: v_log10_f16:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
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; ;
; GFX900-LABEL: v_log10_fabs_f16: ; GFX900-LABEL: v_log10_fabs_f16:
; GFX900: ; %bb.0: ; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_log_f16_e64 v0, |v0| ; GFX900-NEXT: v_log_f16_e64 v0, |v0|
; GFX900-NEXT: v_mul_f16_e32 v0, 0x34d1, v0 ; GFX900-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX900-NEXT: s_setpc_b64 s[30:31] ; GFX900-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log10_fabs_f16:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f16_e64 v0, |v0|
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log10_fabs_f16: ; R600-LABEL: v_log10_fabs_f16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_fabs_f16: ; CM-LABEL: v_log10_fabs_f16:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
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; ;
; GFX900-LABEL: v_log10_fneg_fabs_f16: ; GFX900-LABEL: v_log10_fneg_fabs_f16:
; GFX900: ; %bb.0: ; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_log_f16_e64 v0, -|v0| ; GFX900-NEXT: v_log_f16_e64 v0, -|v0|
; GFX900-NEXT: v_mul_f16_e32 v0, 0x34d1, v0 ; GFX900-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX900-NEXT: s_setpc_b64 s[30:31] ; GFX900-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log10_fneg_fabs_f16:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f16_e64 v0, -|v0|
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log10_fneg_fabs_f16: ; R600-LABEL: v_log10_fneg_fabs_f16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_fneg_fabs_f16: ; CM-LABEL: v_log10_fneg_fabs_f16:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
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; ;
; GFX900-LABEL: v_log10_fneg_f16: ; GFX900-LABEL: v_log10_fneg_f16:
; GFX900: ; %bb.0: ; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_log_f16_e64 v0, -v0 ; GFX900-NEXT: v_log_f16_e64 v0, -v0
; GFX900-NEXT: v_mul_f16_e32 v0, 0x34d1, v0 ; GFX900-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX900-NEXT: s_setpc_b64 s[30:31] ; GFX900-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log10_fneg_f16:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f16_e64 v0, -v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log10_fneg_f16: ; R600-LABEL: v_log10_fneg_f16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_fneg_f16: ; CM-LABEL: v_log10_fneg_f16:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
Show All 31 Lines
; ;
; GFX900-LABEL: v_log10_f16_fast: ; GFX900-LABEL: v_log10_f16_fast:
; GFX900: ; %bb.0: ; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_log_f16_e32 v0, v0 ; GFX900-NEXT: v_log_f16_e32 v0, v0
; GFX900-NEXT: v_mul_f16_e32 v0, 0x34d1, v0 ; GFX900-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX900-NEXT: s_setpc_b64 s[30:31] ; GFX900-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log10_f16_fast:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f16_e32 v0, v0
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log10_f16_fast: ; R600-LABEL: v_log10_f16_fast:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_f16_fast: ; CM-LABEL: v_log10_f16_fast:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_log_f16_e32 v1, v0 ; GFX900-NEXT: v_log_f16_e32 v1, v0
; GFX900-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX900-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX900-NEXT: v_mul_f16_e32 v1, 0x34d1, v1 ; GFX900-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
; GFX900-NEXT: v_mul_f16_e32 v0, 0x34d1, v0 ; GFX900-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX900-NEXT: v_pack_b32_f16 v0, v1, v0 ; GFX900-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX900-NEXT: s_setpc_b64 s[30:31] ; GFX900-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log10_v2f16:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-NEXT: v_log_f16_e32 v0, v0
; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1100-NEXT: v_log_f16_e32 v1, v1
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
; GFX1100-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log10_v2f16: ; R600-LABEL: v_log10_v2f16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_v2f16: ; CM-LABEL: v_log10_v2f16:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
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; GFX900-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0 ; GFX900-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
; GFX900-GISEL-NEXT: v_log_f16_e32 v1, v0 ; GFX900-GISEL-NEXT: v_log_f16_e32 v1, v0
; GFX900-GISEL-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX900-GISEL-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX900-GISEL-NEXT: v_mul_f16_e32 v1, 0x34d1, v1 ; GFX900-GISEL-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
; GFX900-GISEL-NEXT: v_mul_f16_e32 v0, 0x34d1, v0 ; GFX900-GISEL-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v0 ; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-SDAG-LABEL: v_log10_fabs_v2f16:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-SDAG-NEXT: v_log_f16_e64 v0, |v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_log_f16_e64 v1, |v1|
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-SDAG-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
; GFX1100-SDAG-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-LABEL: v_log10_fabs_v2f16:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-GISEL-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-NEXT: v_log_f16_e32 v1, v1
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-GISEL-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log10_fabs_v2f16: ; R600-LABEL: v_log10_fabs_v2f16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_fabs_v2f16: ; CM-LABEL: v_log10_fabs_v2f16:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines
; GFX900-GISEL-NEXT: v_or_b32_e32 v0, 0x80008000, v0 ; GFX900-GISEL-NEXT: v_or_b32_e32 v0, 0x80008000, v0
; GFX900-GISEL-NEXT: v_log_f16_e32 v1, v0 ; GFX900-GISEL-NEXT: v_log_f16_e32 v1, v0
; GFX900-GISEL-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX900-GISEL-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX900-GISEL-NEXT: v_mul_f16_e32 v1, 0x34d1, v1 ; GFX900-GISEL-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
; GFX900-GISEL-NEXT: v_mul_f16_e32 v0, 0x34d1, v0 ; GFX900-GISEL-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v0 ; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-SDAG-LABEL: v_log10_fneg_fabs_v2f16:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-SDAG-NEXT: v_log_f16_e64 v0, -|v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_log_f16_e64 v1, -|v1|
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-SDAG-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
; GFX1100-SDAG-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-LABEL: v_log10_fneg_fabs_v2f16:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-GISEL-NEXT: v_or_b32_e32 v0, 0x80008000, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-GISEL-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-NEXT: v_log_f16_e32 v1, v1
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-GISEL-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log10_fneg_fabs_v2f16: ; R600-LABEL: v_log10_fneg_fabs_v2f16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_fneg_fabs_v2f16: ; CM-LABEL: v_log10_fneg_fabs_v2f16:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
; GFX900-GISEL-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 ; GFX900-GISEL-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
; GFX900-GISEL-NEXT: v_log_f16_e32 v1, v0 ; GFX900-GISEL-NEXT: v_log_f16_e32 v1, v0
; GFX900-GISEL-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX900-GISEL-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX900-GISEL-NEXT: v_mul_f16_e32 v1, 0x34d1, v1 ; GFX900-GISEL-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
; GFX900-GISEL-NEXT: v_mul_f16_e32 v0, 0x34d1, v0 ; GFX900-GISEL-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v0 ; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-SDAG-LABEL: v_log10_fneg_v2f16:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-SDAG-NEXT: v_log_f16_e64 v0, -v0
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_log_f16_e64 v1, -v1
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-SDAG-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
; GFX1100-SDAG-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-LABEL: v_log10_fneg_v2f16:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-GISEL-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-GISEL-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-NEXT: v_log_f16_e32 v1, v1
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-GISEL-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log10_fneg_v2f16: ; R600-LABEL: v_log10_fneg_v2f16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_fneg_v2f16: ; CM-LABEL: v_log10_fneg_v2f16:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_log_f16_e32 v1, v0 ; GFX900-NEXT: v_log_f16_e32 v1, v0
; GFX900-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX900-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX900-NEXT: v_mul_f16_e32 v1, 0x34d1, v1 ; GFX900-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
; GFX900-NEXT: v_mul_f16_e32 v0, 0x34d1, v0 ; GFX900-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX900-NEXT: v_pack_b32_f16 v0, v1, v0 ; GFX900-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX900-NEXT: s_setpc_b64 s[30:31] ; GFX900-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log10_v2f16_fast:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-NEXT: v_log_f16_e32 v0, v0
; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX1100-NEXT: v_log_f16_e32 v1, v1
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_mul_f16_e32 v0, 0x34d1, v0
; GFX1100-NEXT: v_mul_f16_e32 v1, 0x34d1, v1
; GFX1100-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log10_v2f16_fast: ; R600-LABEL: v_log10_v2f16_fast:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log10_v2f16_fast: ; CM-LABEL: v_log10_v2f16_fast:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
Show All 18 Lines

llvm/test/CodeGen/AMDGPU/llvm.log2.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -global-isel=0 -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI,GCN-SDAG,SI-SDAG %s ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GFX689,SI,GFX689-SDAG,SI-SDAG %s
; RUN: llc -global-isel=1 -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI,GCN-GISEL,SI-GISEL %s ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GFX689,SI,GFX689-GISEL,SI-GISEL %s
; RUN: llc -global-isel=0 -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI,GCN-SDAG,VI-SDAG %s ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GFX689,VI,GFX689-SDAG,VI-SDAG %s
; RUN: llc -global-isel=1 -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI,GCN-GISEL,VI-GISEL %s ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GFX689,VI,GFX689-GISEL,VI-GISEL %s
; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-SDAG,GFX900-SDAG %s ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX689,GFX900,GFX689-SDAG,GFX900-SDAG %s
; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-GISEL,GFX900-GISEL %s ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX689,GFX900,GFX689-GISEL,GFX900-GISEL %s
; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-SDAG %s
; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX1100,GFX1100-GISEL %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s ; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
define amdgpu_kernel void @s_log2_f32(ptr addrspace(1) %out, float %in) { define amdgpu_kernel void @s_log2_f32(ptr addrspace(1) %out, float %in) {
; SI-LABEL: s_log2_f32: ; SI-LABEL: s_log2_f32:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dword s2, s[0:1], 0xb ; SI-NEXT: s_load_dword s2, s[0:1], 0xb
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; GFX900-NEXT: s_load_dword s4, s[0:1], 0x2c ; GFX900-NEXT: s_load_dword s4, s[0:1], 0x2c
; GFX900-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX900-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
; GFX900-NEXT: v_mov_b32_e32 v1, 0 ; GFX900-NEXT: v_mov_b32_e32 v1, 0
; GFX900-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: v_log_f32_e32 v0, s4 ; GFX900-NEXT: v_log_f32_e32 v0, s4
; GFX900-NEXT: global_store_dword v1, v0, s[2:3] ; GFX900-NEXT: global_store_dword v1, v0, s[2:3]
; GFX900-NEXT: s_endpgm ; GFX900-NEXT: s_endpgm
; ;
; GFX1100-LABEL: s_log2_f32:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_clause 0x1
; GFX1100-NEXT: s_load_b32 s2, s[0:1], 0x2c
; GFX1100-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
; GFX1100-NEXT: v_mov_b32_e32 v1, 0
; GFX1100-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-NEXT: v_log_f32_e32 v0, s2
; GFX1100-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX1100-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX1100-NEXT: s_endpgm
;
; R600-LABEL: s_log2_f32: ; R600-LABEL: s_log2_f32:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[] ; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4: ; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: LSHR T0.X, KC0[2].Y, literal.x, ; R600-NEXT: LSHR T0.X, KC0[2].Y, literal.x,
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; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-GISEL-NEXT: v_log_f32_e32 v0, s2 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, s2
; GFX900-GISEL-NEXT: v_log_f32_e32 v1, s3 ; GFX900-GISEL-NEXT: v_log_f32_e32 v1, s3
; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX900-GISEL-NEXT: s_endpgm ; GFX900-GISEL-NEXT: s_endpgm
; ;
; GFX1100-SDAG-LABEL: s_log2_v2f32:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
; GFX1100-SDAG-NEXT: v_mov_b32_e32 v2, 0
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v1, s3
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, s2
; GFX1100-SDAG-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1100-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX1100-SDAG-NEXT: s_endpgm
;
; GFX1100-GISEL-LABEL: s_log2_v2f32:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
; GFX1100-GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, s2
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, s3
; GFX1100-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1100-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log2_v2f32: ; R600-LABEL: s_log2_v2f32:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[] ; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4: ; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: LOG_IEEE * T0.Y, KC0[3].X, ; R600-NEXT: LOG_IEEE * T0.Y, KC0[3].X,
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; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0
; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-GISEL-NEXT: v_log_f32_e32 v0, s4 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, s4
; GFX900-GISEL-NEXT: v_log_f32_e32 v1, s5 ; GFX900-GISEL-NEXT: v_log_f32_e32 v1, s5
; GFX900-GISEL-NEXT: v_log_f32_e32 v2, s6 ; GFX900-GISEL-NEXT: v_log_f32_e32 v2, s6
; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3] ; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
; GFX900-GISEL-NEXT: s_endpgm ; GFX900-GISEL-NEXT: s_endpgm
; ;
; GFX1100-SDAG-LABEL: s_log2_v3f32:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_clause 0x1
; GFX1100-SDAG-NEXT: s_load_b128 s[4:7], s[0:1], 0x34
; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
; GFX1100-SDAG-NEXT: v_mov_b32_e32 v3, 0
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v2, s6
; GFX1100-SDAG-NEXT: v_log_f32_e32 v1, s5
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, s4
; GFX1100-SDAG-NEXT: global_store_b96 v3, v[0:2], s[0:1]
; GFX1100-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX1100-SDAG-NEXT: s_endpgm
;
; GFX1100-GISEL-LABEL: s_log2_v3f32:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_clause 0x1
; GFX1100-GISEL-NEXT: s_load_b128 s[4:7], s[0:1], 0x34
; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
; GFX1100-GISEL-NEXT: v_mov_b32_e32 v3, 0
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, s4
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, s5
; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, s6
; GFX1100-GISEL-NEXT: global_store_b96 v3, v[0:2], s[0:1]
; GFX1100-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log2_v3f32: ; R600-LABEL: s_log2_v3f32:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[] ; R600-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.X, T2.X, 0 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.X, T2.X, 0
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: ALU clause starting at 4: ; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: LOG_IEEE * T0.Y, KC0[3].Z, ; R600-NEXT: LOG_IEEE * T0.Y, KC0[3].Z,
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; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-GISEL-NEXT: v_log_f32_e32 v0, s4 ; GFX900-GISEL-NEXT: v_log_f32_e32 v0, s4
; GFX900-GISEL-NEXT: v_log_f32_e32 v1, s5 ; GFX900-GISEL-NEXT: v_log_f32_e32 v1, s5
; GFX900-GISEL-NEXT: v_log_f32_e32 v2, s6 ; GFX900-GISEL-NEXT: v_log_f32_e32 v2, s6
; GFX900-GISEL-NEXT: v_log_f32_e32 v3, s7 ; GFX900-GISEL-NEXT: v_log_f32_e32 v3, s7
; GFX900-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] ; GFX900-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
; GFX900-GISEL-NEXT: s_endpgm ; GFX900-GISEL-NEXT: s_endpgm
; ;
; GFX1100-SDAG-LABEL: s_log2_v4f32:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_clause 0x1
; GFX1100-SDAG-NEXT: s_load_b128 s[4:7], s[0:1], 0x34
; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
; GFX1100-SDAG-NEXT: v_mov_b32_e32 v4, 0
; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-SDAG-NEXT: v_log_f32_e32 v3, s7
; GFX1100-SDAG-NEXT: v_log_f32_e32 v2, s6
; GFX1100-SDAG-NEXT: v_log_f32_e32 v1, s5
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, s4
; GFX1100-SDAG-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX1100-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX1100-SDAG-NEXT: s_endpgm
;
; GFX1100-GISEL-LABEL: s_log2_v4f32:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_clause 0x1
; GFX1100-GISEL-NEXT: s_load_b128 s[4:7], s[0:1], 0x34
; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
; GFX1100-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, s4
; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, s5
; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, s6
; GFX1100-GISEL-NEXT: v_log_f32_e32 v3, s7
; GFX1100-GISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX1100-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log2_v4f32: ; R600-LABEL: s_log2_v4f32:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[] ; R600-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4: ; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: LOG_IEEE * T0.W, KC0[4].X, ; R600-NEXT: LOG_IEEE * T0.W, KC0[4].X,
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; CM-NEXT: LOG_IEEE T1.Z (MASKED), KC0[3].Y, ; CM-NEXT: LOG_IEEE T1.Z (MASKED), KC0[3].Y,
; CM-NEXT: LOG_IEEE * T1.W (MASKED), KC0[3].Y, ; CM-NEXT: LOG_IEEE * T1.W (MASKED), KC0[3].Y,
%result = call <4 x float> @llvm.log2.v4f32(<4 x float> %in) %result = call <4 x float> @llvm.log2.v4f32(<4 x float> %in)
store <4 x float> %result, ptr addrspace(1) %out store <4 x float> %result, ptr addrspace(1) %out
ret void ret void
} }
define float @v_log2_f32(float %in) { define float @v_log2_f32(float %in) {
; GCN-LABEL: v_log2_f32: ; GFX689-LABEL: v_log2_f32:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log2_f32:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log2_f32: ; R600-LABEL: v_log2_f32:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_f32: ; CM-LABEL: v_log2_f32:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call float @llvm.log2.f32(float %in) %result = call float @llvm.log2.f32(float %in)
ret float %result ret float %result
} }
define float @v_log2_fabs_f32(float %in) { define float @v_log2_fabs_f32(float %in) {
; GCN-LABEL: v_log2_fabs_f32: ; GFX689-LABEL: v_log2_fabs_f32:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e64 v0, |v0| ; GFX689-NEXT: v_log_f32_e64 v0, |v0|
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log2_fabs_f32:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e64 v0, |v0|
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log2_fabs_f32: ; R600-LABEL: v_log2_fabs_f32:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_fabs_f32: ; CM-LABEL: v_log2_fabs_f32:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%fabs = call float @llvm.fabs.f32(float %in) %fabs = call float @llvm.fabs.f32(float %in)
%result = call float @llvm.log2.f32(float %fabs) %result = call float @llvm.log2.f32(float %fabs)
ret float %result ret float %result
} }
define float @v_log2_fneg_fabs_f32(float %in) { define float @v_log2_fneg_fabs_f32(float %in) {
; GCN-LABEL: v_log2_fneg_fabs_f32: ; GFX689-LABEL: v_log2_fneg_fabs_f32:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e64 v0, -|v0| ; GFX689-NEXT: v_log_f32_e64 v0, -|v0|
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log2_fneg_fabs_f32:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e64 v0, -|v0|
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log2_fneg_fabs_f32: ; R600-LABEL: v_log2_fneg_fabs_f32:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_fneg_fabs_f32: ; CM-LABEL: v_log2_fneg_fabs_f32:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%fabs = call float @llvm.fabs.f32(float %in) %fabs = call float @llvm.fabs.f32(float %in)
%fneg.fabs = fneg float %fabs %fneg.fabs = fneg float %fabs
%result = call float @llvm.log2.f32(float %fneg.fabs) %result = call float @llvm.log2.f32(float %fneg.fabs)
ret float %result ret float %result
} }
define float @v_log2_fneg_f32(float %in) { define float @v_log2_fneg_f32(float %in) {
; GCN-LABEL: v_log2_fneg_f32: ; GFX689-LABEL: v_log2_fneg_f32:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e64 v0, -v0 ; GFX689-NEXT: v_log_f32_e64 v0, -v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log2_fneg_f32:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e64 v0, -v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log2_fneg_f32: ; R600-LABEL: v_log2_fneg_f32:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_fneg_f32: ; CM-LABEL: v_log2_fneg_f32:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%fneg = fneg float %in %fneg = fneg float %in
%result = call float @llvm.log2.f32(float %fneg) %result = call float @llvm.log2.f32(float %fneg)
ret float %result ret float %result
} }
define float @v_log2_f32_fast(float %in) { define float @v_log2_f32_fast(float %in) {
; GCN-LABEL: v_log2_f32_fast: ; GFX689-LABEL: v_log2_f32_fast:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log2_f32_fast:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log2_f32_fast: ; R600-LABEL: v_log2_f32_fast:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_f32_fast: ; CM-LABEL: v_log2_f32_fast:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call fast float @llvm.log2.f32(float %in) %result = call fast float @llvm.log2.f32(float %in)
ret float %result ret float %result
} }
define float @v_log2_f32_unsafe_math_attr(float %in) "unsafe-fp-math"="true" { define float @v_log2_f32_unsafe_math_attr(float %in) "unsafe-fp-math"="true" {
; GCN-LABEL: v_log2_f32_unsafe_math_attr: ; GFX689-LABEL: v_log2_f32_unsafe_math_attr:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log2_f32_unsafe_math_attr:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log2_f32_unsafe_math_attr: ; R600-LABEL: v_log2_f32_unsafe_math_attr:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_f32_unsafe_math_attr: ; CM-LABEL: v_log2_f32_unsafe_math_attr:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call float @llvm.log2.f32(float %in) %result = call float @llvm.log2.f32(float %in)
ret float %result ret float %result
} }
define float @v_log2_f32_approx_fn_attr(float %in) "approx-func-fp-math"="true" { define float @v_log2_f32_approx_fn_attr(float %in) "approx-func-fp-math"="true" {
; GCN-LABEL: v_log2_f32_approx_fn_attr: ; GFX689-LABEL: v_log2_f32_approx_fn_attr:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log2_f32_approx_fn_attr:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log2_f32_approx_fn_attr: ; R600-LABEL: v_log2_f32_approx_fn_attr:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_f32_approx_fn_attr: ; CM-LABEL: v_log2_f32_approx_fn_attr:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call float @llvm.log2.f32(float %in) %result = call float @llvm.log2.f32(float %in)
ret float %result ret float %result
} }
define float @v_log2_f32_ninf(float %in) { define float @v_log2_f32_ninf(float %in) {
; GCN-LABEL: v_log2_f32_ninf: ; GFX689-LABEL: v_log2_f32_ninf:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log2_f32_ninf:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log2_f32_ninf: ; R600-LABEL: v_log2_f32_ninf:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_f32_ninf: ; CM-LABEL: v_log2_f32_ninf:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call ninf float @llvm.log2.f32(float %in) %result = call ninf float @llvm.log2.f32(float %in)
ret float %result ret float %result
} }
define float @v_log2_f32_afn(float %in) { define float @v_log2_f32_afn(float %in) {
; GCN-LABEL: v_log2_f32_afn: ; GFX689-LABEL: v_log2_f32_afn:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log2_f32_afn:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log2_f32_afn: ; R600-LABEL: v_log2_f32_afn:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_f32_afn: ; CM-LABEL: v_log2_f32_afn:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call afn float @llvm.log2.f32(float %in) %result = call afn float @llvm.log2.f32(float %in)
ret float %result ret float %result
} }
define float @v_log2_f32_afn_daz(float %in) #0 { define float @v_log2_f32_afn_daz(float %in) #0 {
; GCN-LABEL: v_log2_f32_afn_daz: ; GFX689-LABEL: v_log2_f32_afn_daz:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log2_f32_afn_daz:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log2_f32_afn_daz: ; R600-LABEL: v_log2_f32_afn_daz:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_f32_afn_daz: ; CM-LABEL: v_log2_f32_afn_daz:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call afn float @llvm.log2.f32(float %in) %result = call afn float @llvm.log2.f32(float %in)
ret float %result ret float %result
} }
define float @v_log2_f32_afn_dynamic(float %in) #1 { define float @v_log2_f32_afn_dynamic(float %in) #1 {
; GCN-LABEL: v_log2_f32_afn_dynamic: ; GFX689-LABEL: v_log2_f32_afn_dynamic:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log2_f32_afn_dynamic:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log2_f32_afn_dynamic: ; R600-LABEL: v_log2_f32_afn_dynamic:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_f32_afn_dynamic: ; CM-LABEL: v_log2_f32_afn_dynamic:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call afn float @llvm.log2.f32(float %in) %result = call afn float @llvm.log2.f32(float %in)
ret float %result ret float %result
} }
define float @v_fabs_log2_f32_afn(float %in) { define float @v_fabs_log2_f32_afn(float %in) {
; GCN-LABEL: v_fabs_log2_f32_afn: ; GFX689-LABEL: v_fabs_log2_f32_afn:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e64 v0, |v0| ; GFX689-NEXT: v_log_f32_e64 v0, |v0|
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_fabs_log2_f32_afn:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e64 v0, |v0|
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_fabs_log2_f32_afn: ; R600-LABEL: v_fabs_log2_f32_afn:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_fabs_log2_f32_afn: ; CM-LABEL: v_fabs_log2_f32_afn:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%fabs = call float @llvm.fabs.f32(float %in) %fabs = call float @llvm.fabs.f32(float %in)
%result = call afn float @llvm.log2.f32(float %fabs) %result = call afn float @llvm.log2.f32(float %fabs)
ret float %result ret float %result
} }
define float @v_log2_f32_daz(float %in) #0 { define float @v_log2_f32_daz(float %in) #0 {
; GCN-LABEL: v_log2_f32_daz: ; GFX689-LABEL: v_log2_f32_daz:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log2_f32_daz:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log2_f32_daz: ; R600-LABEL: v_log2_f32_daz:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_f32_daz: ; CM-LABEL: v_log2_f32_daz:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call float @llvm.log2.f32(float %in) %result = call float @llvm.log2.f32(float %in)
ret float %result ret float %result
} }
define float @v_log2_f32_nnan(float %in) { define float @v_log2_f32_nnan(float %in) {
; GCN-LABEL: v_log2_f32_nnan: ; GFX689-LABEL: v_log2_f32_nnan:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log2_f32_nnan:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log2_f32_nnan: ; R600-LABEL: v_log2_f32_nnan:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_f32_nnan: ; CM-LABEL: v_log2_f32_nnan:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call nnan float @llvm.log2.f32(float %in) %result = call nnan float @llvm.log2.f32(float %in)
ret float %result ret float %result
} }
define float @v_log2_f32_nnan_daz(float %in) #0 { define float @v_log2_f32_nnan_daz(float %in) #0 {
; GCN-LABEL: v_log2_f32_nnan_daz: ; GFX689-LABEL: v_log2_f32_nnan_daz:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log2_f32_nnan_daz:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log2_f32_nnan_daz: ; R600-LABEL: v_log2_f32_nnan_daz:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_f32_nnan_daz: ; CM-LABEL: v_log2_f32_nnan_daz:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call nnan float @llvm.log2.f32(float %in) %result = call nnan float @llvm.log2.f32(float %in)
ret float %result ret float %result
} }
define float @v_log2_f32_nnan_dynamic(float %in) #1 { define float @v_log2_f32_nnan_dynamic(float %in) #1 {
; GCN-LABEL: v_log2_f32_nnan_dynamic: ; GFX689-LABEL: v_log2_f32_nnan_dynamic:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log2_f32_nnan_dynamic:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log2_f32_nnan_dynamic: ; R600-LABEL: v_log2_f32_nnan_dynamic:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_f32_nnan_dynamic: ; CM-LABEL: v_log2_f32_nnan_dynamic:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call nnan float @llvm.log2.f32(float %in) %result = call nnan float @llvm.log2.f32(float %in)
ret float %result ret float %result
} }
define float @v_log2_f32_ninf_daz(float %in) #0 { define float @v_log2_f32_ninf_daz(float %in) #0 {
; GCN-LABEL: v_log2_f32_ninf_daz: ; GFX689-LABEL: v_log2_f32_ninf_daz:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log2_f32_ninf_daz:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log2_f32_ninf_daz: ; R600-LABEL: v_log2_f32_ninf_daz:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_f32_ninf_daz: ; CM-LABEL: v_log2_f32_ninf_daz:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call ninf float @llvm.log2.f32(float %in) %result = call ninf float @llvm.log2.f32(float %in)
ret float %result ret float %result
} }
define float @v_log2_f32_ninf_dynamic(float %in) #1 { define float @v_log2_f32_ninf_dynamic(float %in) #1 {
; GCN-LABEL: v_log2_f32_ninf_dynamic: ; GFX689-LABEL: v_log2_f32_ninf_dynamic:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log2_f32_ninf_dynamic:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log2_f32_ninf_dynamic: ; R600-LABEL: v_log2_f32_ninf_dynamic:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_f32_ninf_dynamic: ; CM-LABEL: v_log2_f32_ninf_dynamic:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call ninf float @llvm.log2.f32(float %in) %result = call ninf float @llvm.log2.f32(float %in)
ret float %result ret float %result
} }
define float @v_log2_f32_nnan_ninf(float %in) { define float @v_log2_f32_nnan_ninf(float %in) {
; GCN-LABEL: v_log2_f32_nnan_ninf: ; GFX689-LABEL: v_log2_f32_nnan_ninf:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log2_f32_nnan_ninf:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log2_f32_nnan_ninf: ; R600-LABEL: v_log2_f32_nnan_ninf:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_f32_nnan_ninf: ; CM-LABEL: v_log2_f32_nnan_ninf:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call nnan ninf float @llvm.log2.f32(float %in) %result = call nnan ninf float @llvm.log2.f32(float %in)
ret float %result ret float %result
} }
define float @v_log2_f32_nnan_ninf_daz(float %in) #0 { define float @v_log2_f32_nnan_ninf_daz(float %in) #0 {
; GCN-LABEL: v_log2_f32_nnan_ninf_daz: ; GFX689-LABEL: v_log2_f32_nnan_ninf_daz:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log2_f32_nnan_ninf_daz:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log2_f32_nnan_ninf_daz: ; R600-LABEL: v_log2_f32_nnan_ninf_daz:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_f32_nnan_ninf_daz: ; CM-LABEL: v_log2_f32_nnan_ninf_daz:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call nnan ninf float @llvm.log2.f32(float %in) %result = call nnan ninf float @llvm.log2.f32(float %in)
ret float %result ret float %result
} }
define float @v_log2_f32_nnan_ninf_dynamic(float %in) #1 { define float @v_log2_f32_nnan_ninf_dynamic(float %in) #1 {
; GCN-LABEL: v_log2_f32_nnan_ninf_dynamic: ; GFX689-LABEL: v_log2_f32_nnan_ninf_dynamic:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log2_f32_nnan_ninf_dynamic:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log2_f32_nnan_ninf_dynamic: ; R600-LABEL: v_log2_f32_nnan_ninf_dynamic:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_f32_nnan_ninf_dynamic: ; CM-LABEL: v_log2_f32_nnan_ninf_dynamic:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call nnan ninf float @llvm.log2.f32(float %in) %result = call nnan ninf float @llvm.log2.f32(float %in)
ret float %result ret float %result
} }
define float @v_log2_f32_fast_daz(float %in) #0 { define float @v_log2_f32_fast_daz(float %in) #0 {
; GCN-LABEL: v_log2_f32_fast_daz: ; GFX689-LABEL: v_log2_f32_fast_daz:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log2_f32_fast_daz:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log2_f32_fast_daz: ; R600-LABEL: v_log2_f32_fast_daz:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_f32_fast_daz: ; CM-LABEL: v_log2_f32_fast_daz:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call fast float @llvm.log2.f32(float %in) %result = call fast float @llvm.log2.f32(float %in)
ret float %result ret float %result
} }
define float @v_log2_f32_dynamic_mode(float %in) #1 { define float @v_log2_f32_dynamic_mode(float %in) #1 {
; GCN-LABEL: v_log2_f32_dynamic_mode: ; GFX689-LABEL: v_log2_f32_dynamic_mode:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log2_f32_dynamic_mode:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log2_f32_dynamic_mode: ; R600-LABEL: v_log2_f32_dynamic_mode:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_f32_dynamic_mode: ; CM-LABEL: v_log2_f32_dynamic_mode:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call float @llvm.log2.f32(float %in) %result = call float @llvm.log2.f32(float %in)
ret float %result ret float %result
} }
define float @v_log2_f32_undef() { define float @v_log2_f32_undef() {
; GCN-LABEL: v_log2_f32_undef: ; GFX689-LABEL: v_log2_f32_undef:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, s4 ; GFX689-NEXT: v_log_f32_e32 v0, s4
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log2_f32_undef:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f32_e32 v0, s0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log2_f32_undef: ; R600-LABEL: v_log2_f32_undef:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_f32_undef: ; CM-LABEL: v_log2_f32_undef:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call float @llvm.log2.f32(float undef) %result = call float @llvm.log2.f32(float undef)
ret float %result ret float %result
} }
define float @v_log2_f32_0() { define float @v_log2_f32_0() {
; GCN-SDAG-LABEL: v_log2_f32_0: ; GFX689-SDAG-LABEL: v_log2_f32_0:
; GCN-SDAG: ; %bb.0: ; GFX689-SDAG: ; %bb.0:
; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-SDAG-NEXT: v_log_f32_e32 v0, 0 ; GFX689-SDAG-NEXT: v_log_f32_e32 v0, 0
; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] ; GFX689-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GCN-GISEL-LABEL: v_log2_f32_0: ; GFX689-GISEL-LABEL: v_log2_f32_0:
; GCN-GISEL: ; %bb.0: ; GFX689-GISEL: ; %bb.0:
; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-GISEL-NEXT: v_mov_b32_e32 v0, 0xff800000 ; GFX689-GISEL-NEXT: v_mov_b32_e32 v0, 0xff800000
; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX689-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-LABEL: v_log2_f32_0:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, 0
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-LABEL: v_log2_f32_0:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-GISEL-NEXT: v_mov_b32_e32 v0, 0xff800000
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log2_f32_0: ; R600-LABEL: v_log2_f32_0:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_f32_0: ; CM-LABEL: v_log2_f32_0:
; CM: ; %bb.0: ; CM: ; %bb.0:
Show All 9 Lines
; GFX89-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX89-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX89-GISEL-NEXT: v_mov_b32_e32 v0, 0xff800000 ; GFX89-GISEL-NEXT: v_mov_b32_e32 v0, 0xff800000
; GFX89-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX89-GISEL-NEXT: s_setpc_b64 s[30:31]
%result = call float @llvm.log2.f32(float 0.0) %result = call float @llvm.log2.f32(float 0.0)
ret float %result ret float %result
} }
define float @v_log2_f32_from_fpext_f16(i16 %src.i) { define float @v_log2_f32_from_fpext_f16(i16 %src.i) {
; GCN-LABEL: v_log2_f32_from_fpext_f16: ; GFX689-LABEL: v_log2_f32_from_fpext_f16:
; GCN: ; %bb.0: ; GFX689: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX689-NEXT: v_cvt_f32_f16_e32 v0, v0
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX689-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX689-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-LABEL: v_log2_f32_from_fpext_f16:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log2_f32_from_fpext_f16: ; R600-LABEL: v_log2_f32_from_fpext_f16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_f32_from_fpext_f16: ; CM-LABEL: v_log2_f32_from_fpext_f16:
; CM: ; %bb.0: ; CM: ; %bb.0:
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; GFX900-LABEL: v_log2_f32_from_fpext_math_f16: ; GFX900-LABEL: v_log2_f32_from_fpext_math_f16:
; GFX900: ; %bb.0: ; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_add_f16_e32 v0, v0, v1 ; GFX900-NEXT: v_add_f16_e32 v0, v0, v1
; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX900-NEXT: v_log_f32_e32 v0, v0 ; GFX900-NEXT: v_log_f32_e32 v0, v0
; GFX900-NEXT: s_setpc_b64 s[30:31] ; GFX900-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log2_f32_from_fpext_math_f16:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_add_f16_e32 v0, v0, v1
; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX1100-NEXT: v_log_f32_e32 v0, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log2_f32_from_fpext_math_f16: ; R600-LABEL: v_log2_f32_from_fpext_math_f16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_f32_from_fpext_math_f16: ; CM-LABEL: v_log2_f32_from_fpext_math_f16:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
Show All 9 Lines; GFX89-NEXT: s_setpc_b64 s[30:31]
%src1 = bitcast i16 %src1.i to half %src1 = bitcast i16 %src1.i to half
%fadd = fadd half %src0, %src1 %fadd = fadd half %src0, %src1
%fpext = fpext half %fadd to float %fpext = fpext half %fadd to float
%result = call float @llvm.log2.f32(float %fpext) %result = call float @llvm.log2.f32(float %fpext)
ret float %result ret float %result
} }
define float @v_log2_f32_from_fpext_bf16(bfloat %src) { define float @v_log2_f32_from_fpext_bf16(bfloat %src) {
; GCN-SDAG-LABEL: v_log2_f32_from_fpext_bf16: ; GFX689-SDAG-LABEL: v_log2_f32_from_fpext_bf16:
; GCN-SDAG: ; %bb.0: ; GFX689-SDAG: ; %bb.0:
; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-SDAG-NEXT: v_log_f32_e32 v0, v0 ; GFX689-SDAG-NEXT: v_log_f32_e32 v0, v0
; GCN-SDAG-NEXT: s_setpc_b64 s[30:31] ; GFX689-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GCN-GISEL-LABEL: v_log2_f32_from_fpext_bf16: ; GFX689-GISEL-LABEL: v_log2_f32_from_fpext_bf16:
; GCN-GISEL: ; %bb.0: ; GFX689-GISEL: ; %bb.0:
; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX689-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX689-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0 ; GFX689-GISEL-NEXT: v_log_f32_e32 v0, v0
; GCN-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX689-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-LABEL: v_log2_f32_from_fpext_bf16:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-LABEL: v_log2_f32_from_fpext_bf16:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_log2_f32_from_fpext_bf16: ; R600-LABEL: v_log2_f32_from_fpext_bf16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_f32_from_fpext_bf16: ; CM-LABEL: v_log2_f32_from_fpext_bf16:
; CM: ; %bb.0: ; CM: ; %bb.0:
Show All 39 Lines
; VI-NEXT: s_setpc_b64 s[30:31] ; VI-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-LABEL: v_log2_f16: ; GFX900-LABEL: v_log2_f16:
; GFX900: ; %bb.0: ; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_log_f16_e32 v0, v0 ; GFX900-NEXT: v_log_f16_e32 v0, v0
; GFX900-NEXT: s_setpc_b64 s[30:31] ; GFX900-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log2_f16:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f16_e32 v0, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log2_f16: ; R600-LABEL: v_log2_f16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_f16: ; CM-LABEL: v_log2_f16:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
Show All 31 Lines
; VI-NEXT: s_setpc_b64 s[30:31] ; VI-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-LABEL: v_log2_fabs_f16: ; GFX900-LABEL: v_log2_fabs_f16:
; GFX900: ; %bb.0: ; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_log_f16_e64 v0, |v0| ; GFX900-NEXT: v_log_f16_e64 v0, |v0|
; GFX900-NEXT: s_setpc_b64 s[30:31] ; GFX900-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log2_fabs_f16:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f16_e64 v0, |v0|
; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log2_fabs_f16: ; R600-LABEL: v_log2_fabs_f16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_fabs_f16: ; CM-LABEL: v_log2_fabs_f16:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
Show All 32 Lines
; VI-NEXT: s_setpc_b64 s[30:31] ; VI-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-LABEL: v_log2_fneg_fabs_f16: ; GFX900-LABEL: v_log2_fneg_fabs_f16:
; GFX900: ; %bb.0: ; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_log_f16_e64 v0, -|v0| ; GFX900-NEXT: v_log_f16_e64 v0, -|v0|
; GFX900-NEXT: s_setpc_b64 s[30:31] ; GFX900-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log2_fneg_fabs_f16:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f16_e64 v0, -|v0|
; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log2_fneg_fabs_f16: ; R600-LABEL: v_log2_fneg_fabs_f16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_fneg_fabs_f16: ; CM-LABEL: v_log2_fneg_fabs_f16:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
Show All 33 Lines
; VI-NEXT: s_setpc_b64 s[30:31] ; VI-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-LABEL: v_log2_fneg_f16: ; GFX900-LABEL: v_log2_fneg_f16:
; GFX900: ; %bb.0: ; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_log_f16_e64 v0, -v0 ; GFX900-NEXT: v_log_f16_e64 v0, -v0
; GFX900-NEXT: s_setpc_b64 s[30:31] ; GFX900-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log2_fneg_f16:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f16_e64 v0, -v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log2_fneg_f16: ; R600-LABEL: v_log2_fneg_f16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_fneg_f16: ; CM-LABEL: v_log2_fneg_f16:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
Show All 32 Lines
; VI-NEXT: s_setpc_b64 s[30:31] ; VI-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-LABEL: v_log2_f16_fast: ; GFX900-LABEL: v_log2_f16_fast:
; GFX900: ; %bb.0: ; GFX900: ; %bb.0:
; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-NEXT: v_log_f16_e32 v0, v0 ; GFX900-NEXT: v_log_f16_e32 v0, v0
; GFX900-NEXT: s_setpc_b64 s[30:31] ; GFX900-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log2_f16_fast:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_log_f16_e32 v0, v0
; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log2_f16_fast: ; R600-LABEL: v_log2_f16_fast:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_f16_fast: ; CM-LABEL: v_log2_f16_fast:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; GFX900-GISEL-LABEL: v_log2_v2f16: ; GFX900-GISEL-LABEL: v_log2_v2f16:
; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: v_log_f16_e32 v1, v0 ; GFX900-GISEL-NEXT: v_log_f16_e32 v1, v0
; GFX900-GISEL-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX900-GISEL-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v0 ; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log2_v2f16:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-NEXT: v_log_f16_e32 v0, v0
; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-NEXT: v_log_f16_e32 v1, v1
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log2_v2f16: ; R600-LABEL: v_log2_v2f16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_v2f16: ; CM-LABEL: v_log2_v2f16:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0 ; GFX900-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
; GFX900-GISEL-NEXT: v_log_f16_e32 v1, v0 ; GFX900-GISEL-NEXT: v_log_f16_e32 v1, v0
; GFX900-GISEL-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX900-GISEL-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v0 ; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-SDAG-LABEL: v_log2_fabs_v2f16:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-SDAG-NEXT: v_log_f16_e64 v0, |v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_log_f16_e64 v1, |v1|
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-LABEL: v_log2_fabs_v2f16:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-GISEL-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-NEXT: v_log_f16_e32 v1, v1
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log2_fabs_v2f16: ; R600-LABEL: v_log2_fabs_v2f16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_fabs_v2f16: ; CM-LABEL: v_log2_fabs_v2f16:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: v_or_b32_e32 v0, 0x80008000, v0 ; GFX900-GISEL-NEXT: v_or_b32_e32 v0, 0x80008000, v0
; GFX900-GISEL-NEXT: v_log_f16_e32 v1, v0 ; GFX900-GISEL-NEXT: v_log_f16_e32 v1, v0
; GFX900-GISEL-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX900-GISEL-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v0 ; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-SDAG-LABEL: v_log2_fneg_fabs_v2f16:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-SDAG-NEXT: v_log_f16_e64 v0, -|v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_log_f16_e64 v1, -|v1|
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-LABEL: v_log2_fneg_fabs_v2f16:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-GISEL-NEXT: v_or_b32_e32 v0, 0x80008000, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-GISEL-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-NEXT: v_log_f16_e32 v1, v1
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log2_fneg_fabs_v2f16: ; R600-LABEL: v_log2_fneg_fabs_v2f16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_fneg_fabs_v2f16: ; CM-LABEL: v_log2_fneg_fabs_v2f16:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 ; GFX900-GISEL-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
; GFX900-GISEL-NEXT: v_log_f16_e32 v1, v0 ; GFX900-GISEL-NEXT: v_log_f16_e32 v1, v0
; GFX900-GISEL-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX900-GISEL-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v0 ; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-SDAG-LABEL: v_log2_fneg_v2f16:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-SDAG-NEXT: v_log_f16_e64 v0, -v0
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_log_f16_e64 v1, -v1
; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-SDAG-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-GISEL-LABEL: v_log2_fneg_v2f16:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-GISEL-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1100-GISEL-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-GISEL-NEXT: v_log_f16_e32 v0, v0
; GFX1100-GISEL-NEXT: v_log_f16_e32 v1, v1
; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-GISEL-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log2_fneg_v2f16: ; R600-LABEL: v_log2_fneg_v2f16:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_fneg_v2f16: ; CM-LABEL: v_log2_fneg_v2f16:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
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; GFX900-GISEL-LABEL: v_log2_v2f16_fast: ; GFX900-GISEL-LABEL: v_log2_v2f16_fast:
; GFX900-GISEL: ; %bb.0: ; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: v_log_f16_e32 v1, v0 ; GFX900-GISEL-NEXT: v_log_f16_e32 v1, v0
; GFX900-GISEL-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; GFX900-GISEL-NEXT: v_log_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v0 ; GFX900-GISEL-NEXT: v_pack_b32_f16 v0, v1, v0
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX1100-LABEL: v_log2_v2f16_fast:
; GFX1100: ; %bb.0:
; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1100-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1100-NEXT: v_log_f16_e32 v0, v0
; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1100-NEXT: v_log_f16_e32 v1, v1
; GFX1100-NEXT: s_waitcnt_depctr 0xfff
; GFX1100-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX1100-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log2_v2f16_fast: ; R600-LABEL: v_log2_v2f16_fast:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_log2_v2f16_fast: ; CM-LABEL: v_log2_v2f16_fast:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
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llvm/test/CodeGen/AMDGPU/llvm.powi.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii < %s | FileCheck -check-prefixes=GCN,GFX7 %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii < %s | FileCheck -check-prefixes=GFX78,GFX7 %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8 %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck -check-prefixes=GFX78,GFX8 %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
define i16 @v_powi_f16(i16 %l, i32 %r) { define i16 @v_powi_f16(i16 %l, i32 %r) {
; GCN-LABEL: v_powi_f16: ; GFX78-LABEL: v_powi_f16:
; GCN: ; %bb.0: ; GFX78: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX78-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX78-NEXT: v_cvt_f32_f16_e32 v0, v0
; GCN-NEXT: v_cvt_f32_i32_e32 v1, v1 ; GFX78-NEXT: v_cvt_f32_i32_e32 v1, v1
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX78-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 ; GFX78-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
; GCN-NEXT: v_exp_f32_e32 v0, v0 ; GFX78-NEXT: v_exp_f32_e32 v0, v0
; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX78-NEXT: v_cvt_f16_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX78-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_powi_f16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX11-NEXT: v_cvt_f32_i32_e32 v1, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_log_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
; GFX11-NEXT: v_exp_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%l.cast = bitcast i16 %l to half %l.cast = bitcast i16 %l to half
%res = call half @llvm.powi.f16.i32(half %l.cast, i32 %r) %res = call half @llvm.powi.f16.i32(half %l.cast, i32 %r)
%res.cast = bitcast half %res to i16 %res.cast = bitcast half %res to i16
ret i16 %res.cast ret i16 %res.cast
} }
define float @v_powi_f32(float %l, i32 %r) { define float @v_powi_f32(float %l, i32 %r) {
; GCN-LABEL: v_powi_f32: ; GFX78-LABEL: v_powi_f32:
; GCN: ; %bb.0: ; GFX78: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX78-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_log_f32_e32 v0, v0 ; GFX78-NEXT: v_log_f32_e32 v0, v0
; GCN-NEXT: v_cvt_f32_i32_e32 v1, v1 ; GFX78-NEXT: v_cvt_f32_i32_e32 v1, v1
; GCN-NEXT: v_mul_legacy_f32_e32 v0, v1, v0 ; GFX78-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
; GCN-NEXT: v_exp_f32_e32 v0, v0 ; GFX78-NEXT: v_exp_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX78-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_powi_f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_log_f32_e32 v0, v0
; GFX11-NEXT: v_cvt_f32_i32_e32 v1, v1
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%res = call float @llvm.powi.f32.i32(float %l, i32 %r) %res = call float @llvm.powi.f32.i32(float %l, i32 %r)
ret float %res ret float %res
} }
define float @v_powi_0_f32(float %l) { define float @v_powi_0_f32(float %l) {
; GCN-LABEL: v_powi_0_f32: ; GFX78-LABEL: v_powi_0_f32:
; GCN: ; %bb.0: ; GFX78: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX78-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, 1.0 ; GFX78-NEXT: v_mov_b32_e32 v0, 1.0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX78-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_powi_0_f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_mov_b32_e32 v0, 1.0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%res = call float @llvm.powi.f32.i32(float %l, i32 0) %res = call float @llvm.powi.f32.i32(float %l, i32 0)
ret float %res ret float %res
} }
define float @v_powi_1_f32(float %l) { define float @v_powi_1_f32(float %l) {
; GCN-LABEL: v_powi_1_f32: ; GFX78-LABEL: v_powi_1_f32:
; GCN: ; %bb.0: ; GFX78: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX78-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX78-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_powi_1_f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%res = call float @llvm.powi.f32.i32(float %l, i32 1) %res = call float @llvm.powi.f32.i32(float %l, i32 1)
ret float %res ret float %res
} }
define float @v_powi_neg1_f32(float %l) { define float @v_powi_neg1_f32(float %l) {
; GFX7-LABEL: v_powi_neg1_f32: ; GFX7-LABEL: v_powi_neg1_f32:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8-NEXT: v_fma_f32 v3, v4, v3, v3 ; GFX8-NEXT: v_fma_f32 v3, v4, v3, v3
; GFX8-NEXT: v_mul_f32_e32 v4, v2, v3 ; GFX8-NEXT: v_mul_f32_e32 v4, v2, v3
; GFX8-NEXT: v_fma_f32 v5, -v1, v4, v2 ; GFX8-NEXT: v_fma_f32 v5, -v1, v4, v2
; GFX8-NEXT: v_fma_f32 v4, v5, v3, v4 ; GFX8-NEXT: v_fma_f32 v4, v5, v3, v4
; GFX8-NEXT: v_fma_f32 v1, -v1, v4, v2 ; GFX8-NEXT: v_fma_f32 v1, -v1, v4, v2
; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v4 ; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v4
; GFX8-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0 ; GFX8-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_powi_neg1_f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_div_scale_f32 v1, null, v0, v0, 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_rcp_f32_e32 v2, v1
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_fma_f32 v3, -v1, v2, 1.0
; GFX11-NEXT: v_fmac_f32_e32 v2, v3, v2
; GFX11-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v0, 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_f32_e32 v4, v3, v2
; GFX11-NEXT: v_fma_f32 v5, -v1, v4, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fmac_f32_e32 v4, v5, v2
; GFX11-NEXT: v_fma_f32 v1, -v1, v4, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_div_fmas_f32 v1, v1, v2, v4
; GFX11-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%res = call float @llvm.powi.f32.i32(float %l, i32 -1) %res = call float @llvm.powi.f32.i32(float %l, i32 -1)
ret float %res ret float %res
} }
define float @v_powi_2_f32(float %l) { define float @v_powi_2_f32(float %l) {
; GCN-LABEL: v_powi_2_f32: ; GFX78-LABEL: v_powi_2_f32:
; GCN: ; %bb.0: ; GFX78: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX78-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mul_f32_e32 v0, v0, v0 ; GFX78-NEXT: v_mul_f32_e32 v0, v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX78-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_powi_2_f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%res = call float @llvm.powi.f32.i32(float %l, i32 2) %res = call float @llvm.powi.f32.i32(float %l, i32 2)
ret float %res ret float %res
} }
define float @v_powi_neg2_f32(float %l) { define float @v_powi_neg2_f32(float %l) {
; GFX7-LABEL: v_powi_neg2_f32: ; GFX7-LABEL: v_powi_neg2_f32:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8-NEXT: v_fma_f32 v3, v4, v3, v3 ; GFX8-NEXT: v_fma_f32 v3, v4, v3, v3
; GFX8-NEXT: v_mul_f32_e32 v4, v2, v3 ; GFX8-NEXT: v_mul_f32_e32 v4, v2, v3
; GFX8-NEXT: v_fma_f32 v5, -v1, v4, v2 ; GFX8-NEXT: v_fma_f32 v5, -v1, v4, v2
; GFX8-NEXT: v_fma_f32 v4, v5, v3, v4 ; GFX8-NEXT: v_fma_f32 v4, v5, v3, v4
; GFX8-NEXT: v_fma_f32 v1, -v1, v4, v2 ; GFX8-NEXT: v_fma_f32 v1, -v1, v4, v2
; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v4 ; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v4
; GFX8-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0 ; GFX8-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_powi_neg2_f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_div_scale_f32 v1, null, v0, v0, 1.0
; GFX11-NEXT: v_rcp_f32_e32 v2, v1
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_fma_f32 v3, -v1, v2, 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fmac_f32_e32 v2, v3, v2
; GFX11-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v0, 1.0
; GFX11-NEXT: v_mul_f32_e32 v4, v3, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fma_f32 v5, -v1, v4, v3
; GFX11-NEXT: v_fmac_f32_e32 v4, v5, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fma_f32 v1, -v1, v4, v3
; GFX11-NEXT: v_div_fmas_f32 v1, v1, v2, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%res = call float @llvm.powi.f32.i32(float %l, i32 -2) %res = call float @llvm.powi.f32.i32(float %l, i32 -2)
ret float %res ret float %res
} }
define float @v_powi_4_f32(float %l) { define float @v_powi_4_f32(float %l) {
; GCN-LABEL: v_powi_4_f32: ; GFX78-LABEL: v_powi_4_f32:
; GCN: ; %bb.0: ; GFX78: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX78-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mul_f32_e32 v0, v0, v0 ; GFX78-NEXT: v_mul_f32_e32 v0, v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, v0, v0 ; GFX78-NEXT: v_mul_f32_e32 v0, v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX78-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_powi_4_f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%res = call float @llvm.powi.f32.i32(float %l, i32 4) %res = call float @llvm.powi.f32.i32(float %l, i32 4)
ret float %res ret float %res
} }
define float @v_powi_8_f32(float %l) { define float @v_powi_8_f32(float %l) {
; GCN-LABEL: v_powi_8_f32: ; GFX78-LABEL: v_powi_8_f32:
; GCN: ; %bb.0: ; GFX78: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX78-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mul_f32_e32 v0, v0, v0 ; GFX78-NEXT: v_mul_f32_e32 v0, v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, v0, v0 ; GFX78-NEXT: v_mul_f32_e32 v0, v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, v0, v0 ; GFX78-NEXT: v_mul_f32_e32 v0, v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX78-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_powi_8_f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v0
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%res = call float @llvm.powi.f32.i32(float %l, i32 8) %res = call float @llvm.powi.f32.i32(float %l, i32 8)
ret float %res ret float %res
} }
define float @v_powi_16_f32(float %l) { define float @v_powi_16_f32(float %l) {
; GCN-LABEL: v_powi_16_f32: ; GFX78-LABEL: v_powi_16_f32:
; GCN: ; %bb.0: ; GFX78: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX78-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mul_f32_e32 v0, v0, v0 ; GFX78-NEXT: v_mul_f32_e32 v0, v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, v0, v0 ; GFX78-NEXT: v_mul_f32_e32 v0, v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, v0, v0 ; GFX78-NEXT: v_mul_f32_e32 v0, v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, v0, v0 ; GFX78-NEXT: v_mul_f32_e32 v0, v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX78-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_powi_16_f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v0
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%res = call float @llvm.powi.f32.i32(float %l, i32 16) %res = call float @llvm.powi.f32.i32(float %l, i32 16)
ret float %res ret float %res
} }
define float @v_powi_128_f32(float %l) { define float @v_powi_128_f32(float %l) {
; GCN-LABEL: v_powi_128_f32: ; GFX78-LABEL: v_powi_128_f32:
; GCN: ; %bb.0: ; GFX78: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX78-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mul_f32_e32 v0, v0, v0 ; GFX78-NEXT: v_mul_f32_e32 v0, v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, v0, v0 ; GFX78-NEXT: v_mul_f32_e32 v0, v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, v0, v0 ; GFX78-NEXT: v_mul_f32_e32 v0, v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, v0, v0 ; GFX78-NEXT: v_mul_f32_e32 v0, v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, v0, v0 ; GFX78-NEXT: v_mul_f32_e32 v0, v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, v0, v0 ; GFX78-NEXT: v_mul_f32_e32 v0, v0, v0
; GCN-NEXT: v_mul_f32_e32 v0, v0, v0 ; GFX78-NEXT: v_mul_f32_e32 v0, v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GFX78-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_powi_128_f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v0
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v0
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v0
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%res = call float @llvm.powi.f32.i32(float %l, i32 128) %res = call float @llvm.powi.f32.i32(float %l, i32 128)
ret float %res ret float %res
} }
define float @v_powi_neg128_f32(float %l) { define float @v_powi_neg128_f32(float %l) {
; GFX7-LABEL: v_powi_neg128_f32: ; GFX7-LABEL: v_powi_neg128_f32:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX8-NEXT: v_fma_f32 v3, v4, v3, v3 ; GFX8-NEXT: v_fma_f32 v3, v4, v3, v3
; GFX8-NEXT: v_mul_f32_e32 v4, v2, v3 ; GFX8-NEXT: v_mul_f32_e32 v4, v2, v3
; GFX8-NEXT: v_fma_f32 v5, -v1, v4, v2 ; GFX8-NEXT: v_fma_f32 v5, -v1, v4, v2
; GFX8-NEXT: v_fma_f32 v4, v5, v3, v4 ; GFX8-NEXT: v_fma_f32 v4, v5, v3, v4
; GFX8-NEXT: v_fma_f32 v1, -v1, v4, v2 ; GFX8-NEXT: v_fma_f32 v1, -v1, v4, v2
; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v4 ; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v4
; GFX8-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0 ; GFX8-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_powi_neg128_f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v0
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v0
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v0
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_div_scale_f32 v1, null, v0, v0, 1.0
; GFX11-NEXT: v_rcp_f32_e32 v2, v1
; GFX11-NEXT: s_waitcnt_depctr 0xfff
; GFX11-NEXT: v_fma_f32 v3, -v1, v2, 1.0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fmac_f32_e32 v2, v3, v2
; GFX11-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v0, 1.0
; GFX11-NEXT: v_mul_f32_e32 v4, v3, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fma_f32 v5, -v1, v4, v3
; GFX11-NEXT: v_fmac_f32_e32 v4, v5, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_fma_f32 v1, -v1, v4, v3
; GFX11-NEXT: v_div_fmas_f32 v1, v1, v2, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%res = call float @llvm.powi.f32.i32(float %l, i32 -128) %res = call float @llvm.powi.f32.i32(float %l, i32 -128)
ret float %res ret float %res
} }
; FIXME: f64 broken ; FIXME: f64 broken
; define double @v_powi_f64(double %l, i32 %r) { ; define double @v_powi_f64(double %l, i32 %r) {
; %res = call double @llvm.powi.f64.i32(double %l, i32 %r) ; %res = call double @llvm.powi.f64.i32(double %l, i32 %r)
; ret double %res ; ret double %res
; } ; }
declare half @llvm.powi.f16.i32(half, i32) #0 declare half @llvm.powi.f16.i32(half, i32) #0
declare float @llvm.powi.f32.i32(float, i32) #0 declare float @llvm.powi.f32.i32(float, i32) #0
declare double @llvm.powi.f64.i32(double, i32) #0 declare double @llvm.powi.f64.i32(double, i32) #0
attributes #0 = { nounwind readnone speculatable willreturn } attributes #0 = { nounwind readnone speculatable willreturn }