[LV] Add option to tune the cost model, NFC

[Allen]

Summary

For Neon, the default nonconst stride cost is conservative,
and it is a local variable, which is not convenience to
to tune the loop vectorize.
So I try to use a option, which is similar to SVEGatherOverhead brought in D115143.

[dmgreen]

Sounds OK to me. Feel free to add an option for MaxMergeDistance too if it is useful.

[fhahn]

Could you please add a test for the flag?

[Allen]

Add a test for -neon-nonconst-stride-overhead=5

[Allen]

In D152253#4399006, @fhahn wrote:

Could you please add a test for the flag?

Done, thanks

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

                                            cl::Hidden);
 
 static cl::opt<unsigned> SVEScatterOverhead("sve-scatter-overhead",
                                             cl::init(10), cl::Hidden);
 
 static cl::opt<unsigned> SVETailFoldInsnThreshold("sve-tail-folding-insn-threshold",
                                                   cl::init(15), cl::Hidden);
 
+static cl::opt<unsigned>
+    NeonNonConstStrideOverhead("neon-nonconst-stride-overhead", cl::init(10),
+                               cl::Hidden);
+
 namespace {
 class TailFoldingOption {
   // These bitfields will only ever be set to something non-zero in operator=,
   // when setting the -sve-tail-folding option. This option should always be of
   // the form (default|simple|all|disable)[+(Flag1|Flag2|etc)], where here
   // InitialBits is one of (disabled|all|simple). EnableBits represents
   // additional flags we're enabling, and DisableBits for those flags we're
   // disabling. The default flag is tracked in the variable NeedsDefault, since

 
 InstructionCost AArch64TTIImpl::getAddressComputationCost(Type *Ty,
                                                           ScalarEvolution *SE,
                                                           const SCEV *Ptr) {
   // Address computations in vectorized code with non-consecutive addresses will
   // likely result in more instructions compared to scalar code where the
   // computation can more often be merged into the index mode. The resulting
   // extra micro-ops can significantly decrease throughput.
-  unsigned NumVectorInstToHideOverhead = 10;
+  unsigned NumVectorInstToHideOverhead = NeonNonConstStrideOverhead;
   int MaxMergeDistance = 64;
 
   if (Ty->isVectorTy() && SE &&
       !BaseT::isConstantStridedAccessLessThan(SE, Ptr, MaxMergeDistance + 1))
     return NumVectorInstToHideOverhead;
 
   // In many cases the address computation is not merged into the instruction
   // addressing mode.