This is an archive of the discontinued LLVM Phabricator instance.

Differential D151285

[MC] Check if register is non-null before calling isSubRegisterEq (NFCI)
ClosedPublic

Authored by barannikov88 on May 23 2023, 9:15 PM.

Details

Reviewers
Amir
rafauler
maksfb
Commits
rGee1d5f637286: [MC] Check if register is non-null before calling isSubRegisterEq (NFCI)
Summary

D151036 adds an assertions that prohibits iterating over sub- and
super-registers of a null register. This is already the case when
iterating over register units of a null register, and worked by
accident for sub- and super-registers.

Diff Detail

Event Timeline

barannikov88 created this revision.May 23 2023, 9:15 PM
Herald added a reviewer: rafauler. · View Herald TranscriptMay 23 2023, 9:15 PM
Herald added a reviewer: maksfb. · View Herald Transcript
Herald added a project: Restricted Project. · View Herald Transcript
Herald added subscribers: ayermolo, hiraditya. · View Herald Transcript
barannikov88 requested review of this revision.May 23 2023, 9:15 PM
Herald added a project: Restricted Project. · View Herald TranscriptMay 23 2023, 9:15 PM
Herald added subscribers: llvm-commits, yota9. · View Herald Transcript
barannikov88 mentioned this in D151036: [CodeGen] Fix incorrect usage of MCPhysReg for diff list elements.May 23 2023, 9:17 PM
barannikov88 added a child revision: D151036: [CodeGen] Fix incorrect usage of MCPhysReg for diff list elements.May 23 2023, 9:18 PM
Harbormaster completed remote builds in B234067: Diff 524992.May 23 2023, 9:35 PM
barannikov88 updated this revision to Diff 524994.May 23 2023, 9:41 PM

Fix typo

barannikov88 added a child revision: D151288: [MIPS] Check if register is non-null before calling isSuperOrSubRegisterEq (NFCI).May 23 2023, 10:08 PM
barannikov88 removed a child revision: D151036: [CodeGen] Fix incorrect usage of MCPhysReg for diff list elements.
Harbormaster completed remote builds in B234069: Diff 524994.May 23 2023, 10:12 PM
barannikov88 updated this revision to Diff 525035.May 24 2023, 12:27 AM

Rebase onto 8e16365c to get a green mark

barannikov88 added a child revision: D151036: [CodeGen] Fix incorrect usage of MCPhysReg for diff list elements.May 24 2023, 12:28 AM
barannikov88 removed a child revision: D151288: [MIPS] Check if register is non-null before calling isSuperOrSubRegisterEq (NFCI).
Harbormaster completed remote builds in B234101: Diff 525035.May 24 2023, 1:15 AM
Amir accepted this revision.May 24 2023, 10:25 PM
This revision is now accepted and ready to land.May 24 2023, 10:25 PM
Closed by commit rGee1d5f637286: [MC] Check if register is non-null before calling isSubRegisterEq (NFCI) (authored by barannikov88). · Explain WhyMay 24 2023, 10:53 PM
This revision was automatically updated to reflect the committed changes.
barannikov88 added a commit: rGee1d5f637286: [MC] Check if register is non-null before calling isSubRegisterEq (NFCI).

Revision Contents

PathSize
bolt/
lib/
Core/
2 lines
llvm/
lib/
MC/
2 lines

Diff 524994

bolt/lib/Core/MCPlusBuilder.cpp

Show First 20 Lines • Show All 419 Lines • ▼ Show 20 Lines
bool MCPlusBuilder::hasDefOfPhysReg(const MCInst &MI, unsigned Reg) const { bool MCPlusBuilder::hasDefOfPhysReg(const MCInst &MI, unsigned Reg) const {
const MCInstrDesc &InstInfo = Info->get(MI.getOpcode()); const MCInstrDesc &InstInfo = Info->get(MI.getOpcode());
return InstInfo.hasDefOfPhysReg(MI, Reg, *RegInfo); return InstInfo.hasDefOfPhysReg(MI, Reg, *RegInfo);
} }
bool MCPlusBuilder::hasUseOfPhysReg(const MCInst &MI, unsigned Reg) const { bool MCPlusBuilder::hasUseOfPhysReg(const MCInst &MI, unsigned Reg) const {
const MCInstrDesc &InstInfo = Info->get(MI.getOpcode()); const MCInstrDesc &InstInfo = Info->get(MI.getOpcode());
for (int I = InstInfo.NumDefs; I < InstInfo.NumOperands; ++I) for (int I = InstInfo.NumDefs; I < InstInfo.NumOperands; ++I)
if (MI.getOperand(I).isReg() && if (MI.getOperand(I).isReg() && MI.getOperand(I).getReg() &&
RegInfo->isSubRegisterEq(Reg, MI.getOperand(I).getReg())) RegInfo->isSubRegisterEq(Reg, MI.getOperand(I).getReg()))
return true; return true;
for (MCPhysReg ImplicitUse : InstInfo.implicit_uses()) { for (MCPhysReg ImplicitUse : InstInfo.implicit_uses()) {
if (ImplicitUse == Reg || RegInfo->isSubRegister(Reg, ImplicitUse)) if (ImplicitUse == Reg || RegInfo->isSubRegister(Reg, ImplicitUse))
return true; return true;
} }
return false; return false;
} }
▲ Show 20 Lines • Show All 70 Lines • Show Last 20 Lines

llvm/lib/MC/MCInstrDesc.cpp

Show All 34 Lines for (MCPhysReg ImpDef : implicit_defs())
if (ImpDef == Reg || (MRI && MRI->isSubRegister(Reg, ImpDef))) if (ImpDef == Reg || (MRI && MRI->isSubRegister(Reg, ImpDef)))
return true; return true;
return false; return false;
} }
bool MCInstrDesc::hasDefOfPhysReg(const MCInst &MI, unsigned Reg, bool MCInstrDesc::hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
const MCRegisterInfo &RI) const { const MCRegisterInfo &RI) const {
for (int i = 0, e = NumDefs; i != e; ++i) for (int i = 0, e = NumDefs; i != e; ++i)
if (MI.getOperand(i).isReg() && if (MI.getOperand(i).isReg() && MI.getOperand(i).getReg() &&
RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg())) RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
return true; return true;
if (variadicOpsAreDefs()) if (variadicOpsAreDefs())
for (int i = NumOperands - 1, e = MI.getNumOperands(); i != e; ++i) for (int i = NumOperands - 1, e = MI.getNumOperands(); i != e; ++i)
if (MI.getOperand(i).isReg() && if (MI.getOperand(i).isReg() &&
RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg())) RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
return true; return true;
return hasImplicitDefOfPhysReg(Reg, &RI); return hasImplicitDefOfPhysReg(Reg, &RI);
} }