[RISCV] Increase scalar integer divide latency for SiFive7.

[craig.topper]

Summary

The scalar divider produces 1 bit per cycle so the worst case
latency is the input width plus a couple cycles.

[michaelmaitland]

llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

201–202

1 bit per cycle so the worst case latency is the input width plus a couple cycles.

Why does latency take 2 extra cycles and resource cycles is only 1 extra cycle?

[craig.topper]

llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

201–202

I might still have the numbers off by a couple cycles, but it's probably better than being off by a factor of 2 or 4. They were already 1 apart so I left them 1 apart. This is what's currently in our downstream.

The basic idea is that there is one pipeline stage in the divider that is used repeatedly in a loop. There is 1-2 stages in front of that and 1-2 stages after that. Two divides can't overlap in the repeated part but we might be able to start a new divide while the previous divide is still in the stages after the repeated part. The ResourceCycles for SiFive7IDiv is intended to track the number of cycles that can't overlap. Unfortunately, I don't have the exact number for how much they can overlap.

[michaelmaitland]

LGTM.

llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

 // Integer multiplication
 let Latency = 3 in {
 def : WriteRes<WriteIMul, [SiFive7PipeB]>;
 def : WriteRes<WriteIMul32, [SiFive7PipeB]>;
 }
 
 // Integer division
 def : WriteRes<WriteIDiv, [SiFive7PipeB, SiFive7IDiv]> {
-  let Latency = 16;
-  let ResourceCycles = [1, 15];
+  let Latency = 66;
+  let ResourceCycles = [1, 65];
 }
 def : WriteRes<WriteIDiv32,  [SiFive7PipeB, SiFive7IDiv]> {
-  let Latency = 16;
-  let ResourceCycles = [1, 15];
+  let Latency = 34;
+  let ResourceCycles = [1, 33];
 }
 
 // Bitmanip
 let Latency = 3 in {
 // Rotates are in the late-B ALU.
 def : WriteRes<WriteRotateImm, [SiFive7PipeB]>;
 def : WriteRes<WriteRotateImm32, [SiFive7PipeB]>;
 def : WriteRes<WriteRotateReg, [SiFive7PipeB]>;