[KnownBits] Return zero instead of unknown for always poison shifts

[nikic]

Summary

For always poison shifts, any KnownBits return value is valid. Currently we return unknown, but returning zero is generally more profitable. We had some code in ValueTracking that tried to do this, but was actually dead code.

[foad]

Shouldn't something have simplified these shifts to poison already?

No objection to the patch.

[nikic]

In D150648#4345159, @foad wrote:

Shouldn't something have simplified these shifts to poison already?

No objection to the patch.

On the IR level, yes, we do that here: https://github.com/llvm/llvm-project/blob/bba9209f1d198efc7e492f0e273fff0b0a5ef060/llvm/lib/Analysis/InstructionSimplify.cpp#L1361-L1365 The changes in InstCombine are because the shift is a constant expression, so these don't get simplified (until I get around to removing support for shift expressions...) The backend doesn't have something equivalent (and probably shouldn't have it -- doesn't seem like something that is valuable enough to compute known bits for).

[goldstein.w.n]

Think this makes sense. Don't think I really have the domain knowledge to approve though.

[nikic]

Ping :)

[foad]

LGTM

llvm/lib/Analysis/ValueTracking.cpp

static void computeKnownBitsFromShiftOperator(
   // limit value (which implies all bits are known).
   uint64_t ShiftAmtKZ = Known.Zero.zextOrTrunc(64).getZExtValue();
   uint64_t ShiftAmtKO = Known.One.zextOrTrunc(64).getZExtValue();
   bool ShiftAmtIsConstant = Known.isConstant();
   bool MaxShiftAmtIsOutOfRange = Known.getMaxValue().uge(BitWidth);
 
   if (ShiftAmtIsConstant) {
     Known = KF(Known2, Known);
-
-    // If the known bits conflict, this must be an overflowing left shift, so
-    // the shift result is poison. We can return anything we want. Choose 0 for
-    // the best folding opportunity.
-    if (Known.hasConflict())
-      Known.setAllZero();
-
     return;
   }
 
   // If the shift amount could be greater than or equal to the bit-width of the
   // LHS, the value could be poison, but bail out because the check below is
   // expensive.
   // TODO: Should we just carry on?
   if (MaxShiftAmtIsOutOfRange) {

llvm/lib/Support/KnownBits.cpp

if (RHS.isConstant() && RHS.getConstant().ult(BitWidth)) {
     Known.Zero.setLowBits(Shift);
     return Known;
   }
 
   // No matter the shift amount, the trailing zeros will stay zero.
   unsigned MinTrailingZeros = LHS.countMinTrailingZeros();
 
   APInt MinShiftAmount = RHS.getMinValue();
-  if (MinShiftAmount.uge(BitWidth))
-    // Always poison. Return unknown because we don't like returning conflict.
+  if (MinShiftAmount.uge(BitWidth)) {
+    // Always poison. Return zero because we don't like returning conflict.
+    Known.setAllZero();
     return Known;
+  }
 
   // Minimum shift amount low bits are known zero.
   MinTrailingZeros += MinShiftAmount.getZExtValue();
   MinTrailingZeros = std::min(MinTrailingZeros, BitWidth);
 
   // If the maximum shift is in range, then find the common bits from all
   // possible shifts.
   APInt MaxShiftAmount = RHS.getMaxValue();
if (RHS.isConstant() && RHS.getConstant().ult(BitWidth)) {
     return Known;
   }
 
   // No matter the shift amount, the leading zeros will stay zero.
   unsigned MinLeadingZeros = LHS.countMinLeadingZeros();
 
   // Minimum shift amount high bits are known zero.
   APInt MinShiftAmount = RHS.getMinValue();
-  if (MinShiftAmount.uge(BitWidth))
-    // Always poison. Return unknown because we don't like returning conflict.
+  if (MinShiftAmount.uge(BitWidth)) {
+    // Always poison. Return zero because we don't like returning conflict.
+    Known.setAllZero();
     return Known;
+  }
 
   MinLeadingZeros += MinShiftAmount.getZExtValue();
   MinLeadingZeros = std::min(MinLeadingZeros, BitWidth);
 
   // If the maximum shift is in range, then find the common bits from all
   // possible shifts.
   APInt MaxShiftAmount = RHS.getMaxValue();
   if (!LHS.isUnknown()) {
KnownBits KnownBits::ashr(const KnownBits &LHS, const KnownBits &RHS) {
   }
 
   // No matter the shift amount, the leading sign bits will stay.
   unsigned MinLeadingZeros = LHS.countMinLeadingZeros();
   unsigned MinLeadingOnes = LHS.countMinLeadingOnes();
 
   // Minimum shift amount high bits are known sign bits.
   APInt MinShiftAmount = RHS.getMinValue();
-  if (MinShiftAmount.uge(BitWidth))
-    // Always poison. Return unknown because we don't like returning conflict.
+  if (MinShiftAmount.uge(BitWidth)) {
+    // Always poison. Return zero because we don't like returning conflict.
+    Known.setAllZero();
     return Known;
+  }
 
   if (MinLeadingZeros) {
     MinLeadingZeros += MinShiftAmount.getZExtValue();
     MinLeadingZeros = std::min(MinLeadingZeros, BitWidth);
   }
   if (MinLeadingOnes) {
     MinLeadingOnes += MinShiftAmount.getZExtValue();
     MinLeadingOnes = std::min(MinLeadingOnes, BitWidth);

llvm/test/Analysis/ScalarEvolution/ashr.ll

;
   %i0 = ashr exact i32 %x, 4
   ret i32 %i0
 }
 ; As long as the shift amount is in-bounds
 define i32 @t4(i32 %x, i32 %y) {
 ; CHECK-LABEL: 't4'
 ; CHECK-NEXT:  Classifying expressions for: @t4
 ; CHECK-NEXT:    %i0 = ashr exact i32 %x, 32
-; CHECK-NEXT:    --> %i0 U: full-set S: full-set
+; CHECK-NEXT:    --> %i0 U: [0,1) S: [0,1)
 ; CHECK-NEXT:  Determining loop execution counts for: @t4
 ;
   %i0 = ashr exact i32 %x, 32
   ret i32 %i0
 }
 
 ; One more test, just to see that we model constant correctly
 define i32 @t5(i32 %x, i32 %y) {

llvm/test/CodeGen/AArch64/GlobalISel/form-bitfield-extract-from-sextinreg.mir

bb.0:
     ; LSB must be in 0-31.
 
     ; CHECK-LABEL: name: dont_apply_shift_imm_too_large
     ; CHECK: liveins: $w0
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %x:_(s32) = COPY $w0
     ; CHECK-NEXT: %lsb:_(s32) = G_CONSTANT i32 32
     ; CHECK-NEXT: %shift:_(s32) = G_ASHR %x, %lsb(s32)
-    ; CHECK-NEXT: %sext_inreg:_(s32) = G_SEXT_INREG %shift, 1
-    ; CHECK-NEXT: $w0 = COPY %sext_inreg(s32)
+    ; CHECK-NEXT: $w0 = COPY %shift(s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %x:_(s32) = COPY $w0
     %lsb:_(s32) = G_CONSTANT i32 32
     %shift:_(s32) = G_ASHR %x, %lsb
     %sext_inreg:_(s32) = G_SEXT_INREG %shift, 1
     $w0 = COPY %sext_inreg
     RET_ReallyLR implicit $w0
 
bb.0:
     ; LSB must be in 0-31.
 
     ; CHECK-LABEL: name: dont_apply_negative_shift_imm
     ; CHECK: liveins: $w0
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %x:_(s32) = COPY $w0
     ; CHECK-NEXT: %lsb:_(s32) = G_CONSTANT i32 -1
     ; CHECK-NEXT: %shift:_(s32) = G_ASHR %x, %lsb(s32)
-    ; CHECK-NEXT: %sext_inreg:_(s32) = G_SEXT_INREG %shift, 1
-    ; CHECK-NEXT: $w0 = COPY %sext_inreg(s32)
+    ; CHECK-NEXT: $w0 = COPY %shift(s32)
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %x:_(s32) = COPY $w0
     %lsb:_(s32) = G_CONSTANT i32 -1
     %shift:_(s32) = G_ASHR %x, %lsb
     %sext_inreg:_(s32) = G_SEXT_INREG %shift, 1
     $w0 = COPY %sext_inreg
     RET_ReallyLR implicit $w0
 

llvm/test/CodeGen/LoongArch/rotl-rotr.ll

; LA64-NEXT:    ret
   %e = lshr i64 %x, %d
   %f = or i64 %b, %e
   ret i64 %f
 }
 
 define i64 @rotl_64_mask_or_128_or_64(i64 %x, i64 %y) nounwind {
 ; LA32-LABEL: rotl_64_mask_or_128_or_64:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    sll.w $a3, $a0, $a2
 ; LA32-NEXT:    sub.w $a0, $zero, $a2
 ; LA32-NEXT:    srl.w $a0, $a1, $a0
-; LA32-NEXT:    move $a1, $a3
+; LA32-NEXT:    move $a1, $zero
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: rotl_64_mask_or_128_or_64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    sub.d $a1, $zero, $a1
 ; LA64-NEXT:    rotr.d $a0, $a0, $a1
 ; LA64-NEXT:    ret
   %a = or i64 %y, 128
; LA64-NEXT:    ret
   %e = shl i64 %x, %d
   %f = or i64 %b, %e
   ret i64 %f
 }
 
 define i64 @rotr_64_mask_or_128_or_64(i64 %x, i64 %y) nounwind {
 ; LA32-LABEL: rotr_64_mask_or_128_or_64:
 ; LA32:       # %bb.0:
-; LA32-NEXT:    srl.w $a3, $a1, $a2
-; LA32-NEXT:    sub.w $a1, $zero, $a2
-; LA32-NEXT:    sll.w $a1, $a0, $a1
-; LA32-NEXT:    move $a0, $a3
+; LA32-NEXT:    srl.w $a0, $a1, $a2
+; LA32-NEXT:    move $a1, $zero
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: rotr_64_mask_or_128_or_64:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    rotr.d $a0, $a0, $a1
 ; LA64-NEXT:    ret
   %a = or i64 %y, 128
   %b = lshr i64 %x, %a

llvm/test/CodeGen/RISCV/rotl-rotr.ll

; RV64XTHEADBB-NEXT:    ret
   %e = lshr i32 %x, %d
   %f = or i32 %b, %e
   ret i32 %f
 }
 
 define i32 @rotl_32_mask_or_64_or_32(i32 %x, i32 %y) nounwind {
 ; RV32I-LABEL: rotl_32_mask_or_64_or_32:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    ori a2, a1, 64
-; RV32I-NEXT:    sll a2, a0, a2
 ; RV32I-NEXT:    neg a1, a1
 ; RV32I-NEXT:    ori a1, a1, 32
 ; RV32I-NEXT:    srl a0, a0, a1
-; RV32I-NEXT:    or a0, a2, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: rotl_32_mask_or_64_or_32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    sllw a2, a0, a1
 ; RV64I-NEXT:    negw a1, a1
 ; RV64I-NEXT:    srlw a0, a0, a1
-; RV64I-NEXT:    or a0, a2, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: rotl_32_mask_or_64_or_32:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    rol a0, a0, a1
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: rotl_32_mask_or_64_or_32:
; RV64XTHEADBB-NEXT:    ret
   %e = shl i32 %x, %d
   %f = or i32 %b, %e
   ret i32 %f
 }
 
 define i32 @rotr_32_mask_or_64_or_32(i32 %x, i32 %y) nounwind {
 ; RV32I-LABEL: rotr_32_mask_or_64_or_32:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    ori a2, a1, 64
-; RV32I-NEXT:    srl a2, a0, a2
-; RV32I-NEXT:    neg a1, a1
-; RV32I-NEXT:    ori a1, a1, 32
-; RV32I-NEXT:    sll a0, a0, a1
-; RV32I-NEXT:    or a0, a2, a0
+; RV32I-NEXT:    ori a1, a1, 64
+; RV32I-NEXT:    srl a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: rotr_32_mask_or_64_or_32:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    srlw a2, a0, a1
-; RV64I-NEXT:    negw a1, a1
-; RV64I-NEXT:    sllw a0, a0, a1
-; RV64I-NEXT:    or a0, a2, a0
+; RV64I-NEXT:    srlw a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: rotr_32_mask_or_64_or_32:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    ror a0, a0, a1
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: rotr_32_mask_or_64_or_32:
; RV64XTHEADBB-NEXT:    ret
   %e = lshr i64 %x, %d
   %f = or i64 %b, %e
   ret i64 %f
 }
 
 define i64 @rotl_64_mask_or_128_or_64(i64 %x, i64 %y) nounwind {
 ; RV32I-LABEL: rotl_64_mask_or_128_or_64:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    sll a3, a0, a2
 ; RV32I-NEXT:    neg a0, a2
 ; RV32I-NEXT:    srl a0, a1, a0
-; RV32I-NEXT:    mv a1, a3
+; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: rotl_64_mask_or_128_or_64:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    ori a2, a1, 128
-; RV64I-NEXT:    sll a2, a0, a2
 ; RV64I-NEXT:    negw a1, a1
 ; RV64I-NEXT:    ori a1, a1, 64
 ; RV64I-NEXT:    srl a0, a0, a1
-; RV64I-NEXT:    or a0, a2, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: rotl_64_mask_or_128_or_64:
 ; RV32ZBB:       # %bb.0:
-; RV32ZBB-NEXT:    sll a3, a0, a2
 ; RV32ZBB-NEXT:    neg a0, a2
 ; RV32ZBB-NEXT:    srl a0, a1, a0
-; RV32ZBB-NEXT:    mv a1, a3
+; RV32ZBB-NEXT:    li a1, 0
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: rotl_64_mask_or_128_or_64:
 ; RV64ZBB:       # %bb.0:
 ; RV64ZBB-NEXT:    rol a0, a0, a1
 ; RV64ZBB-NEXT:    ret
 ;
 ; RV32XTHEADBB-LABEL: rotl_64_mask_or_128_or_64:
 ; RV32XTHEADBB:       # %bb.0:
-; RV32XTHEADBB-NEXT:    sll a3, a0, a2
 ; RV32XTHEADBB-NEXT:    neg a0, a2
 ; RV32XTHEADBB-NEXT:    srl a0, a1, a0
-; RV32XTHEADBB-NEXT:    mv a1, a3
+; RV32XTHEADBB-NEXT:    li a1, 0
 ; RV32XTHEADBB-NEXT:    ret
 ;
 ; RV64XTHEADBB-LABEL: rotl_64_mask_or_128_or_64:
 ; RV64XTHEADBB:       # %bb.0:
 ; RV64XTHEADBB-NEXT:    sll a2, a0, a1
 ; RV64XTHEADBB-NEXT:    neg a1, a1
 ; RV64XTHEADBB-NEXT:    srl a0, a0, a1
 ; RV64XTHEADBB-NEXT:    or a0, a2, a0
; RV64XTHEADBB-NEXT:    ret
   %e = shl i64 %x, %d
   %f = or i64 %b, %e
   ret i64 %f
 }
 
 define i64 @rotr_64_mask_or_128_or_64(i64 %x, i64 %y) nounwind {
 ; RV32I-LABEL: rotr_64_mask_or_128_or_64:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    srl a3, a1, a2
-; RV32I-NEXT:    neg a1, a2
-; RV32I-NEXT:    sll a1, a0, a1
-; RV32I-NEXT:    mv a0, a3
+; RV32I-NEXT:    srl a0, a1, a2
+; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: rotr_64_mask_or_128_or_64:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    ori a2, a1, 128
-; RV64I-NEXT:    srl a2, a0, a2
-; RV64I-NEXT:    negw a1, a1
-; RV64I-NEXT:    ori a1, a1, 64
-; RV64I-NEXT:    sll a0, a0, a1
-; RV64I-NEXT:    or a0, a2, a0
+; RV64I-NEXT:    ori a1, a1, 128
+; RV64I-NEXT:    srl a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: rotr_64_mask_or_128_or_64:
 ; RV32ZBB:       # %bb.0:
-; RV32ZBB-NEXT:    srl a3, a1, a2
-; RV32ZBB-NEXT:    neg a1, a2
-; RV32ZBB-NEXT:    sll a1, a0, a1
-; RV32ZBB-NEXT:    mv a0, a3
+; RV32ZBB-NEXT:    srl a0, a1, a2
+; RV32ZBB-NEXT:    li a1, 0
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: rotr_64_mask_or_128_or_64:
 ; RV64ZBB:       # %bb.0:
 ; RV64ZBB-NEXT:    ror a0, a0, a1
 ; RV64ZBB-NEXT:    ret
 ;
 ; RV32XTHEADBB-LABEL: rotr_64_mask_or_128_or_64:
 ; RV32XTHEADBB:       # %bb.0:
-; RV32XTHEADBB-NEXT:    srl a3, a1, a2
-; RV32XTHEADBB-NEXT:    neg a1, a2
-; RV32XTHEADBB-NEXT:    sll a1, a0, a1
-; RV32XTHEADBB-NEXT:    mv a0, a3
+; RV32XTHEADBB-NEXT:    srl a0, a1, a2
+; RV32XTHEADBB-NEXT:    li a1, 0
 ; RV32XTHEADBB-NEXT:    ret
 ;
 ; RV64XTHEADBB-LABEL: rotr_64_mask_or_128_or_64:
 ; RV64XTHEADBB:       # %bb.0:
 ; RV64XTHEADBB-NEXT:    srl a2, a0, a1
 ; RV64XTHEADBB-NEXT:    neg a1, a1
 ; RV64XTHEADBB-NEXT:    sll a0, a0, a1
 ; RV64XTHEADBB-NEXT:    or a0, a2, a0

llvm/test/Transforms/InstCombine/not-add.ll

cond.end:
   %sub = sub nsw i32 %v3, %cond
   ret i32 %sub
 }
 
 @g = extern_weak global i32
 define void @pr50370(i32 %x) {
 ; CHECK-LABEL: @pr50370(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[XOR:%.*]] = xor i32 [[X:%.*]], 1
-; CHECK-NEXT:    [[B15:%.*]] = srem i32 ashr (i32 65536, i32 or (i32 zext (i1 icmp eq (ptr @g, ptr null) to i32), i32 65537)), [[XOR]]
-; CHECK-NEXT:    [[B12:%.*]] = add nsw i32 [[B15]], ashr (i32 65536, i32 or (i32 zext (i1 icmp eq (ptr @g, ptr null) to i32), i32 65537))
-; CHECK-NEXT:    [[B:%.*]] = xor i32 [[B12]], -1
-; CHECK-NEXT:    store i32 [[B]], ptr undef, align 4
 ; CHECK-NEXT:    ret void
 ;
 entry:
   %xor = xor i32 %x, 1
   %or4 = or i32 or (i32 zext (i1 icmp eq (ptr @g, ptr null) to i32), i32 1), 65536
   %B6 = ashr i32 65536, %or4
   %B15 = srem i32 %B6, %xor
   %B20 = sdiv i32 %or4, 2147483647

llvm/test/Transforms/InstCombine/oss_fuzz_32759.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -passes=instcombine -S | FileCheck %s
 target datalayout = "n32"
 
 define i1 @oss_fuzz_32759(i1 %y, i1 %c1) {
 ; CHECK-LABEL: @oss_fuzz_32759(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br i1 [[C1:%.*]], label [[COND_TRUE:%.*]], label [[END:%.*]]
 ; CHECK:       cond.true:
 ; CHECK-NEXT:    br label [[END]]
 ; CHECK:       end:
-; CHECK-NEXT:    ret i1 false
+; CHECK-NEXT:    ret i1 [[C1]]
 ;
 entry:
   br i1 %c1, label %cond.true, label %end
 
 cond.true:                                        ; preds = %entry
   %zy = zext i1 %y to i32
   %B6 = shl i32 %zy, 2147483647
   %B3 = ashr i32 %B6, 2147483647

llvm/test/Transforms/InstCombine/shift.ll

;
   store i177 %B28, ptr %G62
   ret void
 }
 
 ; OSS Fuzz #26135
 ; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=26135
 define void @ashr_out_of_range_1(ptr %A) {
 ; CHECK-LABEL: @ashr_out_of_range_1(
-; CHECK-NEXT:    [[L:%.*]] = load i177, ptr [[A:%.*]], align 4
-; CHECK-NEXT:    [[G11:%.*]] = getelementptr i177, ptr [[A]], i64 -1
-; CHECK-NEXT:    [[B24_LOBIT:%.*]] = ashr i177 [[L]], 175
-; CHECK-NEXT:    [[TMP1:%.*]] = trunc i177 [[B24_LOBIT]] to i64
-; CHECK-NEXT:    [[G62:%.*]] = getelementptr i177, ptr [[G11]], i64 [[TMP1]]
-; CHECK-NEXT:    store i177 0, ptr [[G62]], align 4
 ; CHECK-NEXT:    ret void
 ;
   %L = load i177, ptr %A, align 4
   %B5 = udiv i177 %L, -1
   %B4 = add i177 %B5, -1
   %B = and i177 %B4, %L
   %B2 = add i177 %B, -1
   %G11 = getelementptr i177, ptr %A, i177 %B2

llvm/unittests/Analysis/ValueTrackingTest.cpp

 }
 
 TEST_F(ValueTrackingTest, ComputeNumSignBits_PR32045) {
   parseAssembly(
       "define i32 @test(i32 %a) {\n"
       "  %A = ashr i32 %a, -1\n"
       "  ret i32 %A\n"
       "}\n");
-  EXPECT_EQ(ComputeNumSignBits(A, M->getDataLayout()), 1u);
+  EXPECT_EQ(ComputeNumSignBits(A, M->getDataLayout()), 32u);
 }
 
 // No guarantees for canonical IR in this analysis, so this just bails out.
 TEST_F(ValueTrackingTest, ComputeNumSignBits_Shuffle) {
   parseAssembly(
       "define <2 x i32> @test() {\n"
       "  %A = shufflevector <2 x i32> undef, <2 x i32> undef, <2 x i32> <i32 0, i32 0>\n"
       "  ret <2 x i32> %A\n"

llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp

)";
   MachineInstr *BiggerSizedCopy = MRI->getVRegDef(BiggerSizedCopyReg);
   Register BiggerSizedShl = BiggerSizedCopy->getOperand(1).getReg();
 
   GISelKnownBits Info(*MF);
   KnownBits EqSizeRes = Info.getKnownBits(EqSizedShl);
   KnownBits BiggerSizeRes = Info.getKnownBits(BiggerSizedShl);
 
 
-  // We don't know what the result of the shift is, but we should not crash
+  // Result can be anything, but we should not crash.
   EXPECT_TRUE(EqSizeRes.One.isZero());
-  EXPECT_TRUE(EqSizeRes.Zero.isZero());
+  EXPECT_TRUE(EqSizeRes.Zero.isAllOnes());
 
   EXPECT_TRUE(BiggerSizeRes.One.isZero());
-  EXPECT_TRUE(BiggerSizeRes.Zero.isZero());
+  EXPECT_TRUE(BiggerSizeRes.Zero.isAllOnes());
 }
 
 TEST_F(AArch64GISelMITest, TestKnownBitsAssertZext) {
   StringRef MIRString = R"(
    %copy:_(s64) = COPY $x0
 
    %assert8:_(s64) = G_ASSERT_ZEXT %copy, 8
    %copy_assert8:_(s64) = COPY %assert8

llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp

)";
   MachineInstr *BiggerSizedCopy = MRI->getVRegDef(BiggerSizedCopyReg);
   Register BiggerSizedShl = BiggerSizedCopy->getOperand(1).getReg();
 
   GISelKnownBits Info(*MF);
   KnownBits EqSizeRes = Info.getKnownBits(EqSizedShl);
   KnownBits BiggerSizeRes = Info.getKnownBits(BiggerSizedShl);
 
   EXPECT_TRUE(EqSizeRes.One.isZero());
-  EXPECT_TRUE(EqSizeRes.Zero.isZero());
+  EXPECT_TRUE(EqSizeRes.Zero.isAllOnes());
 
   EXPECT_TRUE(BiggerSizeRes.One.isZero());
-  EXPECT_TRUE(BiggerSizeRes.Zero.isZero());
+  EXPECT_TRUE(BiggerSizeRes.Zero.isAllOnes());
 }
 
 TEST_F(AArch64GISelMITest, TestKnownBitsVectorAssertZext) {
   StringRef MIRString = R"(
    %copy_x0:_(s64) = COPY $x0
    %copy_x1:_(s64) = COPY $x1
    %x0_x1:_(<2 x s64>) = G_BUILD_VECTOR %copy_x0, %copy_x1