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Differential D150559

[AArch64] Add implicit uses to speculative hardening MIR test
ClosedPublic

Authored by foad on May 15 2023, 5:24 AM.

Details

Reviewers
arsenm
RKSimon
bogner
t.p.northover
foad
Commits
rG47d30de54995: [AArch64] Add implicit uses to speculative hardening MIR test
Summary

A couple of tests were setting liveins to add fake live registers, but
that only works if you track liveness forwards. Add some implicit uses
too, so that it also works if you track liveness backwards.

Diff Detail

Event Timeline

foad created this revision.May 15 2023, 5:24 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 15 2023, 5:24 AM
Herald added subscribers: StephenFan, kristof.beyls. · View Herald Transcript
foad requested review of this revision.May 15 2023, 5:24 AM
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foad added a child revision: D150560: [AArch64] Avoid RegScavenger::forward in AArch64SpeculationHardening.May 15 2023, 5:25 AM
Harbormaster completed remote builds in B231963: Diff 522131.May 15 2023, 5:59 AM
foad accepted this revision.May 23 2023, 1:30 AM

Self-approving.

This revision is now accepted and ready to land.May 23 2023, 1:30 AM
This revision was landed with ongoing or failed builds.May 23 2023, 1:32 AM
Closed by commit rG47d30de54995: [AArch64] Add implicit uses to speculative hardening MIR test (authored by foad). · Explain Why
This revision was automatically updated to reflect the committed changes.
foad added a commit: rG47d30de54995: [AArch64] Add implicit uses to speculative hardening MIR test.

Revision Contents

PathSize
llvm/
test/
CodeGen/
AArch64/
6 lines

Diff 524606

llvm/test/CodeGen/AArch64/speculation-hardening.mir

Show First 20 Lines • Show All 165 Lines • ▼ Show 20 Lines
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: indirect_call_lr ; CHECK-LABEL: indirect_call_lr
; CHECK: mov x1, sp ; CHECK: mov x1, sp
; CHECK: and x1, x1, x16 ; CHECK: and x1, x1, x16
; CHECK-NEXT: mov sp, x1 ; CHECK-NEXT: mov sp, x1
; CHECK-NEXT: blr x30 ; CHECK-NEXT: blr x30
liveins: $x0, $lr liveins: $x0, $lr
BLR killed renamable $lr, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $w0 BLR killed renamable $lr, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $w0, implicit $x0
$w0 = nsw ADDWri killed $w0, 1, 0 $w0 = nsw ADDWri killed $w0, 1, 0
RET undef $lr, implicit $w0 RET undef $lr, implicit $w0
... ...
--- ---
name: RS_cannot_find_available_regs name: RS_cannot_find_available_regs
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
Show All 9 Lines bb.0:
; The following 2 instructions come from propagating the taint encoded in ; The following 2 instructions come from propagating the taint encoded in
; sp at function entry to x16. It turns out the taint info in x16 is not ; sp at function entry to x16. It turns out the taint info in x16 is not
; used in this function, so those instructions could be optimized away. An ; used in this function, so those instructions could be optimized away. An
; optimization for later if it turns out this situation occurs often enough. ; optimization for later if it turns out this situation occurs often enough.
; CHECK-NEXT: cmp sp, #0 ; CHECK-NEXT: cmp sp, #0
; CHECK-NEXT: csetm x16, ne ; CHECK-NEXT: csetm x16, ne
; CHECK-NEXT: ret ; CHECK-NEXT: ret
liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $fp, $lr liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $fp, $lr
$x0 = LDRXui killed $x0, 0 $x0 = LDRXui killed $x0, 0
RET undef $lr, implicit $x0 RET $lr, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x17, implicit $x18, implicit $x19, implicit $x20, implicit $x21, implicit $x22, implicit $x23, implicit $x24, implicit $x25, implicit $x26, implicit $x27, implicit $x28
... ...