[DAGCombiner] Improve `computeKnownBits` implementations of `sdiv` and `udiv`

[goldstein.w.n]

Summary

Add exact flag handling for udiv and add entire sdiv case.

[RKSimon]

LGTM

[goldstein.w.n]

Causes regression in ARM

[goldstein.w.n]

llvm/test/CodeGen/ARM/select-imm.ll

660–665

@RKSimon this ends up causing a regression. Had only run x86 backend tests by mistake earlier. @t.p.northover is this acceptable for you guys? The change here is just adding more information to computeKnownBits so a regression in ARM backend likely means there is buggy/flakey fold.

[goldstein.w.n]

llvm/test/CodeGen/ARM/select-imm.ll

660–665

I'm going to assume this is okay. The middle end would never produce the IR (it constant evaluates to true).

[goldstein.w.n]

Rebase

[goldstein.w.n]

Rebase

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

case ISD::ADDE: {
     Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
     Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
     Known = KnownBits::computeForAddCarry(Known, Known2, Carry);
     break;
   }
   case ISD::UDIV: {
     Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
     Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
-    Known = KnownBits::udiv(Known, Known2);
+    Known = KnownBits::udiv(Known, Known2, Op->getFlags().hasExact());
+    break;
+  }
+  case ISD::SDIV: {
+    Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
+    Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
+    Known = KnownBits::sdiv(Known, Known2, Op->getFlags().hasExact());
     break;
   }
   case ISD::SREM: {
     Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
     Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
     Known = KnownBits::srem(Known, Known2);
     break;
   }

llvm/test/CodeGen/ARM/select-imm.ll

 ;
 ; V8MBASE-LABEL: t10:
 ; V8MBASE:       @ %bb.0: @ %entry
 ; V8MBASE-NEXT:    .pad #8
 ; V8MBASE-NEXT:    sub sp, #8
 ; V8MBASE-NEXT:    movs r0, #7
 ; V8MBASE-NEXT:    mvns r0, r0
 ; V8MBASE-NEXT:    str r0, [sp]
-; V8MBASE-NEXT:    adds r0, r0, #5
-; V8MBASE-NEXT:    str r0, [sp, #4]
-; V8MBASE-NEXT:    movs r1, #0
+; V8MBASE-NEXT:    adds r1, r0, #5
+; V8MBASE-NEXT:    str r1, [sp, #4]
+; V8MBASE-NEXT:    sdiv r2, r1, r0
+; V8MBASE-NEXT:    muls r2, r0, r2
+; V8MBASE-NEXT:    subs r0, r1, r2
+; V8MBASE-NEXT:    subs r1, r0, r1
 ; V8MBASE-NEXT:    rsbs r0, r1, #0
 ; V8MBASE-NEXT:    adcs r0, r1
 ; V8MBASE-NEXT:    add sp, #8
 ; V8MBASE-NEXT:    bx lr
 entry:
   %q = alloca i32
   %p = alloca i32
   store i32 -3, ptr %q

llvm/test/CodeGen/X86/knownbits-div.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s
 
 define i8 @sdiv_neg_neg_high_bits(i8 %x, i8 %y) {
 ; CHECK-LABEL: sdiv_neg_neg_high_bits:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    orb $-128, %dil
-; CHECK-NEXT:    orb $-125, %sil
-; CHECK-NEXT:    movsbl %dil, %eax
-; CHECK-NEXT:    idivb %sil
-; CHECK-NEXT:    andb $-128, %al
+; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    retq
   %num = or i8 %x, 128
   %denum = or i8 %y, 131
   %div = sdiv i8 %num, %denum
   %r = and i8 %div, 128
   ret i8 %r
 }
 
 define i8 @sdiv_exact_odd_odd(i8 %x, i8 %y) {
 ; CHECK-LABEL: sdiv_exact_odd_odd:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    orb $1, %dil
-; CHECK-NEXT:    orb $1, %sil
-; CHECK-NEXT:    movsbl %dil, %eax
-; CHECK-NEXT:    idivb %sil
-; CHECK-NEXT:    andb $1, %al
+; CHECK-NEXT:    movb $1, %al
 ; CHECK-NEXT:    retq
   %num = or i8 %x, 1
   %denum = or i8 %y, 1
   %div = sdiv exact i8 %num, %denum
   %r = and i8 %div, 1
   ret i8 %r
 }
 
; CHECK-NEXT:    retq
   %div = sdiv exact i8 %num, %denum
   %r = and i8 %div, 1
   ret i8 %r
 }
 
 define i8 @udiv_exact_even_odd(i8 %x, i8 %y) {
 ; CHECK-LABEL: udiv_exact_even_odd:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    andb $-2, %dil
-; CHECK-NEXT:    orb $1, %sil
-; CHECK-NEXT:    movzbl %dil, %eax
-; CHECK-NEXT:    divb %sil
-; CHECK-NEXT:    andb $1, %al
+; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    retq
   %num = and i8 %x, -2
   %denum = or i8 %y, 1
   %div = udiv exact i8 %num, %denum
   %r = and i8 %div, 1
   ret i8 %r
 }