[LoongArch] Define `ual` feature and override `allowsMisalignedMemoryAccesses`

[SixWeining]

Summary

Some CPUs do not allow memory accesses to be unaligned, e.g. 2k1000la
who uses the la264 core on which misaligned access will trigger an
exception.

In this patch, a backend feature called ual is defined to decribe
whether the CPU supports unaligned memroy accesses. And this feature
can be toggled by clang options -m[no-]unaligned-access or the
aliases -m[no-]strict-align. When this feature is on,
allowsMisalignedMemoryAccesses sets the speed number to 1 and returns
true that allows the codegen to generate unaligned memory access insns.

Clang options -m[no-]unaligned-access are moved from m_arm_Features_Group
to m_Group because now more than one targets use them. And a test
is added to show that they remain unused on a target that does not
support them. In addition, to keep compatible with gcc, a new alias
-mno-strict-align is added which is equal to -munaligned-access.

The feature name ual is consistent with linux kernel [1] and the
output of lscpu or /proc/cpuinfo [2].

There is an LLT variant of allowsMisalignedMemoryAccesses, but
seems that curently it is only used in GlobalISel which LoongArch
doesn't support yet. So this variant is not implemented in this patch.

[1]: https://github.com/torvalds/linux/blob/master/arch/loongarch/include/asm/cpu.h#L77
[2]: https://github.com/torvalds/linux/blob/master/arch/loongarch/kernel/proc.c#L75

[SixWeining]

TODO: update llvm/clang release notes.

[rengolin]

Rationale and implementation make sense to me. I'll let this one sit so that other folks, including Arm, can have a look, too.

[peter.smith]

No objections for moving out m_arm_Features_Group or adding the alias. It looks like that is currently unused i.e. no driver filters out the m_arm_Features_Group. I can't comment on the LoongArch specific parts of the patch.

I think you may want to note in the help that the option is not universally supported. Perhaps add a test to show that it remains unused on a target that does not support it. For example for an x86_64 target:

clang: warning: argument unused during compilation: '-munaligned-access' [-Wunused-command-line-argument]

clang/include/clang/Driver/Options.td

3701

I think this is AArch32/AArch64/LoongArch only. I don't think this patch adds support for all other Targets.

[SixWeining]

Add a test to show related options remain unused on a target that does not support them.

[SixWeining]

Thanks @rengolin and @peter.smith. I just added a new test to show options remain unused on a target that does not support them.

[xen0n]

From a LoongArch developer's perspective, it may be better to only enable UAL for LA464 and other supporting models, instead of for the generic loongarch64 model too. This is because although all server- and desktop-class LoongArch models have UAL, the embedded-class (Loongson-1 and Loongson-2 series' older models) doesn't, and some of them e.g. Loongson 2K1000LA are readily available on the market so they're arguably relevant. We don't want to generate misaligned memory accesses for those systems only to fall back to much slower emulation later.

[SixWeining]

In D149946#4324803, @xen0n wrote:

From a LoongArch developer's perspective, it may be better to only enable UAL for LA464 and other supporting models, instead of for the generic loongarch64 model too. This is because although all server- and desktop-class LoongArch models have UAL, the embedded-class (Loongson-1 and Loongson-2 series' older models) doesn't, and some of them e.g. Loongson 2K1000LA are readily available on the market so they're arguably relevant. We don't want to generate misaligned memory accesses for those systems only to fall back to much slower emulation later.

If so, CPUs that support UAL will not benefit from this feature in default build (i.e. without -march or -mcpu or -mtune being specified).

Does generic model mean the lowest model or the most popular model?

[xry111]

In D149946#4324877, @SixWeining wrote:

In D149946#4324803, @xen0n wrote:

From a LoongArch developer's perspective, it may be better to only enable UAL for LA464 and other supporting models, instead of for the generic loongarch64 model too. This is because although all server- and desktop-class LoongArch models have UAL, the embedded-class (Loongson-1 and Loongson-2 series' older models) doesn't, and some of them e.g. Loongson 2K1000LA are readily available on the market so they're arguably relevant. We don't want to generate misaligned memory accesses for those systems only to fall back to much slower emulation later.

If so, CPUs that support UAL will not benefit from this feature in default build (i.e. without -march or -mcpu or -mtune being specified).

Does generic model mean the lowest model or the most popular model?

Technically generic should mean the lowest. But as a desktop user, frankly I don't want to pay the extra cost for 2K models.

[xry111]

OTOH if the Linux kernel is expected to emulate UAL, -march=generic should be allowed to generate unaligned access instructions for Linux targets. Frankly I prefer this personally, But I'm not sure if it will be a good practice in general...

[xen0n]

I've thought about this a bit harder; it now seems better longer-term to enable unaligned accesses by default (making the UAL-less models the special case).

But most importantly, there's new information suggesting that UAL support is to become ubiquitous in the future. A sample /proc/cpuinfo output on a Loongson 2K2000 (LA364 uarch) recently is circulated in various user groups (unfortunately there doesn't seem to be a public link), that clearly shows LA364 has UAL. So this very likely means all future Loongson-2 series will feature UAL, and that the non-UAL case is to gradually become less relevant.

Also, in some cases (distro packaging, mesa llvmpipe, etc.) it may not be as easy to specify march flags, but we may want to assume a more popular model nevertheless. Again the UAL-less models should be seen as special cases and get adapted individually later.

With the reasoning becoming clear, the LoongArch target part of the change LGTM; thanks for taking care of this!

[SixWeining]

rebase

[MaskRay]

[1]: https://github.com/torvalds/linux/blob/master/arch/loongarch/include/asm/cpu.h#L77
[2]: https://github.com/torvalds/linux/blob/master/arch/loongarch/kernel/proc.c#L75

master will point to different commits. It'd be better to use a specific commit for future patches.

[MaskRay]

In D149946#4322904, @peter.smith wrote:

No objections for moving out m_arm_Features_Group or adding the alias. It looks like that is currently unused i.e. no driver filters out the m_arm_Features_Group. I can't comment on the LoongArch specific parts of the patch.

I think you may want to note in the help that the option is not universally supported. Perhaps add a test to show that it remains unused on a target that does not support it. For example for an x86_64 target:

clang: warning: argument unused during compilation: '-munaligned-access' [-Wunused-command-line-argument]

I'll make -munaligned-access TargetSpecific (D151590) to report errors for unsupported targets.

clang/include/clang/Driver/Options.td

def menable_experimental_extensions : Flag<["-"], "menable-experimental-extensions">, Group<m_Group>,
   HelpText<"Enable use of experimental RISC-V extensions.">;
 def mrvv_vector_bits_EQ : Joined<["-"], "mrvv-vector-bits=">, Group<m_Group>,
   HelpText<"Specify the size in bits of an RVV vector register. Defaults to "
            "the vector length agnostic value of \"scalable\". Accepts power of "
            "2 values between 64 and 65536. Also accepts \"zvl\" "
            "to use the value implied by -march/-mcpu. Value will be reflected "
            "in __riscv_v_fixed_vlen preprocessor define (RISC-V only)">;
 
-def munaligned_access : Flag<["-"], "munaligned-access">, Group<m_arm_Features_Group>,
-  HelpText<"Allow memory accesses to be unaligned (AArch32/AArch64 only)">;
-def mno_unaligned_access : Flag<["-"], "mno-unaligned-access">, Group<m_arm_Features_Group>,
-  HelpText<"Force all memory accesses to be aligned (AArch32/AArch64 only)">;
+def munaligned_access : Flag<["-"], "munaligned-access">, Group<m_Group>,
+  HelpText<"Allow memory accesses to be unaligned (AArch32/AArch64/LoongArch only)">;
+def mno_unaligned_access : Flag<["-"], "mno-unaligned-access">, Group<m_Group>,
+  HelpText<"Force all memory accesses to be aligned (AArch32/AArch64/LoongArch only)">;
 def mstrict_align : Flag<["-"], "mstrict-align">, Alias<mno_unaligned_access>, Flags<[CC1Option,HelpHidden]>,
   HelpText<"Force all memory accesses to be aligned (same as mno-unaligned-access)">;
+def mno_strict_align : Flag<["-"], "mno-strict-align">, Alias<munaligned_access>, Flags<[CC1Option,HelpHidden]>,
+  HelpText<"Allow memory accesses to be unaligned (same as munaligned-access)">;
 def mno_thumb : Flag<["-"], "mno-thumb">, Group<m_arm_Features_Group>;
 def mrestrict_it: Flag<["-"], "mrestrict-it">, Group<m_arm_Features_Group>,
   HelpText<"Disallow generation of complex IT blocks.">;
 def mno_restrict_it: Flag<["-"], "mno-restrict-it">, Group<m_arm_Features_Group>,
   HelpText<"Allow generation of complex IT blocks.">;
 def marm : Flag<["-"], "marm">, Alias<mno_thumb>;
 def ffixed_r9 : Flag<["-"], "ffixed-r9">, Group<m_arm_Features_Group>,
   HelpText<"Reserve the r9 register (ARM only)">;

clang/lib/Driver/ToolChains/Arch/LoongArch.cpp

 //===--- LoongArch.cpp - LoongArch Helpers for Tools ------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "LoongArch.h"
+#include "ToolChains/CommonArgs.h"
 #include "clang/Basic/DiagnosticDriver.h"
 #include "clang/Driver/Driver.h"
 #include "clang/Driver/DriverDiagnostic.h"
 #include "clang/Driver/Options.h"
 #include "llvm/TargetParser/LoongArchTargetParser.h"
 
 using namespace clang::driver;
 using namespace clang::driver::tools;
if (FPU == "64") {
       Features.push_back("-d");
     } else if (FPU == "0" || FPU == "none") {
       Features.push_back("-f");
       Features.push_back("-d");
     } else {
       D.Diag(diag::err_drv_loongarch_invalid_mfpu_EQ) << FPU;
     }
   }
+
+  // Select the `ual` feature determined by -m[no-]unaligned-access
+  // or the alias -m[no-]strict-align.
+  AddTargetFeature(Args, Features, options::OPT_munaligned_access,
+                   options::OPT_mno_unaligned_access, "ual");
 }

clang/test/Driver/loongarch-default-features.c

 // RUN: %clang --target=loongarch32 -S -emit-llvm %s -o - | FileCheck %s --check-prefix=LA32
 // RUN: %clang --target=loongarch64 -S -emit-llvm %s -o - | FileCheck %s --check-prefix=LA64
 
 // LA32: "target-features"="+32bit"
-// LA64: "target-features"="+64bit,+d,+f"
+// LA64: "target-features"="+64bit,+d,+f,+ual"
 
 int foo(void) {
   return 3;
 }

clang/test/Driver/loongarch-march.c

 // RUN: %clang --target=loongarch64 -march=loongarch64 -fsyntax-only %s -### 2>&1 | \
 // RUN:   FileCheck %s --check-prefix=CC1-LOONGARCH64
 // RUN: %clang --target=loongarch64 -march=la464 -fsyntax-only %s -### 2>&1 | \
 // RUN:   FileCheck %s --check-prefix=CC1-LA464
 // RUN: %clang --target=loongarch64 -march=loongarch64 -S -emit-llvm %s -o - | \
 // RUN:   FileCheck %s --check-prefix=IR-LOONGARCH64
 // RUN: %clang --target=loongarch64 -march=la464 -S -emit-llvm %s -o - | \
 // RUN:   FileCheck %s --check-prefix=IR-LA464
 
 // CC1-LOONGARCH64-NOT: "-target-feature"
-// CC1-LOONGARCH64: "-target-feature" "+64bit" "-target-feature" "+f" "-target-feature" "+d"
+// CC1-LOONGARCH64: "-target-feature" "+64bit" "-target-feature" "+f" "-target-feature" "+d" "-target-feature" "+ual"
 // CC1-LOONGARCH64-NOT: "-target-feature"
 // CC1-LOONGARCH64: "-target-abi" "lp64d"
 
 // CC1-LA464-NOT: "-target-feature"
-// CC1-LA464: "-target-feature" "+64bit" "-target-feature" "+f" "-target-feature" "+d" "-target-feature" "+lsx" "-target-feature" "+lasx"
+// CC1-LA464: "-target-feature" "+64bit" "-target-feature" "+f" "-target-feature" "+d" "-target-feature" "+lsx" "-target-feature" "+lasx" "-target-feature" "+ual"
 // CC1-LA464-NOT: "-target-feature"
 // CC1-LA464: "-target-abi" "lp64d"
 
-// IR-LOONGARCH64: attributes #[[#]] ={{.*}}"target-features"="+64bit,+d,+f"
-// IR-LA464: attributes #[[#]] ={{.*}}"target-features"="+64bit,+d,+f,+lasx,+lsx"
+// IR-LOONGARCH64: attributes #[[#]] ={{.*}}"target-features"="+64bit,+d,+f,+ual"
+// IR-LA464: attributes #[[#]] ={{.*}}"target-features"="+64bit,+d,+f,+lasx,+lsx,+ual"
 
 int foo(void) {
   return 3;
 }

clang/test/Driver/loongarch-mdouble-float.c

 // RUN: %clang --target=loongarch64 -mdouble-float -fsyntax-only %s -### 2>&1 | \
 // RUN:   FileCheck %s --check-prefix=CC1
 // RUN: %clang --target=loongarch64 -mdouble-float -mfpu=0 -mabi=lp64s -fsyntax-only %s -### 2>&1 | \
 // RUN:   FileCheck %s --check-prefixes=CC1,WARN
 // RUN: %clang --target=loongarch64 -mdouble-float -S -emit-llvm %s -o - | \
 // RUN:   FileCheck %s --check-prefix=IR
 
 // WARN: warning: argument unused during compilation: '-mfpu=0'
 // WARN: warning: argument unused during compilation: '-mabi=lp64s'
 
-// CC1-NOT: "-target-feature"
-// CC1: "-target-feature" "+64bit" "-target-feature" "+f" "-target-feature" "+d"
-// CC1-NOT: "-target-feature"
+// CC1: "-target-feature" "+f"{{.*}} "-target-feature" "+d"
 // CC1: "-target-abi" "lp64d"
 
-// IR: attributes #[[#]] ={{.*}}"target-features"="+64bit,+d,+f"
+// IR: attributes #[[#]] ={{.*}}"target-features"="{{(.*,)?}}+d,{{(.*,)?}}+f{{(,.*)?}}"
 
 int foo(void) {
   return 3;
 }

clang/test/Driver/loongarch-mfpu.c

 // RUN:   FileCheck %s --check-prefix=IR-FPU64
 // RUN: %clang --target=loongarch64 -mfpu=32 -S -emit-llvm %s -o - | \
 // RUN:   FileCheck %s --check-prefix=IR-FPU32
 // RUN: %clang --target=loongarch64 -mfpu=0 -S -emit-llvm %s -o - | \
 // RUN:   FileCheck %s --check-prefix=IR-FPU0
 // RUN: %clang --target=loongarch64 -mfpu=none -S -emit-llvm %s -o - | \
 // RUN:   FileCheck %s --check-prefix=IR-FPU0
 
-// CC1-FPU64-NOT: "-target-feature"
-// CC1-FPU64: "-target-feature" "+64bit" "-target-feature" "+f" "-target-feature" "+d"
-// CC1-FPU64-NOT: "-target-feature"
+// CC1-FPU64: "-target-feature" "+f"{{.*}} "-target-feature" "+d"
 // CC1-FPU64: "-target-abi" "lp64d"
 
-// CC1-FPU32-NOT: "-target-feature"
-// CC1-FPU32: "-target-feature" "+64bit" "-target-feature" "+f" "-target-feature" "-d"
-// CC1-FPU32-NOT: "-target-feature"
+// CC1-FPU32: "-target-feature" "+f"{{.*}} "-target-feature" "-d"
 // CC1-FPU32: "-target-abi" "lp64f"
 
-// CC1-FPU0-NOT: "-target-feature"
-// CC1-FPU0: "-target-feature" "+64bit" "-target-feature" "-f" "-target-feature" "-d"
-// CC1-FPU0-NOT: "-target-feature"
+// CC1-FPU0: "-target-feature" "-f"{{.*}} "-target-feature" "-d"
 // CC1-FPU0: "-target-abi" "lp64s"
 
-// IR-FPU64: attributes #[[#]] ={{.*}}"target-features"="+64bit,+d,+f"
-// IR-FPU32: attributes #[[#]] ={{.*}}"target-features"="+64bit,+f,-d"
-// IR-FPU0: attributes #[[#]] ={{.*}}"target-features"="+64bit,-d,-f"
+// IR-FPU64: attributes #[[#]] ={{.*}}"target-features"="{{(.*,)?}}+d,{{(.*,)?}}+f{{(,.*)?}}"
+// IR-FPU32: attributes #[[#]] ={{.*}}"target-features"="{{(.*,)?}}+f,{{(.*,)?}}-d{{(,.*)?}}"
+// IR-FPU0: attributes #[[#]] ={{.*}}"target-features"="{{(.*,)?}}-d,{{(.*,)?}}-f{{(,.*)?}}"
 
 int foo(void) {
   return 3;
 }

clang/test/Driver/loongarch-msingle-float.c

 // RUN: %clang --target=loongarch64 -msingle-float -fsyntax-only %s -### 2>&1 | \
 // RUN:   FileCheck %s --check-prefix=CC1
 // RUN: %clang --target=loongarch64 -msingle-float -mfpu=0 -mabi=lp64s -fsyntax-only %s -### 2>&1 | \
 // RUN:   FileCheck %s --check-prefixes=CC1,WARN
 // RUN: %clang --target=loongarch64 -msingle-float -S -emit-llvm %s -o - | \
 // RUN:   FileCheck %s --check-prefix=IR
 
 // WARN: warning: argument unused during compilation: '-mfpu=0'
 // WARN: warning: argument unused during compilation: '-mabi=lp64s'
 
-// CC1-NOT: "-target-feature"
-// CC1: "-target-feature" "+64bit" "-target-feature" "+f" "-target-feature" "-d"
-// CC1-NOT: "-target-feature"
+// CC1: "-target-feature" "+f"{{.*}} "-target-feature" "-d"
 // CC1: "-target-abi" "lp64f"
 
-// IR: attributes #[[#]] ={{.*}}"target-features"="+64bit,+f,-d"
+// IR: attributes #[[#]] ={{.*}}"target-features"="{{(.*,)?}}+f,{{(.*,)?}}-d"
 
 int foo(void) {
   return 3;
 }

clang/test/Driver/loongarch-msoft-float.c

 // RUN: %clang --target=loongarch64 -msoft-float -fsyntax-only %s -### 2>&1 | \
 // RUN:   FileCheck %s --check-prefix=CC1
 // RUN: %clang --target=loongarch64 -msoft-float -mfpu=64 -mabi=lp64d -fsyntax-only %s -### 2>&1 | \
 // RUN:   FileCheck %s --check-prefixes=CC1,WARN
 // RUN: %clang --target=loongarch64 -msoft-float -S -emit-llvm %s -o - | \
 // RUN:   FileCheck %s --check-prefix=IR
 
 // WARN: warning: argument unused during compilation: '-mfpu=64'
 // WARN: warning: argument unused during compilation: '-mabi=lp64d'
 
-// CC1-NOT: "-target-feature"
-// CC1: "-target-feature" "+64bit" "-target-feature" "-f" "-target-feature" "-d"
-// CC1-NOT: "-target-feature"
+// CC1: "-target-feature" "-f"{{.*}} "-target-feature" "-d"
 // CC1: "-target-abi" "lp64s"
 
-// IR: attributes #[[#]] ={{.*}}"target-features"="+64bit,-d,-f"
+// IR: attributes #[[#]] ={{.*}}"target-features"="{{(.*,)?}}-d,{{(.*,)?}}-f{{(,.*)?}}"
 
 int foo(void) {
   return 3;
 }

clang/test/Driver/loongarch-munaligned-access.c

+/// Test -m[no-]unaligned-access and -m[no-]strict-align options.
+
+// RUN: %clang --target=loongarch64 -munaligned-access -fsyntax-only %s -### 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CC1-UNALIGNED
+// RUN: %clang --target=loongarch64 -mno-unaligned-access -fsyntax-only %s -### 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CC1-NO-UNALIGNED
+// RUN: %clang --target=loongarch64 -mstrict-align -fsyntax-only %s -### 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CC1-NO-UNALIGNED
+// RUN: %clang --target=loongarch64 -mno-strict-align -fsyntax-only %s -### 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CC1-UNALIGNED
+// RUN: %clang --target=loongarch64 -munaligned-access -mno-unaligned-access -fsyntax-only %s -### 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CC1-NO-UNALIGNED
+// RUN: %clang --target=loongarch64 -mno-unaligned-access -munaligned-access -fsyntax-only %s -### 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CC1-UNALIGNED
+// RUN: %clang --target=loongarch64 -mstrict-align -mno-strict-align -fsyntax-only %s -### 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CC1-UNALIGNED
+// RUN: %clang --target=loongarch64 -mno-strict-align -mstrict-align -fsyntax-only %s -### 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CC1-NO-UNALIGNED
+// RUN: %clang --target=loongarch64 -munaligned-access -mstrict-align -fsyntax-only %s -### 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CC1-NO-UNALIGNED
+// RUN: %clang --target=loongarch64 -mstrict-align -munaligned-access -fsyntax-only %s -### 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CC1-UNALIGNED
+// RUN: %clang --target=loongarch64 -mno-unaligned-access -mno-strict-align -fsyntax-only %s -### 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CC1-UNALIGNED
+// RUN: %clang --target=loongarch64 -mno-strict-align -mno-unaligned-access -fsyntax-only %s -### 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CC1-NO-UNALIGNED
+
+// RUN: %clang --target=loongarch64 -munaligned-access -S -emit-llvm %s -o - | \
+// RUN:   FileCheck %s --check-prefix=IR-UNALIGNED
+// RUN: %clang --target=loongarch64 -mno-unaligned-access -S -emit-llvm %s -o - | \
+// RUN:   FileCheck %s --check-prefix=IR-NO-UNALIGNED
+// RUN: %clang --target=loongarch64 -mstrict-align -S -emit-llvm %s -o - | \
+// RUN:   FileCheck %s --check-prefix=IR-NO-UNALIGNED
+// RUN: %clang --target=loongarch64 -mno-strict-align -S -emit-llvm %s -o - | \
+// RUN:   FileCheck %s --check-prefix=IR-UNALIGNED
+// RUN: %clang --target=loongarch64 -munaligned-access -mno-unaligned-access -S -emit-llvm %s -o - | \
+// RUN:   FileCheck %s --check-prefix=IR-NO-UNALIGNED
+// RUN: %clang --target=loongarch64 -mno-unaligned-access -munaligned-access -S -emit-llvm %s -o - | \
+// RUN:   FileCheck %s --check-prefix=IR-UNALIGNED
+// RUN: %clang --target=loongarch64 -mstrict-align -mno-strict-align -S -emit-llvm %s -o - | \
+// RUN:   FileCheck %s --check-prefix=IR-UNALIGNED
+// RUN: %clang --target=loongarch64 -mno-strict-align -mstrict-align -S -emit-llvm %s -o - | \
+// RUN:   FileCheck %s --check-prefix=IR-NO-UNALIGNED
+// RUN: %clang --target=loongarch64 -munaligned-access -mstrict-align -S -emit-llvm %s -o - | \
+// RUN:   FileCheck %s --check-prefix=IR-NO-UNALIGNED
+// RUN: %clang --target=loongarch64 -mstrict-align -munaligned-access -S -emit-llvm %s -o - | \
+// RUN:   FileCheck %s --check-prefix=IR-UNALIGNED
+// RUN: %clang --target=loongarch64 -mno-unaligned-access -mno-strict-align -S -emit-llvm %s -o - | \
+// RUN:   FileCheck %s --check-prefix=IR-UNALIGNED
+// RUN: %clang --target=loongarch64 -mno-strict-align -mno-unaligned-access -S -emit-llvm %s -o - | \
+// RUN:   FileCheck %s --check-prefix=IR-NO-UNALIGNED
+
+// CC1-UNALIGNED: "-target-feature" "+ual"
+// CC1-NO-UNALIGNED: "-target-feature" "-ual"
+
+// IR-UNALIGNED: attributes #[[#]] ={{.*}}"target-features"="{{(.*,)?}}+ual{{(,.*)?}}"
+// IR-NO-UNALIGNED: attributes #[[#]] ={{.*}}"target-features"="{{(.*,)?}}-ual{{(,.*)?}}"
+
+int foo(void) {
+  return 3;
+}

clang/test/Driver/munaligned-access-unused.c

+/// Check -m[no-]unaligned-access and -m[no-]strict-align are warned unused on a target that does not support them.
+
+// RUN: %clang --target=x86_64 -munaligned-access -fsyntax-only %s -### 2>&1 | FileCheck %s -DOPTION=unaligned-access
+// RUN: %clang --target=x86_64 -mno-unaligned-access -fsyntax-only %s -### 2>&1 | FileCheck %s -DOPTION=no-unaligned-access
+// RUN: %clang --target=x86_64 -mstrict-align -fsyntax-only %s -### 2>&1 | FileCheck %s -DOPTION=strict-align
+// RUN: %clang --target=x86_64 -mno-strict-align -fsyntax-only %s -### 2>&1 | FileCheck %s -DOPTION=no-strict-align
+
+// CHECK: clang: warning: argument unused during compilation: '-m[[OPTION]]' [-Wunused-command-line-argument]

llvm/include/llvm/TargetParser/LoongArchTargetParser.h

enum FeatureKind : uint32_t {
   // Loongson Advanced SIMD Extension is available.
   FK_LASX = 1 << 5,
 
   // Loongson Binary Translation Extension is available.
   FK_LBT = 1 << 6,
 
   // Loongson Virtualization Extension is available.
   FK_LVZ = 1 << 7,
+
+  // Allow memory accesses to be unaligned.
+  FK_UAL = 1 << 8,
 };
 
 struct FeatureInfo {
   StringRef Name;
   FeatureKind Kind;
 };
 
 enum class ArchKind {

llvm/include/llvm/TargetParser/LoongArchTargetParser.def

 #ifndef LOONGARCH_FEATURE
 #define LOONGARCH_FEATURE(NAME, KIND)
 #endif
 
 LOONGARCH_FEATURE("invalid", FK_INVALID)
 LOONGARCH_FEATURE("none", FK_NONE)
 LOONGARCH_FEATURE("+64bit", FK_64BIT)
 LOONGARCH_FEATURE("+f", FK_FP32)
 LOONGARCH_FEATURE("+d", FK_FP64)
 LOONGARCH_FEATURE("+lsx", FK_LSX)
 LOONGARCH_FEATURE("+lasx", FK_LASX)
 LOONGARCH_FEATURE("+lbt", FK_LBT)
 LOONGARCH_FEATURE("+lvz", FK_LVZ)
+LOONGARCH_FEATURE("+ual", FK_UAL)
 
 #undef LOONGARCH_FEATURE
 
 #ifndef LOONGARCH_ARCH
 #define LOONGARCH_ARCH(NAME, KIND, FEATURES)
 #endif
 
 LOONGARCH_ARCH("invalid", AK_INVALID, FK_INVALID)
-LOONGARCH_ARCH("loongarch64", AK_LOONGARCH64, FK_64BIT | FK_FP32 | FK_FP64)
-LOONGARCH_ARCH("la464", AK_LA464, FK_64BIT | FK_FP32 | FK_FP64 | FK_LSX | FK_LASX)
+LOONGARCH_ARCH("loongarch64", AK_LOONGARCH64, FK_64BIT | FK_FP32 | FK_FP64 | FK_UAL)
+LOONGARCH_ARCH("la464", AK_LA464, FK_64BIT | FK_FP32 | FK_FP64 | FK_LSX | FK_LASX | FK_UAL)
 
 #undef LOONGARCH_ARCH

llvm/lib/Target/LoongArch/LoongArch.td

 def LaLocalWithAbs
     : SubtargetFeature<"la-local-with-abs", "HasLaLocalWithAbs", "true",
                        "Expand la.local as la.abs">;
 def HasLaLocalWithAbs
     : Predicate<"Subtarget->hasLaLocalWithAbs()">,
       AssemblerPredicate<(all_of LaLocalWithAbs),
                          "Expand la.local as la.abs">;
 
+// Unaligned memory access
+def FeatureUAL
+    : SubtargetFeature<"ual", "HasUAL", "true",
+                       "Allow memory accesses to be unaligned">;
+
 //===----------------------------------------------------------------------===//
 // Registers, instruction descriptions ...
 //===----------------------------------------------------------------------===//
 
 include "LoongArchRegisterInfo.td"
 include "LoongArchCallingConv.td"
 include "LoongArchInstrInfo.td"
 
 //===----------------------------------------------------------------------===//
 // LoongArch processors supported.
 //===----------------------------------------------------------------------===//
 
 def : ProcessorModel<"generic-la32", NoSchedModel, [Feature32Bit]>;
-def : ProcessorModel<"generic-la64", NoSchedModel, [Feature64Bit]>;
+def : ProcessorModel<"generic-la64", NoSchedModel, [Feature64Bit, FeatureUAL]>;
 
 // Support generic for compatibility with other targets. The triple will be used
 // to change to the appropriate la32/la64 version.
 def : ProcessorModel<"generic", NoSchedModel, []>;
 
 def : ProcessorModel<"la464", NoSchedModel, [Feature64Bit,
+                                             FeatureUAL,
                                              FeatureExtLASX,
                                              FeatureExtLVZ,
                                              FeatureExtLBT]>;
 
 //===----------------------------------------------------------------------===//
 // Define the LoongArch target.
 //===----------------------------------------------------------------------===//
 

llvm/lib/Target/LoongArch/LoongArchISelLowering.h

public:
   bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
                              unsigned AS,
                              Instruction *I = nullptr) const override;
 
   bool hasAndNotCompare(SDValue Y) const override;
 
   bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }
 
+  bool allowsMisalignedMemoryAccesses(
+      EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
+      MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
+      unsigned *Fast = nullptr) const override;
+
 private:
   /// Target-specific function used to lower LoongArch calling conventions.
   typedef bool LoongArchCCAssignFn(const DataLayout &DL, LoongArchABI::ABI ABI,
                                    unsigned ValNo, MVT ValVT,
                                    CCValAssign::LocInfo LocInfo,
                                    ISD::ArgFlagsTy ArgFlags, CCState &State,
                                    bool IsFixed, bool IsReg, Type *OrigTy);
 

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

MachineInstr *ReadFCSR =
             .addReg(LoongArch::FCSR0 + MI.getOperand(1).getImm());
     ReadFCSR->getOperand(1).setIsUndef();
     MI.eraseFromParent();
     return BB;
   }
   }
 }
 
+bool LoongArchTargetLowering::allowsMisalignedMemoryAccesses(
+    EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags,
+    unsigned *Fast) const {
+  if (!Subtarget.hasUAL())
+    return false;
+
+  // TODO: set reasonable speed number.
+  if (Fast)
+    *Fast = 1;
+  return true;
+}
+
 const char *LoongArchTargetLowering::getTargetNodeName(unsigned Opcode) const {
   switch ((LoongArchISD::NodeType)Opcode) {
   case LoongArchISD::FIRST_NUMBER:
     break;
 
 #define NODE_NAME_CASE(node)                                                   \
   case LoongArchISD::node:                                                     \
     return "LoongArchISD::" #node;

llvm/lib/Target/LoongArch/LoongArchSubtarget.h

class LoongArchSubtarget : public LoongArchGenSubtargetInfo {
   bool HasBasicD = false;
   bool HasExtLSX = false;
   bool HasExtLASX = false;
   bool HasExtLVZ = false;
   bool HasExtLBT = false;
   bool HasLaGlobalWithPcrel = false;
   bool HasLaGlobalWithAbs = false;
   bool HasLaLocalWithAbs = false;
+  bool HasUAL = false;
   unsigned GRLen = 32;
   MVT GRLenVT = MVT::i32;
   LoongArchABI::ABI TargetABI = LoongArchABI::ABI_Unknown;
   LoongArchFrameLowering FrameLowering;
   LoongArchInstrInfo InstrInfo;
   LoongArchRegisterInfo RegInfo;
   LoongArchTargetLowering TLInfo;
   SelectionDAGTargetInfo TSInfo;
public:
   bool hasBasicD() const { return HasBasicD; }
   bool hasExtLSX() const { return HasExtLSX; }
   bool hasExtLASX() const { return HasExtLASX; }
   bool hasExtLVZ() const { return HasExtLVZ; }
   bool hasExtLBT() const { return HasExtLBT; }
   bool hasLaGlobalWithPcrel() const { return HasLaGlobalWithPcrel; }
   bool hasLaGlobalWithAbs() const { return HasLaGlobalWithAbs; }
   bool hasLaLocalWithAbs() const { return HasLaLocalWithAbs; }
+  bool hasUAL() const { return HasUAL; }
   MVT getGRLenVT() const { return GRLenVT; }
   unsigned getGRLen() const { return GRLen; }
   LoongArchABI::ABI getTargetABI() const { return TargetABI; }
 };
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHSUBTARGET_H

llvm/test/CodeGen/LoongArch/calling-conv-common.ll

 }
 
 ;; Check return struct which size is more than 2*GRLen.
 
 define void @callee_large_struct_ret(ptr noalias sret(%struct.large) %agg.result) nounwind {
 ; CHECK-LABEL: callee_large_struct_ret:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    ori $a1, $zero, 4
-; CHECK-NEXT:    st.w $a1, $a0, 24
+; CHECK-NEXT:    st.d $a1, $a0, 24
 ; CHECK-NEXT:    ori $a1, $zero, 3
-; CHECK-NEXT:    st.w $a1, $a0, 16
+; CHECK-NEXT:    st.d $a1, $a0, 16
 ; CHECK-NEXT:    ori $a1, $zero, 2
-; CHECK-NEXT:    st.w $a1, $a0, 8
-; CHECK-NEXT:    st.w $zero, $a0, 28
-; CHECK-NEXT:    st.w $zero, $a0, 20
-; CHECK-NEXT:    st.w $zero, $a0, 12
-; CHECK-NEXT:    st.w $zero, $a0, 4
+; CHECK-NEXT:    st.d $a1, $a0, 8
 ; CHECK-NEXT:    ori $a1, $zero, 1
-; CHECK-NEXT:    st.w $a1, $a0, 0
+; CHECK-NEXT:    st.d $a1, $a0, 0
 ; CHECK-NEXT:    ret
   %a = getelementptr inbounds %struct.large, ptr %agg.result, i64 0, i32 0
   store i64 1, ptr %a, align 4
   %b = getelementptr inbounds %struct.large, ptr %agg.result, i64 0, i32 1
   store i64 2, ptr %b, align 4
   %c = getelementptr inbounds %struct.large, ptr %agg.result, i64 0, i32 2
   store i64 3, ptr %c, align 4
   %d = getelementptr inbounds %struct.large, ptr %agg.result, i64 0, i32 3

llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-fp.ll

 ; LA64F-NEXT:    addi.d $sp, $sp, -64
 ; LA64F-NEXT:    st.d $ra, $sp, 56 # 8-byte Folded Spill
 ; LA64F-NEXT:    st.d $fp, $sp, 48 # 8-byte Folded Spill
 ; LA64F-NEXT:    st.d $s0, $sp, 40 # 8-byte Folded Spill
 ; LA64F-NEXT:    st.d $s1, $sp, 32 # 8-byte Folded Spill
 ; LA64F-NEXT:    st.d $s2, $sp, 24 # 8-byte Folded Spill
 ; LA64F-NEXT:    st.d $s3, $sp, 16 # 8-byte Folded Spill
 ; LA64F-NEXT:    move $fp, $a0
-; LA64F-NEXT:    ld.wu $a0, $a0, 0
-; LA64F-NEXT:    ld.wu $a1, $fp, 4
-; LA64F-NEXT:    slli.d $a1, $a1, 32
-; LA64F-NEXT:    or $a0, $a1, $a0
+; LA64F-NEXT:    ld.d $a0, $a0, 0
 ; LA64F-NEXT:    ori $s0, $zero, 8
 ; LA64F-NEXT:    addi.d $s1, $sp, 8
 ; LA64F-NEXT:    addi.d $s2, $sp, 0
 ; LA64F-NEXT:    ori $s3, $zero, 2
 ; LA64F-NEXT:  .LBB4_1: # %atomicrmw.start
 ; LA64F-NEXT:    # =>This Inner Loop Header: Depth=1
 ; LA64F-NEXT:    st.d $a0, $sp, 8
 ; LA64F-NEXT:    lu52i.d $a1, $zero, 1023

 ; LA64D-NEXT:    st.d $ra, $sp, 72 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $fp, $sp, 64 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $s0, $sp, 56 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $s1, $sp, 48 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $s2, $sp, 40 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $s3, $sp, 32 # 8-byte Folded Spill
 ; LA64D-NEXT:    fst.d $fs0, $sp, 24 # 8-byte Folded Spill
 ; LA64D-NEXT:    move $fp, $a0
-; LA64D-NEXT:    ld.wu $a0, $a0, 0
-; LA64D-NEXT:    ld.wu $a1, $fp, 4
-; LA64D-NEXT:    slli.d $a1, $a1, 32
-; LA64D-NEXT:    or $a0, $a1, $a0
-; LA64D-NEXT:    movgr2fr.d $fa0, $a0
+; LA64D-NEXT:    fld.d $fa0, $a0, 0
 ; LA64D-NEXT:    addi.d $a0, $zero, 1
 ; LA64D-NEXT:    movgr2fr.d $fs0, $a0
 ; LA64D-NEXT:    ori $s0, $zero, 8
 ; LA64D-NEXT:    addi.d $s1, $sp, 16
 ; LA64D-NEXT:    addi.d $s2, $sp, 8
 ; LA64D-NEXT:    ori $s3, $zero, 2
 ; LA64D-NEXT:  .LBB4_1: # %atomicrmw.start
 ; LA64D-NEXT:    # =>This Inner Loop Header: Depth=1

 ; LA64F-NEXT:    addi.d $sp, $sp, -64
 ; LA64F-NEXT:    st.d $ra, $sp, 56 # 8-byte Folded Spill
 ; LA64F-NEXT:    st.d $fp, $sp, 48 # 8-byte Folded Spill
 ; LA64F-NEXT:    st.d $s0, $sp, 40 # 8-byte Folded Spill
 ; LA64F-NEXT:    st.d $s1, $sp, 32 # 8-byte Folded Spill
 ; LA64F-NEXT:    st.d $s2, $sp, 24 # 8-byte Folded Spill
 ; LA64F-NEXT:    st.d $s3, $sp, 16 # 8-byte Folded Spill
 ; LA64F-NEXT:    move $fp, $a0
-; LA64F-NEXT:    ld.wu $a0, $a0, 0
-; LA64F-NEXT:    ld.wu $a1, $fp, 4
-; LA64F-NEXT:    slli.d $a1, $a1, 32
-; LA64F-NEXT:    or $a0, $a1, $a0
+; LA64F-NEXT:    ld.d $a0, $a0, 0
 ; LA64F-NEXT:    ori $s0, $zero, 8
 ; LA64F-NEXT:    addi.d $s1, $sp, 8
 ; LA64F-NEXT:    addi.d $s2, $sp, 0
 ; LA64F-NEXT:    ori $s3, $zero, 2
 ; LA64F-NEXT:  .LBB5_1: # %atomicrmw.start
 ; LA64F-NEXT:    # =>This Inner Loop Header: Depth=1
 ; LA64F-NEXT:    st.d $a0, $sp, 8
 ; LA64F-NEXT:    lu52i.d $a1, $zero, -1025

 ; LA64D-NEXT:    st.d $ra, $sp, 72 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $fp, $sp, 64 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $s0, $sp, 56 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $s1, $sp, 48 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $s2, $sp, 40 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $s3, $sp, 32 # 8-byte Folded Spill
 ; LA64D-NEXT:    fst.d $fs0, $sp, 24 # 8-byte Folded Spill
 ; LA64D-NEXT:    move $fp, $a0
-; LA64D-NEXT:    ld.wu $a0, $a0, 0
-; LA64D-NEXT:    ld.wu $a1, $fp, 4
-; LA64D-NEXT:    slli.d $a1, $a1, 32
-; LA64D-NEXT:    or $a0, $a1, $a0
-; LA64D-NEXT:    movgr2fr.d $fa0, $a0
+; LA64D-NEXT:    fld.d $fa0, $a0, 0
 ; LA64D-NEXT:    pcalau12i $a0, %pc_hi20(.LCPI5_0)
 ; LA64D-NEXT:    addi.d $a0, $a0, %pc_lo12(.LCPI5_0)
 ; LA64D-NEXT:    fld.d $fs0, $a0, 0
 ; LA64D-NEXT:    ori $s0, $zero, 8
 ; LA64D-NEXT:    addi.d $s1, $sp, 16
 ; LA64D-NEXT:    addi.d $s2, $sp, 8
 ; LA64D-NEXT:    ori $s3, $zero, 2
 ; LA64D-NEXT:  .LBB5_1: # %atomicrmw.start

 ; LA64F-NEXT:    addi.d $sp, $sp, -64
 ; LA64F-NEXT:    st.d $ra, $sp, 56 # 8-byte Folded Spill
 ; LA64F-NEXT:    st.d $fp, $sp, 48 # 8-byte Folded Spill
 ; LA64F-NEXT:    st.d $s0, $sp, 40 # 8-byte Folded Spill
 ; LA64F-NEXT:    st.d $s1, $sp, 32 # 8-byte Folded Spill
 ; LA64F-NEXT:    st.d $s2, $sp, 24 # 8-byte Folded Spill
 ; LA64F-NEXT:    st.d $s3, $sp, 16 # 8-byte Folded Spill
 ; LA64F-NEXT:    move $fp, $a0
-; LA64F-NEXT:    ld.wu $a0, $a0, 0
-; LA64F-NEXT:    ld.wu $a1, $fp, 4
-; LA64F-NEXT:    slli.d $a1, $a1, 32
-; LA64F-NEXT:    or $a0, $a1, $a0
+; LA64F-NEXT:    ld.d $a0, $a0, 0
 ; LA64F-NEXT:    ori $s0, $zero, 8
 ; LA64F-NEXT:    addi.d $s1, $sp, 8
 ; LA64F-NEXT:    addi.d $s2, $sp, 0
 ; LA64F-NEXT:    ori $s3, $zero, 2
 ; LA64F-NEXT:  .LBB6_1: # %atomicrmw.start
 ; LA64F-NEXT:    # =>This Inner Loop Header: Depth=1
 ; LA64F-NEXT:    st.d $a0, $sp, 8
 ; LA64F-NEXT:    lu52i.d $a1, $zero, 1023

 ; LA64D-NEXT:    st.d $ra, $sp, 72 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $fp, $sp, 64 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $s0, $sp, 56 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $s1, $sp, 48 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $s2, $sp, 40 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $s3, $sp, 32 # 8-byte Folded Spill
 ; LA64D-NEXT:    fst.d $fs0, $sp, 24 # 8-byte Folded Spill
 ; LA64D-NEXT:    move $fp, $a0
-; LA64D-NEXT:    ld.wu $a0, $a0, 0
-; LA64D-NEXT:    ld.wu $a1, $fp, 4
-; LA64D-NEXT:    slli.d $a1, $a1, 32
-; LA64D-NEXT:    or $a0, $a1, $a0
-; LA64D-NEXT:    movgr2fr.d $fa0, $a0
+; LA64D-NEXT:    fld.d $fa0, $a0, 0
 ; LA64D-NEXT:    addi.d $a0, $zero, 1
 ; LA64D-NEXT:    movgr2fr.d $fs0, $a0
 ; LA64D-NEXT:    ori $s0, $zero, 8
 ; LA64D-NEXT:    addi.d $s1, $sp, 16
 ; LA64D-NEXT:    addi.d $s2, $sp, 8
 ; LA64D-NEXT:    ori $s3, $zero, 2
 ; LA64D-NEXT:  .LBB6_1: # %atomicrmw.start
 ; LA64D-NEXT:    # =>This Inner Loop Header: Depth=1

 ; LA64F-NEXT:    addi.d $sp, $sp, -64
 ; LA64F-NEXT:    st.d $ra, $sp, 56 # 8-byte Folded Spill
 ; LA64F-NEXT:    st.d $fp, $sp, 48 # 8-byte Folded Spill
 ; LA64F-NEXT:    st.d $s0, $sp, 40 # 8-byte Folded Spill
 ; LA64F-NEXT:    st.d $s1, $sp, 32 # 8-byte Folded Spill
 ; LA64F-NEXT:    st.d $s2, $sp, 24 # 8-byte Folded Spill
 ; LA64F-NEXT:    st.d $s3, $sp, 16 # 8-byte Folded Spill
 ; LA64F-NEXT:    move $fp, $a0
-; LA64F-NEXT:    ld.wu $a0, $a0, 0
-; LA64F-NEXT:    ld.wu $a1, $fp, 4
-; LA64F-NEXT:    slli.d $a1, $a1, 32
-; LA64F-NEXT:    or $a0, $a1, $a0
+; LA64F-NEXT:    ld.d $a0, $a0, 0
 ; LA64F-NEXT:    ori $s0, $zero, 8
 ; LA64F-NEXT:    addi.d $s1, $sp, 8
 ; LA64F-NEXT:    addi.d $s2, $sp, 0
 ; LA64F-NEXT:    ori $s3, $zero, 2
 ; LA64F-NEXT:  .LBB7_1: # %atomicrmw.start
 ; LA64F-NEXT:    # =>This Inner Loop Header: Depth=1
 ; LA64F-NEXT:    st.d $a0, $sp, 8
 ; LA64F-NEXT:    lu52i.d $a1, $zero, 1023

 ; LA64D-NEXT:    st.d $ra, $sp, 72 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $fp, $sp, 64 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $s0, $sp, 56 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $s1, $sp, 48 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $s2, $sp, 40 # 8-byte Folded Spill
 ; LA64D-NEXT:    st.d $s3, $sp, 32 # 8-byte Folded Spill
 ; LA64D-NEXT:    fst.d $fs0, $sp, 24 # 8-byte Folded Spill
 ; LA64D-NEXT:    move $fp, $a0
-; LA64D-NEXT:    ld.wu $a0, $a0, 0
-; LA64D-NEXT:    ld.wu $a1, $fp, 4
-; LA64D-NEXT:    slli.d $a1, $a1, 32
-; LA64D-NEXT:    or $a0, $a1, $a0
-; LA64D-NEXT:    movgr2fr.d $fa0, $a0
+; LA64D-NEXT:    fld.d $fa0, $a0, 0
 ; LA64D-NEXT:    addi.d $a0, $zero, 1
 ; LA64D-NEXT:    movgr2fr.d $fs0, $a0
 ; LA64D-NEXT:    ori $s0, $zero, 8
 ; LA64D-NEXT:    addi.d $s1, $sp, 16
 ; LA64D-NEXT:    addi.d $s2, $sp, 8
 ; LA64D-NEXT:    ori $s3, $zero, 2
 ; LA64D-NEXT:  .LBB7_1: # %atomicrmw.start
 ; LA64D-NEXT:    # =>This Inner Loop Header: Depth=1

llvm/test/CodeGen/LoongArch/tail-calls.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
 
 ;; Perform tail call optimization for global address.
 declare i32 @callee_tail(i32 %i)
 define i32 @caller_tail(i32 %i) nounwind {
 ; CHECK-LABEL: caller_tail:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    b %plt(callee_tail)
 entry:
   %r = tail call i32 @callee_tail(i32 %i)
   ret i32 %r
 }
 
 ;; Perform tail call optimization for external symbol.
+;; Bytes copied should be large enough, otherwise the memcpy call would be optimized to multiple ld/st insns.
 @dest = global [2 x i8] zeroinitializer
 declare void @llvm.memcpy.p0i8.p0i8.i32(ptr, ptr, i32, i1)
 define void @caller_extern(ptr %src) optsize {
 ; CHECK-LABEL: caller_extern:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    move $a1, $a0
 ; CHECK-NEXT:    pcalau12i $a0, %got_pc_hi20(dest)
 ; CHECK-NEXT:    ld.d $a0, $a0, %got_pc_lo12(dest)
-; CHECK-NEXT:    ori $a2, $zero, 7
+; CHECK-NEXT:    ori $a2, $zero, 33
 ; CHECK-NEXT:    b %plt(memcpy)
 entry:
-  tail call void @llvm.memcpy.p0i8.p0i8.i32(ptr getelementptr inbounds ([2 x i8], ptr @dest, i32 0, i32 0), ptr %src, i32 7, i1 false)
+  tail call void @llvm.memcpy.p0i8.p0i8.i32(ptr getelementptr inbounds ([2 x i8], ptr @dest, i32 0, i32 0), ptr %src, i32 33, i1 false)
   ret void
 }
 
 ;; Perform indirect tail call optimization (for function pointer call).
 declare void @callee_indirect1()
 declare void @callee_indirect2()
 define void @caller_indirect_tail(i32 %a) nounwind {
 ; CHECK-LABEL: caller_indirect_tail:

llvm/test/CodeGen/LoongArch/unaligned-access.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+
+;; Test the ual feature which is similar to AArch64/arm64-strict-align.ll.
+
+; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s --check-prefix=LA32-ALIGNED
+; RUN: llc --mtriple=loongarch32 --mattr=+ual < %s | FileCheck %s --check-prefix=LA32-UNALIGNED
+; RUN: llc --mtriple=loongarch32 --mattr=-ual < %s | FileCheck %s --check-prefix=LA32-ALIGNED
+
+; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s --check-prefix=LA64-UNALIGNED
+; RUN: llc --mtriple=loongarch64 --mattr=+ual < %s | FileCheck %s --check-prefix=LA64-UNALIGNED
+; RUN: llc --mtriple=loongarch64 --mattr=-ual < %s | FileCheck %s --check-prefix=LA64-ALIGNED
+
+define i32 @f0(ptr %p) nounwind {
+; LA32-ALIGNED-LABEL: f0:
+; LA32-ALIGNED:       # %bb.0:
+; LA32-ALIGNED-NEXT:    ld.hu $a1, $a0, 0
+; LA32-ALIGNED-NEXT:    ld.hu $a0, $a0, 2
+; LA32-ALIGNED-NEXT:    slli.w $a0, $a0, 16
+; LA32-ALIGNED-NEXT:    or $a0, $a0, $a1
+; LA32-ALIGNED-NEXT:    ret
+;
+; LA32-UNALIGNED-LABEL: f0:
+; LA32-UNALIGNED:       # %bb.0:
+; LA32-UNALIGNED-NEXT:    ld.w $a0, $a0, 0
+; LA32-UNALIGNED-NEXT:    ret
+;
+; LA64-UNALIGNED-LABEL: f0:
+; LA64-UNALIGNED:       # %bb.0:
+; LA64-UNALIGNED-NEXT:    ld.w $a0, $a0, 0
+; LA64-UNALIGNED-NEXT:    ret
+;
+; LA64-ALIGNED-LABEL: f0:
+; LA64-ALIGNED:       # %bb.0:
+; LA64-ALIGNED-NEXT:    ld.hu $a1, $a0, 0
+; LA64-ALIGNED-NEXT:    ld.h $a0, $a0, 2
+; LA64-ALIGNED-NEXT:    slli.d $a0, $a0, 16
+; LA64-ALIGNED-NEXT:    or $a0, $a0, $a1
+; LA64-ALIGNED-NEXT:    ret
+  %tmp = load i32, ptr %p, align 2
+  ret i32 %tmp
+}
+
+define i64 @f1(ptr %p) nounwind {
+; LA32-ALIGNED-LABEL: f1:
+; LA32-ALIGNED:       # %bb.0:
+; LA32-ALIGNED-NEXT:    ld.w $a2, $a0, 0
+; LA32-ALIGNED-NEXT:    ld.w $a1, $a0, 4
+; LA32-ALIGNED-NEXT:    move $a0, $a2
+; LA32-ALIGNED-NEXT:    ret
+;
+; LA32-UNALIGNED-LABEL: f1:
+; LA32-UNALIGNED:       # %bb.0:
+; LA32-UNALIGNED-NEXT:    ld.w $a2, $a0, 0
+; LA32-UNALIGNED-NEXT:    ld.w $a1, $a0, 4
+; LA32-UNALIGNED-NEXT:    move $a0, $a2
+; LA32-UNALIGNED-NEXT:    ret
+;
+; LA64-UNALIGNED-LABEL: f1:
+; LA64-UNALIGNED:       # %bb.0:
+; LA64-UNALIGNED-NEXT:    ld.d $a0, $a0, 0
+; LA64-UNALIGNED-NEXT:    ret
+;
+; LA64-ALIGNED-LABEL: f1:
+; LA64-ALIGNED:       # %bb.0:
+; LA64-ALIGNED-NEXT:    ld.wu $a1, $a0, 0
+; LA64-ALIGNED-NEXT:    ld.wu $a0, $a0, 4
+; LA64-ALIGNED-NEXT:    slli.d $a0, $a0, 32
+; LA64-ALIGNED-NEXT:    or $a0, $a0, $a1
+; LA64-ALIGNED-NEXT:    ret
+  %tmp = load i64, ptr %p, align 4
+  ret i64 %tmp
+}

llvm/test/CodeGen/LoongArch/unaligned-memcpy-inline.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+
+;; Test how memcpy is optimized when ual is turned off which is similar to AArch64/arm64-misaligned-memcpy-inline.ll.
+
+; RUN: llc --mtriple=loongarch32 --mattr=-ual < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --mattr=-ual < %s | FileCheck %s --check-prefix=LA64
+
+;; Small (16 bytes here) unaligned memcpy() should be a function call if
+;; ual is turned off.
+define void @t0(ptr %out, ptr %in) {
+; LA32-LABEL: t0:
+; LA32:       # %bb.0: # %entry
+; LA32-NEXT:    addi.w $sp, $sp, -16
+; LA32-NEXT:    .cfi_def_cfa_offset 16
+; LA32-NEXT:    st.w $ra, $sp, 12 # 4-byte Folded Spill
+; LA32-NEXT:    .cfi_offset 1, -4
+; LA32-NEXT:    ori $a2, $zero, 16
+; LA32-NEXT:    bl %plt(memcpy)
+; LA32-NEXT:    ld.w $ra, $sp, 12 # 4-byte Folded Reload
+; LA32-NEXT:    addi.w $sp, $sp, 16
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: t0:
+; LA64:       # %bb.0: # %entry
+; LA64-NEXT:    addi.d $sp, $sp, -16
+; LA64-NEXT:    .cfi_def_cfa_offset 16
+; LA64-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
+; LA64-NEXT:    .cfi_offset 1, -8
+; LA64-NEXT:    ori $a2, $zero, 16
+; LA64-NEXT:    bl %plt(memcpy)
+; LA64-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
+; LA64-NEXT:    addi.d $sp, $sp, 16
+; LA64-NEXT:    ret
+entry:
+  call void @llvm.memcpy.p0.p0.i64(ptr %out, ptr %in, i64 16, i1 false)
+  ret void
+}
+
+;; Small (16 bytes here) aligned memcpy() should be inlined even if
+;; ual is turned off.
+define void @t1(ptr align 8 %out, ptr align 8 %in) {
+; LA32-LABEL: t1:
+; LA32:       # %bb.0: # %entry
+; LA32-NEXT:    ld.w $a2, $a1, 12
+; LA32-NEXT:    st.w $a2, $a0, 12
+; LA32-NEXT:    ld.w $a2, $a1, 8
+; LA32-NEXT:    st.w $a2, $a0, 8
+; LA32-NEXT:    ld.w $a2, $a1, 4
+; LA32-NEXT:    st.w $a2, $a0, 4
+; LA32-NEXT:    ld.w $a1, $a1, 0
+; LA32-NEXT:    st.w $a1, $a0, 0
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: t1:
+; LA64:       # %bb.0: # %entry
+; LA64-NEXT:    ld.d $a2, $a1, 8
+; LA64-NEXT:    st.d $a2, $a0, 8
+; LA64-NEXT:    ld.d $a1, $a1, 0
+; LA64-NEXT:    st.d $a1, $a0, 0
+; LA64-NEXT:    ret
+entry:
+  call void @llvm.memcpy.p0.p0.i64(ptr align 8 %out, ptr align 8 %in, i64 16, i1 false)
+  ret void
+}
+
+;; Tiny (4 bytes here) unaligned memcpy() should be inlined with byte sized
+;; loads and stores if ual is turned off.
+define void @t2(ptr %out, ptr %in) {
+; LA32-LABEL: t2:
+; LA32:       # %bb.0: # %entry
+; LA32-NEXT:    ld.b $a2, $a1, 3
+; LA32-NEXT:    st.b $a2, $a0, 3
+; LA32-NEXT:    ld.b $a2, $a1, 2
+; LA32-NEXT:    st.b $a2, $a0, 2
+; LA32-NEXT:    ld.b $a2, $a1, 1
+; LA32-NEXT:    st.b $a2, $a0, 1
+; LA32-NEXT:    ld.b $a1, $a1, 0
+; LA32-NEXT:    st.b $a1, $a0, 0
+; LA32-NEXT:    ret
+;
+; LA64-LABEL: t2:
+; LA64:       # %bb.0: # %entry
+; LA64-NEXT:    ld.b $a2, $a1, 3
+; LA64-NEXT:    st.b $a2, $a0, 3
+; LA64-NEXT:    ld.b $a2, $a1, 2
+; LA64-NEXT:    st.b $a2, $a0, 2
+; LA64-NEXT:    ld.b $a2, $a1, 1
+; LA64-NEXT:    st.b $a2, $a0, 1
+; LA64-NEXT:    ld.b $a1, $a1, 0
+; LA64-NEXT:    st.b $a1, $a0, 0
+; LA64-NEXT:    ret
+entry:
+  call void @llvm.memcpy.p0.p0.i64(ptr %out, ptr %in, i64 4, i1 false)
+  ret void
+}
+
+declare void @llvm.memcpy.p0.p0.i64(ptr nocapture, ptr nocapture readonly, i64, i1)