[AArch64] Extend fp64 top zeroing peephole to all instructions

[dmgreen]

Summary

D147235 added a fold to remove instructions that zero the upper half of a register if the instruction already implicitly zeros the register. As far as I can tell this applies to all instructions that define a FPR64 register in AArch64. This patch switches to a check for the register class. The full list of instructions is

BSPv8i8
FMOVD0
ABSv1i64
ABSv2i32
ABSv4i16
ABSv8i8
ADDHNv2i64_v2i32
ADDHNv4i32_v4i16
ADDHNv8i16_v8i8
ADDPv2i32
ADDPv2i64p
ADDPv4i16
ADDPv8i8
ADDv1i64
ADDv2i32
ADDv4i16
ADDv8i8
ANDv8i8
BF16DOTlanev4bf16
BFDOTv4bf16
BICv2i32
BICv4i16
BICv8i8
BIFv8i8
BITv8i8
BSLv8i8
CLASTA_VPZ_D
CLASTB_VPZ_D
CLSv2i32
CLSv4i16
CLSv8i8
CLZv2i32
CLZv4i16
CLZv8i8
CMEQv1i64
CMEQv1i64rz
CMEQv2i32
CMEQv2i32rz
CMEQv4i16
CMEQv4i16rz
CMEQv8i8
CMEQv8i8rz
CMGEv1i64
CMGEv1i64rz
CMGEv2i32
CMGEv2i32rz
CMGEv4i16
CMGEv4i16rz
CMGEv8i8
CMGEv8i8rz
CMGTv1i64
CMGTv1i64rz
CMGTv2i32
CMGTv2i32rz
CMGTv4i16
CMGTv4i16rz
CMGTv8i8
CMGTv8i8rz
CMHIv1i64
CMHIv2i32
CMHIv4i16
CMHIv8i8
CMHSv1i64
CMHSv2i32
CMHSv4i16
CMHSv8i8
CMLEv1i64rz
CMLEv2i32rz
CMLEv4i16rz
CMLEv8i8rz
CMLTv1i64rz
CMLTv2i32rz
CMLTv4i16rz
CMLTv8i8rz
CMTSTv1i64
CMTSTv2i32
CMTSTv4i16
CMTSTv8i8
CNTv8i8
DUPi64
DUPv2i32gpr
DUPv2i32lane
DUPv4i16gpr
DUPv4i16lane
DUPv8i8gpr
DUPv8i8lane
EORv8i8
EXTv8i8
FABD64
FABDv2f32
FABDv4f16
FABSDr
FABSv2f32
FABSv4f16
FACGE64
FACGEv2f32
FACGEv4f16
FACGT64
FACGTv2f32
FACGTv4f16
FADDDrr
FADDPv2f32
FADDPv2i64p
FADDPv4f16
FADDv2f32
FADDv4f16
FCADDv2f32
FCADDv4f16
FCMEQ64
FCMEQv1i64rz
FCMEQv2f32
FCMEQv2i32rz
FCMEQv4f16
FCMEQv4i16rz
FCMGE64
FCMGEv1i64rz
FCMGEv2f32
FCMGEv2i32rz
FCMGEv4f16
FCMGEv4i16rz
FCMGT64
FCMGTv1i64rz
FCMGTv2f32
FCMGTv2i32rz
FCMGTv4f16
FCMGTv4i16rz
FCMLAv2f32
FCMLAv4f16
FCMLAv4f16_indexed
FCMLEv1i64rz
FCMLEv2i32rz
FCMLEv4i16rz
FCMLTv1i64rz
FCMLTv2i32rz
FCMLTv4i16rz
FCSELDrrr
FCVTASv1i64
FCVTASv2f32
FCVTASv4f16
FCVTAUv1i64
FCVTAUv2f32
FCVTAUv4f16
FCVTDHr
FCVTDSr
FCVTMSv1i64
FCVTMSv2f32
FCVTMSv4f16
FCVTMUv1i64
FCVTMUv2f32
FCVTMUv4f16
FCVTNSv1i64
FCVTNSv2f32
FCVTNSv4f16
FCVTNUv1i64
FCVTNUv2f32
FCVTNUv4f16
FCVTNv2i32
FCVTNv4i16
FCVTPSv1i64
FCVTPSv2f32
FCVTPSv4f16
FCVTPUv1i64
FCVTPUv2f32
FCVTPUv4f16
FCVTXNv2f32
FCVTZSd
FCVTZSv1i64
FCVTZSv2f32
FCVTZSv2i32_shift
FCVTZSv4f16
FCVTZSv4i16_shift
FCVTZUd
FCVTZUv1i64
FCVTZUv2f32
FCVTZUv2i32_shift
FCVTZUv4f16
FCVTZUv4i16_shift
FDIVDrr
FDIVv2f32
FDIVv4f16
FMADDDrrr
FMAXDrr
FMAXNMDrr
FMAXNMPv2f32
FMAXNMPv2i64p
FMAXNMPv4f16
FMAXNMv2f32
FMAXNMv4f16
FMAXPv2f32
FMAXPv2i64p
FMAXPv4f16
FMAXv2f32
FMAXv4f16
FMINDrr
FMINNMDrr
FMINNMPv2f32
FMINNMPv2i64p
FMINNMPv4f16
FMINNMv2f32
FMINNMv4f16
FMINPv2f32
FMINPv2i64p
FMINPv4f16
FMINv2f32
FMINv4f16
FMLAL2lanev4f16
FMLAL2v4f16
FMLALlanev4f16
FMLALv4f16
FMLAv1i64_indexed
FMLAv2f32
FMLAv2i32_indexed
FMLAv4f16
FMLAv4i16_indexed
FMLSL2lanev4f16
FMLSL2v4f16
FMLSLlanev4f16
FMLSLv4f16
FMLSv1i64_indexed
FMLSv2f32
FMLSv2i32_indexed
FMLSv4f16
FMLSv4i16_indexed
FMOVDi
FMOVDr
FMOVXDr
FMOVv2f32_ns
FMOVv4f16_ns
FMSUBDrrr
FMULDrr
FMULX64
FMULXv1i64_indexed
FMULXv2f32
FMULXv2i32_indexed
FMULXv4f16
FMULXv4i16_indexed
FMULv1i64_indexed
FMULv2f32
FMULv2i32_indexed
FMULv4f16
FMULv4i16_indexed
FNEGDr
FNEGv2f32
FNEGv4f16
FNMADDDrrr
FNMSUBDrrr
FNMULDrr
FRECPEv1i64
FRECPEv2f32
FRECPEv4f16
FRECPS64
FRECPSv2f32
FRECPSv4f16
FRECPXv1i64
FRINT32XDr
FRINT32Xv2f32
FRINT32ZDr
FRINT32Zv2f32
FRINT64XDr
FRINT64Xv2f32
FRINT64ZDr
FRINT64Zv2f32
FRINTADr
FRINTAv2f32
FRINTAv4f16
FRINTIDr
FRINTIv2f32
FRINTIv4f16
FRINTMDr
FRINTMv2f32
FRINTMv4f16
FRINTNDr
FRINTNv2f32
FRINTNv4f16
FRINTPDr
FRINTPv2f32
FRINTPv4f16
FRINTXDr
FRINTXv2f32
FRINTXv4f16
FRINTZDr
FRINTZv2f32
FRINTZv4f16
FRSQRTEv1i64
FRSQRTEv2f32
FRSQRTEv4f16
FRSQRTS64
FRSQRTSv2f32
FRSQRTSv4f16
FSQRTDr
FSQRTv2f32
FSQRTv4f16
FSUBDrr
FSUBv2f32
FSUBv4f16
LASTA_VPZ_D
LASTB_VPZ_D
LD1Onev1d
LD1Onev2s
LD1Onev4h
LD1Onev8b
LD1Rv1d
LD1Rv2s
LD1Rv4h
LD1Rv8b
LDAPURdi
LDNPDi
LDPDi
LDRDl
LDRDroW
LDRDroX
LDRDui
LDURDi
MLAv2i32
MLAv2i32_indexed
MLAv4i16
MLAv4i16_indexed
MLAv8i8
MLSv2i32
MLSv2i32_indexed
MLSv4i16
MLSv4i16_indexed
MLSv8i8
MOVID
MOVIv2i32
MOVIv2s_msl
MOVIv4i16
MOVIv8b_ns
MULv2i32
MULv2i32_indexed
MULv4i16
MULv4i16_indexed
MULv8i8
MVNIv2i32
MVNIv2s_msl
MVNIv4i16
NEGv1i64
NEGv2i32
NEGv4i16
NEGv8i8
NOTv8i8
ORNv8i8
ORRv2i32
ORRv4i16
ORRv8i8
PMULv8i8
RADDHNv2i64_v2i32
RADDHNv4i32_v4i16
RADDHNv8i16_v8i8
RBITv8i8
REV16v8i8
REV32v4i16
REV32v8i8
REV64v2i32
REV64v4i16
REV64v8i8
RSHRNv2i32_shift
RSHRNv4i16_shift
RSHRNv8i8_shift
RSUBHNv2i64_v2i32
RSUBHNv4i32_v4i16
RSUBHNv8i16_v8i8
SABAv2i32
SABAv4i16
SABAv8i8
SABDv2i32
SABDv4i16
SABDv8i8
SADALPv2i32_v1i64
SADALPv4i16_v2i32
SADALPv8i8_v4i16
SADDLPv2i32_v1i64
SADDLPv4i16_v2i32
SADDLPv8i8_v4i16
SADDLVv4i32v
SCVTFSWDri
SCVTFSXDri
SCVTFUWDri
SCVTFUXDri
SCVTFd
SCVTFv1i64
SCVTFv2f32
SCVTFv2i32_shift
SCVTFv4f16
SCVTFv4i16_shift
SDOTlanev8i8
SDOTv8i8
SHADDv2i32
SHADDv4i16
SHADDv8i8
SHLd
SHLv2i32_shift
SHLv4i16_shift
SHLv8i8_shift
SHRNv2i32_shift
SHRNv4i16_shift
SHRNv8i8_shift
SHSUBv2i32
SHSUBv4i16
SHSUBv8i8
SLId
SLIv2i32_shift
SLIv4i16_shift
SLIv8i8_shift
SMAXPv2i32
SMAXPv4i16
SMAXPv8i8
SMAXv2i32
SMAXv4i16
SMAXv8i8
SMINPv2i32
SMINPv4i16
SMINPv8i8
SMINv2i32
SMINv4i16
SMINv8i8
SQABSv1i64
SQABSv2i32
SQABSv4i16
SQABSv8i8
SQADDv1i64
SQADDv2i32
SQADDv4i16
SQADDv8i8
SQDMLALi32
SQDMLALv1i64_indexed
SQDMLSLi32
SQDMLSLv1i64_indexed
SQDMULHv2i32
SQDMULHv2i32_indexed
SQDMULHv4i16
SQDMULHv4i16_indexed
SQDMULLi32
SQDMULLv1i64_indexed
SQNEGv1i64
SQNEGv2i32
SQNEGv4i16
SQNEGv8i8
SQRDMLAHv2i32
SQRDMLAHv2i32_indexed
SQRDMLAHv4i16
SQRDMLAHv4i16_indexed
SQRDMLSHv2i32
SQRDMLSHv2i32_indexed
SQRDMLSHv4i16
SQRDMLSHv4i16_indexed
SQRDMULHv2i32
SQRDMULHv2i32_indexed
SQRDMULHv4i16
SQRDMULHv4i16_indexed
SQRSHLv1i64
SQRSHLv2i32
SQRSHLv4i16
SQRSHLv8i8
SQRSHRNv2i32_shift
SQRSHRNv4i16_shift
SQRSHRNv8i8_shift
SQRSHRUNv2i32_shift
SQRSHRUNv4i16_shift
SQRSHRUNv8i8_shift
SQSHLUd
SQSHLUv2i32_shift
SQSHLUv4i16_shift
SQSHLUv8i8_shift
SQSHLd
SQSHLv1i64
SQSHLv2i32
SQSHLv2i32_shift
SQSHLv4i16
SQSHLv4i16_shift
SQSHLv8i8
SQSHLv8i8_shift
SQSHRNv2i32_shift
SQSHRNv4i16_shift
SQSHRNv8i8_shift
SQSHRUNv2i32_shift
SQSHRUNv4i16_shift
SQSHRUNv8i8_shift
SQSUBv1i64
SQSUBv2i32
SQSUBv4i16
SQSUBv8i8
SQXTNv2i32
SQXTNv4i16
SQXTNv8i8
SQXTUNv2i32
SQXTUNv4i16
SQXTUNv8i8
SRHADDv2i32
SRHADDv4i16
SRHADDv8i8
SRId
SRIv2i32_shift
SRIv4i16_shift
SRIv8i8_shift
SRSHLv1i64
SRSHLv2i32
SRSHLv4i16
SRSHLv8i8
SRSHRd
SRSHRv2i32_shift
SRSHRv4i16_shift
SRSHRv8i8_shift
SRSRAd
SRSRAv2i32_shift
SRSRAv4i16_shift
SRSRAv8i8_shift
SSHLv1i64
SSHLv2i32
SSHLv4i16
SSHLv8i8
SSHRd
SSHRv2i32_shift
SSHRv4i16_shift
SSHRv8i8_shift
SSRAd
SSRAv2i32_shift
SSRAv4i16_shift
SSRAv8i8_shift
SUBHNv2i64_v2i32
SUBHNv4i32_v4i16
SUBHNv8i16_v8i8
SUBv1i64
SUBv2i32
SUBv4i16
SUBv8i8
SUDOTlanev8i8
SUQADDv1i64
SUQADDv2i32
SUQADDv4i16
SUQADDv8i8
TBLv8i8Four
TBLv8i8One
TBLv8i8Three
TBLv8i8Two
TBXv8i8Four
TBXv8i8One
TBXv8i8Three
TBXv8i8Two
TRN1v2i32
TRN1v4i16
TRN1v8i8
TRN2v2i32
TRN2v4i16
TRN2v8i8
UABAv2i32
UABAv4i16
UABAv8i8
UABDv2i32
UABDv4i16
UABDv8i8
UADALPv2i32_v1i64
UADALPv4i16_v2i32
UADALPv8i8_v4i16
UADDLPv2i32_v1i64
UADDLPv4i16_v2i32
UADDLPv8i8_v4i16
UADDLVv4i32v
UCVTFSWDri
UCVTFSXDri
UCVTFUWDri
UCVTFUXDri
UCVTFd
UCVTFv1i64
UCVTFv2f32
UCVTFv2i32_shift
UCVTFv4f16
UCVTFv4i16_shift
UDOTlanev8i8
UDOTv8i8
UHADDv2i32
UHADDv4i16
UHADDv8i8
UHSUBv2i32
UHSUBv4i16
UHSUBv8i8
UMAXPv2i32
UMAXPv4i16
UMAXPv8i8
UMAXv2i32
UMAXv4i16
UMAXv8i8
UMINPv2i32
UMINPv4i16
UMINPv8i8
UMINv2i32
UMINv4i16
UMINv8i8
UQADDv1i64
UQADDv2i32
UQADDv4i16
UQADDv8i8
UQRSHLv1i64
UQRSHLv2i32
UQRSHLv4i16
UQRSHLv8i8
UQRSHRNv2i32_shift
UQRSHRNv4i16_shift
UQRSHRNv8i8_shift
UQSHLd
UQSHLv1i64
UQSHLv2i32
UQSHLv2i32_shift
UQSHLv4i16
UQSHLv4i16_shift
UQSHLv8i8
UQSHLv8i8_shift
UQSHRNv2i32_shift
UQSHRNv4i16_shift
UQSHRNv8i8_shift
UQSUBv1i64
UQSUBv2i32
UQSUBv4i16
UQSUBv8i8
UQXTNv2i32
UQXTNv4i16
UQXTNv8i8
URECPEv2i32
URHADDv2i32
URHADDv4i16
URHADDv8i8
URSHLv1i64
URSHLv2i32
URSHLv4i16
URSHLv8i8
URSHRd
URSHRv2i32_shift
URSHRv4i16_shift
URSHRv8i8_shift
URSQRTEv2i32
URSRAd
URSRAv2i32_shift
URSRAv4i16_shift
URSRAv8i8_shift
USDOTlanev8i8
USDOTv8i8
USHLv1i64
USHLv2i32
USHLv4i16
USHLv8i8
USHRd
USHRv2i32_shift
USHRv4i16_shift
USHRv8i8_shift
USQADDv1i64
USQADDv2i32
USQADDv4i16
USQADDv8i8
USRAd
USRAv2i32_shift
USRAv4i16_shift
USRAv8i8_shift
UZP1v2i32
UZP1v4i16
UZP1v8i8
UZP2v2i32
UZP2v4i16
UZP2v8i8
XTNv2i32
XTNv4i16
XTNv8i8
ZIP1v2i32
ZIP1v4i16
ZIP1v8i8
ZIP2v2i32
ZIP2v4i16
ZIP2v8i8

[SjoerdMeijer]

Looks like a good idea.

[dmgreen]

6e7840dd42d1c0a23f69bcfcda457f086ed35743

llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp

MachineInstr *INSvilaneMI =
           .addImm(0);
 
   LLVM_DEBUG(dbgs() << MI << "  replace by:\n: " << *INSvilaneMI << "\n");
   (void)INSvilaneMI;
   MI.eraseFromParent();
   return true;
 }
 
-static bool is64bitDefwithZeroHigh64bit(MachineInstr *MI) {
-  // ToDo: check and add more MIs which set zero for high 64bits.
-  switch (MI->getOpcode()) {
-  default:
-    break;
-  case AArch64::FCVTNv2i32:
-  case AArch64::FCVTNv4i16:
-  case AArch64::RSHRNv2i32_shift:
-  case AArch64::RSHRNv4i16_shift:
-  case AArch64::RSHRNv8i8_shift :
-  case AArch64::SHRNv2i32_shift:
-  case AArch64::SHRNv4i16_shift:
-  case AArch64::SHRNv8i8_shift:
-    return true;
-  }
-
+// All instructions that set a FPR64 will implicitly zero the top bits of the
+// register.
+static bool is64bitDefwithZeroHigh64bit(MachineInstr *MI,
+                                        MachineRegisterInfo *MRI) {
+  if (!MI->getOperand(0).isDef() || !MI->getOperand(0).isReg())
+    return false;
+  const TargetRegisterClass *RC = MRI->getRegClass(MI->getOperand(0).getReg());
+  if (RC != &AArch64::FPR64RegClass)
     return false;
+  return MI->getOpcode() > TargetOpcode::GENERIC_OP_END;
 }
 
 bool AArch64MIPeepholeOpt::visitINSvi64lane(MachineInstr &MI) {
   // Check the MI for low 64-bits sets zero for high 64-bits implicitly.
   // We are expecting below case.
   //
   //  %1:fpr64 = nofpexcept FCVTNv4i16 %0:fpr128, implicit $fpcr
   //  %6:fpr128 = IMPLICIT_DEF
   //  %5:fpr128 = INSERT_SUBREG %6:fpr128(tied-def 0), killed %1:fpr64, %subreg.dsub
   //  %7:fpr128 = INSvi64lane %5:fpr128(tied-def 0), 1, killed %3:fpr128, 0
   MachineInstr *Low64MI = MRI->getUniqueVRegDef(MI.getOperand(1).getReg());
   if (Low64MI->getOpcode() != AArch64::INSERT_SUBREG)
     return false;
   Low64MI = MRI->getUniqueVRegDef(Low64MI->getOperand(2).getReg());
-  if (!is64bitDefwithZeroHigh64bit(Low64MI))
+  if (!Low64MI || !is64bitDefwithZeroHigh64bit(Low64MI, MRI))
     return false;
 
   // Check there is `mov 0` MI for high 64-bits.
   // We are expecting below cases.
   //
   //  %2:fpr64 = MOVID 0
   //  %4:fpr128 = IMPLICIT_DEF
   //  %3:fpr128 = INSERT_SUBREG %4:fpr128(tied-def 0), killed %2:fpr64, %subreg.dsub
   //  %7:fpr128 = INSvi64lane %5:fpr128(tied-def 0), 1, killed %3:fpr128, 0
   // or
   //  %5:fpr128 = MOVIv2d_ns 0
   //  %6:fpr64 = COPY %5.dsub:fpr128
   //  %8:fpr128 = IMPLICIT_DEF
   //  %7:fpr128 = INSERT_SUBREG %8:fpr128(tied-def 0), killed %6:fpr64, %subreg.dsub
   //  %11:fpr128 = INSvi64lane %9:fpr128(tied-def 0), 1, killed %7:fpr128, 0
   MachineInstr *High64MI = MRI->getUniqueVRegDef(MI.getOperand(3).getReg());
-  if (High64MI->getOpcode() != AArch64::INSERT_SUBREG)
+  if (!High64MI || High64MI->getOpcode() != AArch64::INSERT_SUBREG)
     return false;
   High64MI = MRI->getUniqueVRegDef(High64MI->getOperand(2).getReg());
-  if (High64MI->getOpcode() == TargetOpcode::COPY)
+  if (High64MI && High64MI->getOpcode() == TargetOpcode::COPY)
     High64MI = MRI->getUniqueVRegDef(High64MI->getOperand(1).getReg());
-  if (High64MI->getOpcode() != AArch64::MOVID &&
-      High64MI->getOpcode() != AArch64::MOVIv2d_ns)
+  if (!High64MI || (High64MI->getOpcode() != AArch64::MOVID &&
+                    High64MI->getOpcode() != AArch64::MOVIv2d_ns))
     return false;
   if (High64MI->getOperand(1).getImm() != 0)
     return false;
 
   // Let's remove MIs for high 64-bits.
   Register OldDef = MI.getOperand(0).getReg();
   Register NewDef = MI.getOperand(1).getReg();
   MRI->replaceRegWith(OldDef, NewDef);

llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll

 }
 
 define void @typei1_orig(i64 %a, ptr %p, ptr %q) {
 ; CHECK-LABEL: typei1_orig:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmp x0, #0
 ; CHECK-NEXT:    ldr q0, [x2]
 ; CHECK-NEXT:    cset w8, gt
-; CHECK-NEXT:    movi v2.2d, #0000000000000000
 ; CHECK-NEXT:    cmtst v0.8h, v0.8h, v0.8h
 ; CHECK-NEXT:    dup v1.8h, w8
 ; CHECK-NEXT:    cmeq v1.8h, v1.8h, #0
 ; CHECK-NEXT:    bic v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    xtn v0.8b, v0.8h
-; CHECK-NEXT:    mov v0.d[1], v2.d[0]
 ; CHECK-NEXT:    str q0, [x1]
 ; CHECK-NEXT:    ret
     %tmp = xor <16 x i1> zeroinitializer, <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>
     %tmp6 = load <8 x i16>, ptr %q, align 2
     %tmp7 = sub <8 x i16> zeroinitializer, %tmp6
     %tmp8 = shufflevector <8 x i16> %tmp7, <8 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
     %tmp9 = icmp slt i64 0, %a
     %tmp10 = zext i1 %tmp9 to i16

llvm/test/CodeGen/AArch64/implicitly-set-zero-high-64-bits.ll

entry:
   %vtbl1.i = shufflevector <8 x i8> %vshrn_n, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %vtbl11.i = tail call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %idx)
   ret <8 x i8> %vtbl11.i
 }
 
 define <8 x i16> @addpv4i16(<4 x i16> noundef %a, <4 x i16> noundef %b) {
 ; CHECK-LABEL: addpv4i16:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    movi v2.2d, #0000000000000000
 ; CHECK-NEXT:    addp v0.4h, v0.4h, v1.4h
-; CHECK-NEXT:    mov v0.d[1], v2.d[0]
 ; CHECK-NEXT:    ret
 entry:
   %vpadd_v2.i = tail call <4 x i16> @llvm.aarch64.neon.addp.v4i16(<4 x i16> %a, <4 x i16> %b)
   %shuffle.i = shufflevector <4 x i16> %vpadd_v2.i, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %shuffle.i
 }
 
 define <8 x i16> @addv4i16(<4 x i16> noundef %a, <4 x i16> noundef %b) {
 ; CHECK-LABEL: addv4i16:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    movi v2.2d, #0000000000000000
 ; CHECK-NEXT:    add v0.4h, v1.4h, v0.4h
-; CHECK-NEXT:    mov v0.d[1], v2.d[0]
 ; CHECK-NEXT:    ret
 entry:
   %add.i = add <4 x i16> %b, %a
   %shuffle.i = shufflevector <4 x i16> %add.i, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %shuffle.i
 }
 
 define <16 x i8> @rshrn(<8 x i16> noundef %a, <4 x i16> noundef %b) {
 ; CHECK-LABEL: rshrn:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    rshrn v0.8b, v0.8h, #3
 ; CHECK-NEXT:    ret
 entry:
   %vrshrn_n1 = tail call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> %a, i32 3)
   %shuffle.i = shufflevector <8 x i8> %vrshrn_n1, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %shuffle.i
 }
 
 define <16 x i8> @tbl1(<16 x i8> %a, <8 x i8> %b) {
 ; CHECK-LABEL: tbl1:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    movi v2.2d, #0000000000000000
 ; CHECK-NEXT:    tbl v0.8b, { v0.16b }, v1.8b
-; CHECK-NEXT:    mov v0.d[1], v2.d[0]
 ; CHECK-NEXT:    ret
 entry:
   %vtbl11 = tail call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %a, <8 x i8> %b)
   %shuffle.i = shufflevector <8 x i8> %vtbl11, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %shuffle.i
 }
 
 define <2 x double> @fadd(double noundef %x, double noundef %y) {
entry:
   %vecinit1 = insertelement <2 x double> poison, double %add, i64 0
   %vecinit2 = insertelement <2 x double> %vecinit1, double 0.0, i64 1
   ret <2 x double> %vecinit2
 }
 
 define <16 x i8> @bsl(<4 x i16> noundef %a, <4 x i16> noundef %c, <4 x i16> noundef %d, <4 x i16> noundef %b) {
 ; CHECK-LABEL: bsl:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    movi v3.2d, #0000000000000000
 ; CHECK-NEXT:    bsl v0.8b, v1.8b, v2.8b
-; CHECK-NEXT:    mov v0.d[1], v3.d[0]
 ; CHECK-NEXT:    ret
 entry:
   %vbsl3.i = and <4 x i16> %c, %a
   %0 = xor <4 x i16> %a, <i16 -1, i16 -1, i16 -1, i16 -1>
   %vbsl4.i = and <4 x i16> %0, %d
   %vbsl5.i = or <4 x i16> %vbsl4.i, %vbsl3.i
   %1 = bitcast <4 x i16> %vbsl5.i to <8 x i8>
   %shuffle.i = shufflevector <8 x i8> %1, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %shuffle.i
 }
 
 
 declare <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16>, i32)
 declare <4 x i16> @llvm.aarch64.neon.addp.v4i16(<4 x i16>, <4 x i16>)

llvm/test/CodeGen/AArch64/peephole-insvigpr.mir

bb.0.entry:
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK-NEXT: [[FADDDrr:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[COPY1]], [[COPY]], implicit $fpcr
     ; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[MOVIv2d_ns]].dsub
     ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
     ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], killed [[COPY2]], %subreg.dsub
     ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
     ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], killed [[FADDDrr]], %subreg.dsub
-    ; CHECK-NEXT: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG1]], 1, killed [[INSERT_SUBREG]], 0
-    ; CHECK-NEXT: $q0 = COPY [[INSvi64lane]]
+    ; CHECK-NEXT: $q0 = COPY [[INSERT_SUBREG1]]
     ; CHECK-NEXT: RET_ReallyLR implicit $q0
     %1:fpr64 = COPY $d1
     %0:fpr64 = COPY $d0
     %2:fpr64 = nofpexcept FADDDrr %0, %1, implicit $fpcr
     %3:fpr128 = MOVIv2d_ns 0
     %4:fpr64 = COPY %3.dsub
     %6:fpr128 = IMPLICIT_DEF
     %5:fpr128 = INSERT_SUBREG %6, killed %4, %subreg.dsub
     %8:fpr128 = IMPLICIT_DEF
     %7:fpr128 = INSERT_SUBREG %8, killed %2, %subreg.dsub
     %9:fpr128 = INSvi64lane %7, 1, killed %5, 0
     $q0 = COPY %9
     RET_ReallyLR implicit $q0
 
 ...