[PowerPC] Look through OR, AND, XOR instructions when checking a clear.

[stefanp]

Summary

This patch adds the additional step of looking through AND, OR, XOR
instructions when we check the number of leading zeros.

[shchenz]

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

231

typo? Seem the two operand of the min/max are the same.

[shchenz]

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

222

record form too?

[amyk]

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

224

Is it possible to pull out MI->getOperand(1).getReg() to be used in both cases?

227

Do we need PPC::OR8, too?

[stefanp]

Fixed the operands because they were not supposed to be the same.
Added the record forms.
Fixed the typo of having two XOR8 and no OR8.

[shchenz]

LGTM.

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

if (Opcode == PPC::LHZ   || Opcode == PPC::LHZX  ||
     return 48;
 
   if (Opcode == PPC::LBZ   || Opcode == PPC::LBZX  ||
       Opcode == PPC::LBZ8  || Opcode == PPC::LBZX8 ||
       Opcode == PPC::LBZU  || Opcode == PPC::LBZUX ||
       Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8)
     return 56;
 
+  if (Opcode == PPC::AND || Opcode == PPC::AND8)
+    return std::max(
+        getKnownLeadingZeroCount(MI->getOperand(1).getReg(), TII, MRI),
+        getKnownLeadingZeroCount(MI->getOperand(1).getReg(), TII, MRI));
+
+  if (Opcode == PPC::OR || Opcode == PPC::XOR8 || Opcode == PPC::XOR ||
+      Opcode == PPC::XOR8)
+    return std::min(
+        getKnownLeadingZeroCount(MI->getOperand(1).getReg(), TII, MRI),
+        getKnownLeadingZeroCount(MI->getOperand(1).getReg(), TII, MRI));
+
   if (TII->isZeroExtended(Reg, MRI))
     return 32;
 
   return 0;
 }
 
 // This function maintains a map for the pairs <TOC Save Instr, Keep>
 // Each time a new TOC save is encountered, it checks if any of the existing

llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll

 ; P8-NEXT:    mtfsb1 31
 ; P8-NEXT:    mtfsb0 30
 ; P8-NEXT:    fadd f1, f2, f1
 ; P8-NEXT:    mtfsf 1, f0
 ; P8-NEXT:    xscvdpsxws f0, f1
 ; P8-NEXT:    mffprwz r3, f0
 ; P8-NEXT:    xor r3, r3, r30
 ; P8-NEXT:    ld r30, 112(r1) # 8-byte Folded Reload
-; P8-NEXT:    clrldi r3, r3, 32
 ; P8-NEXT:    addi r1, r1, 128
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: ppcq_to_u32:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    mflr r0

 ; P9-NEXT:    mffs f0
 ; P9-NEXT:    mtfsb1 31
 ; P9-NEXT:    mtfsb0 30
 ; P9-NEXT:    fadd f1, f2, f1
 ; P9-NEXT:    mtfsf 1, f0
 ; P9-NEXT:    xscvdpsxws f0, f1
 ; P9-NEXT:    mffprwz r3, f0
 ; P9-NEXT:    xor r3, r3, r30
-; P9-NEXT:    clrldi r3, r3, 32
 ; P9-NEXT:    addi r1, r1, 48
 ; P9-NEXT:    ld r0, 16(r1)
 ; P9-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; P9-NEXT:    mtlr r0
 ; P9-NEXT:    blr
 ;
 ; NOVSX-LABEL: ppcq_to_u32:
 ; NOVSX:       # %bb.0: # %entry

 ; NOVSX-NEXT:    fadd f1, f2, f1
 ; NOVSX-NEXT:    mtfsf 1, f0
 ; NOVSX-NEXT:    fctiwz f0, f1
 ; NOVSX-NEXT:    stfiwx f0, 0, r3
 ; NOVSX-NEXT:    lis r3, -32768
 ; NOVSX-NEXT:    lwz r4, 44(r1)
 ; NOVSX-NEXT:    isel r3, 0, r3, 4*cr2+lt
 ; NOVSX-NEXT:    xor r3, r4, r3
-; NOVSX-NEXT:    clrldi r3, r3, 32
 ; NOVSX-NEXT:    addi r1, r1, 48
 ; NOVSX-NEXT:    ld r0, 16(r1)
 ; NOVSX-NEXT:    lwz r12, 8(r1)
 ; NOVSX-NEXT:    mtocrf 32, r12
 ; NOVSX-NEXT:    mtlr r0
 ; NOVSX-NEXT:    blr
 entry:
   %conv = tail call i32 @llvm.experimental.constrained.fptoui.i32.ppcf128(ppc_fp128 %m, metadata !"fpexcept.strict") #0

llvm/test/CodeGen/PowerPC/ppc-clear-before-return.ll

 
 
 define dso_local i64 @test_xor(ptr nocapture noundef readonly %inp) local_unnamed_addr #0 {
 ; 64BIT-LABEL: test_xor:
 ; 64BIT:       # %bb.0: # %entry
 ; 64BIT-NEXT:    lbz r4, 0(r3)
 ; 64BIT-NEXT:    lbz r3, 1(r3)
 ; 64BIT-NEXT:    xor r3, r3, r4
-; 64BIT-NEXT:    clrldi r3, r3, 56
 ; 64BIT-NEXT:    blr
 ;
 ; 32BIT-LABEL: test_xor:
 ; 32BIT:       # %bb.0: # %entry
 ; 32BIT-NEXT:    mr r4, r3
 ; 32BIT-NEXT:    li r3, 0
 ; 32BIT-NEXT:    lbz r5, 0(r4)
 ; 32BIT-NEXT:    lbz r4, 1(r4)

 define dso_local i64 @test_xor2(ptr nocapture noundef readonly %inp) local_unnamed_addr #0 {
 ; 64BIT-LABEL: test_xor2:
 ; 64BIT:       # %bb.0: # %entry
 ; 64BIT-NEXT:    lbz r4, 0(r3)
 ; 64BIT-NEXT:    lbz r5, 1(r3)
 ; 64BIT-NEXT:    lbz r3, 2(r3)
 ; 64BIT-NEXT:    xor r4, r5, r4
 ; 64BIT-NEXT:    xor r3, r4, r3
-; 64BIT-NEXT:    clrldi r3, r3, 56
 ; 64BIT-NEXT:    blr
 ;
 ; 32BIT-LABEL: test_xor2:
 ; 32BIT:       # %bb.0: # %entry
 ; 32BIT-NEXT:    mr r4, r3
 ; 32BIT-NEXT:    li r3, 0
 ; 32BIT-NEXT:    lbz r5, 0(r4)
 ; 32BIT-NEXT:    lbz r6, 1(r4)

 }
 
 define dso_local i64 @test_or(ptr nocapture noundef readonly %inp) local_unnamed_addr #0 {
 ; 64BIT-LABEL: test_or:
 ; 64BIT:       # %bb.0: # %entry
 ; 64BIT-NEXT:    lbz r4, 0(r3)
 ; 64BIT-NEXT:    lbz r3, 1(r3)
 ; 64BIT-NEXT:    or r3, r3, r4
-; 64BIT-NEXT:    clrldi r3, r3, 56
 ; 64BIT-NEXT:    blr
 ;
 ; 32BIT-LABEL: test_or:
 ; 32BIT:       # %bb.0: # %entry
 ; 32BIT-NEXT:    mr r4, r3
 ; 32BIT-NEXT:    li r3, 0
 ; 32BIT-NEXT:    lbz r5, 0(r4)
 ; 32BIT-NEXT:    lbz r4, 1(r4)

 define dso_local i64 @test_or2(ptr nocapture noundef readonly %inp) local_unnamed_addr #0 {
 ; 64BIT-LABEL: test_or2:
 ; 64BIT:       # %bb.0: # %entry
 ; 64BIT-NEXT:    lbz r4, 0(r3)
 ; 64BIT-NEXT:    lbz r5, 1(r3)
 ; 64BIT-NEXT:    lbz r3, 2(r3)
 ; 64BIT-NEXT:    or r4, r5, r4
 ; 64BIT-NEXT:    or r3, r4, r3
-; 64BIT-NEXT:    clrldi r3, r3, 56
 ; 64BIT-NEXT:    blr
 ;
 ; 32BIT-LABEL: test_or2:
 ; 32BIT:       # %bb.0: # %entry
 ; 32BIT-NEXT:    mr r4, r3
 ; 32BIT-NEXT:    li r3, 0
 ; 32BIT-NEXT:    lbz r5, 0(r4)
 ; 32BIT-NEXT:    lbz r6, 1(r4)

 }
 
 define dso_local i64 @test_and(ptr nocapture noundef readonly %inp) local_unnamed_addr #0 {
 ; 64BIT-LABEL: test_and:
 ; 64BIT:       # %bb.0: # %entry
 ; 64BIT-NEXT:    lbz r4, 0(r3)
 ; 64BIT-NEXT:    lbz r3, 1(r3)
 ; 64BIT-NEXT:    and r3, r3, r4
-; 64BIT-NEXT:    clrldi r3, r3, 56
 ; 64BIT-NEXT:    blr
 ;
 ; 32BIT-LABEL: test_and:
 ; 32BIT:       # %bb.0: # %entry
 ; 32BIT-NEXT:    mr r4, r3
 ; 32BIT-NEXT:    li r3, 0
 ; 32BIT-NEXT:    lbz r5, 0(r4)
 ; 32BIT-NEXT:    lbz r4, 1(r4)

 define dso_local i64 @test_and2(ptr nocapture noundef readonly %inp) local_unnamed_addr #0 {
 ; 64BIT-LABEL: test_and2:
 ; 64BIT:       # %bb.0: # %entry
 ; 64BIT-NEXT:    lbz r4, 0(r3)
 ; 64BIT-NEXT:    lbz r5, 1(r3)
 ; 64BIT-NEXT:    lbz r3, 2(r3)
 ; 64BIT-NEXT:    and r4, r5, r4
 ; 64BIT-NEXT:    and r3, r4, r3
-; 64BIT-NEXT:    clrldi r3, r3, 56
 ; 64BIT-NEXT:    blr
 ;
 ; 32BIT-LABEL: test_and2:
 ; 32BIT:       # %bb.0: # %entry
 ; 32BIT-NEXT:    mr r4, r3
 ; 32BIT-NEXT:    li r3, 0
 ; 32BIT-NEXT:    lbz r5, 0(r4)
 ; 32BIT-NEXT:    lbz r6, 1(r4)

 ; 64BIT:       # %bb.0: # %entry
 ; 64BIT-NEXT:    lbz r4, 0(r3)
 ; 64BIT-NEXT:    lbz r5, 1(r3)
 ; 64BIT-NEXT:    lbz r6, 2(r3)
 ; 64BIT-NEXT:    lbz r3, 3(r3)
 ; 64BIT-NEXT:    and r4, r5, r4
 ; 64BIT-NEXT:    xor r4, r4, r6
 ; 64BIT-NEXT:    or r3, r4, r3
-; 64BIT-NEXT:    clrldi r3, r3, 56
 ; 64BIT-NEXT:    blr
 ;
 ; 32BIT-LABEL: test_mixed:
 ; 32BIT:       # %bb.0: # %entry
 ; 32BIT-NEXT:    mr r4, r3
 ; 32BIT-NEXT:    li r3, 0
 ; 32BIT-NEXT:    lbz r5, 0(r4)
 ; 32BIT-NEXT:    lbz r6, 1(r4)

 ; 64BIT:       # %bb.0: # %entry
 ; 64BIT-NEXT:    lbz r5, 0(r3)
 ; 64BIT-NEXT:    lhz r6, 2(r4)
 ; 64BIT-NEXT:    lbz r3, 2(r3)
 ; 64BIT-NEXT:    lhz r4, 6(r4)
 ; 64BIT-NEXT:    and r5, r6, r5
 ; 64BIT-NEXT:    xor r3, r5, r3
 ; 64BIT-NEXT:    or r3, r3, r4
-; 64BIT-NEXT:    clrldi r3, r3, 48
 ; 64BIT-NEXT:    blr
 ;
 ; 32BIT-LABEL: test_mixedtype:
 ; 32BIT:       # %bb.0: # %entry
 ; 32BIT-NEXT:    lbz r5, 0(r3)
 ; 32BIT-NEXT:    lhz r6, 2(r4)
 ; 32BIT-NEXT:    lbz r3, 2(r3)
 ; 32BIT-NEXT:    lhz r4, 6(r4)