[BranchFolding] Remove redundant conditional branch.

[skatkov]

Summary

BB1: Conditional jump outside
        Fallthrough or explicit branch to BB2
BB2: The same conditional branch leading to somewhere else outside
        Fallthrough or explicit branch to BB3

can be transformed to

BB1: Conditional jump outside
        Fallthrough or explicit branch to BB2
BB2: Fallthrough or explicit branch to BB3

[danilaml]

llvm/lib/CodeGen/BranchFolding.cpp

1686

Does it also need to check that MBB has no other predecessors?

[skatkov]

llvm/lib/CodeGen/BranchFolding.cpp

1686

Line: 1676, MBB->pred_size() == 1 => MBB has only one predecessor.

[goldstein.w.n]

llvm/lib/CodeGen/BranchFolding.cpp

1684

Does this take into account comparisons against memory? The pointer (operand) stays the same but value in memory is modified in BB1?

[skatkov]

llvm/lib/CodeGen/BranchFolding.cpp

1684

BB1 is a predecessor or MBB? For MBB we check that it is IsBranchOnlyBlock(MBB).

you mean that predecessor may contains store AFTER conditional branch and conditional branch itself may reference memory?

1684

and -> or

[goldstein.w.n]

llvm/lib/CodeGen/BranchFolding.cpp

1676

Instead of only 1 pred, you could check that all predecessors share the conditions?

1679

There is more than just this 1 case no?

IIUC you have

BB1 Cond0
        T -> Narian
        F -> BB2

BB2 Cond0
       T -> Narnia
       F -> BB3
---
BB1 Cond0
      T -> Narnia
      F -> BB2
BB2 -> BB3

But you could also have:

BB1 Cond0
        T -> BB2
        F -> Narian

BB2 Cond0
       T -> BB3
       F -> Narnai
---
BB1 Cond0
      T -> BB2
      F -> Narnia
BB2 -> BB3

BB1 Cond0
        T -> Narian
        F -> BB2

BB2 Cond0
       T -> BB3
       F -> Narnai
---
BB1 Cond0
      T -> Narnia
      F -> BB2
BB2 -> Narnia

BB1 Cond0
        T -> Narian
        F -> BB2

BB2 Cond0
       T -> Narnia
       F -> BB3
---
BB1 Cond0
      T -> Narnia
      F -> BB2
BB2 -> BB3

In which could it would really just be that one of PriorTBB or PriorFBB equals MBB then where MBB goes based on which.

[skatkov]

llvm/lib/CodeGen/BranchFolding.cpp

1676

It makes the patch more complicated... but let's see what we can do here...

1679

The cases 2-3 you added are actually covered by this patch as I see.
The first one, when BB1 conditionally jumps to BB2 is something new which we can cover I guess...

[goldstein.w.n]

llvm/lib/CodeGen/BranchFolding.cpp

1679

Err I duplicates the current case as case 3. There are two cars where BB2 is true. But you should get both as you handle case 1.

1684

BB1 is a predecessor or MBB? For MBB we check that it is IsBranchOnlyBlock(MBB).

you mean that predecessor may contains store AFTER conditional branch and conditional branch itself may reference memory?

Yes, exactly.
If this is still in SSA then it's fine, but x86 machine instructions (and other) have rm modifier where operands match but results can vary

[skatkov]

llvm/lib/CodeGen/BranchFolding.cpp

1684

Interesting, something new to me. At least on x86_64 conditional instruction is JCC which actually only reads the eflags and has no access to memory. If there is no other modification of eflags - we are ok.

But at least I need to check two things:

1. is it possible that there are some instructions after conditional branch which may affect the result of next equivalent conditional branch.
2. Are there any platforms where two conditional branches, one right after another one, may produce the right results.

Thanks for good question.

1684

may produce the right results. -> may produce different results.

[goldstein.w.n]

llvm/lib/CodeGen/BranchFolding.cpp

1684

Interesting, something new to me. At least on x86_64 conditional instruction is JCC which actually only reads the eflags and has no access to memory. If there is no other modification of eflags - we are ok.

But at least I need to check two things:

1. is it possible that there are some instructions after conditional branch which may affect the result of next equivalent conditional branch.
2. Are there any platforms where two conditional branches, one right after another one, may produce the right results.

Thanks for good question.

I think I confused myself (and possibly you a bit).

I assumed match operands was matching the comparison that lead to it i.e

cmpl %rdi, (%rsi); jcc not just the jcc. If its just the jcc then yeah, there is no concern about the rm stuff.

If its just jcc, then yeah just checking that there are no instructions that write to the jump flags should be enough.

[skatkov]

llvm/lib/CodeGen/BranchFolding.cpp

1684

your question still makes sense. If on some platform there exist instruction which does a comparison and jump (for example, cbz on AARCH) I need to ensure that there is no modification of memory/register between two such operations...

In this patch I'm base on analyzeBranch utility. And It might be a problem. I'll try to create some tests which reproduce this problem and probably I need to find how to fix it.
Moreover if it is true problem then probably analyzeBranch is not enough and I need to do something more and probably in different place.

[dantrushin]

Would be nice to have few dedicated tests. All existing test changes are noisy

llvm/lib/CodeGen/BranchFolding.cpp

1682

until -> unless ?

[skatkov]

At the moment, I do not see an easy way to implement this one in platform independent way. I put it on hold due to busy with other stuff.

llvm/lib/CodeGen/BranchFolding.cpp

 // Blocks with only debug info and branches should be considered the same
 // as blocks with only branches.
 static bool IsBranchOnlyBlock(MachineBasicBlock *MBB) {
   MachineBasicBlock::iterator I = MBB->getFirstNonDebugInstr();
   assert(I != MBB->end() && "empty block!");
   return I->isBranch();
 }
 
+static bool AreOperandsIdentical(SmallVectorImpl<MachineOperand> &V1,
+                                 SmallVectorImpl<MachineOperand> &V2) {
+  if (V1.size() != V2.size())
+    return false;
+  return std::equal(V1.begin(), V1.end(), V2.begin(),
+                    [](MachineOperand &Op1,
+                       MachineOperand &Op2) { return Op1.isIdenticalTo(Op2); });
+}
+
 /// IsBetterFallthrough - Return true if it would be clearly better to
 /// fall-through to MBB1 than to fall through into MBB2.  This has to return
 /// a strict ordering, returning true for both (MBB1,MBB2) and (MBB2,MBB1) will
 /// result in infinite loops.
 static bool IsBetterFallthrough(MachineBasicBlock *MBB1,
                                 MachineBasicBlock *MBB2) {
   assert(MBB1 && MBB2 && "Unknown MachineBasicBlock");
 
if (CurTBB && CurCond.empty() && !CurFBB &&
         }
       }
 
       // Add the branch back if the block is more than just an uncond branch.
       TII->insertBranch(*MBB, CurTBB, nullptr, CurCond, dl);
     }
   }
 
+  // BB1: Conditional jump outside
+  //      Fallthrough or explicit branch to BB2
+  // BB2: The same conditional branch leading to somewhere else outside
+  //      Fallthrough or explicit branch to BB3
+  // can be transformed to
+  // BB1: Conditional jump outside
+  //      Fallthrough or explicit branch to BB2
+  // BB2: Fallthrough or explicit branch to BB3
+  if (!CurUnAnalyzable && !PriorUnAnalyzable && MBB->pred_size() == 1) {
+    // If the our predecessor has a conditional branch to other block and
+    // fallthrough or jump to us
+    if (PriorTBB && PriorTBB != MBB && (!PriorFBB || PriorFBB == MBB)) {
+      // and our block is branch only and has the same conditional branch
+      // it will never be taken, so we can eliminate it
+      // until MBB has address taken or target of an exception handling.
+      if (CurTBB && IsBranchOnlyBlock(MBB) &&
+          AreOperandsIdentical(CurCond, PriorCond) && !MBB->hasAddressTaken() &&
+          !MBB->isEHPad()) {
+        assert(PrevBB.isSuccessor(MBB) && "Not a predecessor?");
+        TII->removeBranch(*MBB);
+        if (IsEmptyBlock(MBB))
+          MBB->erase(MBB->begin(), MBB->end());
+        // If we had unconditional jump, just restore it.
+        if (CurFBB)
+          TII->insertUnconditionalBranch(*MBB, CurFBB,
+                                         getBranchDebugLoc(*CurFBB));
+        MadeChange = true;
+        ++NumBranchOpts;
+        goto ReoptimizeBlock;
+      }
+    }
+  }
+
   // If the prior block doesn't fall through into this block, and if this
   // block doesn't fall through into some other block, see if we can find a
   // place to move this block where a fall-through will happen.
   if (!PrevBB.canFallThrough()) {
     // Now we know that there was no fall-through into this block, check to
     // see if it has a fall-through into its successor.
     bool CurFallsThru = MBB->canFallThrough();
 

llvm/test/CodeGen/AMDGPU/swdev373493.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -o - %s -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs | FileCheck %s
 
 @global = external protected addrspace(4) externally_initialized global [4096 x i64], align 16
 
 define hidden fastcc void @bar(i32 %arg, ptr %arg1, ptr %arg2, ptr %arg3, ptr %arg4, ptr %arg5, ptr %arg6) unnamed_addr align 2 {
 ; CHECK-LABEL: bar:
 ; CHECK:       ; %bb.0: ; %bb
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:    v_mov_b32_e32 v15, v12
-; CHECK-NEXT:    v_mov_b32_e32 v14, v11
-; CHECK-NEXT:    v_mov_b32_e32 v13, v10
-; CHECK-NEXT:    v_mov_b32_e32 v12, v9
-; CHECK-NEXT:    v_mov_b32_e32 v11, v8
-; CHECK-NEXT:    v_mov_b32_e32 v10, v7
-; CHECK-NEXT:    v_mov_b32_e32 v9, v6
-; CHECK-NEXT:    v_mov_b32_e32 v8, v5
-; CHECK-NEXT:    v_mov_b32_e32 v7, v4
-; CHECK-NEXT:    v_mov_b32_e32 v6, v3
 ; CHECK-NEXT:    s_cmp_lt_i32 s4, 3
-; CHECK-NEXT:    s_cbranch_scc0 .LBB0_3
-; CHECK-NEXT:  ; %bb.1: ; %LeafBlock
-; CHECK-NEXT:    s_cbranch_scc1 .LBB0_5
-; CHECK-NEXT:  ; %bb.2: ; %bb7
-; CHECK-NEXT:    flat_load_dwordx2 v[2:3], v[0:1]
-; CHECK-NEXT:    s_getpc_b64 s[16:17]
-; CHECK-NEXT:    s_add_u32 s16, s16, global@rel32@lo+1948
-; CHECK-NEXT:    s_addc_u32 s17, s17, global@rel32@hi+1956
-; CHECK-NEXT:    v_mov_b32_e32 v5, 0
-; CHECK-NEXT:    v_mov_b32_e32 v0, s16
-; CHECK-NEXT:    v_mov_b32_e32 v1, s17
-; CHECK-NEXT:    s_getpc_b64 s[18:19]
-; CHECK-NEXT:    s_add_u32 s18, s18, eggs@rel32@lo+4
-; CHECK-NEXT:    s_addc_u32 s19, s19, eggs@rel32@hi+12
-; CHECK-NEXT:    s_setpc_b64 s[18:19]
-; CHECK-NEXT:  .LBB0_3: ; %LeafBlock1
-; CHECK-NEXT:    s_cbranch_scc0 .LBB0_5
-; CHECK-NEXT:  ; %bb.4: ; %bb8
-; CHECK-NEXT:    v_mov_b32_e32 v0, v1
-; CHECK-NEXT:    v_mov_b32_e32 v1, v2
-; CHECK-NEXT:    v_mov_b32_e32 v2, v6
-; CHECK-NEXT:    v_mov_b32_e32 v3, v7
-; CHECK-NEXT:    v_mov_b32_e32 v4, v8
-; CHECK-NEXT:    v_mov_b32_e32 v5, v9
-; CHECK-NEXT:    v_mov_b32_e32 v6, v10
-; CHECK-NEXT:    v_mov_b32_e32 v7, v11
-; CHECK-NEXT:    v_mov_b32_e32 v8, v12
-; CHECK-NEXT:    v_mov_b32_e32 v9, v13
-; CHECK-NEXT:    v_mov_b32_e32 v10, v14
-; CHECK-NEXT:    v_mov_b32_e32 v11, v15
-; CHECK-NEXT:    s_getpc_b64 s[16:17]
-; CHECK-NEXT:    s_add_u32 s16, s16, quux@rel32@lo+4
-; CHECK-NEXT:    s_addc_u32 s17, s17, quux@rel32@hi+12
-; CHECK-NEXT:    s_setpc_b64 s[16:17]
-; CHECK-NEXT:  .LBB0_5: ; %bb9
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
 bb:
   switch i32 undef, label %bb9 [
     i32 3, label %bb8
     i32 1, label %bb7
   ]
 
 bb7:                                              ; preds = %bb

llvm/test/CodeGen/Hexagon/newvaluejump-kill.ll

 ; RUN: llc -march=hexagon -O3 -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 -hexagon-instsimplify=0 < %s | FileCheck %s
 ;
 ; Check that this testcase compiles successfully and that a new-value jump
 ; has been created.
 ; CHECK: if (cmp.gtu(r{{[0-9]+}}.new,r{{[0-9]+}})) jump
 
 target triple = "hexagon"
 
 @g0 = external hidden unnamed_addr global [182 x i16], align 8
 
-define void @fred(i16 signext %a0, i16 signext %a1) #0 {
+define void @fred(i16 signext %a0, i16 signext %a1, i1 %c) #0 {
 b1:
   %v1 = sext i16 %a0 to i32
   %v2 = getelementptr inbounds [182 x i16], ptr @g0, i32 0, i32 %v1
   %v3 = sext i16 %a1 to i32
   %v4 = call i32 @llvm.hexagon.A2.asrh(i32 undef)
   %v5 = trunc i32 %v4 to i16
   br i1 undef, label %b6, label %b14
 
b14:                                              ; preds = %b1
   br i1 undef, label %b16, label %b15
 
 b15:                                              ; preds = %b14
   unreachable
 
 b16:                                              ; preds = %b14
   %v17 = getelementptr [182 x i16], ptr @g0, i32 0, i32 %v3
   %v18 = icmp ugt ptr %v17, %v2
-  %v19 = or i1 %v18, undef
+  %v19 = or i1 %v18, %c
   br i1 %v19, label %b20, label %b21
 
 b20:                                              ; preds = %b16
   unreachable
 
 b21:                                              ; preds = %b16
   ret void
 }
 
 declare i32 @llvm.hexagon.A2.asrh(i32) #1
 
 attributes #0 = { nounwind "target-cpu"="hexagonv62" }
 attributes #1 = { nounwind readnone }

llvm/test/CodeGen/PowerPC/aantidep-inline-asm-use.ll

 ; RUN: llc -O2 -verify-machineinstrs < %s | FileCheck %s
 ; ModuleID = 'bugpoint-reduced-simplified.bc'
 target datalayout = "e-m:e-i64:64-n32:64"
 target triple = "powerpc64le-grtev4-linux-gnu"
 
 ; Function Attrs: nounwind
-define void @_ZN10SubProcess19ScrubbedForkAndExecEiPiS0_PNS_7ResultsE() #0 align 2 {
+define void @_ZN10SubProcess19ScrubbedForkAndExecEiPiS0_PNS_7ResultsE(i1 %c) #0 align 2 {
 ; CHECK: lis 3, 1234
 ; CHECK-NOT: li 3
 ; CHECK-NOT: ori 3
 ; CHECK-NOT: addi 3
 ; CHECK-NOT: addis 3
 ; CHECK-NOT: lis 3
 ; CHECK: sc
-  br i1 undef, label %1, label %2
+  br i1 %c, label %1, label %2
 
 ; <label>:1                                       ; preds = %0
   br label %60
 
 ; <label>:2                                       ; preds = %0
   br i1 undef, label %3, label %4
 
 ; <label>:3                                       ; preds = %2

llvm/test/CodeGen/PowerPC/bdzlr.ll

 %union.TKey.5.680 = type { %struct.anon.0.4.679 }
 %struct.anon.0.4.679 = type { %union.Value.16.691, i32, ptr }
 %union.TString.9.684 = type { %struct.anon.1.8.683 }
 %struct.anon.1.8.683 = type { ptr, i8, i8, i8, i32, i64 }
 %struct.CallInfo.11.686 = type { ptr, ptr, ptr, ptr, i32, i32 }
 %struct.lua_Debug.12.687 = type { i32, ptr, ptr, ptr, ptr, i32, i32, i32, i32, [60 x i8], i32 }
 %struct.lua_longjmp.13.688 = type opaque
 
-define void @lua_xmove(i32 signext %n) #0 {
+define void @lua_xmove(i32 signext %n, i1 %c) #0 {
 entry:
-  br i1 undef, label %for.end, label %if.end
+  br i1 %c, label %for.end, label %if.end
 
 if.end:                                           ; preds = %entry
   br i1 undef, label %for.body.lr.ph, label %for.end
 
 for.body.lr.ph:                                   ; preds = %if.end
   br label %for.body
 
 for.body:                                         ; preds = %for.body.for.body_crit_edge, %for.body.lr.ph

llvm/test/CodeGen/PowerPC/ifcvt-forked-bug-2016-08-08.ll

 ; ModuleID = 'bugpoint-reduced-instructions.bc'
 ; RUN: llc -O2 -o - %s -verify-machineinstrs | FileCheck %s
 source_filename = "bugpoint-output-9ad75f8.bc"
 target datalayout = "e-m:e-i64:64-n32:64"
 target triple = "powerpc64le-unknown-linux-gnu"
 
 ; Function Attrs: nounwind uwtable
-define hidden void @_ZN11__sanitizer25MaybeStartBackgroudThreadEv() local_unnamed_addr #0 {
+define hidden void @_ZN11__sanitizer25MaybeStartBackgroudThreadEv(i1 %c) local_unnamed_addr #0 {
 entry:
-  br i1 undef, label %land.lhs.true, label %if.end
+  br i1 %c, label %land.lhs.true, label %if.end
 
 ; CHECK: # %land.lhs.true
 ; Test updated due D63152 where any load/store prevents shrink-wrapping
 ; CHECK-NEXT: bc
 ; CHECK-NEXT: # %if.end4
 land.lhs.true:                                    ; preds = %entry
   br i1 undef, label %return, label %if.end4
 

llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll

 ; CHECK-NEXT:    .cfi_def_cfa_offset 48
 ; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    .cfi_offset r30, -16
 ; CHECK-NEXT:    .cfi_offset cr2, 8
 ; CHECK-NEXT:    .cfi_offset cr3, 8
 ; CHECK-NEXT:    .cfi_offset cr4, 8
 ; CHECK-NEXT:    std r30, 32(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    bl call_2@notoc
-; CHECK-NEXT:    bc 12, 4*cr5+lt, .LBB0_13
-; CHECK-NEXT:  # %bb.1: # %bb
-; CHECK-NEXT:    bc 4, 4*cr5+lt, .LBB0_14
-; CHECK-NEXT:  # %bb.2: # %bb4
-; CHECK-NEXT:    cmpdi cr3, r3, 0
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    # implicit-def: $r30
-; CHECK-NEXT:    crnot 4*cr3+lt, 4*cr3+eq
-; CHECK-NEXT:    cmpwi cr4, r3, 0
-; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:    bc 12, 4*cr5+lt, .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %bb2
+; CHECK-NEXT:  .LBB0_2: # %bb3
 ; CHECK-NEXT:  .LBB0_3: # %bb12
-; CHECK-NEXT:    #
 ; CHECK-NEXT:    bl call_3@notoc
 ; CHECK-NEXT:    cmpwi r3, 1
 ; CHECK-NEXT:    crnand 4*cr5+lt, eq, 4*cr4+gt
 ; CHECK-NEXT:    bc 4, 4*cr5+lt, .LBB0_8
 ; CHECK-NEXT:  # %bb.4: # %bb23
-; CHECK-NEXT:    #
 ; CHECK-NEXT:    plwz r3, call_1@PCREL(0), 1
 ; CHECK-NEXT:    cmplwi r3, 0
-; CHECK-NEXT:    bne- cr0, .LBB0_10
+; CHECK-NEXT:    bne- cr0, .LBB0_9
 ; CHECK-NEXT:  # %bb.5: # %bb30
-; CHECK-NEXT:    #
-; CHECK-NEXT:    bc 12, 4*cr3+eq, .LBB0_9
+; CHECK-NEXT:    bc 12, 4*cr3+eq, .LBB0_11
 ; CHECK-NEXT:  # %bb.6: # %bb32
-; CHECK-NEXT:    #
 ; CHECK-NEXT:    rlwinm r30, r30, 0, 24, 22
 ; CHECK-NEXT:    andi. r3, r30, 2
 ; CHECK-NEXT:    mcrf cr2, cr0
 ; CHECK-NEXT:    bl call_4@notoc
 ; CHECK-NEXT:    beq+ cr2, .LBB0_3
 ; CHECK-NEXT:  # %bb.7: # %bb37
 ; CHECK-NEXT:  .LBB0_8: # %bb22
-; CHECK-NEXT:  .LBB0_9: # %bb35
-; CHECK-NEXT:  .LBB0_10: # %bb27
+; CHECK-NEXT:  .LBB0_9: # %bb27
 ; CHECK-NEXT:    bc 4, 4*cr3+lt, .LBB0_12
-; CHECK-NEXT:  # %bb.11: # %bb28
+; CHECK-NEXT:  # %bb.10: # %bb28
+; CHECK-NEXT:  .LBB0_11: # %bb35
 ; CHECK-NEXT:  .LBB0_12: # %bb29
-; CHECK-NEXT:  .LBB0_13: # %bb3
-; CHECK-NEXT:  .LBB0_14: # %bb2
 ;
 ; CHECK-BE-LABEL: P10_Spill_CR_LT:
 ; CHECK-BE:       # %bb.0: # %bb
 ; CHECK-BE-NEXT:    mfcr r12
 ; CHECK-BE-NEXT:    mflr r0
 ; CHECK-BE-NEXT:    std r0, 16(r1)
 ; CHECK-BE-NEXT:    stw r12, 8(r1)
 ; CHECK-BE-NEXT:    stdu r1, -144(r1)
 ; CHECK-BE-NEXT:    .cfi_def_cfa_offset 144
 ; CHECK-BE-NEXT:    .cfi_offset lr, 16
 ; CHECK-BE-NEXT:    .cfi_offset r29, -24
 ; CHECK-BE-NEXT:    .cfi_offset r30, -16
 ; CHECK-BE-NEXT:    .cfi_offset cr2, 8
 ; CHECK-BE-NEXT:    .cfi_offset cr2, 8
 ; CHECK-BE-NEXT:    .cfi_offset cr2, 8
 ; CHECK-BE-NEXT:    std r29, 120(r1) # 8-byte Folded Spill
 ; CHECK-BE-NEXT:    std r30, 128(r1) # 8-byte Folded Spill
 ; CHECK-BE-NEXT:    bl call_2
 ; CHECK-BE-NEXT:    nop
-; CHECK-BE-NEXT:    bc 12, 4*cr5+lt, .LBB0_13
-; CHECK-BE-NEXT:  # %bb.1: # %bb
-; CHECK-BE-NEXT:    bc 4, 4*cr5+lt, .LBB0_14
-; CHECK-BE-NEXT:  # %bb.2: # %bb4
-; CHECK-BE-NEXT:    cmpdi cr3, r3, 0
-; CHECK-BE-NEXT:    lwz r3, 0(r3)
-; CHECK-BE-NEXT:    addis r30, r2, call_1@toc@ha
-; CHECK-BE-NEXT:    # implicit-def: $r29
-; CHECK-BE-NEXT:    crnot 4*cr3+lt, 4*cr3+eq
-; CHECK-BE-NEXT:    cmpwi cr4, r3, 0
-; CHECK-BE-NEXT:    .p2align 4
+; CHECK-BE-NEXT:    bc 12, 4*cr5+lt, .LBB0_2
+; CHECK-BE-NEXT:  # %bb.1: # %bb2
+; CHECK-BE-NEXT:  .LBB0_2: # %bb3
 ; CHECK-BE-NEXT:  .LBB0_3: # %bb12
-; CHECK-BE-NEXT:    #
 ; CHECK-BE-NEXT:    bl call_3
 ; CHECK-BE-NEXT:    nop
 ; CHECK-BE-NEXT:    cmpwi r3, 1
 ; CHECK-BE-NEXT:    crnand 4*cr5+lt, eq, 4*cr4+gt
 ; CHECK-BE-NEXT:    bc 4, 4*cr5+lt, .LBB0_8
 ; CHECK-BE-NEXT:  # %bb.4: # %bb23
-; CHECK-BE-NEXT:    #
 ; CHECK-BE-NEXT:    lwz r3, call_1@toc@l(r30)
 ; CHECK-BE-NEXT:    cmplwi r3, 0
-; CHECK-BE-NEXT:    bne- cr0, .LBB0_10
+; CHECK-BE-NEXT:    bne- cr0, .LBB0_9
 ; CHECK-BE-NEXT:  # %bb.5: # %bb30
-; CHECK-BE-NEXT:    #
-; CHECK-BE-NEXT:    bc 12, 4*cr3+eq, .LBB0_9
+; CHECK-BE-NEXT:    bc 12, 4*cr3+eq, .LBB0_11
 ; CHECK-BE-NEXT:  # %bb.6: # %bb32
-; CHECK-BE-NEXT:    #
 ; CHECK-BE-NEXT:    rlwinm r29, r29, 0, 24, 22
 ; CHECK-BE-NEXT:    andi. r3, r29, 2
 ; CHECK-BE-NEXT:    mcrf cr2, cr0
 ; CHECK-BE-NEXT:    bl call_4
 ; CHECK-BE-NEXT:    nop
 ; CHECK-BE-NEXT:    beq+ cr2, .LBB0_3
 ; CHECK-BE-NEXT:  # %bb.7: # %bb37
 ; CHECK-BE-NEXT:  .LBB0_8: # %bb22
-; CHECK-BE-NEXT:  .LBB0_9: # %bb35
-; CHECK-BE-NEXT:  .LBB0_10: # %bb27
+; CHECK-BE-NEXT:  .LBB0_9: # %bb27
 ; CHECK-BE-NEXT:    bc 4, 4*cr3+lt, .LBB0_12
-; CHECK-BE-NEXT:  # %bb.11: # %bb28
+; CHECK-BE-NEXT:  # %bb.10: # %bb28
+; CHECK-BE-NEXT:  .LBB0_11: # %bb35
 ; CHECK-BE-NEXT:  .LBB0_12: # %bb29
-; CHECK-BE-NEXT:  .LBB0_13: # %bb3
-; CHECK-BE-NEXT:  .LBB0_14: # %bb2
 bb:
   %tmp = tail call ptr @call_2()
   %tmp1 = icmp ne ptr %tmp, null
   switch i32 undef, label %bb4 [
     i32 3, label %bb2
     i32 2, label %bb3
   ]
 

llvm/test/CodeGen/PowerPC/p10-spill-crun.ll

 ; CHECK-NEXT:  # %bb.1: # %bb9
 ; CHECK-NEXT:    mr r3, r29
 ; CHECK-NEXT:    mr r4, r30
 ; CHECK-NEXT:    bl call_3@notoc
 ; CHECK-NEXT:  .LBB0_2: # %bb12
 ; CHECK-NEXT:    srwi r3, r28, 7
 ; CHECK-NEXT:    andi. r3, r3, 1
 ; CHECK-NEXT:    crmove 4*cr2+un, gt
-; CHECK-NEXT:    bc 12, 4*cr2+eq, .LBB0_7
+; CHECK-NEXT:    bc 12, 4*cr2+eq, .LBB0_5
 ; CHECK-NEXT:  # %bb.3: # %bb37
 ; CHECK-NEXT:    lwz r28, 0(r3)
-; CHECK-NEXT:    bc 12, 4*cr5+lt, .LBB0_5
-; CHECK-NEXT:  # %bb.4: # %bb37
-; CHECK-NEXT:    bc 4, 4*cr5+lt, .LBB0_14
-; CHECK-NEXT:  .LBB0_5: # %bb42
-; CHECK-NEXT:    paddi r3, 0, global_1@PCREL, 1
-; CHECK-NEXT:    li r4, 0
-; CHECK-NEXT:    cmpwi r28, 0
-; CHECK-NEXT:    isel r3, r3, r4, 4*cr2+gt
-; CHECK-NEXT:    crnot 4*cr2+lt, eq
-; CHECK-NEXT:    bl call_5@notoc
-; CHECK-NEXT:    pld r3, global_2@got@pcrel(0), 1
-; CHECK-NEXT:    addi r3, r3, 8682
-; CHECK-NEXT:    lxsihzx v2, 0, r3
-; CHECK-NEXT:    vextsh2d v2, v2
-; CHECK-NEXT:    xscvsxdsp f0, v2
-; CHECK-NEXT:    bc 12, 4*cr2+lt, .LBB0_12
-; CHECK-NEXT:  # %bb.6: # %bb42
-; CHECK-NEXT:    xxspltidp vs1, 1069547520
-; CHECK-NEXT:    b .LBB0_13
-; CHECK-NEXT:  .LBB0_7: # %bb19
+; CHECK-NEXT:    bc 12, 4*cr5+lt, .LBB0_10
+; CHECK-NEXT:  # %bb.4: # %bb41
+; CHECK-NEXT:    # implicit-def: $r3
+; CHECK-NEXT:    b .LBB0_14
+; CHECK-NEXT:  .LBB0_5: # %bb19
 ; CHECK-NEXT:    setnbc r3, 4*cr2+un
 ; CHECK-NEXT:    paddi r4, 0, global_4@PCREL, 1
 ; CHECK-NEXT:    stw r3, 176(r1)
 ; CHECK-NEXT:    pld r3, global_3@got@pcrel(0), 1
 ; CHECK-NEXT:  .Lpcrel0:
 ; CHECK-NEXT:    .reloc .Lpcrel0-8,R_PPC64_PCREL_OPT,.-(.Lpcrel0-8)
 ; CHECK-NEXT:    ld r12, 0(r3)
 ; CHECK-NEXT:    mtctr r12
 ; CHECK-NEXT:    bctrl
 ; CHECK-NEXT:    cmpdi cr4, r3, 0
 ; CHECK-NEXT:    andi. r3, r28, 4
 ; CHECK-NEXT:    cmpwi cr2, r27, 0
 ; CHECK-NEXT:    mcrf cr3, cr0
 ; CHECK-NEXT:    .p2align 5
-; CHECK-NEXT:  .LBB0_8: # %bb27
+; CHECK-NEXT:  .LBB0_6: # %bb27
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    mr r3, r30
 ; CHECK-NEXT:    li r4, 0
 ; CHECK-NEXT:    bl call_6@notoc
-; CHECK-NEXT:    bc 4, 4*cr4+eq, .LBB0_18
-; CHECK-NEXT:  # %bb.9: # %bb31
+; CHECK-NEXT:    bc 4, 4*cr4+eq, .LBB0_17
+; CHECK-NEXT:  # %bb.7: # %bb31
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    bc 4, 4*cr3+eq, .LBB0_18
-; CHECK-NEXT:  # %bb.10: # %bb33
+; CHECK-NEXT:    bc 4, 4*cr3+eq, .LBB0_17
+; CHECK-NEXT:  # %bb.8: # %bb33
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    bc 4, 4*cr2+eq, .LBB0_8
-; CHECK-NEXT:  # %bb.11: # %bb36
+; CHECK-NEXT:    bc 4, 4*cr2+eq, .LBB0_6
+; CHECK-NEXT:  # %bb.9: # %bb36
 ; CHECK-NEXT:    stb r3, 181(r1)
 ; CHECK-NEXT:    # implicit-def: $cr2un
 ; CHECK-NEXT:    mfocrf r3, 32
 ; CHECK-NEXT:    lwz r4, 176(r1)
 ; CHECK-NEXT:    rlwimi r3, r4, 21, 11, 11
 ; CHECK-NEXT:    mtocrf 32, r3
-; CHECK-NEXT:    b .LBB0_16
+; CHECK-NEXT:    b .LBB0_15
+; CHECK-NEXT:  .LBB0_10: # %bb42
+; CHECK-NEXT:    paddi r3, 0, global_1@PCREL, 1
+; CHECK-NEXT:    li r4, 0
+; CHECK-NEXT:    cmpwi r28, 0
+; CHECK-NEXT:    isel r3, r3, r4, 4*cr2+gt
+; CHECK-NEXT:    crnot 4*cr2+lt, eq
+; CHECK-NEXT:    bl call_5@notoc
+; CHECK-NEXT:    pld r3, global_2@got@pcrel(0), 1
+; CHECK-NEXT:    addi r3, r3, 8682
+; CHECK-NEXT:    lxsihzx v2, 0, r3
+; CHECK-NEXT:    vextsh2d v2, v2
+; CHECK-NEXT:    xscvsxdsp f0, v2
+; CHECK-NEXT:    bc 12, 4*cr2+lt, .LBB0_12
+; CHECK-NEXT:  # %bb.11: # %bb42
+; CHECK-NEXT:    xxspltidp vs1, 1069547520
+; CHECK-NEXT:    b .LBB0_13
 ; CHECK-NEXT:  .LBB0_12:
 ; CHECK-NEXT:    xxspltidp vs1, 1071644672
 ; CHECK-NEXT:  .LBB0_13: # %bb42
 ; CHECK-NEXT:    xsmulsp f0, f1, f0
 ; CHECK-NEXT:    xscvdpsxws f0, f0
 ; CHECK-NEXT:    mffprwz r3, f0
-; CHECK-NEXT:    b .LBB0_15
-; CHECK-NEXT:  .LBB0_14: # %bb41
-; CHECK-NEXT:    # implicit-def: $r3
-; CHECK-NEXT:  .LBB0_15: # %bb50
+; CHECK-NEXT:  .LBB0_14: # %bb50
 ; CHECK-NEXT:    li r4, 0
 ; CHECK-NEXT:    xxspltidp vs3, -1082130432
 ; CHECK-NEXT:    xxspltidp vs4, -1082130432
 ; CHECK-NEXT:    extsh r9, r3
 ; CHECK-NEXT:    extsw r6, r28
 ; CHECK-NEXT:    li r5, 0
 ; CHECK-NEXT:    li r7, 0
 ; CHECK-NEXT:    std r30, 104(r1)
 ; CHECK-NEXT:    std r29, 96(r1)
 ; CHECK-NEXT:    li r8, 0
 ; CHECK-NEXT:    li r10, 0
 ; CHECK-NEXT:    xxlxor f1, f1, f1
 ; CHECK-NEXT:    std r4, 152(r1)
 ; CHECK-NEXT:    li r4, -1
 ; CHECK-NEXT:    std r4, 112(r1)
 ; CHECK-NEXT:    li r4, 1024
 ; CHECK-NEXT:    bl call_4@notoc
-; CHECK-NEXT:  .LBB0_16: # %bb54
-; CHECK-NEXT:    bc 12, 4*cr2+un, .LBB0_19
-; CHECK-NEXT:  # %bb.17: # %bb56
+; CHECK-NEXT:  .LBB0_15: # %bb54
+; CHECK-NEXT:    bc 12, 4*cr2+un, .LBB0_18
+; CHECK-NEXT:  # %bb.16: # %bb56
 ; CHECK-NEXT:    ld r30, 208(r1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld r29, 200(r1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld r28, 192(r1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld r27, 184(r1) # 8-byte Folded Reload
 ; CHECK-NEXT:    addi r1, r1, 224
 ; CHECK-NEXT:    ld r0, 16(r1)
 ; CHECK-NEXT:    lwz r12, 8(r1)
 ; CHECK-NEXT:    mtlr r0
 ; CHECK-NEXT:    mtocrf 32, r12
 ; CHECK-NEXT:    mtocrf 16, r12
 ; CHECK-NEXT:    mtocrf 8, r12
 ; CHECK-NEXT:    blr
-; CHECK-NEXT:  .LBB0_18: # %bb30
+; CHECK-NEXT:  .LBB0_17: # %bb30
 ; CHECK-NEXT:    stb r3, 181(r1)
-; CHECK-NEXT:  .LBB0_19: # %bb55
+; CHECK-NEXT:  .LBB0_18: # %bb55
 ;
 ; CHECK-BE-LABEL: P10_Spill_CR_UN:
 ; CHECK-BE:       # %bb.0: # %bb
 ; CHECK-BE-NEXT:    mfcr r12
 ; CHECK-BE-NEXT:    mflr r0
 ; CHECK-BE-NEXT:    std r0, 16(r1)
 ; CHECK-BE-NEXT:    stw r12, 8(r1)
 ; CHECK-BE-NEXT:    stdu r1, -240(r1)

 ; CHECK-BE-NEXT:    mr r3, r29
 ; CHECK-BE-NEXT:    mr r4, r30
 ; CHECK-BE-NEXT:    bl call_3
 ; CHECK-BE-NEXT:    nop
 ; CHECK-BE-NEXT:  .LBB0_2: # %bb12
 ; CHECK-BE-NEXT:    srwi r3, r28, 7
 ; CHECK-BE-NEXT:    andi. r3, r3, 1
 ; CHECK-BE-NEXT:    crmove 4*cr2+un, gt
-; CHECK-BE-NEXT:    bc 12, 4*cr2+eq, .LBB0_7
+; CHECK-BE-NEXT:    bc 12, 4*cr2+eq, .LBB0_5
 ; CHECK-BE-NEXT:  # %bb.3: # %bb37
 ; CHECK-BE-NEXT:    lwz r28, 0(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, global_1@toc@ha
-; CHECK-BE-NEXT:    bc 12, 4*cr5+lt, .LBB0_5
-; CHECK-BE-NEXT:  # %bb.4: # %bb37
-; CHECK-BE-NEXT:    bc 4, 4*cr5+lt, .LBB0_14
-; CHECK-BE-NEXT:  .LBB0_5: # %bb42
-; CHECK-BE-NEXT:    addi r3, r3, global_1@toc@l
-; CHECK-BE-NEXT:    li r4, 0
-; CHECK-BE-NEXT:    cmpwi r28, 0
-; CHECK-BE-NEXT:    isel r3, r3, r4, 4*cr2+gt
-; CHECK-BE-NEXT:    crnot 4*cr2+lt, eq
-; CHECK-BE-NEXT:    bl call_5
-; CHECK-BE-NEXT:    nop
-; CHECK-BE-NEXT:    addis r3, r2, .LC0@toc@ha
-; CHECK-BE-NEXT:    ld r3, .LC0@toc@l(r3)
-; CHECK-BE-NEXT:    addi r3, r3, 8682
-; CHECK-BE-NEXT:    lxsihzx v2, 0, r3
-; CHECK-BE-NEXT:    vextsh2d v2, v2
-; CHECK-BE-NEXT:    xscvsxdsp f0, v2
-; CHECK-BE-NEXT:    bc 12, 4*cr2+lt, .LBB0_12
-; CHECK-BE-NEXT:  # %bb.6: # %bb42
-; CHECK-BE-NEXT:    xxspltidp vs1, 1069547520
-; CHECK-BE-NEXT:    b .LBB0_13
-; CHECK-BE-NEXT:  .LBB0_7: # %bb19
+; CHECK-BE-NEXT:    bc 12, 4*cr5+lt, .LBB0_10
+; CHECK-BE-NEXT:  # %bb.4: # %bb41
+; CHECK-BE-NEXT:    # implicit-def: $r3
+; CHECK-BE-NEXT:    b .LBB0_14
+; CHECK-BE-NEXT:  .LBB0_5: # %bb19
 ; CHECK-BE-NEXT:    setnbc r3, 4*cr2+un
 ; CHECK-BE-NEXT:    addis r4, r2, global_4@toc@ha
 ; CHECK-BE-NEXT:    stw r3, 192(r1)
-; CHECK-BE-NEXT:    addis r3, r2, .LC1@toc@ha
+; CHECK-BE-NEXT:    addis r3, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    std r2, 40(r1)
 ; CHECK-BE-NEXT:    addi r4, r4, global_4@toc@l
-; CHECK-BE-NEXT:    ld r3, .LC1@toc@l(r3)
+; CHECK-BE-NEXT:    ld r3, .LC0@toc@l(r3)
 ; CHECK-BE-NEXT:    ld r3, 0(r3)
 ; CHECK-BE-NEXT:    ld r2, 8(r3)
 ; CHECK-BE-NEXT:    ld r11, 16(r3)
 ; CHECK-BE-NEXT:    ld r3, 0(r3)
 ; CHECK-BE-NEXT:    mtctr r3
 ; CHECK-BE-NEXT:    bctrl
 ; CHECK-BE-NEXT:    ld 2, 40(r1)
 ; CHECK-BE-NEXT:    cmpdi cr4, r3, 0
 ; CHECK-BE-NEXT:    andi. r3, r28, 4
 ; CHECK-BE-NEXT:    cmpwi cr2, r27, 0
 ; CHECK-BE-NEXT:    mcrf cr3, cr0
 ; CHECK-BE-NEXT:    .p2align 5
-; CHECK-BE-NEXT:  .LBB0_8: # %bb27
+; CHECK-BE-NEXT:  .LBB0_6: # %bb27
 ; CHECK-BE-NEXT:    #
 ; CHECK-BE-NEXT:    mr r3, r30
 ; CHECK-BE-NEXT:    li r4, 0
 ; CHECK-BE-NEXT:    bl call_6
 ; CHECK-BE-NEXT:    nop
-; CHECK-BE-NEXT:    bc 4, 4*cr4+eq, .LBB0_18
-; CHECK-BE-NEXT:  # %bb.9: # %bb31
+; CHECK-BE-NEXT:    bc 4, 4*cr4+eq, .LBB0_17
+; CHECK-BE-NEXT:  # %bb.7: # %bb31
 ; CHECK-BE-NEXT:    #
-; CHECK-BE-NEXT:    bc 4, 4*cr3+eq, .LBB0_18
-; CHECK-BE-NEXT:  # %bb.10: # %bb33
+; CHECK-BE-NEXT:    bc 4, 4*cr3+eq, .LBB0_17
+; CHECK-BE-NEXT:  # %bb.8: # %bb33
 ; CHECK-BE-NEXT:    #
-; CHECK-BE-NEXT:    bc 4, 4*cr2+eq, .LBB0_8
-; CHECK-BE-NEXT:  # %bb.11: # %bb36
+; CHECK-BE-NEXT:    bc 4, 4*cr2+eq, .LBB0_6
+; CHECK-BE-NEXT:  # %bb.9: # %bb36
 ; CHECK-BE-NEXT:    stb r3, 197(r1)
 ; CHECK-BE-NEXT:    # implicit-def: $cr2un
 ; CHECK-BE-NEXT:    mfocrf r3, 32
 ; CHECK-BE-NEXT:    lwz r4, 192(r1)
 ; CHECK-BE-NEXT:    rlwimi r3, r4, 21, 11, 11
 ; CHECK-BE-NEXT:    mtocrf 32, r3
-; CHECK-BE-NEXT:    b .LBB0_16
+; CHECK-BE-NEXT:    b .LBB0_15
+; CHECK-BE-NEXT:  .LBB0_10: # %bb42
+; CHECK-BE-NEXT:    addi r3, r3, global_1@toc@l
+; CHECK-BE-NEXT:    li r4, 0
+; CHECK-BE-NEXT:    cmpwi r28, 0
+; CHECK-BE-NEXT:    isel r3, r3, r4, 4*cr2+gt
+; CHECK-BE-NEXT:    crnot 4*cr2+lt, eq
+; CHECK-BE-NEXT:    bl call_5
+; CHECK-BE-NEXT:    nop
+; CHECK-BE-NEXT:    addis r3, r2, .LC1@toc@ha
+; CHECK-BE-NEXT:    ld r3, .LC1@toc@l(r3)
+; CHECK-BE-NEXT:    addi r3, r3, 8682
+; CHECK-BE-NEXT:    lxsihzx v2, 0, r3
+; CHECK-BE-NEXT:    vextsh2d v2, v2
+; CHECK-BE-NEXT:    xscvsxdsp f0, v2
+; CHECK-BE-NEXT:    bc 12, 4*cr2+lt, .LBB0_12
+; CHECK-BE-NEXT:  # %bb.11: # %bb42
+; CHECK-BE-NEXT:    xxspltidp vs1, 1069547520
+; CHECK-BE-NEXT:    b .LBB0_13
 ; CHECK-BE-NEXT:  .LBB0_12:
 ; CHECK-BE-NEXT:    xxspltidp vs1, 1071644672
 ; CHECK-BE-NEXT:  .LBB0_13: # %bb42
 ; CHECK-BE-NEXT:    xsmulsp f0, f1, f0
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    b .LBB0_15
-; CHECK-BE-NEXT:  .LBB0_14: # %bb41
-; CHECK-BE-NEXT:    # implicit-def: $r3
-; CHECK-BE-NEXT:  .LBB0_15: # %bb50
+; CHECK-BE-NEXT:  .LBB0_14: # %bb50
 ; CHECK-BE-NEXT:    li r4, 0
 ; CHECK-BE-NEXT:    xxspltidp vs3, -1082130432
 ; CHECK-BE-NEXT:    xxspltidp vs4, -1082130432
 ; CHECK-BE-NEXT:    extsh r9, r3
 ; CHECK-BE-NEXT:    extsw r6, r28
 ; CHECK-BE-NEXT:    li r5, 0
 ; CHECK-BE-NEXT:    li r7, 0
 ; CHECK-BE-NEXT:    std r30, 120(r1)
 ; CHECK-BE-NEXT:    std r29, 112(r1)
 ; CHECK-BE-NEXT:    li r8, 0
 ; CHECK-BE-NEXT:    li r10, 0
 ; CHECK-BE-NEXT:    xxlxor f1, f1, f1
 ; CHECK-BE-NEXT:    std r4, 168(r1)
 ; CHECK-BE-NEXT:    li r4, -1
 ; CHECK-BE-NEXT:    std r4, 128(r1)
 ; CHECK-BE-NEXT:    li r4, 1024
 ; CHECK-BE-NEXT:    bl call_4
 ; CHECK-BE-NEXT:    nop
-; CHECK-BE-NEXT:  .LBB0_16: # %bb54
-; CHECK-BE-NEXT:    bc 12, 4*cr2+un, .LBB0_19
-; CHECK-BE-NEXT:  # %bb.17: # %bb56
+; CHECK-BE-NEXT:  .LBB0_15: # %bb54
+; CHECK-BE-NEXT:    bc 12, 4*cr2+un, .LBB0_18
+; CHECK-BE-NEXT:  # %bb.16: # %bb56
 ; CHECK-BE-NEXT:    ld r30, 224(r1) # 8-byte Folded Reload
 ; CHECK-BE-NEXT:    ld r29, 216(r1) # 8-byte Folded Reload
 ; CHECK-BE-NEXT:    ld r28, 208(r1) # 8-byte Folded Reload
 ; CHECK-BE-NEXT:    ld r27, 200(r1) # 8-byte Folded Reload
 ; CHECK-BE-NEXT:    addi r1, r1, 240
 ; CHECK-BE-NEXT:    ld r0, 16(r1)
 ; CHECK-BE-NEXT:    lwz r12, 8(r1)
 ; CHECK-BE-NEXT:    mtlr r0
 ; CHECK-BE-NEXT:    mtocrf 32, r12
 ; CHECK-BE-NEXT:    mtocrf 16, r12
 ; CHECK-BE-NEXT:    mtocrf 8, r12
 ; CHECK-BE-NEXT:    blr
-; CHECK-BE-NEXT:  .LBB0_18: # %bb30
+; CHECK-BE-NEXT:  .LBB0_17: # %bb30
 ; CHECK-BE-NEXT:    stb r3, 197(r1)
-; CHECK-BE-NEXT:  .LBB0_19: # %bb55
+; CHECK-BE-NEXT:  .LBB0_18: # %bb55
 bb:
   %tmp = alloca [3 x i8], align 1
   %tmp3 = tail call zeroext i8 @call_1(ptr %arg1)
   %tmp4 = icmp ne i8 %tmp3, 0
   %tmp5 = tail call signext i32 @call_2(ptr %arg, ptr %arg1)
   %tmp6 = and i32 %arg2, 16
   %tmp7 = icmp ne i32 %tmp6, 0
   br label %bb8

llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll

 
 if.end:
   ret void
 }
 
 ; Another infinite loop test this time with two nested infinite loop.
 ; CHECK-LABEL: {{.*}}infiniteloop3
 ; CHECK: bclr
-define void @infiniteloop3() {
+define void @infiniteloop3(i1 %c1, i1 %c2) {
 entry:
-  br i1 undef, label %loop2a, label %body
+  br i1 %c1, label %loop2a, label %body
 
 body:                                             ; preds = %entry
-  br i1 undef, label %loop2a, label %end
+  br i1 %c2, label %loop2a, label %end
 
 loop1:                                            ; preds = %loop2a, %loop2b
   %var.phi = phi ptr [ %next.phi, %loop2b ], [ %var, %loop2a ]
   %next.phi = phi ptr [ %next.load, %loop2b ], [ %next.var, %loop2a ]
   %0 = icmp eq ptr %var, null
   %next.load = load ptr, ptr undef
   br i1 %0, label %loop2a, label %loop2b
 

llvm/test/CodeGen/PowerPC/pr45448.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN: FileCheck %s
 define hidden void @julia_tryparse_internal_45896() #0 {
 ; CHECK-LABEL: julia_tryparse_internal_45896:
 ; CHECK:       # %bb.0: # %top
 ; CHECK-NEXT:    ld r3, 0(r3)
 ; CHECK-NEXT:    cmpldi r3, 0
 ; CHECK-NEXT:    beq cr0, .LBB0_3
 ; CHECK-NEXT:  # %bb.1: # %top
 ; CHECK-NEXT:    cmpldi r3, 10
 ; CHECK-NEXT:    beq cr0, .LBB0_4
 ; CHECK-NEXT:  # %bb.2: # %top
 ; CHECK-NEXT:  .LBB0_3: # %fail194
 ; CHECK-NEXT:  .LBB0_4: # %L294
-; CHECK-NEXT:    bc 12, 4*cr5+lt, .LBB0_6
-; CHECK-NEXT:  # %bb.5: # %L294
-; CHECK-NEXT:    bc 4, 4*cr5+lt, .LBB0_7
-; CHECK-NEXT:  .LBB0_6: # %L1057.preheader
-; CHECK-NEXT:  .LBB0_7: # %L670
+; CHECK-NEXT:    bc 12, 4*cr5+lt, .LBB0_8
+; CHECK-NEXT:  # %bb.5: # %L670
 ; CHECK-NEXT:    li r5, -3
 ; CHECK-NEXT:    cmpdi r3, 0
 ; CHECK-NEXT:    sradi r4, r3, 63
 ; CHECK-NEXT:    rldic r5, r5, 4, 32
 ; CHECK-NEXT:    crnot 4*cr5+lt, eq
 ; CHECK-NEXT:    mulhdu r3, r3, r5
 ; CHECK-NEXT:    maddld r6, r4, r5, r3
 ; CHECK-NEXT:    cmpld cr1, r6, r3
 ; CHECK-NEXT:    mulhdu. r3, r4, r5
-; CHECK-NEXT:    bc 4, 4*cr5+lt, .LBB0_10
-; CHECK-NEXT:  # %bb.8: # %L670
+; CHECK-NEXT:    bc 4, 4*cr5+lt, .LBB0_9
+; CHECK-NEXT:  # %bb.6: # %L670
 ; CHECK-NEXT:    crorc 4*cr5+lt, 4*cr1+lt, eq
-; CHECK-NEXT:    bc 4, 4*cr5+lt, .LBB0_10
-; CHECK-NEXT:  # %bb.9: # %L917
-; CHECK-NEXT:  .LBB0_10: # %L994
+; CHECK-NEXT:    bc 4, 4*cr5+lt, .LBB0_9
+; CHECK-NEXT:  # %bb.7: # %L917
+; CHECK-NEXT:  .LBB0_8: # %L1057.preheader
+; CHECK-NEXT:  .LBB0_9: # %L994
 top:
   %0 = load i64, ptr undef, align 8
   %1 = icmp ne i64 %0, 0
   %2 = sext i64 %0 to i128
   switch i64 %0, label %pass195 [
     i64 10, label %L294
     i64 16, label %L294.fold.split
     i64 0, label %fail194

llvm/test/CodeGen/PowerPC/pr49509.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s
 
 target datalayout = "E-m:e-p:32:32-i64:64-n32"
 
 define void @test() {
 ; CHECK-LABEL: test:
 ; CHECK:       # %bb.0: # %bb
 ; CHECK-NEXT:    bc 12, 20, .LBB0_2
 ; CHECK-NEXT:  # %bb.1: # %bb2
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    stw 3, 0(3)
 ; CHECK-NEXT:    lis 3, 256
 ; CHECK-NEXT:    stw 3, 0(3)
 ; CHECK-NEXT:    blr
-; CHECK-NEXT:  .LBB0_2: # %bb1
-; CHECK-NEXT:    bclr 4, 20, 0
-; CHECK-NEXT:  # %bb.3: # %bb66
+; CHECK-NEXT:  .LBB0_2: # %bb66
 ; CHECK-NEXT:    lwz 4, 12(0)
 ; CHECK-NEXT:    lwz 5, 8(0)
 ; CHECK-NEXT:    lwz 6, 0(0)
 ; CHECK-NEXT:    lwz 7, 4(0)
 ; CHECK-NEXT:    lbz 3, 0(3)
 ; CHECK-NEXT:    and 5, 5, 6
 ; CHECK-NEXT:    and 4, 4, 7
 ; CHECK-NEXT:    and 4, 4, 5
 ; CHECK-NEXT:    cmpwi 3, 0
 ; CHECK-NEXT:    lis 3, 256
 ; CHECK-NEXT:    lis 7, 512
-; CHECK-NEXT:    bc 12, 2, .LBB0_4
-; CHECK-NEXT:    b .LBB0_5
-; CHECK-NEXT:  .LBB0_4: # %bb66
+; CHECK-NEXT:    bc 12, 2, .LBB0_3
+; CHECK-NEXT:    b .LBB0_4
+; CHECK-NEXT:  .LBB0_3: # %bb66
 ; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:  .LBB0_5: # %bb66
+; CHECK-NEXT:  .LBB0_4: # %bb66
 ; CHECK-NEXT:    cmpwi 1, 4, -1
 ; CHECK-NEXT:    cmpwi 5, 4, -1
 ; CHECK-NEXT:    li 6, 0
-; CHECK-NEXT:    bc 12, 6, .LBB0_6
-; CHECK-NEXT:    b .LBB0_7
-; CHECK-NEXT:  .LBB0_6: # %bb66
+; CHECK-NEXT:    bc 12, 6, .LBB0_5
+; CHECK-NEXT:    b .LBB0_6
+; CHECK-NEXT:  .LBB0_5: # %bb66
 ; CHECK-NEXT:    addi 3, 7, 0
-; CHECK-NEXT:  .LBB0_7: # %bb66
+; CHECK-NEXT:  .LBB0_6: # %bb66
 ; CHECK-NEXT:    cror 20, 22, 2
 ; CHECK-NEXT:    stw 3, 0(3)
-; CHECK-NEXT:    bc 12, 20, .LBB0_9
-; CHECK-NEXT:  # %bb.8: # %bb66
+; CHECK-NEXT:    bc 12, 20, .LBB0_8
+; CHECK-NEXT:  # %bb.7: # %bb66
 ; CHECK-NEXT:    ori 3, 6, 0
-; CHECK-NEXT:    b .LBB0_10
-; CHECK-NEXT:  .LBB0_9: # %bb66
+; CHECK-NEXT:    b .LBB0_9
+; CHECK-NEXT:  .LBB0_8: # %bb66
 ; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:  .LBB0_10: # %bb66
+; CHECK-NEXT:  .LBB0_9: # %bb66
 ; CHECK-NEXT:    stw 3, 0(3)
 ; CHECK-NEXT:    blr
 bb:
   br i1 undef, label %bb2, label %bb1
 
 bb2:                                              ; preds = %bb
   %i = select i1 undef, i64 0, i64 72057594037927936
   store i64 %i, ptr undef, align 8

llvm/test/CodeGen/Thumb/consthoist-few-dependents.ll

 ; OPT-3-NEXT: store i16 -5, ptr @global.3, align 1
 ; OPT-3: bb3:
 ; OPT-3-NEXT:   store i16 -5, ptr @global.4, align 1
 ; OPT-3-NEXT:   store i16 -5, ptr @global.3, align 1
 ; OPT-3-NOT: add
 ; OPT-3-NOT: bitcast
 
 ; LLC-LABEL: carla
-; LLC-DAG: ldr r{{[0-9]+}}, .LCPI2_1
-; LLC-DAG: ldr r{{[0-9]+}}, .LCPI2_3
+; LLC-DAG: ldr r{{[0-9]+}}, .LCPI2_0
+; LLC-DAG: ldr r{{[0-9]+}}, .LCPI2_2
 ; LLC-NOT: mvn
 ; LLC-NOT: add
 
 @global.3 = local_unnamed_addr global i16 undef, align 2
 @global.4 = local_unnamed_addr global i16 undef, align 2
 
 define void @carla() {
 bb:

llvm/test/CodeGen/Thumb2/thumb2-cbnz.ll

 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -arm-atomic-cfg-tidy=0 | FileCheck %s
 ; rdar://7354379
 
 declare double @foo(double) nounwind readnone
 
 define void @t(i32 %c, double %b) {
 entry:
-; CHECK:      cmp r0, #0
+; CHECK:      cbz r0
   %cmp1 = icmp ne i32 %c, 0
   br i1 %cmp1, label %bb3, label %bb1
 
 bb1:                                              ; preds = %entry
   unreachable
 
 bb3:                                              ; preds = %entry
   %cmp2 = icmp ne i32 %c, 0

llvm/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll

 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .LBB0_1: # %bb.i5
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    movl %ecx, %eax
 ; CHECK-NEXT:    addl %ebx, %ebx
 ; CHECK-NEXT:    xorl %ecx, %ecx
 ; CHECK-NEXT:    testb $1, %al
 ; CHECK-NEXT:    jne .LBB0_1
-; CHECK-NEXT:  # %bb.2: # %mp_unexp_mp2d.exit.i
-; CHECK-NEXT:    je .LBB0_10
-; CHECK-NEXT:  # %bb.3: # %cond_next.i
-; CHECK-NEXT:    testb $1, %al
-; CHECK-NEXT:    jne .LBB0_10
-; CHECK-NEXT:  # %bb.4: # %cond_next36.i
-; CHECK-NEXT:    movl $0, 0
-; CHECK-NEXT:    movzbl %al, %ebp
-; CHECK-NEXT:    andl $1, %ebp
-; CHECK-NEXT:    xorpd %xmm0, %xmm0
-; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    xorl %ecx, %ecx
-; CHECK-NEXT:    xorpd %xmm1, %xmm1
-; CHECK-NEXT:    .p2align 4, 0x90
-; CHECK-NEXT:  .LBB0_5: # %bb.i28.i
-; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:  .LBB0_2: # %cond_true.i
+; CHECK-NEXT:    popl %esi
+; CHECK-NEXT:    popl %edi
+; CHECK-NEXT:    popl %ebx
+; CHECK-NEXT:    popl %ebp
+; CHECK-NEXT:    retl
+; CHECK-NEXT:  .LBB0_3: # %bb.i28.i
 ; CHECK-NEXT:    cvttsd2si %xmm1, %edx
 ; CHECK-NEXT:    cmpl %esi, %edx
 ; CHECK-NEXT:    cmovgel %eax, %edx
 ; CHECK-NEXT:    addl $2, %ecx
-; CHECK-NEXT:    xorps %xmm2, %xmm2
 ; CHECK-NEXT:    cvtsi2sd %edx, %xmm2
-; CHECK-NEXT:    xorpd %xmm1, %xmm1
+; CHECK-NEXT:    xorps %xmm1, %xmm1
 ; CHECK-NEXT:    subsd %xmm2, %xmm1
 ; CHECK-NEXT:    mulsd %xmm0, %xmm1
 ; CHECK-NEXT:    addl $-2, %ebp
-; CHECK-NEXT:    jne .LBB0_5
-; CHECK-NEXT:  # %bb.6: # %mp_unexp_d2mp.exit29.i
+; CHECK-NEXT:    jne .LBB0_3
+; CHECK-NEXT:  # %bb.4: # %mp_unexp_d2mp.exit29.i
 ; CHECK-NEXT:    movl $0, 0
-; CHECK-NEXT:    je .LBB0_7
-; CHECK-NEXT:  # %bb.8: # %mp_sqrt_init.exit
+; CHECK-NEXT:    je .LBB0_5
+; CHECK-NEXT:  # %bb.6: # %mp_sqrt_init.exit
 ; CHECK-NEXT:    xorl %ecx, %ecx
 ; CHECK-NEXT:    movl %edi, %edx
 ; CHECK-NEXT:    calll mp_mul_csqu@PLT
 ; CHECK-NEXT:    xorl %ecx, %ecx
 ; CHECK-NEXT:    movl $-1, %edx
 ; CHECK-NEXT:    pushl {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    pushl {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    pushl $0
 ; CHECK-NEXT:    calll rdft@PLT
 ; CHECK-NEXT:    addl $12, %esp
 ; CHECK-NEXT:    xorl %ecx, %ecx
 ; CHECK-NEXT:    movl %esi, %edx
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    pushl %eax
 ; CHECK-NEXT:    pushl %edi
 ; CHECK-NEXT:    pushl $0
 ; CHECK-NEXT:    calll mp_mul_d2i@PLT
 ; CHECK-NEXT:    addl $12, %esp
 ; CHECK-NEXT:    testl %ebp, %ebp
-; CHECK-NEXT:    jne .LBB0_10
-; CHECK-NEXT:  # %bb.9: # %cond_false.i
+; CHECK-NEXT:    jne .LBB0_2
+; CHECK-NEXT:  # %bb.7: # %cond_false.i
 ; CHECK-NEXT:    xorl %ecx, %ecx
 ; CHECK-NEXT:    movl %esi, %edx
 ; CHECK-NEXT:    pushl {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    pushl $0
 ; CHECK-NEXT:    calll mp_round@PLT
 ; CHECK-NEXT:    addl $8, %esp
 ; CHECK-NEXT:    xorl %ecx, %ecx
 ; CHECK-NEXT:    movl %esi, %edx

 ; CHECK-NEXT:    addl $8, %esp
 ; CHECK-NEXT:    xorl %ecx, %ecx
 ; CHECK-NEXT:    movl %esi, %edx
 ; CHECK-NEXT:    pushl %ebp
 ; CHECK-NEXT:    pushl {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    pushl %ebx
 ; CHECK-NEXT:    calll mp_mul_d2i@PLT
 ; CHECK-NEXT:    addl $12, %esp
-; CHECK-NEXT:  .LBB0_10: # %cond_true.i
-; CHECK-NEXT:    popl %esi
-; CHECK-NEXT:    popl %edi
-; CHECK-NEXT:    popl %ebx
-; CHECK-NEXT:    popl %ebp
-; CHECK-NEXT:    retl
-; CHECK-NEXT:    .p2align 4, 0x90
-; CHECK-NEXT:  .LBB0_7: # %bb.i.i
-; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    jmp .LBB0_7
+; CHECK-NEXT:    jmp .LBB0_2
+; CHECK-NEXT:  .LBB0_5: # %bb.i.i
+; CHECK-NEXT:    jmp .LBB0_5
 entry:
   br label %bb.i5
 
 bb.i5:    ; preds = %bb.i5, %entry
   %nfft_init.0.i = phi i32 [ 1, %entry ], [ %tmp7.i3, %bb.i5 ]    ; <i32> [#uses=1]
   %foo = phi i1 [1, %entry], [0, %bb.i5]
   %tmp7.i3 = shl i32 %nfft_init.0.i, 1    ; <i32> [#uses=2]
   br i1 %foo, label %bb.i5, label %mp_unexp_mp2d.exit.i

llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll

 ; CHECK-NEXT:    .cfi_def_cfa_offset 48
 ; CHECK-NEXT:    .cfi_offset %esi, -20
 ; CHECK-NEXT:    .cfi_offset %edi, -16
 ; CHECK-NEXT:    .cfi_offset %ebx, -12
 ; CHECK-NEXT:    .cfi_offset %ebp, -8
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %esi
 ; CHECK-NEXT:    movzbl {{[0-9]+}}(%esp), %ebx
 ; CHECK-NEXT:    testb $1, %bl
-; CHECK-NEXT:    je LBB0_25
-; CHECK-NEXT:  ## %bb.1: ## %bb116.i
-; CHECK-NEXT:    je LBB0_25
-; CHECK-NEXT:  ## %bb.2: ## %bb52.i.i
+; CHECK-NEXT:    je LBB0_23
+; CHECK-NEXT:  ## %bb.1: ## %bb52.i.i
 ; CHECK-NEXT:    testb $1, %bl
-; CHECK-NEXT:    je LBB0_25
-; CHECK-NEXT:  ## %bb.3: ## %bb142.i
-; CHECK-NEXT:    je LBB0_25
-; CHECK-NEXT:  ## %bb.4:
+; CHECK-NEXT:    je LBB0_23
+; CHECK-NEXT:  ## %bb.2:
 ; CHECK-NEXT:    movl L_.str89$non_lazy_ptr, %edi
 ; CHECK-NEXT:    movb $1, %bh
 ; CHECK-NEXT:    movl L_.str$non_lazy_ptr, %ebp
-; CHECK-NEXT:    jmp LBB0_5
-; CHECK-NEXT:  LBB0_21: ## %bb7806
-; CHECK-NEXT:    ## in Loop: Header=BB0_5 Depth=1
+; CHECK-NEXT:    jmp LBB0_3
+; CHECK-NEXT:    .p2align     4, 0x90
+; CHECK-NEXT:  LBB0_19: ## %bb7806
+; CHECK-NEXT:    ## in Loop: Header=BB0_3 Depth=1
 ; CHECK-NEXT:  Ltmp16:
 ; CHECK-NEXT:    movl $0, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movl $1, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movl $0, (%esp)
 ; CHECK-NEXT:    calll __ZN12wxStringBase6appendEmw
 ; CHECK-NEXT:  Ltmp17:
-; CHECK-NEXT:  LBB0_5: ## %bb3261
+; CHECK-NEXT:  LBB0_3: ## %bb3261
 ; CHECK-NEXT:    ## =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    cmpl $37, 0
-; CHECK-NEXT:    jne LBB0_25
-; CHECK-NEXT:  ## %bb.6: ## %bb3306
-; CHECK-NEXT:    ## in Loop: Header=BB0_5 Depth=1
+; CHECK-NEXT:    jne LBB0_23
+; CHECK-NEXT:  ## %bb.4: ## %bb3306
+; CHECK-NEXT:    ## in Loop: Header=BB0_3 Depth=1
 ; CHECK-NEXT:  Ltmp0:
 ; CHECK-NEXT:    movl %edi, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movl $0, (%esp)
 ; CHECK-NEXT:    calll __ZN12wxStringBaseaSEPKw
 ; CHECK-NEXT:  Ltmp1:
-; CHECK-NEXT:  ## %bb.7: ## %bb3314
-; CHECK-NEXT:    ## in Loop: Header=BB0_5 Depth=1
+; CHECK-NEXT:  ## %bb.5: ## %bb3314
+; CHECK-NEXT:    ## in Loop: Header=BB0_3 Depth=1
 ; CHECK-NEXT:    movl 0, %eax
 ; CHECK-NEXT:    cmpl $121, %eax
-; CHECK-NEXT:    ja LBB0_25
-; CHECK-NEXT:  ## %bb.8: ## %bb3314
-; CHECK-NEXT:    ## in Loop: Header=BB0_5 Depth=1
+; CHECK-NEXT:    ja LBB0_23
+; CHECK-NEXT:  ## %bb.6: ## %bb3314
+; CHECK-NEXT:    ## in Loop: Header=BB0_3 Depth=1
 ; CHECK-NEXT:    jmpl *LJTI0_0(,%eax,4)
-; CHECK-NEXT:  LBB0_10: ## %bb5809
-; CHECK-NEXT:    ## in Loop: Header=BB0_5 Depth=1
+; CHECK-NEXT:  LBB0_8: ## %bb5809
+; CHECK-NEXT:    ## in Loop: Header=BB0_3 Depth=1
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    testb %al, %al
-; CHECK-NEXT:    jne LBB0_25
-; CHECK-NEXT:  ## %bb.11: ## %bb5809
-; CHECK-NEXT:    ## in Loop: Header=BB0_5 Depth=1
+; CHECK-NEXT:    jne LBB0_23
+; CHECK-NEXT:  ## %bb.9: ## %bb5809
+; CHECK-NEXT:    ## in Loop: Header=BB0_3 Depth=1
 ; CHECK-NEXT:    testb %bh, %bh
-; CHECK-NEXT:    je LBB0_25
-; CHECK-NEXT:  ## %bb.12: ## %bb91.i8504
-; CHECK-NEXT:    ## in Loop: Header=BB0_5 Depth=1
+; CHECK-NEXT:    je LBB0_23
+; CHECK-NEXT:  ## %bb.10: ## %bb91.i8504
+; CHECK-NEXT:    ## in Loop: Header=BB0_3 Depth=1
 ; CHECK-NEXT:    testb $1, %bl
-; CHECK-NEXT:    je LBB0_14
-; CHECK-NEXT:  ## %bb.13: ## %bb155.i8541
-; CHECK-NEXT:    ## in Loop: Header=BB0_5 Depth=1
+; CHECK-NEXT:    je LBB0_12
+; CHECK-NEXT:  ## %bb.11: ## %bb155.i8541
+; CHECK-NEXT:    ## in Loop: Header=BB0_3 Depth=1
 ; CHECK-NEXT:  Ltmp4:
 ; CHECK-NEXT:    movl $0, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movl $0, (%esp)
 ; CHECK-NEXT:    calll _gmtime_r
 ; CHECK-NEXT:  Ltmp5:
-; CHECK-NEXT:  LBB0_14: ## %bb182.i8560
-; CHECK-NEXT:    ## in Loop: Header=BB0_5 Depth=1
+; CHECK-NEXT:  LBB0_12: ## %bb182.i8560
+; CHECK-NEXT:    ## in Loop: Header=BB0_3 Depth=1
 ; CHECK-NEXT:    testb $1, %bl
-; CHECK-NEXT:    je LBB0_15
-; CHECK-NEXT:  ## %bb.16: ## %bb278.i8617
-; CHECK-NEXT:    ## in Loop: Header=BB0_5 Depth=1
-; CHECK-NEXT:    je LBB0_18
-; CHECK-NEXT:  ## %bb.17: ## %bb440.i8663
-; CHECK-NEXT:    ## in Loop: Header=BB0_5 Depth=1
+; CHECK-NEXT:    je LBB0_13
+; CHECK-NEXT:  ## %bb.14: ## %bb278.i8617
+; CHECK-NEXT:    ## in Loop: Header=BB0_3 Depth=1
+; CHECK-NEXT:    je LBB0_16
+; CHECK-NEXT:  ## %bb.15: ## %bb440.i8663
+; CHECK-NEXT:    ## in Loop: Header=BB0_3 Depth=1
 ; CHECK-NEXT:  Ltmp6:
 ; CHECK-NEXT:    movl L_.str4$non_lazy_ptr, %eax
 ; CHECK-NEXT:    movl %eax, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movl L_.str33$non_lazy_ptr, %eax
 ; CHECK-NEXT:    movl %eax, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movl L__ZZNK10wxDateTime5GetTmERKNS_8TimeZoneEE12__FUNCTION__$non_lazy_ptr, %eax
 ; CHECK-NEXT:    movl %eax, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movl %ebp, (%esp)
 ; CHECK-NEXT:    movl $1717, {{[0-9]+}}(%esp) ## imm = 0x6B5
 ; CHECK-NEXT:    calll __Z10wxOnAssertPKwiPKcS0_S0_
 ; CHECK-NEXT:  Ltmp7:
-; CHECK-NEXT:    jmp LBB0_18
-; CHECK-NEXT:  LBB0_15: ## %bb187.i8591
-; CHECK-NEXT:    ## in Loop: Header=BB0_5 Depth=1
-; CHECK-NEXT:    jne LBB0_25
-; CHECK-NEXT:  LBB0_18: ## %invcont5814
-; CHECK-NEXT:    ## in Loop: Header=BB0_5 Depth=1
+; CHECK-NEXT:    jmp LBB0_16
+; CHECK-NEXT:  LBB0_13: ## %bb187.i8591
+; CHECK-NEXT:    ## in Loop: Header=BB0_3 Depth=1
+; CHECK-NEXT:    jne LBB0_23
+; CHECK-NEXT:  LBB0_16: ## %invcont5814
+; CHECK-NEXT:    ## in Loop: Header=BB0_3 Depth=1
 ; CHECK-NEXT:  Ltmp8:
 ; CHECK-NEXT:    movl $0, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movl $0, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movl $0, (%esp)
 ; CHECK-NEXT:    calll __ZN8wxString6FormatEPKwz
 ; CHECK-NEXT:    subl $4, %esp
 ; CHECK-NEXT:  Ltmp9:
-; CHECK-NEXT:  ## %bb.19: ## %invcont5831
-; CHECK-NEXT:    ## in Loop: Header=BB0_5 Depth=1
+; CHECK-NEXT:  ## %bb.17: ## %invcont5831
+; CHECK-NEXT:    ## in Loop: Header=BB0_3 Depth=1
 ; CHECK-NEXT:  Ltmp10:
 ; CHECK-NEXT:    movl $0, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movl $0, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movl $0, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movl $0, (%esp)
 ; CHECK-NEXT:    calll __ZN12wxStringBase10ConcatSelfEmPKwm
 ; CHECK-NEXT:  Ltmp11:
-; CHECK-NEXT:    jmp LBB0_5
-; CHECK-NEXT:  LBB0_9: ## %bb5657
+; CHECK-NEXT:    jmp LBB0_3
+; CHECK-NEXT:  LBB0_7: ## %bb5657
 ; CHECK-NEXT:  Ltmp13:
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    movl %eax, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    movl %eax, (%esp)
 ; CHECK-NEXT:    calll __ZNK10wxDateTime12GetDayOfYearERKNS_8TimeZoneE
 ; CHECK-NEXT:  Ltmp14:
-; CHECK-NEXT:    jmp LBB0_25
-; CHECK-NEXT:  LBB0_20: ## %bb5968
+; CHECK-NEXT:    jmp LBB0_23
+; CHECK-NEXT:  LBB0_18: ## %bb5968
 ; CHECK-NEXT:  Ltmp2:
 ; CHECK-NEXT:    movl $0, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movl $0, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movl $0, (%esp)
 ; CHECK-NEXT:    calll __ZN8wxString6FormatEPKwz
 ; CHECK-NEXT:    subl $4, %esp
 ; CHECK-NEXT:  Ltmp3:
-; CHECK-NEXT:  LBB0_25: ## %bb115.critedge.i
+; CHECK-NEXT:  LBB0_23: ## %bb115.critedge.i
 ; CHECK-NEXT:    movl %esi, %eax
 ; CHECK-NEXT:    addl $28, %esp
 ; CHECK-NEXT:    popl %esi
 ; CHECK-NEXT:    popl %edi
 ; CHECK-NEXT:    popl %ebx
 ; CHECK-NEXT:    popl %ebp
 ; CHECK-NEXT:    retl $4
-; CHECK-NEXT:  LBB0_23: ## %lpad.loopexit.split-lp
+; CHECK-NEXT:  LBB0_21: ## %lpad.loopexit.split-lp
 ; CHECK-NEXT:  Ltmp15:
-; CHECK-NEXT:    jmp LBB0_25
-; CHECK-NEXT:  LBB0_24: ## %lpad8185
+; CHECK-NEXT:    jmp LBB0_23
+; CHECK-NEXT:  LBB0_22: ## %lpad8185
 ; CHECK-NEXT:  Ltmp12:
-; CHECK-NEXT:    jmp LBB0_25
-; CHECK-NEXT:  LBB0_22: ## %lpad.loopexit
+; CHECK-NEXT:    jmp LBB0_23
+; CHECK-NEXT:  LBB0_20: ## %lpad.loopexit
 ; CHECK-NEXT:  Ltmp18:
-; CHECK-NEXT:    jmp LBB0_25
+; CHECK-NEXT:    jmp LBB0_23
 ; CHECK-NEXT:  Lfunc_end0:
 entry:
   br i1 %foo, label %bb116.i, label %bb115.critedge.i
 bb115.critedge.i:   ; preds = %entry
   ret void
 bb116.i:    ; preds = %entry
   br i1 %foo, label %bb52.i.i, label %bb3118
 bb3118:   ; preds = %bb116.i