For floating-point instructions, SEW won't be 8. So we don't need
to generate scheduling resources for it.
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Thanks for working on this. I was going to add a similar patch today!
| llvm/lib/Target/RISCV/RISCVScheduleV.td | ||
|---|---|---|
| 37 | Under the vector specification, what does it mean for a vector floating point instruction to execute under MF8? Is this allowed? In our scheduler, what does it mean for a vector floating point pseudo to be MF8? Under this implementation, does it mean we do not define scheduling resources for it since sew set is empty? I wonder whether we need a MxListF that does not contain MF8, if it is the case that floating point vector instructions under MF8 don't make sense. | |
| llvm/lib/Target/RISCV/RISCVScheduleV.td | ||
|---|---|---|
| 37 |
My understanding is:
In general, the requirement is to support LMUL ≥ SEWMIN/ELEN, where SEWMIN is the narrowest supported SEW value and ELEN is the widest supported SEW value. When LMUL < SEWMIN/ELEN, there is no guarantee an implementation would have enough bits in the fractional vector register to store at least one element, as VLEN=ELEN is a valid implementation choice. For example, with VLEN=ELEN=32, and SEW MIN=8, an LMUL of 1/8 would only provide four bits of storage in a vector register.
Yes, we won't define any scheduling resources for it as we won't generate MF8 pseudos(see https://github.com/llvm/llvm-project/blob/9fdf82dc32dc38e0b92dab3215a83d8f3c2f9bbf/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td#L112).
It makes sense to me to add a MxListF. I keep the MF8 case in SchedSEWSetF just because there is no MxList parameter in LMULSEWWriteResImpl and LMULSEWReadAdvanceImpl(we iterate over SchedMxList). A !exist can be added just like LMULWriteResImpl and LMULReadAdvanceImpl. | |
| llvm/lib/Target/RISCV/RISCVScheduleV.td | ||
|---|---|---|
| 37 | Nope…… | |
| llvm/lib/Target/RISCV/RISCVScheduleV.td | ||
|---|---|---|
| 37 | multiclass LMULSEWWriteResImpl<string name, list<ProcResourceKind> resources,
bit isF = 0> {
def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;
// Now I think we can remove MF8 from SchedSEWSetF
foreach mx = !if(isF, SchedMxListF, SchedMxList) in {
defvar sews = !if(isF, SchedSEWSetF<mx>.val, SchedSEWSet<mx>.val);
foreach sew = sews in
def : WriteRes<!cast<SchedWrite>(name # "_" # mx # "_E" # sew), resources>;
}
} | |
Under the vector specification, what does it mean for a vector floating point instruction to execute under MF8? Is this allowed?
In our scheduler, what does it mean for a vector floating point pseudo to be MF8? Under this implementation, does it mean we do not define scheduling resources for it since sew set is empty?
I wonder whether we need a MxListF that does not contain MF8, if it is the case that floating point vector instructions under MF8 don't make sense.