[RISCV] Remove SEW=8 case for floating-point

[• pcwang-thead]

Summary

For floating-point instructions, SEW won't be 8. So we don't need
to generate scheduling resources for it.

[michaelmaitland]

Thanks for working on this. I was going to add a similar patch today!

llvm/lib/Target/RISCV/RISCVScheduleV.td

39

Under the vector specification, what does it mean for a vector floating point instruction to execute under MF8? Is this allowed?

In our scheduler, what does it mean for a vector floating point pseudo to be MF8? Under this implementation, does it mean we do not define scheduling resources for it since sew set is empty?

I wonder whether we need a MxListF that does not contain MF8, if it is the case that floating point vector instructions under MF8 don't make sense.

[• pcwang-thead]

llvm/lib/Target/RISCV/RISCVScheduleV.td

39

Under the vector specification, what does it mean for a vector floating point instruction to execute under MF8? Is this allowed?

My understanding is:

1. SEW=8 is illegal since there is no standard 8 bits floating point format currently.
2. The spec (3.4.2. Vector Register Grouping) says:

In general, the requirement is to support LMUL ≥ SEWMIN/ELEN, where SEWMIN is the narrowest supported SEW value and ELEN is the widest supported SEW value.
When LMUL < SEWMIN/ELEN, there is no guarantee an implementation would have enough bits in the fractional vector register to store at least one element, as VLEN=ELEN is a valid implementation choice. For example, with VLEN=ELEN=32, and SEW MIN=8, an LMUL of 1/8 would only provide four bits of storage in a vector register.

3. MF8 may be legal, but it depends on VLEN. So, as you can see, there is no mf8 types in C API(Data Types) and LLVM IR (Vector type mapping to LLVM types).

In our scheduler, what does it mean for a vector floating point pseudo to be MF8? Under this implementation, does it mean we do not define scheduling resources for it since sew set is empty?

Yes, we won't define any scheduling resources for it as we won't generate MF8 pseudos(see https://github.com/llvm/llvm-project/blob/9fdf82dc32dc38e0b92dab3215a83d8f3c2f9bbf/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td#L112).

I wonder whether we need a MxListF that does not contain MF8, if it is the case that floating point vector instructions under MF8 don't make sense.

It makes sense to me to add a MxListF. I keep the MF8 case in SchedSEWSetF just because there is no MxList parameter in LMULSEWWriteResImpl and LMULSEWReadAdvanceImpl(we iterate over SchedMxList). A !exist can be added just like LMULWriteResImpl and LMULReadAdvanceImpl.

[• pcwang-thead]

llvm/lib/Target/RISCV/RISCVScheduleV.td

39

Nope……
We can't use !exists since we need to get sews first.

[michaelmaitland]

llvm/lib/Target/RISCV/RISCVScheduleV.td

39

multiclass LMULSEWWriteResImpl<string name, list<ProcResourceKind> resources,
                               bit isF = 0> {
  def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;
  // Now I think we can remove MF8 from SchedSEWSetF
  foreach mx = !if(isF, SchedMxListF, SchedMxList) in {
    defvar sews = !if(isF, SchedSEWSetF<mx>.val, SchedSEWSet<mx>.val); 
    foreach sew = sews in
      def : WriteRes<!cast<SchedWrite>(name # "_" # mx # "_E" # sew), resources>;
  }
}

[• pcwang-thead]

• Rebase.
• Add SchedMxListF.

[craig.topper]

LGTM but I'll let @michaelmaitland give final approval

[michaelmaitland]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

let VLMul = m.value in {
                                  Sched<[WriteVFClassV_MX, ReadVFClassV_MX, ReadVMask]>;
     }
   }
 }
 
 multiclass VPseudoVSQR_V {
   foreach m = MxListF in {
     defvar mx = m.MX;
-    defvar sews = SchedSEWSet<m.MX>.val;
+    defvar sews = SchedSEWSetF<m.MX>.val;
 
     let VLMul = m.value in
       foreach e = sews in {
         defvar suffix = "_" # mx # "_E" # e;
         defvar WriteVFSqrtV_MX_E = !cast<SchedWrite>("WriteVFSqrtV" # suffix);
         defvar ReadVFSqrtV_MX_E = !cast<SchedRead>("ReadVFSqrtV" # suffix);
 
         def "_V" # suffix : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
foreach m = f.MxList in {
                 Sched<[WriteVFMulF_MX, ReadVFMulV_MX, ReadVFMulF_MX, ReadVMask]>;
     }
   }
 }
 
 multiclass VPseudoVFDIV_VV_VF {
   foreach m = MxListF in {
     defvar mx = m.MX;
-    defvar sews = SchedSEWSet<mx>.val;
+    defvar sews = SchedSEWSetF<mx>.val;
     foreach e = sews in {
       defvar WriteVFDivV_MX_E = !cast<SchedWrite>("WriteVFDivV_" # mx # "_E" # e);
       defvar ReadVFDivV_MX_E = !cast<SchedRead>("ReadVFDivV_" # mx # "_E" # e);
 
       defm "" : VPseudoBinaryFV_VV_E<m, e>,
                 Sched<[WriteVFDivV_MX_E, ReadVFDivV_MX_E, ReadVFDivV_MX_E, ReadVMask]>;
     }
   }
 
   foreach f = FPList in {
     foreach m = f.MxList in {
       defvar mx = m.MX;
-      defvar sews = SchedSEWSet<mx>.val;
+      defvar sews = SchedSEWSetF<mx>.val;
       foreach e = sews in {
         defvar WriteVFDivF_MX_E = !cast<SchedWrite>("WriteVFDivF_" # mx # "_E" # e);
         defvar ReadVFDivV_MX_E = !cast<SchedRead>("ReadVFDivV_" # mx # "_E" # e);
         defvar ReadVFDivF_MX_E = !cast<SchedRead>("ReadVFDivF_" # mx # "_E" # e);
 
         defm "" : VPseudoBinaryV_VF_E<m, e, f>,
                   Sched<[WriteVFDivF_MX_E, ReadVFDivV_MX_E, ReadVFDivF_MX_E, ReadVMask]>;
       }
     }
   }
 }
 
 multiclass VPseudoVFRDIV_VF {
   foreach f = FPList in {
     foreach m = f.MxList in {
       defvar mx = m.MX;
-      defvar sews = SchedSEWSet<mx>.val;
+      defvar sews = SchedSEWSetF<mx>.val;
       foreach e = sews in {
         defvar WriteVFDivF_MX_E = !cast<SchedWrite>("WriteVFDivF_" # mx # "_E" # e);
         defvar ReadVFDivV_MX_E = !cast<SchedRead>("ReadVFDivV_" # mx # "_E" # e);
         defvar ReadVFDivF_MX_E = !cast<SchedRead>("ReadVFDivF_" # mx # "_E" # e);
 
         defm "" : VPseudoBinaryV_VF_E<m, e, f>,
                   Sched<[WriteVFDivF_MX_E, ReadVFDivV_MX_E, ReadVFDivF_MX_E, ReadVMask]>;
       }

llvm/lib/Target/RISCV/RISCVScheduleV.td

 //===- RISCVScheduleV.td - RISC-V Scheduling Definitions V -*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 /// Define scheduler resources associated with def operands.
 
 defvar SchedMxList = ["M1", "M2", "M4", "M8", "MF2", "MF4", "MF8"];
 // Used for widening and narrowing instructions as it doesn't contain M8.
 defvar SchedMxListW = !listremove(SchedMxList, ["M8"]);
 defvar SchedMxListFW = !listremove(SchedMxList, ["M8", "MF8"]);
+// Used for floating-point as it doesn't contain MF8.
+defvar SchedMxListF = !listremove(SchedMxList, ["MF8"]);
 // Used for widening floating-point Reduction as it doesn't contain MF8.
-defvar SchedMxListFWRed = !listremove(SchedMxList, ["MF8"]);
+defvar SchedMxListFWRed = SchedMxListF;
 
 class SchedSEWSet<string mx> {
   list<int> val = !cond(!eq(mx, "M1"):  [8, 16, 32, 64],
                         !eq(mx, "M2"):  [8, 16, 32, 64],
                         !eq(mx, "M4"):  [8, 16, 32, 64],
                         !eq(mx, "M8"):  [8, 16, 32, 64],
                         !eq(mx, "MF2"): [8, 16, 32],
                         !eq(mx, "MF4"): [8, 16],
                         !eq(mx, "MF8"): [8]);
 }
 
+// For floating-point instructions, SEW won't be 8.
+class SchedSEWSetF<string mx> {
+  list<int> val = !cond(!eq(mx, "M1"):  [16, 32, 64],
+                        !eq(mx, "M2"):  [16, 32, 64],
+                        !eq(mx, "M4"):  [16, 32, 64],
+                        !eq(mx, "M8"):  [16, 32, 64],
+                        !eq(mx, "MF2"): [16, 32],
+                        !eq(mx, "MF4"): [16]);
+}
+
 // Define multiclasses to define SchedWrite, SchedRead,  WriteRes, and
 // ReadAdvance for each (name, LMUL) pair and for each LMUL in each of the
 // SchedMxList variants above. Each multiclass is responsible for defining
 // a record that represents the WorseCase behavior for name.
 multiclass LMULSchedWritesImpl<string name, list<string> MxList> {
   def name # "_WorstCase" : SchedWrite;
   foreach mx = MxList in {
     def name # "_" # mx : SchedWrite;
if !exists<SchedRead>(name # "_" # mx) then
       def : ReadAdvance<!cast<SchedRead>(name # "_" # mx), val, writes>;
   }
 }
 
 // Define multiclasses to define SchedWrite, SchedRead,  WriteRes, and
 // ReadAdvance for each (name, LMUL, SEW) tuple for each LMUL in each of the
 // SchedMxList variants above. Each multiclass is responsible for defining
 // a record that represents the WorseCase behavior for name.
-multiclass LMULSEWSchedWritesImpl<string name, list<string> MxList> {
+multiclass LMULSEWSchedWritesImpl<string name, list<string> MxList, bit isF = 0> {
   def name # "_WorstCase" : SchedWrite;
   foreach mx = MxList in {
-    foreach sew = SchedSEWSet<mx>.val in
+    foreach sew = !if(isF, SchedSEWSetF<mx>.val, SchedSEWSet<mx>.val) in
       def name # "_" # mx # "_E" # sew : SchedWrite;
   }
 }
-multiclass LMULSEWSchedReadsImpl<string name, list<string> MxList> {
+multiclass LMULSEWSchedReadsImpl<string name, list<string> MxList, bit isF = 0> {
   def name # "_WorstCase" : SchedRead;
   foreach mx = MxList in {
-    foreach sew = SchedSEWSet<mx>.val in
+    foreach sew = !if(isF, SchedSEWSetF<mx>.val, SchedSEWSet<mx>.val) in
       def name # "_" # mx # "_E" # sew : SchedRead;
   }
 }
-multiclass LMULSEWWriteResImpl<string name, list<ProcResourceKind> resources> {
+multiclass LMULSEWWriteResImpl<string name, list<ProcResourceKind> resources,
+                               bit isF = 0> {
   def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;
-  foreach mx = SchedMxList in {
-   foreach sew = SchedSEWSet<mx>.val in
+  foreach mx = !if(isF, SchedMxListF, SchedMxList) in {
+    foreach sew = !if(isF, SchedSEWSetF<mx>.val, SchedSEWSet<mx>.val) in
       def : WriteRes<!cast<SchedWrite>(name # "_" # mx # "_E" # sew), resources>;
   }
 }
-multiclass LMULSEWReadAdvanceImpl<string name, int val,
-                                  list<SchedWrite> writes = []> {
+multiclass LMULSEWReadAdvanceImpl<string name, int val, list<SchedWrite> writes = [],
+                                  bit isF = 0> {
   def : ReadAdvance<!cast<SchedRead>(name # "_WorstCase"), val, writes>;
-  foreach mx = SchedMxList in {
-    foreach sew = SchedSEWSet<mx>.val in
+  foreach mx = !if(isF, SchedMxListF, SchedMxList) in {
+    foreach sew = !if(isF, SchedSEWSetF<mx>.val, SchedSEWSet<mx>.val) in
       def : ReadAdvance<!cast<SchedRead>(name # "_" # mx # "_E" # sew), val, writes>;
   }
 }
 // Define classes to define list containing all SchedWrites for each (name, LMUL)
 // pair for each LMUL in each of the SchedMxList variants above and name in
 // argument `names`. These classes can be used to construct a list of existing
 // definitions of writes corresponding to each (name, LMUL) pair, that are needed
 // by the ReadAdvance. For example:

 
 multiclass LMULSEWSchedWrites<string name> : LMULSEWSchedWritesImpl<name, SchedMxList>;
 multiclass LMULSEWSchedReads<string name> : LMULSEWSchedReadsImpl<name, SchedMxList>;
 multiclass LMULSEWWriteRes<string name, list<ProcResourceKind> resources>
   : LMULSEWWriteResImpl<name, resources>;
 multiclass LMULSEWReadAdvance<string name, int val, list<SchedWrite> writes = []>
   : LMULSEWReadAdvanceImpl<name, val, writes>;
 
+multiclass LMULSEWSchedWritesF<string name> : LMULSEWSchedWritesImpl<name, SchedMxListF, 1>;
+multiclass LMULSEWSchedReadsF<string name> : LMULSEWSchedReadsImpl<name, SchedMxListF, 1>;
+multiclass LMULSEWWriteResF<string name, list<ProcResourceKind> resources>
+  : LMULSEWWriteResImpl<name, resources, 1>;
+multiclass LMULSEWReadAdvanceF<string name, int val, list<SchedWrite> writes = []>
+  : LMULSEWReadAdvanceImpl<name, val, writes, 1>;
+
 multiclass LMULSchedWritesW<string name> : LMULSchedWritesImpl<name, SchedMxListW>;
 multiclass LMULSchedReadsW<string name> : LMULSchedReadsImpl<name, SchedMxListW>;
 multiclass LMULWriteResW<string name, list<ProcResourceKind> resources>
   : LMULWriteResImpl<name, resources>;
 multiclass LMULReadAdvanceW<string name, int val, list<SchedWrite> writes = []>
   : LMULReadAdvanceImpl<name, val, writes>;
 class LMULSchedWriteListW<list<string> names> : LMULSchedWriteListImpl<names, SchedMxListW>;
 

 defm "" : LMULSchedWrites<"WriteVFALUV">;
 defm "" : LMULSchedWrites<"WriteVFALUF">;
 // 13.3. Vector Widening Floating-Point Add/Subtract Instructions
 defm "" : LMULSchedWritesFW<"WriteVFWALUV">;
 defm "" : LMULSchedWritesFW<"WriteVFWALUF">;
 // 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
 defm "" : LMULSchedWrites<"WriteVFMulV">;
 defm "" : LMULSchedWrites<"WriteVFMulF">;
-defm "" : LMULSEWSchedWrites<"WriteVFDivV">;
-defm "" : LMULSEWSchedWrites<"WriteVFDivF">;
+defm "" : LMULSEWSchedWritesF<"WriteVFDivV">;
+defm "" : LMULSEWSchedWritesF<"WriteVFDivF">;
 // 13.5. Vector Widening Floating-Point Multiply
 defm "" : LMULSchedWritesFW<"WriteVFWMulV">;
 defm "" : LMULSchedWritesFW<"WriteVFWMulF">;
 // 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
 defm "" : LMULSchedWrites<"WriteVFMulAddV">;
 defm "" : LMULSchedWrites<"WriteVFMulAddF">;
 // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
 defm "" : LMULSchedWritesFW<"WriteVFWMulAddV">;
 defm "" : LMULSchedWritesFW<"WriteVFWMulAddF">;
 // 13.8. Vector Floating-Point Square-Root Instruction
-defm "" : LMULSEWSchedWrites<"WriteVFSqrtV">;
+defm "" : LMULSEWSchedWritesF<"WriteVFSqrtV">;
 // 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
 // 13.10. Vector Floating-Point Reciprocal Estimate Instruction
 defm "" : LMULSchedWrites<"WriteVFRecpV">;
 // 13.11. Vector Floating-Point MIN/MAX Instructions
 // 13.13. Vector Floating-Point Compare Instructions
 defm "" : LMULSchedWrites<"WriteVFCmpV">;
 defm "" : LMULSchedWrites<"WriteVFCmpF">;
 // 13.12. Vector Floating-Point Sign-Injection Instructions

 defm "" : LMULSchedReads<"ReadVFALUV">;
 defm "" : LMULSchedReads<"ReadVFALUF">;
 // 13.3. Vector Widening Floating-Point Add/Subtract Instructions
 defm "" : LMULSchedReadsFW<"ReadVFWALUV">;
 defm "" : LMULSchedReadsFW<"ReadVFWALUF">;
 // 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
 defm "" : LMULSchedReads<"ReadVFMulV">;
 defm "" : LMULSchedReads<"ReadVFMulF">;
-defm "" : LMULSEWSchedReads<"ReadVFDivV">;
-defm "" : LMULSEWSchedReads<"ReadVFDivF">;
+defm "" : LMULSEWSchedReadsF<"ReadVFDivV">;
+defm "" : LMULSEWSchedReadsF<"ReadVFDivF">;
 // 13.5. Vector Widening Floating-Point Multiply
 defm "" : LMULSchedReadsFW<"ReadVFWMulV">;
 defm "" : LMULSchedReadsFW<"ReadVFWMulF">;
 // 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
 defm "" : LMULSchedReads<"ReadVFMulAddV">;
 defm "" : LMULSchedReads<"ReadVFMulAddF">;
 // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
 defm "" : LMULSchedReadsFW<"ReadVFWMulAddV">;
 defm "" : LMULSchedReadsFW<"ReadVFWMulAddF">;
 // 13.8. Vector Floating-Point Square-Root Instruction
-defm "" : LMULSEWSchedReads<"ReadVFSqrtV">;
+defm "" : LMULSEWSchedReadsF<"ReadVFSqrtV">;
 // 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
 // 13.10. Vector Floating-Point Reciprocal Estimate Instruction
 defm "" : LMULSchedReads<"ReadVFRecpV">;
 // 13.11. Vector Floating-Point MIN/MAX Instructions
 // 13.13. Vector Floating-Point Compare Instructions
 defm "" : LMULSchedReads<"ReadVFCmpV">;
 defm "" : LMULSchedReads<"ReadVFCmpF">;
 // 13.12. Vector Floating-Point Sign-Injection Instructions

 
 // 13. Vector Floating-Point Instructions
 defm "" : LMULWriteRes<"WriteVFALUV", []>;
 defm "" : LMULWriteRes<"WriteVFALUF", []>;
 defm "" : LMULWriteResFW<"WriteVFWALUV", []>;
 defm "" : LMULWriteResFW<"WriteVFWALUF", []>;
 defm "" : LMULWriteRes<"WriteVFMulV", []>;
 defm "" : LMULWriteRes<"WriteVFMulF", []>;
-defm "" : LMULSEWWriteRes<"WriteVFDivV", []>;
-defm "" : LMULSEWWriteRes<"WriteVFDivF", []>;
+defm "" : LMULSEWWriteResF<"WriteVFDivV", []>;
+defm "" : LMULSEWWriteResF<"WriteVFDivF", []>;
 defm "" : LMULWriteResFW<"WriteVFWMulV", []>;
 defm "" : LMULWriteResFW<"WriteVFWMulF", []>;
 defm "" : LMULWriteRes<"WriteVFMulAddV", []>;
 defm "" : LMULWriteRes<"WriteVFMulAddF", []>;
 defm "" : LMULWriteResFW<"WriteVFWMulAddV", []>;
 defm "" : LMULWriteResFW<"WriteVFWMulAddF", []>;
-defm "" : LMULSEWWriteRes<"WriteVFSqrtV", []>;
+defm "" : LMULSEWWriteResF<"WriteVFSqrtV", []>;
 defm "" : LMULWriteRes<"WriteVFRecpV", []>;
 defm "" : LMULWriteRes<"WriteVFCmpV", []>;
 defm "" : LMULWriteRes<"WriteVFCmpF", []>;
 defm "" : LMULWriteRes<"WriteVFSgnjV", []>;
 defm "" : LMULWriteRes<"WriteVFSgnjF", []>;
 defm "" : LMULWriteRes<"WriteVFClassV", []>;
 defm "" : LMULWriteRes<"WriteVFMergeV", []>;
 defm "" : LMULWriteRes<"WriteVFMovV", []>;

 
 // 13. Vector Floating-Point Instructions
 defm "" : LMULReadAdvance<"ReadVFALUV", 0>;
 defm "" : LMULReadAdvance<"ReadVFALUF", 0>;
 defm "" : LMULReadAdvanceFW<"ReadVFWALUV", 0>;
 defm "" : LMULReadAdvanceFW<"ReadVFWALUF", 0>;
 defm "" : LMULReadAdvance<"ReadVFMulV", 0>;
 defm "" : LMULReadAdvance<"ReadVFMulF", 0>;
-defm "" : LMULSEWReadAdvance<"ReadVFDivV", 0>;
-defm "" : LMULSEWReadAdvance<"ReadVFDivF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFDivV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFDivF", 0>;
 defm "" : LMULReadAdvanceFW<"ReadVFWMulV", 0>;
 defm "" : LMULReadAdvanceFW<"ReadVFWMulF", 0>;
 defm "" : LMULReadAdvance<"ReadVFMulAddV", 0>;
 defm "" : LMULReadAdvance<"ReadVFMulAddF", 0>;
 defm "" : LMULReadAdvanceFW<"ReadVFWMulAddV", 0>;
 defm "" : LMULReadAdvanceFW<"ReadVFWMulAddF", 0>;
-defm "" : LMULSEWReadAdvance<"ReadVFSqrtV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFSqrtV", 0>;
 defm "" : LMULReadAdvance<"ReadVFRecpV", 0>;
 defm "" : LMULReadAdvance<"ReadVFCmpV", 0>;
 defm "" : LMULReadAdvance<"ReadVFCmpF", 0>;
 defm "" : LMULReadAdvance<"ReadVFSgnjV", 0>;
 defm "" : LMULReadAdvance<"ReadVFSgnjF", 0>;
 defm "" : LMULReadAdvance<"ReadVFClassV", 0>;
 defm "" : LMULReadAdvance<"ReadVFMergeV", 0>;
 defm "" : LMULReadAdvance<"ReadVFMergeF", 0>;