Summary: Teach the AArch64 backend patterns to generate the RAX1 instruction.

[dmgreen]

This looks like a good patch. It looks like the two operands for rax1 may be the wrong way around though.

[BK1603]

D147887: Summary: Teach the AArch64 backend patterns to generate the RAX1 instruction.

[BK1603]

@dmgreen

Fixed! Please review.

[dmgreen]

Thanks. LGTM

[BK1603]

Hi @dmgreen

I don't think I have commit access to the repo, so you might have to commit this patch as well. Thanks!

[dmgreen]

Can do. Do you have a "Name <[e-mail]>" I can use for attribution? Thanks

[BK1603]

HI @dmgreen

You can use
Shreyansh Chouhan <[e-mail]>

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxs, v2i64>;
 
 def : Pat<(v2i64 (int_aarch64_crypto_rax1 (v2i64 V128:$Vn), (v2i64 V128:$Vm))),
           (RAX1 (v2i64 V128:$Vn), (v2i64 V128:$Vm))>;
 
 def : Pat<(v2i64 (int_aarch64_crypto_xar (v2i64 V128:$Vn), (v2i64 V128:$Vm), (i64 timm0_63:$imm))),
           (XAR (v2i64 V128:$Vn), (v2i64 V128:$Vm), (timm0_63:$imm))>;
 
+def : Pat<(xor  (v2i64 V128:$Vn), (or (AArch64vlshr (v2i64 V128:$Vm), (i32 63)), (AArch64vshl (v2i64 V128:$Vm), (i32 1)))),
+          (RAX1 (v2i64 V128:$Vn), (v2i64 V128:$Vm))>;
 
 } // HasSHA3
 
 let Predicates = [HasSM4] in {
 def SM3TT1A   : CryptoRRRi2Tied<0b0, 0b00, "sm3tt1a">;
 def SM3TT1B   : CryptoRRRi2Tied<0b0, 0b01, "sm3tt1b">;
 def SM3TT2A   : CryptoRRRi2Tied<0b0, 0b10, "sm3tt2a">;
 def SM3TT2B   : CryptoRRRi2Tied<0b0, 0b11, "sm3tt2b">;

llvm/test/CodeGen/AArch64/rax1.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=aarch64-none-eabi -mattr=+sha3 < %s | FileCheck --check-prefix=SHA3 %s
+; RUN: llc -mtriple=aarch64-none-eabi -mattr=-sha3 < %s | FileCheck --check-prefix=NOSHA3 %s
+
+define <2 x i64> @rax1(<2 x i64> %x, <2 x i64> %y) {
+; SHA3-LABEL: rax1:
+; SHA3:       // %bb.0:
+; SHA3-NEXT:    rax1 v0.2d, v0.2d, v1.2d
+; SHA3-NEXT:    ret
+;
+; NOSHA3-LABEL: rax1:
+; NOSHA3:       // %bb.0:
+; NOSHA3-NEXT:    ushr v2.2d, v1.2d, #63
+; NOSHA3-NEXT:    shl v1.2d, v1.2d, #1
+; NOSHA3-NEXT:    orr v1.16b, v1.16b, v2.16b
+; NOSHA3-NEXT:    eor v0.16b, v0.16b, v1.16b
+; NOSHA3-NEXT:    ret
+    %a = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %y, <2 x i64> %y, <2 x i64> <i64 1, i64 1>)
+    %b = xor <2 x i64> %x, %a
+    ret <2 x i64> %b
+}
+
+declare <2 x i64> @llvm.fshl.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)