[llvm-exegesis][AArch64] Handle OPERAND_UNKNOWN

[kpdev42]

Summary

Patch allows running many instructions on arm64, including ALU, loads, stores, etc.

[kpdev42]

ping

[kpdev42]

ping
@courbet could you please take a look?

[courbet]

I wanted gchatelet@ to have a look at this, because he wrote the Instruction/Operand code. In particular, I'm wondering why we're not using the info on the actual Operand value rather than relying on the MCOperandInfo for the operand. Specifically, we do know that this is a register since we return true for isReg, so we could just bake this knowledge into getExplicitOperandInfo in a target-independant way.

That being said, I don't know how the AArch64 backend is design, but it feels weird that the target info for that opearnd is OPERAND_UNKNOWN if we know that it's a register.

[kpdev42]

In D147776#4286705, @courbet wrote:

I wanted gchatelet@ to have a look at this, because he wrote the Instruction/Operand code. In particular, I'm wondering why we're not using the info on the actual Operand value rather than relying on the MCOperandInfo for the operand. Specifically, we do know that this is a register since we return true for isReg, so we could just bake this knowledge into getExplicitOperandInfo in a target-independant way.

That being said, I don't know how the AArch64 backend is design, but it feels weird that the target info for that opearnd is OPERAND_UNKNOWN if we know that it's a register.

On aarch64 OPERAND_UNKNOWN can be register, shift, extend or noop. If it is register we simply pass it further for randomizeMCOperand to handle it accordingly. If it is immediate then we set it to noop for most ofvindtructions, except those excepting non zero shift value (MOVIv and friends). I am not familiar with other platforms so I'm not handling OPERAND_UNKNOWN for them at all (even when it is register). We have better randomization for aarch64 immediate, which can handle shift/extend which we plan to submit step by step if this one goes in.

llvm/test/tools/llvm-exegesis/AArch64/unknown-operand.s

+# RUN: llvm-exegesis --opcode-name=ADDSWrx --mcpu=cortex-a78 --mtriple=aarch64-linux-gnu \
+# RUN:               --mode=latency --benchmark-phase=prepare-snippet 2>&1 | FileCheck %s --check-prefix=REG
+
+# RUN: llvm-exegesis --opcode-name=LDRXroX --mcpu=cortex-a78 --mtriple=aarch64-linux-gnu \
+# RUN:               --mode=latency --benchmark-phase=prepare-snippet 2>&1 | FileCheck %s --check-prefix=IMM1
+
+# RUN: llvm-exegesis --opcode-name=MOVIv2s_msl --mcpu=cortex-a78 --mtriple=aarch64-linux-gnu \
+# RUN:               --mode=inverse_throughput --benchmark-phase=prepare-snippet 2>&1 | FileCheck %s --check-prefix=IMM2
+
+# RUN: llvm-exegesis --opcode-name=MOVIv4s_msl --mcpu=cortex-a78 --mtriple=aarch64-linux-gnu \
+# RUN:               --mode=inverse_throughput --benchmark-phase=prepare-snippet 2>&1 | FileCheck %s --check-prefix=IMM3
+
+# RUN: llvm-exegesis --opcode-name=MVNIv2s_msl --mcpu=cortex-a78 --mtriple=aarch64-linux-gnu \
+# RUN:               --mode=inverse_throughput --benchmark-phase=prepare-snippet 2>&1 | FileCheck %s --check-prefix=IMM4
+
+# RUN: llvm-exegesis --opcode-name=MVNIv4s_msl --mcpu=cortex-a78 --mtriple=aarch64-linux-gnu \
+# RUN:               --mode=inverse_throughput --benchmark-phase=prepare-snippet 2>&1 | FileCheck %s --check-prefix=IMM5
+
+# unknown operand is register
+# REG: instructions:
+# REG-NEXT: ADDSWrx
+
+# unknown operand is set to zero value immediate
+# IMM1: instructions:
+# IMM1-NEXT: LDRXroX
+
+# unknown operand is set to non-zero value immediate
+# IMM2: instructions:
+# IMM2-NEXT: MOVIv2s_msl
+
+# IMM3: instructions:
+# IMM3-NEXT: MOVIv4s_msl
+
+# IMM4: instructions:
+# IMM4-NEXT: MVNIv2s_msl
+
+# IMM5: instructions:
+# IMM5-NEXT: MVNIv4s_msl
+

llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp

private:
   bool matchesArch(Triple::ArchType Arch) const override {
     return Arch == Triple::aarch64 || Arch == Triple::aarch64_be;
   }
 
   void addTargetSpecificPasses(PassManagerBase &PM) const override {
     // Function return is a pseudo-instruction that needs to be expanded
     PM.add(createAArch64ExpandPseudoPass());
   }
+
+  int getUnknownOperandType(const Instruction &I,
+                            const Operand &Op) const override {
+    return Op.isReg() ? MCOI::OPERAND_REGISTER : MCOI::OPERAND_IMMEDIATE;
+  }
+
+  // Gets immediate based on instruction opcode
+  int64_t getImmediateForOperand(const Instruction &I,
+                                 const Operand &Op) const override {
+    switch (I.Description.getOpcode()) {
+    default:
+      return 0;
+    case AArch64::MOVIv2s_msl:
+    case AArch64::MOVIv4s_msl:
+    case AArch64::MVNIv2s_msl:
+    case AArch64::MVNIv4s_msl:
+      return 8;
+    }
+  }
 };
 
 } // namespace
 
 static ExegesisTarget *getTheExegesisAArch64Target() {
   static ExegesisAArch64Target Target;
   return &Target;
 }
 
 void InitializeAArch64ExegesisTarget() {
   ExegesisTarget::registerTarget(getTheExegesisAArch64Target());
 }
 
 } // namespace exegesis
 } // namespace llvm

llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp

void setRandomAliasing(const AliasingConfigurations &AliasingConfigurations,
   setRegisterOperandValue(randomElement(RandomConf.Uses), UseIB);
 }
 
 static Error randomizeMCOperand(const LLVMState &State,
                                 const Instruction &Instr, const Variable &Var,
                                 MCOperand &AssignedValue,
                                 const BitVector &ForbiddenRegs) {
   const Operand &Op = Instr.getPrimaryOperand(Var);
+  auto &ET = State.getExegesisTarget();
   if (Op.getExplicitOperandInfo().OperandType >=
       MCOI::OperandType::OPERAND_FIRST_TARGET)
-    return State.getExegesisTarget().randomizeTargetMCOperand(
-        Instr, Var, AssignedValue, ForbiddenRegs);
-  switch (Op.getExplicitOperandInfo().OperandType) {
-  case MCOI::OperandType::OPERAND_IMMEDIATE:
-    // FIXME: explore immediate values too.
-    AssignedValue = MCOperand::createImm(1);
+    return ET.randomizeTargetMCOperand(Instr, Var, AssignedValue,
+                                       ForbiddenRegs);
+  int64_t OpType = Op.getExplicitOperandInfo().OperandType, ImmVal = 1;
+  if (OpType == MCOI::OperandType::OPERAND_UNKNOWN)
+    if ((OpType = ET.getUnknownOperandType(Instr, Op)) ==
+        MCOI::OperandType::OPERAND_IMMEDIATE)
+      ImmVal = ET.getImmediateForOperand(Instr, Op);
+
+  switch (OpType) {
+  case MCOI::OperandType::OPERAND_IMMEDIATE:
+    AssignedValue = MCOperand::createImm(ImmVal);
     break;
   case MCOI::OperandType::OPERAND_REGISTER: {
     assert(Op.isReg());
     auto AllowedRegs = Op.getRegisterAliasing().sourceBits();
     assert(AllowedRegs.size() == ForbiddenRegs.size());
     for (auto I : ForbiddenRegs.set_bits())
       AllowedRegs.reset(I);
     if (!AllowedRegs.any())

llvm/tools/llvm-exegesis/lib/Target.h

 
 namespace llvm {
 namespace exegesis {
 
 extern cl::OptionCategory Options;
 extern cl::OptionCategory BenchmarkOptions;
 extern cl::OptionCategory AnalysisOptions;
 
+struct Operand;
+
 struct PfmCountersInfo {
   // An optional name of a performance counter that can be used to measure
   // cycles.
   const char *CycleCounter;
 
   // An optional name of a performance counter that can be used to measure
   // uops.
   const char *UopsCounter;
virtual void fillMemoryOperands(InstructionTemplate &IT, unsigned Reg,
                                   unsigned Offset) const {
     llvm_unreachable(
         "fillMemoryOperands() requires getScratchMemoryRegister() > 0");
   }
 
   // Returns a counter usable as a loop counter.
   virtual unsigned getLoopCounterRegister(const Triple &) const { return 0; }
 
+  // Gets the real operand type for OPERAND_UNKNOWN
+  virtual int getUnknownOperandType(const Instruction &I,
+                                    const Operand &Op) const {
+    return MCOI::OperandType::OPERAND_UNKNOWN;
+  }
+
+  // Gets immediate value
+  virtual int64_t getImmediateForOperand(const Instruction &I,
+                                         const Operand &Op) const {
+    return 0;
+  }
+
   // Adds the code to decrement the loop counter and
   virtual void decrementLoopCounterAndJump(MachineBasicBlock &MBB,
                                            MachineBasicBlock &TargetMBB,
                                            const MCInstrInfo &MII) const {
     llvm_unreachable("decrementLoopCounterAndBranch() requires "
                      "getLoopCounterRegister() > 0");
   }
 
public:
   // and returns and RAII object that restores the state on destruction.
   // By default no state is preserved.
   struct SavedState {
     virtual ~SavedState();
   };
   virtual std::unique_ptr<SavedState> withSavedState() const {
     return std::make_unique<SavedState>();
   }
-
 private:
   virtual bool matchesArch(Triple::ArchType Arch) const = 0;
 
   // Targets can implement their own snippet generators/benchmarks runners by
   // implementing these.
   std::unique_ptr<SnippetGenerator> virtual createSerialSnippetGenerator(
       const LLVMState &State, const SnippetGenerator::Options &Opts) const;
   std::unique_ptr<SnippetGenerator> virtual createParallelSnippetGenerator(