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Differential D147255

[InstCombine][OpaquePtr] Do not try to match store type to value type for opaque stores
AbandonedPublic

Authored by jrbyrnes on Mar 30 2023, 12:05 PM.

Details

Reviewers
nikic
arsenm
Summary

Based on https://github.com/llvm/llvm-project/commit/816d26fe5eeae4adcb0ceda05884747e15f55bb2, it seems the original intent of combineStoreToValueType is to avoid unnecessary bitcasts required to match ptr types of stores. Opaque pointers solves this issue, thus we should not perform this optimization on opaque stores. This optimization currently causes an issue since MergedLoadStoreMotion and SimplifyCFG optimizations are based on finding corresponding ops in different branches -- if the type of stores are conflicting, the optimizations will miss. We should probably not require type matching on memory ops in these passes, but we should first remove typed ptr handling where it is not needed.

Diff Detail

Event Timeline

jrbyrnes created this revision.Mar 30 2023, 12:05 PM
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Harbormaster completed remote builds in B222813: Diff 509767.Mar 30 2023, 12:06 PM
jrbyrnes added a parent revision: D147254: Precommit autogen tests.Mar 30 2023, 12:06 PM
jrbyrnes added reviewers: nikic, arsenm.Mar 30 2023, 12:09 PM
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nikic requested changes to this revision.Mar 30 2023, 12:35 PM

I don't think your characterization here is correct. The point of the transform is to remove the bitcast of the stored value. With typed pointers, this shifted the bitcast from the stored value to the pointer. With opaque pointers, it removes the bitcast entirely. As such, I don't really understand the argument for why we should stop making this transform with opaque pointers. If you look through the test diffs, this patch is causing many optimization regressions.

Besides, even for your motivating case, this is only going to shift the problem in the different direction: What if you had a bitcasted i16 store and a half store to start with, and this transform made sure the types are the same? It's trading one case for another.

We should probably not require type matching on memory ops in these passes

This would be the correct way to address this.

This revision now requires changes to proceed.Mar 30 2023, 12:35 PM
jrbyrnes abandoned this revision.Mar 30 2023, 12:53 PM

@nikic -- thanks for your thoughts on this. Since you disagree with my characterization of the function, and that was the basis of this patch, I'll abandon in favor of a patch addressing from the opposite direction (e.g. MLSM).

Revision Contents

PathSize
llvm/
lib/
Transforms/
InstCombine/
5 lines
test/
CodeGen/
AMDGPU/
12 lines
DebugInfo/
Generic/
assignment-tracking/
instcombine/
5 lines
Transforms/
InstCombine/
3 lines
3 lines
55 lines
2 lines
36 lines
6 lines
6 lines
5 lines
9 lines
15 lines
6 lines
3 lines
PhaseOrdering/
18 lines

Diff 509767

llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp

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/// However, it is risky in case some backend or other part of LLVM is relying /// However, it is risky in case some backend or other part of LLVM is relying
/// on the exact type stored to select appropriate atomic operations. /// on the exact type stored to select appropriate atomic operations.
/// ///
/// \returns true if the store was successfully combined away. This indicates /// \returns true if the store was successfully combined away. This indicates
/// the caller must erase the store instruction. We have to let the caller erase /// the caller must erase the store instruction. We have to let the caller erase
/// the store instruction as otherwise there is no way to signal whether it was /// the store instruction as otherwise there is no way to signal whether it was
/// combined or not: IC.EraseInstFromFunction returns a null pointer. /// combined or not: IC.EraseInstFromFunction returns a null pointer.
static bool combineStoreToValueType(InstCombinerImpl &IC, StoreInst &SI) { static bool combineStoreToValueType(InstCombinerImpl &IC, StoreInst &SI) {
// Opaque stores do not have pointer types by definition, so there is no
// need to match stores to the type of the value being stored. Any bitcasts
// present serve some other purpose.
if (SI.getPointerOperandType()->isOpaquePointerTy())
return false;
// FIXME: We could probably with some care handle both volatile and ordered // FIXME: We could probably with some care handle both volatile and ordered
// atomic stores here but it isn't clear that this is important. // atomic stores here but it isn't clear that this is important.
if (!SI.isUnordered()) if (!SI.isUnordered())
return false; return false;
// swifterror values can't be bitcasted. // swifterror values can't be bitcasted.
if (SI.getPointerOperand()->isSwiftError()) if (SI.getPointerOperand()->isSwiftError())
return false; return false;
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llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll

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; GCN-PRELINK-NEXT: [[__FABS:%.*]] = tail call fast float @_Z4fabsf(float [[TMPVARVAR]]) ; GCN-PRELINK-NEXT: [[__FABS:%.*]] = tail call fast float @_Z4fabsf(float [[TMPVARVAR]])
; GCN-PRELINK-NEXT: [[__LOG2:%.*]] = tail call fast float @_Z4log2f(float [[__FABS]]) ; GCN-PRELINK-NEXT: [[__LOG2:%.*]] = tail call fast float @_Z4log2f(float [[__FABS]])
; GCN-PRELINK-NEXT: [[__YLOGX:%.*]] = fmul fast float [[__LOG2]], 1.013000e+03 ; GCN-PRELINK-NEXT: [[__YLOGX:%.*]] = fmul fast float [[__LOG2]], 1.013000e+03
; GCN-PRELINK-NEXT: [[__EXP2:%.*]] = tail call fast float @_Z4exp2f(float [[__YLOGX]]) ; GCN-PRELINK-NEXT: [[__EXP2:%.*]] = tail call fast float @_Z4exp2f(float [[__YLOGX]])
; GCN-PRELINK-NEXT: [[TMP0:%.*]] = bitcast float [[TMPVARVAR]] to i32 ; GCN-PRELINK-NEXT: [[TMP0:%.*]] = bitcast float [[TMPVARVAR]] to i32
; GCN-PRELINK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[TMP0]], -2147483648 ; GCN-PRELINK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[TMP0]], -2147483648
; GCN-PRELINK-NEXT: [[TMP1:%.*]] = bitcast float [[__EXP2]] to i32 ; GCN-PRELINK-NEXT: [[TMP1:%.*]] = bitcast float [[__EXP2]] to i32
; GCN-PRELINK-NEXT: [[TMP2:%.*]] = or i32 [[__POW_SIGN]], [[TMP1]] ; GCN-PRELINK-NEXT: [[TMP2:%.*]] = or i32 [[__POW_SIGN]], [[TMP1]]
; GCN-PRELINK-NEXT: store i32 [[TMP2]], ptr addrspace(1) [[A]], align 4 ; GCN-PRELINK-NEXT: [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float
; GCN-PRELINK-NEXT: store float [[TMP3]], ptr addrspace(1) [[A]], align 4
; GCN-PRELINK-NEXT: ret void ; GCN-PRELINK-NEXT: ret void
; ;
; GCN-NATIVE-LABEL: define amdgpu_kernel void @test_pow ; GCN-NATIVE-LABEL: define amdgpu_kernel void @test_pow
; GCN-NATIVE-SAME: (ptr addrspace(1) nocapture [[A:%.*]]) local_unnamed_addr { ; GCN-NATIVE-SAME: (ptr addrspace(1) nocapture [[A:%.*]]) local_unnamed_addr {
; GCN-NATIVE-NEXT: entry: ; GCN-NATIVE-NEXT: entry:
; GCN-NATIVE-NEXT: [[TMPVARVAR:%.*]] = load float, ptr addrspace(1) [[A]], align 4 ; GCN-NATIVE-NEXT: [[TMPVARVAR:%.*]] = load float, ptr addrspace(1) [[A]], align 4
; GCN-NATIVE-NEXT: [[__FABS:%.*]] = tail call fast float @_Z4fabsf(float [[TMPVARVAR]]) ; GCN-NATIVE-NEXT: [[__FABS:%.*]] = tail call fast float @_Z4fabsf(float [[TMPVARVAR]])
; GCN-NATIVE-NEXT: [[__LOG2:%.*]] = tail call fast float @_Z4log2f(float [[__FABS]]) ; GCN-NATIVE-NEXT: [[__LOG2:%.*]] = tail call fast float @_Z4log2f(float [[__FABS]])
; GCN-NATIVE-NEXT: [[__YLOGX:%.*]] = fmul fast float [[__LOG2]], 1.013000e+03 ; GCN-NATIVE-NEXT: [[__YLOGX:%.*]] = fmul fast float [[__LOG2]], 1.013000e+03
; GCN-NATIVE-NEXT: [[__EXP2:%.*]] = tail call fast float @_Z4exp2f(float [[__YLOGX]]) ; GCN-NATIVE-NEXT: [[__EXP2:%.*]] = tail call fast float @_Z4exp2f(float [[__YLOGX]])
; GCN-NATIVE-NEXT: [[TMP0:%.*]] = bitcast float [[TMPVARVAR]] to i32 ; GCN-NATIVE-NEXT: [[TMP0:%.*]] = bitcast float [[TMPVARVAR]] to i32
; GCN-NATIVE-NEXT: [[__POW_SIGN:%.*]] = and i32 [[TMP0]], -2147483648 ; GCN-NATIVE-NEXT: [[__POW_SIGN:%.*]] = and i32 [[TMP0]], -2147483648
; GCN-NATIVE-NEXT: [[TMP1:%.*]] = bitcast float [[__EXP2]] to i32 ; GCN-NATIVE-NEXT: [[TMP1:%.*]] = bitcast float [[__EXP2]] to i32
; GCN-NATIVE-NEXT: [[TMP2:%.*]] = or i32 [[__POW_SIGN]], [[TMP1]] ; GCN-NATIVE-NEXT: [[TMP2:%.*]] = or i32 [[__POW_SIGN]], [[TMP1]]
; GCN-NATIVE-NEXT: store i32 [[TMP2]], ptr addrspace(1) [[A]], align 4 ; GCN-NATIVE-NEXT: [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float
; GCN-NATIVE-NEXT: store float [[TMP3]], ptr addrspace(1) [[A]], align 4
; GCN-NATIVE-NEXT: ret void ; GCN-NATIVE-NEXT: ret void
; ;
entry: entry:
%tmpvarvar = load float, ptr addrspace(1) %a, align 4 %tmpvarvar = load float, ptr addrspace(1) %a, align 4
%call = call fast float @_Z3powff(float %tmpvarvar, float 1.013000e+03) %call = call fast float @_Z3powff(float %tmpvarvar, float 1.013000e+03)
store float %call, ptr addrspace(1) %a, align 4 store float %call, ptr addrspace(1) %a, align 4
ret void ret void
} }
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; GCN-PRELINK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[CONV]] to float ; GCN-PRELINK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[CONV]] to float
; GCN-PRELINK-NEXT: [[__YLOGX:%.*]] = fmul fast float [[__LOG2]], [[POWNI2F]] ; GCN-PRELINK-NEXT: [[__YLOGX:%.*]] = fmul fast float [[__LOG2]], [[POWNI2F]]
; GCN-PRELINK-NEXT: [[__EXP2:%.*]] = tail call fast float @_Z4exp2f(float [[__YLOGX]]) ; GCN-PRELINK-NEXT: [[__EXP2:%.*]] = tail call fast float @_Z4exp2f(float [[__YLOGX]])
; GCN-PRELINK-NEXT: [[__YEVEN:%.*]] = shl i32 [[CONV]], 31 ; GCN-PRELINK-NEXT: [[__YEVEN:%.*]] = shl i32 [[CONV]], 31
; GCN-PRELINK-NEXT: [[TMP0:%.*]] = bitcast float [[TMPVARVAR]] to i32 ; GCN-PRELINK-NEXT: [[TMP0:%.*]] = bitcast float [[TMPVARVAR]] to i32
; GCN-PRELINK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP0]] ; GCN-PRELINK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP0]]
; GCN-PRELINK-NEXT: [[TMP1:%.*]] = bitcast float [[__EXP2]] to i32 ; GCN-PRELINK-NEXT: [[TMP1:%.*]] = bitcast float [[__EXP2]] to i32
; GCN-PRELINK-NEXT: [[TMP2:%.*]] = or i32 [[__POW_SIGN]], [[TMP1]] ; GCN-PRELINK-NEXT: [[TMP2:%.*]] = or i32 [[__POW_SIGN]], [[TMP1]]
; GCN-PRELINK-NEXT: store i32 [[TMP2]], ptr addrspace(1) [[A]], align 4 ; GCN-PRELINK-NEXT: [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float
; GCN-PRELINK-NEXT: store float [[TMP3]], ptr addrspace(1) [[A]], align 4
; GCN-PRELINK-NEXT: ret void ; GCN-PRELINK-NEXT: ret void
; ;
; GCN-NATIVE-LABEL: define amdgpu_kernel void @test_pown ; GCN-NATIVE-LABEL: define amdgpu_kernel void @test_pown
; GCN-NATIVE-SAME: (ptr addrspace(1) nocapture [[A:%.*]]) local_unnamed_addr { ; GCN-NATIVE-SAME: (ptr addrspace(1) nocapture [[A:%.*]]) local_unnamed_addr {
; GCN-NATIVE-NEXT: entry: ; GCN-NATIVE-NEXT: entry:
; GCN-NATIVE-NEXT: [[TMPVARVAR:%.*]] = load float, ptr addrspace(1) [[A]], align 4 ; GCN-NATIVE-NEXT: [[TMPVARVAR:%.*]] = load float, ptr addrspace(1) [[A]], align 4
; GCN-NATIVE-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[A]], i64 1 ; GCN-NATIVE-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[A]], i64 1
; GCN-NATIVE-NEXT: [[TMPVARVAR1:%.*]] = load float, ptr addrspace(1) [[ARRAYIDX1]], align 4 ; GCN-NATIVE-NEXT: [[TMPVARVAR1:%.*]] = load float, ptr addrspace(1) [[ARRAYIDX1]], align 4
; GCN-NATIVE-NEXT: [[CONV:%.*]] = fptosi float [[TMPVARVAR1]] to i32 ; GCN-NATIVE-NEXT: [[CONV:%.*]] = fptosi float [[TMPVARVAR1]] to i32
; GCN-NATIVE-NEXT: [[__FABS:%.*]] = tail call fast float @_Z4fabsf(float [[TMPVARVAR]]) ; GCN-NATIVE-NEXT: [[__FABS:%.*]] = tail call fast float @_Z4fabsf(float [[TMPVARVAR]])
; GCN-NATIVE-NEXT: [[__LOG2:%.*]] = tail call fast float @_Z4log2f(float [[__FABS]]) ; GCN-NATIVE-NEXT: [[__LOG2:%.*]] = tail call fast float @_Z4log2f(float [[__FABS]])
; GCN-NATIVE-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[CONV]] to float ; GCN-NATIVE-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[CONV]] to float
; GCN-NATIVE-NEXT: [[__YLOGX:%.*]] = fmul fast float [[__LOG2]], [[POWNI2F]] ; GCN-NATIVE-NEXT: [[__YLOGX:%.*]] = fmul fast float [[__LOG2]], [[POWNI2F]]
; GCN-NATIVE-NEXT: [[__EXP2:%.*]] = tail call fast float @_Z4exp2f(float [[__YLOGX]]) ; GCN-NATIVE-NEXT: [[__EXP2:%.*]] = tail call fast float @_Z4exp2f(float [[__YLOGX]])
; GCN-NATIVE-NEXT: [[__YEVEN:%.*]] = shl i32 [[CONV]], 31 ; GCN-NATIVE-NEXT: [[__YEVEN:%.*]] = shl i32 [[CONV]], 31
; GCN-NATIVE-NEXT: [[TMP0:%.*]] = bitcast float [[TMPVARVAR]] to i32 ; GCN-NATIVE-NEXT: [[TMP0:%.*]] = bitcast float [[TMPVARVAR]] to i32
; GCN-NATIVE-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP0]] ; GCN-NATIVE-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP0]]
; GCN-NATIVE-NEXT: [[TMP1:%.*]] = bitcast float [[__EXP2]] to i32 ; GCN-NATIVE-NEXT: [[TMP1:%.*]] = bitcast float [[__EXP2]] to i32
; GCN-NATIVE-NEXT: [[TMP2:%.*]] = or i32 [[__POW_SIGN]], [[TMP1]] ; GCN-NATIVE-NEXT: [[TMP2:%.*]] = or i32 [[__POW_SIGN]], [[TMP1]]
; GCN-NATIVE-NEXT: store i32 [[TMP2]], ptr addrspace(1) [[A]], align 4 ; GCN-NATIVE-NEXT: [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float
; GCN-NATIVE-NEXT: store float [[TMP3]], ptr addrspace(1) [[A]], align 4
; GCN-NATIVE-NEXT: ret void ; GCN-NATIVE-NEXT: ret void
; ;
entry: entry:
%tmpvarvar = load float, ptr addrspace(1) %a, align 4 %tmpvarvar = load float, ptr addrspace(1) %a, align 4
%arrayidx1 = getelementptr inbounds float, ptr addrspace(1) %a, i64 1 %arrayidx1 = getelementptr inbounds float, ptr addrspace(1) %a, i64 1
%tmpvarvar1 = load float, ptr addrspace(1) %arrayidx1, align 4 %tmpvarvar1 = load float, ptr addrspace(1) %arrayidx1, align 4
%conv = fptosi float %tmpvarvar1 to i32 %conv = fptosi float %tmpvarvar1 to i32
%call = call fast float @_Z4pownfi(float %tmpvarvar, i32 %conv) %call = call fast float @_Z4pownfi(float %tmpvarvar, i32 %conv)
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llvm/test/DebugInfo/Generic/assignment-tracking/instcombine/store-new-type.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt %s -passes=instcombine -S | FileCheck %s ; RUN: opt %s -passes=instcombine -S | FileCheck %s
;; Based on test/Transforms/InstCombine/shufflevec-bitcast.ll in which the ;; Based on test/Transforms/InstCombine/shufflevec-bitcast.ll in which the
;; store of <4 x i4> is replaced with a store of type <2 x i8>. Debug info ;; store of <4 x i4> is replaced with a store of type <2 x i8>. Debug info
;; added by hand. Check the DIAssignID attachment on the store is preserved. ;; added by hand. Check the DIAssignID attachment on the store is preserved.
define <2 x i4> @shuf_bitcast_insert_use2(<2 x i8> %v, i8 %x, ptr %p) { define <2 x i4> @shuf_bitcast_insert_use2(<2 x i8> %v, i8 %x, ptr %p) {
; CHECK-LABEL: define <2 x i4> @shuf_bitcast_insert_use2 ; CHECK-LABEL: define <2 x i4> @shuf_bitcast_insert_use2
; CHECK-SAME: (<2 x i8> [[V:%.*]], i8 [[X:%.*]], ptr [[P:%.*]]) { ; CHECK-SAME: (<2 x i8> [[V:%.*]], i8 [[X:%.*]], ptr [[P:%.*]]) {
; CHECK-NEXT: [[I:%.*]] = insertelement <2 x i8> [[V]], i8 [[X]], i64 0 ; CHECK-NEXT: [[I:%.*]] = insertelement <2 x i8> [[V]], i8 [[X]], i64 0
; CHECK-NEXT: store <2 x i8> [[I]], ptr [[P]], align 2, !DIAssignID [[DIASSIGNID6:![0-9]+]] ; CHECK-NEXT: [[B:%.*]] = bitcast <2 x i8> [[I]] to <4 x i4>
; CHECK-NEXT: call void @llvm.dbg.assign(metadata <2 x i8> [[I]], metadata [[META7:![0-9]+]], metadata !DIExpression(), metadata [[DIASSIGNID6]], metadata ptr [[P]], metadata !DIExpression()), !dbg [[DBG19:![0-9]+]] ; CHECK-NEXT: store <4 x i4> [[B]], ptr [[P]], align 2, !DIAssignID [[DIASSIGNID6:![0-9]+]]
; CHECK-NEXT: call void @llvm.dbg.assign(metadata <4 x i4> [[B]], metadata [[META7:![0-9]+]], metadata !DIExpression(), metadata [[DIASSIGNID6]], metadata ptr [[P]], metadata !DIExpression()), !dbg [[DBG19:![0-9]+]]
; CHECK-NEXT: [[R:%.*]] = bitcast i8 [[X]] to <2 x i4> ; CHECK-NEXT: [[R:%.*]] = bitcast i8 [[X]] to <2 x i4>
; CHECK-NEXT: ret <2 x i4> [[R]] ; CHECK-NEXT: ret <2 x i4> [[R]]
; ;
%i = insertelement <2 x i8> %v, i8 %x, i32 0 %i = insertelement <2 x i8> %v, i8 %x, i32 0
%b = bitcast <2 x i8> %i to <4 x i4> %b = bitcast <2 x i8> %i to <4 x i4>
store <4 x i4> %b, ptr %p, !DIAssignID !37 store <4 x i4> %b, ptr %p, !DIAssignID !37
call void @llvm.dbg.assign(metadata <4 x i4> %b, metadata !28, metadata !DIExpression(), metadata !37, metadata ptr %p, metadata !DIExpression()), !dbg !26 call void @llvm.dbg.assign(metadata <4 x i4> %b, metadata !28, metadata !DIExpression(), metadata !37, metadata ptr %p, metadata !DIExpression()), !dbg !26
%r = shufflevector <4 x i4> %b, <4 x i4> undef, <2 x i32> <i32 0, i32 1> %r = shufflevector <4 x i4> %b, <4 x i4> undef, <2 x i32> <i32 0, i32 1>
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llvm/test/Transforms/InstCombine/2012-6-7-vselect-bitcast.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -passes=instcombine < %s | FileCheck %s ; RUN: opt -S -passes=instcombine < %s | FileCheck %s
define void @foo(<16 x i8> %a, <16 x i8> %b, ptr %c) { define void @foo(<16 x i8> %a, <16 x i8> %b, ptr %c) {
; CHECK-LABEL: @foo( ; CHECK-LABEL: @foo(
; CHECK-NEXT: store <16 x i8> [[B:%.*]], ptr [[C:%.*]], align 4 ; CHECK-NEXT: [[BB:%.*]] = bitcast <16 x i8> [[B:%.*]] to <4 x i32>
; CHECK-NEXT: store <4 x i32> [[BB]], ptr [[C:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%aa = bitcast <16 x i8> %a to <4 x i32> %aa = bitcast <16 x i8> %a to <4 x i32>
%bb = bitcast <16 x i8> %b to <4 x i32> %bb = bitcast <16 x i8> %b to <4 x i32>
%select_v = select <4 x i1> zeroinitializer, <4 x i32> %aa, <4 x i32> %bb %select_v = select <4 x i1> zeroinitializer, <4 x i32> %aa, <4 x i32> %bb
store <4 x i32> %select_v, ptr %c, align 4 store <4 x i32> %select_v, ptr %c, align 4
ret void ret void
} }

llvm/test/Transforms/InstCombine/bitcast-phi-uselistorder.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -passes=instcombine < %s | FileCheck %s ; RUN: opt -S -passes=instcombine < %s | FileCheck %s
@Q = internal unnamed_addr global double 1.000000e+00, align 8 @Q = internal unnamed_addr global double 1.000000e+00, align 8
define double @test(i1 %c, ptr %p) { define double @test(i1 %c, ptr %p) {
; CHECK-LABEL: @test( ; CHECK-LABEL: @test(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[C:%.*]], label [[IF:%.*]], label [[END:%.*]] ; CHECK-NEXT: br i1 [[C:%.*]], label [[IF:%.*]], label [[END:%.*]]
; CHECK: if: ; CHECK: if:
; CHECK-NEXT: [[LOAD1:%.*]] = load double, ptr @Q, align 8 ; CHECK-NEXT: [[LOAD1:%.*]] = load double, ptr @Q, align 8
; CHECK-NEXT: br label [[END]] ; CHECK-NEXT: br label [[END]]
; CHECK: end: ; CHECK: end:
; CHECK-NEXT: [[TMP0:%.*]] = phi double [ 0.000000e+00, [[ENTRY:%.*]] ], [ [[LOAD1]], [[IF]] ] ; CHECK-NEXT: [[TMP0:%.*]] = phi double [ 0.000000e+00, [[ENTRY:%.*]] ], [ [[LOAD1]], [[IF]] ]
; CHECK-NEXT: store double [[TMP0]], ptr [[P:%.*]], align 8 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast double [[TMP0]] to i64
; CHECK-NEXT: store i64 [[TMP1]], ptr [[P:%.*]], align 8
; CHECK-NEXT: ret double [[TMP0]] ; CHECK-NEXT: ret double [[TMP0]]
; ;
entry: entry:
br i1 %c, label %if, label %end br i1 %c, label %if, label %end
if: if:
%load = load i64, ptr @Q, align 8 %load = load i64, ptr @Q, align 8
br label %end br label %end
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llvm/test/Transforms/InstCombine/cast_phi.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=instcombine -S | FileCheck %s ; RUN: opt < %s -passes=instcombine -S | FileCheck %s
target datalayout = "n32:64" target datalayout = "n32:64"
define void @MainKernel(i32 %iNumSteps, i32 %tid, i32 %base) { define void @MainKernel(i32 %iNumSteps, i32 %tid, i32 %base) {
; CHECK-LABEL: @MainKernel( ; CHECK-LABEL: @MainKernel(
; CHECK-NEXT: [[CALLA:%.*]] = alloca [258 x float], align 4 ; CHECK-NEXT: [[CALLA:%.*]] = alloca [258 x float], align 4
; CHECK-NEXT: [[CALLB:%.*]] = alloca [258 x float], align 4 ; CHECK-NEXT: [[CALLB:%.*]] = alloca [258 x float], align 4
; CHECK-NEXT: [[CONV_I:%.*]] = uitofp i32 [[INUMSTEPS:%.*]] to float ; CHECK-NEXT: [[CONV_I:%.*]] = uitofp i32 [[INUMSTEPS:%.*]] to float
; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[CONV_I]] to i32
; CHECK-NEXT: [[CONV_I12:%.*]] = zext i32 [[TID:%.*]] to i64 ; CHECK-NEXT: [[CONV_I12:%.*]] = zext i32 [[TID:%.*]] to i64
; CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [258 x float], ptr [[CALLA]], i64 0, i64 [[CONV_I12]] ; CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [258 x float], ptr [[CALLA]], i64 0, i64 [[CONV_I12]]
; CHECK-NEXT: store float [[CONV_I]], ptr [[ARRAYIDX3]], align 4 ; CHECK-NEXT: store i32 [[TMP1]], ptr [[ARRAYIDX3]], align 4
; CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [258 x float], ptr [[CALLB]], i64 0, i64 [[CONV_I12]] ; CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [258 x float], ptr [[CALLB]], i64 0, i64 [[CONV_I12]]
; CHECK-NEXT: store float [[CONV_I]], ptr [[ARRAYIDX6]], align 4 ; CHECK-NEXT: store i32 [[TMP1]], ptr [[ARRAYIDX6]], align 4
; CHECK-NEXT: [[CMP7:%.*]] = icmp eq i32 [[TID]], 0 ; CHECK-NEXT: [[CMP7:%.*]] = icmp eq i32 [[TID]], 0
; CHECK-NEXT: br i1 [[CMP7]], label [[DOTBB1:%.*]], label [[DOTBB2:%.*]] ; CHECK-NEXT: br i1 [[CMP7]], label [[DOTBB1:%.*]], label [[DOTBB2:%.*]]
; CHECK: .bb1: ; CHECK: .bb1:
; CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [258 x float], ptr [[CALLA]], i64 0, i64 256 ; CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [258 x float], ptr [[CALLA]], i64 0, i64 256
; CHECK-NEXT: store float [[CONV_I]], ptr [[ARRAYIDX10]], align 4 ; CHECK-NEXT: store float [[CONV_I]], ptr [[ARRAYIDX10]], align 4
; CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [258 x float], ptr [[CALLB]], i64 0, i64 256 ; CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [258 x float], ptr [[CALLB]], i64 0, i64 256
; CHECK-NEXT: store float 0.000000e+00, ptr [[ARRAYIDX11]], align 4 ; CHECK-NEXT: store float 0.000000e+00, ptr [[ARRAYIDX11]], align 4
; CHECK-NEXT: br label [[DOTBB2]] ; CHECK-NEXT: br label [[DOTBB2]]
; CHECK: .bb2: ; CHECK: .bb2:
; CHECK-NEXT: [[CMP135:%.*]] = icmp sgt i32 [[INUMSTEPS]], 0 ; CHECK-NEXT: [[CMP135:%.*]] = icmp sgt i32 [[INUMSTEPS]], 0
; CHECK-NEXT: br i1 [[CMP135]], label [[DOTBB3:%.*]], label [[DOTBB8:%.*]] ; CHECK-NEXT: br i1 [[CMP135]], label [[DOTBB3:%.*]], label [[DOTBB8:%.*]]
; CHECK: .bb3: ; CHECK: .bb3:
; CHECK-NEXT: [[TMP1:%.*]] = phi float [ [[TMP10:%.*]], [[DOTBB12:%.*]] ], [ [[CONV_I]], [[DOTBB2]] ] ; CHECK-NEXT: [[TMP2:%.*]] = phi float [ [[TMP13:%.*]], [[DOTBB12:%.*]] ], [ [[CONV_I]], [[DOTBB2]] ]
; CHECK-NEXT: [[TMP2:%.*]] = phi float [ [[TMP11:%.*]], [[DOTBB12]] ], [ [[CONV_I]], [[DOTBB2]] ] ; CHECK-NEXT: [[TMP3:%.*]] = phi float [ [[TMP14:%.*]], [[DOTBB12]] ], [ [[CONV_I]], [[DOTBB2]] ]
; CHECK-NEXT: [[I12_06:%.*]] = phi i32 [ [[SUB:%.*]], [[DOTBB12]] ], [ [[INUMSTEPS]], [[DOTBB2]] ] ; CHECK-NEXT: [[I12_06:%.*]] = phi i32 [ [[SUB:%.*]], [[DOTBB12]] ], [ [[INUMSTEPS]], [[DOTBB2]] ]
; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i32 [[I12_06]], [[BASE:%.*]] ; CHECK-NEXT: [[TMP4:%.*]] = icmp ugt i32 [[I12_06]], [[BASE:%.*]]
; CHECK-NEXT: [[ADD:%.*]] = add i32 [[I12_06]], 1 ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[I12_06]], 1
; CHECK-NEXT: [[CONV_I9:%.*]] = sext i32 [[ADD]] to i64 ; CHECK-NEXT: [[CONV_I9:%.*]] = sext i32 [[ADD]] to i64
; CHECK-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [258 x float], ptr [[CALLA]], i64 0, i64 [[CONV_I9]] ; CHECK-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [258 x float], ptr [[CALLA]], i64 0, i64 [[CONV_I9]]
; CHECK-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [258 x float], ptr [[CALLB]], i64 0, i64 [[CONV_I9]] ; CHECK-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [258 x float], ptr [[CALLB]], i64 0, i64 [[CONV_I9]]
; CHECK-NEXT: [[CMP40:%.*]] = icmp ult i32 [[I12_06]], [[BASE]] ; CHECK-NEXT: [[CMP40:%.*]] = icmp ult i32 [[I12_06]], [[BASE]]
; CHECK-NEXT: br i1 [[TMP3]], label [[DOTBB4:%.*]], label [[DOTBB5:%.*]] ; CHECK-NEXT: br i1 [[TMP4]], label [[DOTBB4:%.*]], label [[DOTBB5:%.*]]
; CHECK: .bb4: ; CHECK: .bb4:
; CHECK-NEXT: [[TMP4:%.*]] = load float, ptr [[ARRAYIDX20]], align 4 ; CHECK-NEXT: [[TMP5:%.*]] = load float, ptr [[ARRAYIDX20]], align 4
; CHECK-NEXT: [[TMP5:%.*]] = load float, ptr [[ARRAYIDX24]], align 4 ; CHECK-NEXT: [[TMP6:%.*]] = load float, ptr [[ARRAYIDX24]], align 4
; CHECK-NEXT: [[ADD33:%.*]] = fadd float [[TMP5]], [[TMP4]] ; CHECK-NEXT: [[ADD33:%.*]] = fadd float [[TMP6]], [[TMP5]]
; CHECK-NEXT: [[ADD33_1:%.*]] = fadd float [[ADD33]], [[TMP1]] ; CHECK-NEXT: [[ADD33_1:%.*]] = fadd float [[ADD33]], [[TMP2]]
; CHECK-NEXT: [[ADD33_2:%.*]] = fadd float [[ADD33_1]], [[TMP2]] ; CHECK-NEXT: [[ADD33_2:%.*]] = fadd float [[ADD33_1]], [[TMP3]]
; CHECK-NEXT: br label [[DOTBB5]] ; CHECK-NEXT: br label [[DOTBB5]]
; CHECK: .bb5: ; CHECK: .bb5:
; CHECK-NEXT: [[TMP6:%.*]] = phi float [ [[ADD33_1]], [[DOTBB4]] ], [ [[TMP1]], [[DOTBB3]] ] ; CHECK-NEXT: [[TMP7:%.*]] = phi float [ [[ADD33_1]], [[DOTBB4]] ], [ [[TMP2]], [[DOTBB3]] ]
; CHECK-NEXT: [[TMP7:%.*]] = phi float [ [[ADD33_2]], [[DOTBB4]] ], [ [[TMP2]], [[DOTBB3]] ] ; CHECK-NEXT: [[TMP8:%.*]] = phi float [ [[ADD33_2]], [[DOTBB4]] ], [ [[TMP3]], [[DOTBB3]] ]
; CHECK-NEXT: br i1 [[CMP40]], label [[DOTBB6:%.*]], label [[DOTBB7:%.*]] ; CHECK-NEXT: br i1 [[CMP40]], label [[DOTBB6:%.*]], label [[DOTBB7:%.*]]
; CHECK: .bb6: ; CHECK: .bb6:
; CHECK-NEXT: store float [[TMP7]], ptr [[ARRAYIDX3]], align 4 ; CHECK-NEXT: [[TMP9:%.*]] = bitcast float [[TMP8]] to i32
; CHECK-NEXT: store float [[TMP6]], ptr [[ARRAYIDX6]], align 4 ; CHECK-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX3]], align 4
; CHECK-NEXT: [[TMP10:%.*]] = bitcast float [[TMP7]] to i32
; CHECK-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX6]], align 4
; CHECK-NEXT: br label [[DOTBB7]] ; CHECK-NEXT: br label [[DOTBB7]]
; CHECK: .bb7: ; CHECK: .bb7:
; CHECK-NEXT: br i1 [[TMP3]], label [[DOTBB9:%.*]], label [[DOTBB10:%.*]] ; CHECK-NEXT: br i1 [[TMP4]], label [[DOTBB9:%.*]], label [[DOTBB10:%.*]]
; CHECK: .bb8: ; CHECK: .bb8:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; CHECK: .bb9: ; CHECK: .bb9:
; CHECK-NEXT: [[TMP8:%.*]] = load float, ptr [[ARRAYIDX20]], align 4 ; CHECK-NEXT: [[TMP11:%.*]] = load float, ptr [[ARRAYIDX20]], align 4
; CHECK-NEXT: [[TMP9:%.*]] = load float, ptr [[ARRAYIDX24]], align 4 ; CHECK-NEXT: [[TMP12:%.*]] = load float, ptr [[ARRAYIDX24]], align 4
; CHECK-NEXT: [[ADD33_112:%.*]] = fadd float [[TMP9]], [[TMP8]] ; CHECK-NEXT: [[ADD33_112:%.*]] = fadd float [[TMP12]], [[TMP11]]
; CHECK-NEXT: [[ADD33_1_1:%.*]] = fadd float [[ADD33_112]], [[TMP6]] ; CHECK-NEXT: [[ADD33_1_1:%.*]] = fadd float [[ADD33_112]], [[TMP7]]
; CHECK-NEXT: [[ADD33_2_1:%.*]] = fadd float [[ADD33_1_1]], [[TMP7]] ; CHECK-NEXT: [[ADD33_2_1:%.*]] = fadd float [[ADD33_1_1]], [[TMP8]]
; CHECK-NEXT: br label [[DOTBB10]] ; CHECK-NEXT: br label [[DOTBB10]]
; CHECK: .bb10: ; CHECK: .bb10:
; CHECK-NEXT: [[TMP10]] = phi float [ [[ADD33_1_1]], [[DOTBB9]] ], [ [[TMP6]], [[DOTBB7]] ] ; CHECK-NEXT: [[TMP13]] = phi float [ [[ADD33_1_1]], [[DOTBB9]] ], [ [[TMP7]], [[DOTBB7]] ]
; CHECK-NEXT: [[TMP11]] = phi float [ [[ADD33_2_1]], [[DOTBB9]] ], [ [[TMP7]], [[DOTBB7]] ] ; CHECK-NEXT: [[TMP14]] = phi float [ [[ADD33_2_1]], [[DOTBB9]] ], [ [[TMP8]], [[DOTBB7]] ]
; CHECK-NEXT: br i1 [[CMP40]], label [[DOTBB11:%.*]], label [[DOTBB12]] ; CHECK-NEXT: br i1 [[CMP40]], label [[DOTBB11:%.*]], label [[DOTBB12]]
; CHECK: .bb11: ; CHECK: .bb11:
; CHECK-NEXT: store float [[TMP11]], ptr [[ARRAYIDX3]], align 4 ; CHECK-NEXT: [[TMP15:%.*]] = bitcast float [[TMP14]] to i32
; CHECK-NEXT: store float [[TMP10]], ptr [[ARRAYIDX6]], align 4 ; CHECK-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX3]], align 4
; CHECK-NEXT: [[TMP16:%.*]] = bitcast float [[TMP13]] to i32
; CHECK-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX6]], align 4
; CHECK-NEXT: br label [[DOTBB12]] ; CHECK-NEXT: br label [[DOTBB12]]
; CHECK: .bb12: ; CHECK: .bb12:
; CHECK-NEXT: [[SUB]] = add i32 [[I12_06]], -4 ; CHECK-NEXT: [[SUB]] = add i32 [[I12_06]], -4
; CHECK-NEXT: [[CMP13:%.*]] = icmp sgt i32 [[SUB]], 0 ; CHECK-NEXT: [[CMP13:%.*]] = icmp sgt i32 [[SUB]], 0
; CHECK-NEXT: br i1 [[CMP13]], label [[DOTBB3]], label [[DOTBB8]] ; CHECK-NEXT: br i1 [[CMP13]], label [[DOTBB3]], label [[DOTBB8]]
; ;
%callA = alloca [258 x float], align 4 %callA = alloca [258 x float], align 4
%callB = alloca [258 x float], align 4 %callB = alloca [258 x float], align 4
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llvm/test/Transforms/InstCombine/icmp-vec.ll

Show First 20 Lines • Show All 580 Lines • ▼ Show 20 Lines
} }
; negative test - extra use ; negative test - extra use
define i1 @eq_cast_eq-1_use2(<2 x i4> %x, <2 x i4> %y, ptr %p) { define i1 @eq_cast_eq-1_use2(<2 x i4> %x, <2 x i4> %y, ptr %p) {
; CHECK-LABEL: @eq_cast_eq-1_use2( ; CHECK-LABEL: @eq_cast_eq-1_use2(
; CHECK-NEXT: [[IC:%.*]] = icmp sgt <2 x i4> [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: [[IC:%.*]] = icmp sgt <2 x i4> [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: [[B:%.*]] = bitcast <2 x i1> [[IC]] to i2 ; CHECK-NEXT: [[B:%.*]] = bitcast <2 x i1> [[IC]] to i2
; CHECK-NEXT: store <2 x i1> [[IC]], ptr [[P:%.*]], align 1 ; CHECK-NEXT: store i2 [[B]], ptr [[P:%.*]], align 1
; CHECK-NEXT: [[R:%.*]] = icmp eq i2 [[B]], -1 ; CHECK-NEXT: [[R:%.*]] = icmp eq i2 [[B]], -1
; CHECK-NEXT: ret i1 [[R]] ; CHECK-NEXT: ret i1 [[R]]
; ;
%ic = icmp sgt <2 x i4> %x, %y %ic = icmp sgt <2 x i4> %x, %y
%b = bitcast <2 x i1> %ic to i2 %b = bitcast <2 x i1> %ic to i2
store i2 %b, ptr %p store i2 %b, ptr %p
%r = icmp eq i2 %b, -1 %r = icmp eq i2 %b, -1
ret i1 %r ret i1 %r
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llvm/test/Transforms/InstCombine/insert-val-extract-elem.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt -S -passes=instcombine %s | FileCheck %s ; RUN: opt -S -passes=instcombine %s | FileCheck %s
define void @julia_2xdouble(ptr sret([2 x double]), ptr) { define void @julia_2xdouble(ptr sret([2 x double]), ptr) {
; CHECK-LABEL: define void @julia_2xdouble ; CHECK-LABEL: define void @julia_2xdouble
; CHECK-SAME: (ptr sret([2 x double]) [[TMP0:%.*]], ptr [[TMP1:%.*]]) { ; CHECK-SAME: (ptr sret([2 x double]) [[TMP0:%.*]], ptr [[TMP1:%.*]]) {
; CHECK-NEXT: top: ; CHECK-NEXT: top:
; CHECK-NEXT: [[X:%.*]] = load <2 x double>, ptr [[TMP1]], align 16 ; CHECK-NEXT: [[X:%.*]] = load <2 x double>, ptr [[TMP1]], align 16
; CHECK-NEXT: store <2 x double> [[X]], ptr [[TMP0]], align 8 ; CHECK-NEXT: [[X0:%.*]] = extractelement <2 x double> [[X]], i64 0
; CHECK-NEXT: [[X1:%.*]] = extractelement <2 x double> [[X]], i64 1
; CHECK-NEXT: store double [[X0]], ptr [[TMP0]], align 8
; CHECK-NEXT: [[DOTREPACK1:%.*]] = getelementptr inbounds [2 x double], ptr [[TMP0]], i64 0, i64 1
; CHECK-NEXT: store double [[X1]], ptr [[DOTREPACK1]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
top: top:
%x = load <2 x double>, ptr %1 %x = load <2 x double>, ptr %1
%x0 = extractelement <2 x double> %x, i32 0 %x0 = extractelement <2 x double> %x, i32 0
%i0 = insertvalue [2 x double] undef, double %x0, 0 %i0 = insertvalue [2 x double] undef, double %x0, 0
%x1 = extractelement <2 x double> %x, i32 1 %x1 = extractelement <2 x double> %x, i32 1
%i1 = insertvalue [2 x double] %i0, double %x1, 1 %i1 = insertvalue [2 x double] %i0, double %x1, 1
store [2 x double] %i1, ptr %0, align 4 store [2 x double] %i1, ptr %0, align 4
ret void ret void
} }
; Test with two inserts to the same index ; Test with two inserts to the same index
define void @julia_2xi64(ptr sret([2 x i64]), ptr) { define void @julia_2xi64(ptr sret([2 x i64]), ptr) {
; CHECK-LABEL: define void @julia_2xi64 ; CHECK-LABEL: define void @julia_2xi64
; CHECK-SAME: (ptr sret([2 x i64]) [[TMP0:%.*]], ptr [[TMP1:%.*]]) { ; CHECK-SAME: (ptr sret([2 x i64]) [[TMP0:%.*]], ptr [[TMP1:%.*]]) {
; CHECK-NEXT: top: ; CHECK-NEXT: top:
; CHECK-NEXT: [[X:%.*]] = load <2 x i64>, ptr [[TMP1]], align 16 ; CHECK-NEXT: [[X:%.*]] = load <2 x i64>, ptr [[TMP1]], align 16
; CHECK-NEXT: store <2 x i64> [[X]], ptr [[TMP0]], align 4 ; CHECK-NEXT: [[X1:%.*]] = extractelement <2 x i64> [[X]], i64 1
; CHECK-NEXT: [[X2:%.*]] = extractelement <2 x i64> [[X]], i64 0
; CHECK-NEXT: store i64 [[X2]], ptr [[TMP0]], align 4
; CHECK-NEXT: [[DOTREPACK1:%.*]] = getelementptr inbounds [2 x i64], ptr [[TMP0]], i64 0, i64 1
; CHECK-NEXT: store i64 [[X1]], ptr [[DOTREPACK1]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
top: top:
%x = load <2 x i64>, ptr %1 %x = load <2 x i64>, ptr %1
%x0 = extractelement <2 x i64> %x, i32 1 %x0 = extractelement <2 x i64> %x, i32 1
%i0 = insertvalue [2 x i64] undef, i64 %x0, 0 %i0 = insertvalue [2 x i64] undef, i64 %x0, 0
%x1 = extractelement <2 x i64> %x, i32 1 %x1 = extractelement <2 x i64> %x, i32 1
%i1 = insertvalue [2 x i64] %i0, i64 %x1, 1 %i1 = insertvalue [2 x i64] %i0, i64 %x1, 1
%x2 = extractelement <2 x i64> %x, i32 0 %x2 = extractelement <2 x i64> %x, i32 0
%i2 = insertvalue [2 x i64] %i1, i64 %x2, 0 %i2 = insertvalue [2 x i64] %i1, i64 %x2, 0
store [2 x i64] %i2, ptr %0, align 4 store [2 x i64] %i2, ptr %0, align 4
ret void ret void
} }
define void @julia_4xfloat(ptr sret([4 x float]), ptr) { define void @julia_4xfloat(ptr sret([4 x float]), ptr) {
; CHECK-LABEL: define void @julia_4xfloat ; CHECK-LABEL: define void @julia_4xfloat
; CHECK-SAME: (ptr sret([4 x float]) [[TMP0:%.*]], ptr [[TMP1:%.*]]) { ; CHECK-SAME: (ptr sret([4 x float]) [[TMP0:%.*]], ptr [[TMP1:%.*]]) {
; CHECK-NEXT: top: ; CHECK-NEXT: top:
; CHECK-NEXT: [[X:%.*]] = load <4 x float>, ptr [[TMP1]], align 16 ; CHECK-NEXT: [[X:%.*]] = load <4 x float>, ptr [[TMP1]], align 16
; CHECK-NEXT: store <4 x float> [[X]], ptr [[TMP0]], align 4 ; CHECK-NEXT: [[X0:%.*]] = extractelement <4 x float> [[X]], i64 0
; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x float> [[X]], i64 1
; CHECK-NEXT: [[X2:%.*]] = extractelement <4 x float> [[X]], i64 2
; CHECK-NEXT: [[X3:%.*]] = extractelement <4 x float> [[X]], i64 3
; CHECK-NEXT: store float [[X0]], ptr [[TMP0]], align 4
; CHECK-NEXT: [[DOTREPACK1:%.*]] = getelementptr inbounds [4 x float], ptr [[TMP0]], i64 0, i64 1
; CHECK-NEXT: store float [[X1]], ptr [[DOTREPACK1]], align 4
; CHECK-NEXT: [[DOTREPACK3:%.*]] = getelementptr inbounds [4 x float], ptr [[TMP0]], i64 0, i64 2
; CHECK-NEXT: store float [[X2]], ptr [[DOTREPACK3]], align 4
; CHECK-NEXT: [[DOTREPACK5:%.*]] = getelementptr inbounds [4 x float], ptr [[TMP0]], i64 0, i64 3
; CHECK-NEXT: store float [[X3]], ptr [[DOTREPACK5]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
top: top:
%x = load <4 x float>, ptr %1 %x = load <4 x float>, ptr %1
%x0 = extractelement <4 x float> %x, i32 0 %x0 = extractelement <4 x float> %x, i32 0
%i0 = insertvalue [4 x float] undef, float %x0, 0 %i0 = insertvalue [4 x float] undef, float %x0, 0
%x1 = extractelement <4 x float> %x, i32 1 %x1 = extractelement <4 x float> %x, i32 1
%i1 = insertvalue [4 x float] %i0, float %x1, 1 %i1 = insertvalue [4 x float] %i0, float %x1, 1
%x2 = extractelement <4 x float> %x, i32 2 %x2 = extractelement <4 x float> %x, i32 2
%i2 = insertvalue [4 x float] %i1, float %x2, 2 %i2 = insertvalue [4 x float] %i1, float %x2, 2
%x3 = extractelement <4 x float> %x, i32 3 %x3 = extractelement <4 x float> %x, i32 3
%i3 = insertvalue [4 x float] %i2, float %x3, 3 %i3 = insertvalue [4 x float] %i2, float %x3, 3
store [4 x float] %i3, ptr %0, align 4 store [4 x float] %i3, ptr %0, align 4
ret void ret void
} }
%pseudovec = type { float, float, float, float } %pseudovec = type { float, float, float, float }
define void @julia_pseudovec(ptr sret(%pseudovec), ptr) { define void @julia_pseudovec(ptr sret(%pseudovec), ptr) {
; CHECK-LABEL: define void @julia_pseudovec ; CHECK-LABEL: define void @julia_pseudovec
; CHECK-SAME: (ptr sret([[PSEUDOVEC:%.*]]) [[TMP0:%.*]], ptr [[TMP1:%.*]]) { ; CHECK-SAME: (ptr sret([[PSEUDOVEC:%.*]]) [[TMP0:%.*]], ptr [[TMP1:%.*]]) {
; CHECK-NEXT: top: ; CHECK-NEXT: top:
; CHECK-NEXT: [[X:%.*]] = load <4 x float>, ptr [[TMP1]], align 16 ; CHECK-NEXT: [[X:%.*]] = load <4 x float>, ptr [[TMP1]], align 16
; CHECK-NEXT: store <4 x float> [[X]], ptr [[TMP0]], align 4 ; CHECK-NEXT: [[X0:%.*]] = extractelement <4 x float> [[X]], i64 0
; CHECK-NEXT: [[X1:%.*]] = extractelement <4 x float> [[X]], i64 1
; CHECK-NEXT: [[X2:%.*]] = extractelement <4 x float> [[X]], i64 2
; CHECK-NEXT: [[X3:%.*]] = extractelement <4 x float> [[X]], i64 3
; CHECK-NEXT: store float [[X0]], ptr [[TMP0]], align 4
; CHECK-NEXT: [[DOTREPACK1:%.*]] = getelementptr inbounds [[PSEUDOVEC]], ptr [[TMP0]], i64 0, i32 1
; CHECK-NEXT: store float [[X1]], ptr [[DOTREPACK1]], align 4
; CHECK-NEXT: [[DOTREPACK3:%.*]] = getelementptr inbounds [[PSEUDOVEC]], ptr [[TMP0]], i64 0, i32 2
; CHECK-NEXT: store float [[X2]], ptr [[DOTREPACK3]], align 4
; CHECK-NEXT: [[DOTREPACK5:%.*]] = getelementptr inbounds [[PSEUDOVEC]], ptr [[TMP0]], i64 0, i32 3
; CHECK-NEXT: store float [[X3]], ptr [[DOTREPACK5]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
top: top:
%x = load <4 x float>, ptr %1 %x = load <4 x float>, ptr %1
%x0 = extractelement <4 x float> %x, i32 0 %x0 = extractelement <4 x float> %x, i32 0
%i0 = insertvalue %pseudovec undef, float %x0, 0 %i0 = insertvalue %pseudovec undef, float %x0, 0
%x1 = extractelement <4 x float> %x, i32 1 %x1 = extractelement <4 x float> %x, i32 1
%i1 = insertvalue %pseudovec %i0, float %x1, 1 %i1 = insertvalue %pseudovec %i0, float %x1, 1
%x2 = extractelement <4 x float> %x, i32 2 %x2 = extractelement <4 x float> %x, i32 2
%i2 = insertvalue %pseudovec %i1, float %x2, 2 %i2 = insertvalue %pseudovec %i1, float %x2, 2
%x3 = extractelement <4 x float> %x, i32 3 %x3 = extractelement <4 x float> %x, i32 3
%i3 = insertvalue %pseudovec %i2, float %x3, 3 %i3 = insertvalue %pseudovec %i2, float %x3, 3
store %pseudovec %i3, ptr %0, align 4 store %pseudovec %i3, ptr %0, align 4
ret void ret void
} }

llvm/test/Transforms/InstCombine/load-bitcast-select.ll

Show All 16 Lines
; CHECK: for.body: ; CHECK: for.body:
; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[I_0]] to i64 ; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[I_0]] to i64
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x float], ptr @a, i64 0, i64 [[TMP0]] ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x float], ptr @a, i64 0, i64 [[TMP0]]
; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [1000 x float], ptr @b, i64 0, i64 [[TMP0]] ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [1000 x float], ptr @b, i64 0, i64 [[TMP0]]
; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[ARRAYIDX]], align 4 ; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = load float, ptr [[ARRAYIDX2]], align 4 ; CHECK-NEXT: [[TMP2:%.*]] = load float, ptr [[ARRAYIDX2]], align 4
; CHECK-NEXT: [[CMP_I:%.*]] = fcmp fast olt float [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[CMP_I:%.*]] = fcmp fast olt float [[TMP1]], [[TMP2]]
; CHECK-NEXT: [[DOTV:%.*]] = select i1 [[CMP_I]], float [[TMP2]], float [[TMP1]] ; CHECK-NEXT: [[DOTV:%.*]] = select i1 [[CMP_I]], float [[TMP2]], float [[TMP1]]
; CHECK-NEXT: store float [[DOTV]], ptr [[ARRAYIDX]], align 4 ; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[DOTV]] to i32
; CHECK-NEXT: store i32 [[TMP3]], ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_0]], 1 ; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_0]], 1
; CHECK-NEXT: br label [[FOR_COND]] ; CHECK-NEXT: br label [[FOR_COND]]
; ;
entry: entry:
br label %for.cond br label %for.cond
for.cond: ; preds = %for.body, %entry for.cond: ; preds = %for.body, %entry
%i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ] %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
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} }
define void @bitcasted_minmax_with_select_of_pointers(ptr %loadaddr1, ptr %loadaddr2, ptr %storeaddr) { define void @bitcasted_minmax_with_select_of_pointers(ptr %loadaddr1, ptr %loadaddr2, ptr %storeaddr) {
; CHECK-LABEL: @bitcasted_minmax_with_select_of_pointers( ; CHECK-LABEL: @bitcasted_minmax_with_select_of_pointers(
; CHECK-NEXT: [[LD1:%.*]] = load float, ptr [[LOADADDR1:%.*]], align 4 ; CHECK-NEXT: [[LD1:%.*]] = load float, ptr [[LOADADDR1:%.*]], align 4
; CHECK-NEXT: [[LD2:%.*]] = load float, ptr [[LOADADDR2:%.*]], align 4 ; CHECK-NEXT: [[LD2:%.*]] = load float, ptr [[LOADADDR2:%.*]], align 4
; CHECK-NEXT: [[COND:%.*]] = fcmp ogt float [[LD1]], [[LD2]] ; CHECK-NEXT: [[COND:%.*]] = fcmp ogt float [[LD1]], [[LD2]]
; CHECK-NEXT: [[LD_V:%.*]] = select i1 [[COND]], float [[LD1]], float [[LD2]] ; CHECK-NEXT: [[LD_V:%.*]] = select i1 [[COND]], float [[LD1]], float [[LD2]]
; CHECK-NEXT: store float [[LD_V]], ptr [[STOREADDR:%.*]], align 4 ; CHECK-NEXT: [[LD:%.*]] = bitcast float [[LD_V]] to i32
; CHECK-NEXT: store i32 [[LD]], ptr [[STOREADDR:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%ld1 = load float, ptr %loadaddr1, align 4 %ld1 = load float, ptr %loadaddr1, align 4
%ld2 = load float, ptr %loadaddr2, align 4 %ld2 = load float, ptr %loadaddr2, align 4
%cond = fcmp ogt float %ld1, %ld2 %cond = fcmp ogt float %ld1, %ld2
%sel = select i1 %cond, ptr %loadaddr1, ptr %loadaddr2 %sel = select i1 %cond, ptr %loadaddr1, ptr %loadaddr2
%ld = load i32, ptr %sel, align 4 %ld = load i32, ptr %sel, align 4
store i32 %ld, ptr %storeaddr, align 4 store i32 %ld, ptr %storeaddr, align 4
ret void ret void
} }

llvm/test/Transforms/InstCombine/load.ll

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define void @test16(ptr %x, ptr %a, ptr %b, ptr %c) { define void @test16(ptr %x, ptr %a, ptr %b, ptr %c) {
; CHECK-LABEL: @test16( ; CHECK-LABEL: @test16(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[X1:%.*]] = load float, ptr [[X:%.*]], align 4 ; CHECK-NEXT: [[X1:%.*]] = load float, ptr [[X:%.*]], align 4
; CHECK-NEXT: store float [[X1]], ptr [[A:%.*]], align 4 ; CHECK-NEXT: store float [[X1]], ptr [[A:%.*]], align 4
; CHECK-NEXT: store float [[X1]], ptr [[B:%.*]], align 4 ; CHECK-NEXT: store float [[X1]], ptr [[B:%.*]], align 4
; CHECK-NEXT: [[X2:%.*]] = load float, ptr [[X]], align 4 ; CHECK-NEXT: [[X2:%.*]] = load float, ptr [[X]], align 4
; CHECK-NEXT: store float [[X2]], ptr [[B]], align 4 ; CHECK-NEXT: store float [[X2]], ptr [[B]], align 4
; CHECK-NEXT: store float [[X2]], ptr [[C:%.*]], align 4 ; CHECK-NEXT: [[X2_CAST:%.*]] = bitcast float [[X2]] to i32
; CHECK-NEXT: store i32 [[X2_CAST]], ptr [[C:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%x1 = load float, ptr %x %x1 = load float, ptr %x
store float %x1, ptr %a store float %x1, ptr %a
store float %x1, ptr %b store float %x1, ptr %b
%x2 = load float, ptr %x %x2 = load float, ptr %x
store float %x2, ptr %b store float %x2, ptr %b
%x2.cast = bitcast float %x2 to i32 %x2.cast = bitcast float %x2 to i32
store i32 %x2.cast, ptr %c store i32 %x2.cast, ptr %c
ret void ret void
} }
define void @test16-vect(ptr %x, ptr %a, ptr %b, ptr %c) { define void @test16-vect(ptr %x, ptr %a, ptr %b, ptr %c) {
; CHECK-LABEL: @test16-vect( ; CHECK-LABEL: @test16-vect(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[X1:%.*]] = load <4 x i8>, ptr [[X:%.*]], align 4 ; CHECK-NEXT: [[X1:%.*]] = load <4 x i8>, ptr [[X:%.*]], align 4
; CHECK-NEXT: store <4 x i8> [[X1]], ptr [[A:%.*]], align 4 ; CHECK-NEXT: store <4 x i8> [[X1]], ptr [[A:%.*]], align 4
; CHECK-NEXT: store <4 x i8> [[X1]], ptr [[B:%.*]], align 4 ; CHECK-NEXT: store <4 x i8> [[X1]], ptr [[B:%.*]], align 4
; CHECK-NEXT: [[X2:%.*]] = load <4 x i8>, ptr [[X]], align 4 ; CHECK-NEXT: [[X2:%.*]] = load <4 x i8>, ptr [[X]], align 4
; CHECK-NEXT: store <4 x i8> [[X2]], ptr [[B]], align 4 ; CHECK-NEXT: store <4 x i8> [[X2]], ptr [[B]], align 4
; CHECK-NEXT: store <4 x i8> [[X2]], ptr [[C:%.*]], align 4 ; CHECK-NEXT: [[X2_CAST:%.*]] = bitcast <4 x i8> [[X2]] to i32
; CHECK-NEXT: store i32 [[X2_CAST]], ptr [[C:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%x1 = load <4 x i8>, ptr %x %x1 = load <4 x i8>, ptr %x
store <4 x i8> %x1, ptr %a store <4 x i8> %x1, ptr %a
store <4 x i8> %x1, ptr %b store <4 x i8> %x1, ptr %b
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llvm/test/Transforms/InstCombine/multiple-uses-load-bitcast-select.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=instcombine -S -data-layout="E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64" | FileCheck %s ; RUN: opt < %s -passes=instcombine -S -data-layout="E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64" | FileCheck %s
define void @PR35618(ptr %st1, ptr %st2) { define void @PR35618(ptr %st1, ptr %st2) {
; CHECK-LABEL: @PR35618( ; CHECK-LABEL: @PR35618(
; CHECK-NEXT: [[Y1:%.*]] = alloca double, align 8 ; CHECK-NEXT: [[Y1:%.*]] = alloca double, align 8
; CHECK-NEXT: [[Z1:%.*]] = alloca double, align 8 ; CHECK-NEXT: [[Z1:%.*]] = alloca double, align 8
; CHECK-NEXT: [[LD1:%.*]] = load double, ptr [[Y1]], align 8 ; CHECK-NEXT: [[LD1:%.*]] = load double, ptr [[Y1]], align 8
; CHECK-NEXT: [[LD2:%.*]] = load double, ptr [[Z1]], align 8 ; CHECK-NEXT: [[LD2:%.*]] = load double, ptr [[Z1]], align 8
; CHECK-NEXT: [[TMPVAR10:%.*]] = fcmp olt double [[LD1]], [[LD2]] ; CHECK-NEXT: [[TMPVAR10:%.*]] = fcmp olt double [[LD1]], [[LD2]]
; CHECK-NEXT: [[TMPVAR12_V:%.*]] = select i1 [[TMPVAR10]], double [[LD1]], double [[LD2]] ; CHECK-NEXT: [[TMPVAR12_V:%.*]] = select i1 [[TMPVAR10]], double [[LD1]], double [[LD2]]
; CHECK-NEXT: store double [[TMPVAR12_V]], ptr [[ST1:%.*]], align 8 ; CHECK-NEXT: [[TMPVAR12:%.*]] = bitcast double [[TMPVAR12_V]] to i64
; CHECK-NEXT: store double [[TMPVAR12_V]], ptr [[ST2:%.*]], align 8 ; CHECK-NEXT: store i64 [[TMPVAR12]], ptr [[ST1:%.*]], align 8
; CHECK-NEXT: store i64 [[TMPVAR12]], ptr [[ST2:%.*]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%y1 = alloca double %y1 = alloca double
%z1 = alloca double %z1 = alloca double
%ld1 = load double, ptr %y1 %ld1 = load double, ptr %y1
%ld2 = load double, ptr %z1 %ld2 = load double, ptr %z1
%tmpvar10 = fcmp olt double %ld1, %ld2 %tmpvar10 = fcmp olt double %ld1, %ld2
%sel = select i1 %tmpvar10, ptr %y1, ptr %z1 %sel = select i1 %tmpvar10, ptr %y1, ptr %z1
%tmpvar12 = load i64, ptr %sel %tmpvar12 = load i64, ptr %sel
store i64 %tmpvar12, ptr %st1 store i64 %tmpvar12, ptr %st1
store i64 %tmpvar12, ptr %st2 store i64 %tmpvar12, ptr %st2
ret void ret void
} }

llvm/test/Transforms/InstCombine/pr25342.ll

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; CHECK-NEXT: [[MUL5_I:%.*]] = fmul float [[TMP3]], [[TMP4]] ; CHECK-NEXT: [[MUL5_I:%.*]] = fmul float [[TMP3]], [[TMP4]]
; CHECK-NEXT: [[MUL6_I:%.*]] = fmul float [[TMP2]], [[TMP5]] ; CHECK-NEXT: [[MUL6_I:%.*]] = fmul float [[TMP2]], [[TMP5]]
; CHECK-NEXT: [[ADD_I4:%.*]] = fadd float [[MUL5_I]], [[MUL6_I]] ; CHECK-NEXT: [[ADD_I4:%.*]] = fadd float [[MUL5_I]], [[MUL6_I]]
; CHECK-NEXT: [[ADD_I]] = fadd float [[SUB_I]], [[TMP0]] ; CHECK-NEXT: [[ADD_I]] = fadd float [[SUB_I]], [[TMP0]]
; CHECK-NEXT: [[ADD4_I]] = fadd float [[ADD_I4]], [[TMP1]] ; CHECK-NEXT: [[ADD4_I]] = fadd float [[ADD_I4]], [[TMP1]]
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_0]], 1 ; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_0]], 1
; CHECK-NEXT: br label [[FOR_COND]] ; CHECK-NEXT: br label [[FOR_COND]]
; CHECK: for.end: ; CHECK: for.end:
; CHECK-NEXT: store float [[TMP0]], ptr @dd, align 4 ; CHECK-NEXT: [[TMP6:%.*]] = bitcast float [[TMP0]] to i32
; CHECK-NEXT: store float [[TMP1]], ptr getelementptr inbounds (%"struct.std::complex", ptr @dd, i64 0, i32 0, i32 1), align 4 ; CHECK-NEXT: store i32 [[TMP6]], ptr @dd, align 4
; CHECK-NEXT: [[TMP7:%.*]] = bitcast float [[TMP1]] to i32
; CHECK-NEXT: store i32 [[TMP7]], ptr getelementptr inbounds (%"struct.std::complex", ptr @dd, i64 0, i32 0, i32 1), align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
br label %for.cond br label %for.cond
for.cond: for.cond:
%ldd.sroa.0.0 = phi i32 [ 0, %entry ], [ %5, %for.body ] %ldd.sroa.0.0 = phi i32 [ 0, %entry ], [ %5, %for.body ]
%ldd.sroa.6.0 = phi i32 [ 0, %entry ], [ %7, %for.body ] %ldd.sroa.6.0 = phi i32 [ 0, %entry ], [ %7, %for.body ]
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; CHECK-NEXT: br i1 [[EVEN_NOT_NOT]], label [[EVEN_BB:%.*]], label [[ODD_BB]] ; CHECK-NEXT: br i1 [[EVEN_NOT_NOT]], label [[EVEN_BB:%.*]], label [[ODD_BB]]
; CHECK: even.bb: ; CHECK: even.bb:
; CHECK-NEXT: [[TMP5:%.*]] = fadd float [[SUB_I]], [[ADD_I]] ; CHECK-NEXT: [[TMP5:%.*]] = fadd float [[SUB_I]], [[ADD_I]]
; CHECK-NEXT: br label [[ODD_BB]] ; CHECK-NEXT: br label [[ODD_BB]]
; CHECK: odd.bb: ; CHECK: odd.bb:
; CHECK-NEXT: [[TMP6]] = phi float [ [[ADD_I]], [[FOR_BODY]] ], [ [[TMP5]], [[EVEN_BB]] ] ; CHECK-NEXT: [[TMP6]] = phi float [ [[ADD_I]], [[FOR_BODY]] ], [ [[TMP5]], [[EVEN_BB]] ]
; CHECK-NEXT: br label [[FOR_COND]] ; CHECK-NEXT: br label [[FOR_COND]]
; CHECK: for.end: ; CHECK: for.end:
; CHECK-NEXT: store float [[TMP0]], ptr @dd, align 4 ; CHECK-NEXT: [[TMP7:%.*]] = bitcast float [[TMP0]] to i32
; CHECK-NEXT: store i32 [[TMP7]], ptr @dd, align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
br label %for.cond br label %for.cond
for.cond: for.cond:
%ldd.sroa.0.0 = phi i32 [ 0, %entry ], [ %9, %odd.bb ] %ldd.sroa.0.0 = phi i32 [ 0, %entry ], [ %9, %odd.bb ]
%i.0 = phi i32 [ 0, %entry ], [ %inc, %odd.bb ] %i.0 = phi i32 [ 0, %entry ], [ %inc, %odd.bb ]
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llvm/test/Transforms/InstCombine/select.ll

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%bc2 = bitcast <vscale x 4 x i32> %select to <vscale x 4 x float> %bc2 = bitcast <vscale x 4 x i32> %select to <vscale x 4 x float>
ret <vscale x 4 x float> %bc2 ret <vscale x 4 x float> %bc2
} }
define void @select_oneuse_bitcast(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x i32> %c, <vscale x 4 x i32> %d, ptr %ptr1) { define void @select_oneuse_bitcast(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x i32> %c, <vscale x 4 x i32> %d, ptr %ptr1) {
; CHECK-LABEL: @select_oneuse_bitcast( ; CHECK-LABEL: @select_oneuse_bitcast(
; CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 4 x i32> [[C:%.*]], [[D:%.*]] ; CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 4 x i32> [[C:%.*]], [[D:%.*]]
; CHECK-NEXT: [[SEL1_V:%.*]] = select <vscale x 4 x i1> [[CMP]], <vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]] ; CHECK-NEXT: [[SEL1_V:%.*]] = select <vscale x 4 x i1> [[CMP]], <vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]
; CHECK-NEXT: store <vscale x 4 x float> [[SEL1_V]], ptr [[PTR1:%.*]], align 16 ; CHECK-NEXT: [[SEL1:%.*]] = bitcast <vscale x 4 x float> [[SEL1_V]] to <vscale x 4 x i32>
; CHECK-NEXT: store <vscale x 4 x i32> [[SEL1]], ptr [[PTR1:%.*]], align 16
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%cmp = icmp ult <vscale x 4 x i32> %c, %d %cmp = icmp ult <vscale x 4 x i32> %c, %d
%bc1 = bitcast <vscale x 4 x float> %a to <vscale x 4 x i32> %bc1 = bitcast <vscale x 4 x float> %a to <vscale x 4 x i32>
%bc2 = bitcast <vscale x 4 x float> %b to <vscale x 4 x i32> %bc2 = bitcast <vscale x 4 x float> %b to <vscale x 4 x i32>
%sel1 = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %bc1, <vscale x 4 x i32> %bc2 %sel1 = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %bc1, <vscale x 4 x i32> %bc2
store <vscale x 4 x i32> %sel1, ptr %ptr1 store <vscale x 4 x i32> %sel1, ptr %ptr1
ret void ret void
} }
; Allow select promotion even if there are multiple uses of bitcasted ops. ; Allow select promotion even if there are multiple uses of bitcasted ops.
; Hoisting the selects allows later pattern matching to see that these are min/max ops. ; Hoisting the selects allows later pattern matching to see that these are min/max ops.
define void @min_max_bitcast(<4 x float> %a, <4 x float> %b, ptr %ptr1, ptr %ptr2) { define void @min_max_bitcast(<4 x float> %a, <4 x float> %b, ptr %ptr1, ptr %ptr2) {
; CHECK-LABEL: @min_max_bitcast( ; CHECK-LABEL: @min_max_bitcast(
; CHECK-NEXT: [[CMP:%.*]] = fcmp olt <4 x float> [[A:%.*]], [[B:%.*]] ; CHECK-NEXT: [[CMP:%.*]] = fcmp olt <4 x float> [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: [[SEL1_V:%.*]] = select <4 x i1> [[CMP]], <4 x float> [[A]], <4 x float> [[B]] ; CHECK-NEXT: [[SEL1_V:%.*]] = select <4 x i1> [[CMP]], <4 x float> [[A]], <4 x float> [[B]]
; CHECK-NEXT: [[SEL1:%.*]] = bitcast <4 x float> [[SEL1_V]] to <4 x i32>
; CHECK-NEXT: [[SEL2_V:%.*]] = select <4 x i1> [[CMP]], <4 x float> [[B]], <4 x float> [[A]] ; CHECK-NEXT: [[SEL2_V:%.*]] = select <4 x i1> [[CMP]], <4 x float> [[B]], <4 x float> [[A]]
; CHECK-NEXT: store <4 x float> [[SEL1_V]], ptr [[PTR1:%.*]], align 16 ; CHECK-NEXT: [[SEL2:%.*]] = bitcast <4 x float> [[SEL2_V]] to <4 x i32>
; CHECK-NEXT: store <4 x float> [[SEL2_V]], ptr [[PTR2:%.*]], align 16 ; CHECK-NEXT: store <4 x i32> [[SEL1]], ptr [[PTR1:%.*]], align 16
; CHECK-NEXT: store <4 x i32> [[SEL2]], ptr [[PTR2:%.*]], align 16
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%cmp = fcmp olt <4 x float> %a, %b %cmp = fcmp olt <4 x float> %a, %b
%bc1 = bitcast <4 x float> %a to <4 x i32> %bc1 = bitcast <4 x float> %a to <4 x i32>
%bc2 = bitcast <4 x float> %b to <4 x i32> %bc2 = bitcast <4 x float> %b to <4 x i32>
%sel1 = select <4 x i1> %cmp, <4 x i32> %bc1, <4 x i32> %bc2 %sel1 = select <4 x i1> %cmp, <4 x i32> %bc1, <4 x i32> %bc2
%sel2 = select <4 x i1> %cmp, <4 x i32> %bc2, <4 x i32> %bc1 %sel2 = select <4 x i1> %cmp, <4 x i32> %bc2, <4 x i32> %bc1
store <4 x i32> %sel1, ptr %ptr1 store <4 x i32> %sel1, ptr %ptr1
store <4 x i32> %sel2, ptr %ptr2 store <4 x i32> %sel2, ptr %ptr2
ret void ret void
} }
define void @min_max_bitcast1(<vscale x 4 x float> %a, <vscale x 4 x float> %b, ptr %ptr1, ptr %ptr2) { define void @min_max_bitcast1(<vscale x 4 x float> %a, <vscale x 4 x float> %b, ptr %ptr1, ptr %ptr2) {
; CHECK-LABEL: @min_max_bitcast1( ; CHECK-LABEL: @min_max_bitcast1(
; CHECK-NEXT: [[CMP:%.*]] = fcmp olt <vscale x 4 x float> [[A:%.*]], [[B:%.*]] ; CHECK-NEXT: [[CMP:%.*]] = fcmp olt <vscale x 4 x float> [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: [[SEL1_V:%.*]] = select <vscale x 4 x i1> [[CMP]], <vscale x 4 x float> [[A]], <vscale x 4 x float> [[B]] ; CHECK-NEXT: [[SEL1_V:%.*]] = select <vscale x 4 x i1> [[CMP]], <vscale x 4 x float> [[A]], <vscale x 4 x float> [[B]]
; CHECK-NEXT: [[SEL1:%.*]] = bitcast <vscale x 4 x float> [[SEL1_V]] to <vscale x 4 x i32>
; CHECK-NEXT: [[SEL2_V:%.*]] = select <vscale x 4 x i1> [[CMP]], <vscale x 4 x float> [[B]], <vscale x 4 x float> [[A]] ; CHECK-NEXT: [[SEL2_V:%.*]] = select <vscale x 4 x i1> [[CMP]], <vscale x 4 x float> [[B]], <vscale x 4 x float> [[A]]
; CHECK-NEXT: store <vscale x 4 x float> [[SEL1_V]], ptr [[PTR1:%.*]], align 16 ; CHECK-NEXT: [[SEL2:%.*]] = bitcast <vscale x 4 x float> [[SEL2_V]] to <vscale x 4 x i32>
; CHECK-NEXT: store <vscale x 4 x float> [[SEL2_V]], ptr [[PTR2:%.*]], align 16 ; CHECK-NEXT: store <vscale x 4 x i32> [[SEL1]], ptr [[PTR1:%.*]], align 16
; CHECK-NEXT: store <vscale x 4 x i32> [[SEL2]], ptr [[PTR2:%.*]], align 16
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%cmp = fcmp olt <vscale x 4 x float> %a, %b %cmp = fcmp olt <vscale x 4 x float> %a, %b
%bc1 = bitcast <vscale x 4 x float> %a to <vscale x 4 x i32> %bc1 = bitcast <vscale x 4 x float> %a to <vscale x 4 x i32>
%bc2 = bitcast <vscale x 4 x float> %b to <vscale x 4 x i32> %bc2 = bitcast <vscale x 4 x float> %b to <vscale x 4 x i32>
%sel1 = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %bc1, <vscale x 4 x i32> %bc2 %sel1 = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %bc1, <vscale x 4 x i32> %bc2
%sel2 = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %bc2, <vscale x 4 x i32> %bc1 %sel2 = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %bc2, <vscale x 4 x i32> %bc1
store <vscale x 4 x i32> %sel1, ptr %ptr1 store <vscale x 4 x i32> %sel1, ptr %ptr1
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llvm/test/Transforms/InstCombine/select_meta.ll

Show All 26 Lines;
%trunc = trunc i32 %sel to i8 %trunc = trunc i32 %sel to i8
ret i8 %trunc ret i8 %trunc
} }
define void @min_max_bitcast(<4 x float> %a, <4 x float> %b, ptr %ptr1, ptr %ptr2) { define void @min_max_bitcast(<4 x float> %a, <4 x float> %b, ptr %ptr1, ptr %ptr2) {
; CHECK-LABEL: @min_max_bitcast( ; CHECK-LABEL: @min_max_bitcast(
; CHECK-NEXT: [[CMP:%.*]] = fcmp olt <4 x float> [[A:%.*]], [[B:%.*]] ; CHECK-NEXT: [[CMP:%.*]] = fcmp olt <4 x float> [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: [[SEL1_V:%.*]] = select <4 x i1> [[CMP]], <4 x float> [[A]], <4 x float> [[B]], !prof [[PROF0]] ; CHECK-NEXT: [[SEL1_V:%.*]] = select <4 x i1> [[CMP]], <4 x float> [[A]], <4 x float> [[B]], !prof [[PROF0]]
; CHECK-NEXT: [[SEL1:%.*]] = bitcast <4 x float> [[SEL1_V]] to <4 x i32>
; CHECK-NEXT: [[SEL2_V:%.*]] = select <4 x i1> [[CMP]], <4 x float> [[B]], <4 x float> [[A]], !prof [[PROF0]] ; CHECK-NEXT: [[SEL2_V:%.*]] = select <4 x i1> [[CMP]], <4 x float> [[B]], <4 x float> [[A]], !prof [[PROF0]]
; CHECK-NEXT: store <4 x float> [[SEL1_V]], ptr [[PTR1:%.*]], align 16 ; CHECK-NEXT: [[SEL2:%.*]] = bitcast <4 x float> [[SEL2_V]] to <4 x i32>
; CHECK-NEXT: store <4 x float> [[SEL2_V]], ptr [[PTR2:%.*]], align 16 ; CHECK-NEXT: store <4 x i32> [[SEL1]], ptr [[PTR1:%.*]], align 16
; CHECK-NEXT: store <4 x i32> [[SEL2]], ptr [[PTR2:%.*]], align 16
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%cmp = fcmp olt <4 x float> %a, %b %cmp = fcmp olt <4 x float> %a, %b
%bc1 = bitcast <4 x float> %a to <4 x i32> %bc1 = bitcast <4 x float> %a to <4 x i32>
%bc2 = bitcast <4 x float> %b to <4 x i32> %bc2 = bitcast <4 x float> %b to <4 x i32>
%sel1 = select <4 x i1> %cmp, <4 x i32> %bc1, <4 x i32> %bc2, !prof !1 %sel1 = select <4 x i1> %cmp, <4 x i32> %bc1, <4 x i32> %bc2, !prof !1
%sel2 = select <4 x i1> %cmp, <4 x i32> %bc2, <4 x i32> %bc1, !prof !1 %sel2 = select <4 x i1> %cmp, <4 x i32> %bc2, <4 x i32> %bc1, !prof !1
store <4 x i32> %sel1, ptr %ptr1 store <4 x i32> %sel1, ptr %ptr1
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llvm/test/Transforms/InstCombine/shufflevec-bitcast.ll

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%b = bitcast <2 x i8> %i to <4 x i4> %b = bitcast <2 x i8> %i to <4 x i4>
%r = shufflevector <4 x i4> %b, <4 x i4> undef, <2 x i32> <i32 0, i32 1> %r = shufflevector <4 x i4> %b, <4 x i4> undef, <2 x i32> <i32 0, i32 1>
ret <2 x i4> %r ret <2 x i4> %r
} }
define <2 x i4> @shuf_bitcast_insert_use2(<2 x i8> %v, i8 %x, ptr %p) { define <2 x i4> @shuf_bitcast_insert_use2(<2 x i8> %v, i8 %x, ptr %p) {
; CHECK-LABEL: @shuf_bitcast_insert_use2( ; CHECK-LABEL: @shuf_bitcast_insert_use2(
; CHECK-NEXT: [[I:%.*]] = insertelement <2 x i8> [[V:%.*]], i8 [[X:%.*]], i64 0 ; CHECK-NEXT: [[I:%.*]] = insertelement <2 x i8> [[V:%.*]], i8 [[X:%.*]], i64 0
; CHECK-NEXT: store <2 x i8> [[I]], ptr [[P:%.*]], align 2 ; CHECK-NEXT: [[B:%.*]] = bitcast <2 x i8> [[I]] to <4 x i4>
; CHECK-NEXT: store <4 x i4> [[B]], ptr [[P:%.*]], align 2
; CHECK-NEXT: [[R:%.*]] = bitcast i8 [[X]] to <2 x i4> ; CHECK-NEXT: [[R:%.*]] = bitcast i8 [[X]] to <2 x i4>
; CHECK-NEXT: ret <2 x i4> [[R]] ; CHECK-NEXT: ret <2 x i4> [[R]]
; ;
%i = insertelement <2 x i8> %v, i8 %x, i32 0 %i = insertelement <2 x i8> %v, i8 %x, i32 0
%b = bitcast <2 x i8> %i to <4 x i4> %b = bitcast <2 x i8> %i to <4 x i4>
store <4 x i4> %b, ptr %p store <4 x i4> %b, ptr %p
%r = shufflevector <4 x i4> %b, <4 x i4> undef, <2 x i32> <i32 0, i32 1> %r = shufflevector <4 x i4> %b, <4 x i4> undef, <2 x i32> <i32 0, i32 1>
ret <2 x i4> %r ret <2 x i4> %r
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llvm/test/Transforms/PhaseOrdering/bitcast-store-branch.ll

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} }
define ptr @parent(ptr align 8 dereferenceable(72) %f, half %val1, i16 %val2, i32 %val3) align 2 { define ptr @parent(ptr align 8 dereferenceable(72) %f, half %val1, i16 %val2, i32 %val3) align 2 {
; CHECK-LABEL: define nonnull ptr @parent ; CHECK-LABEL: define nonnull ptr @parent
; CHECK-SAME: (ptr readonly returned align 8 dereferenceable(72) [[F:%.*]], half [[VAL1:%.*]], i16 [[VAL2:%.*]], i32 [[VAL3:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] align 2 { ; CHECK-SAME: (ptr readonly returned align 8 dereferenceable(72) [[F:%.*]], half [[VAL1:%.*]], i16 [[VAL2:%.*]], i32 [[VAL3:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] align 2 {
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[F]], i64 64 ; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[F]], i64 64
; CHECK-NEXT: [[F_VAL:%.*]] = load ptr, ptr [[TMP0]], align 8 ; CHECK-NEXT: [[F_VAL:%.*]] = load ptr, ptr [[TMP0]], align 8
; CHECK-NEXT: [[VAL1_CAST_I:%.*]] = bitcast half [[VAL1]] to i16
; CHECK-NEXT: [[CMP_NOT_NOT_I:%.*]] = icmp eq i32 [[VAL3]], 0 ; CHECK-NEXT: [[CMP_NOT_NOT_I:%.*]] = icmp eq i32 [[VAL3]], 0
; CHECK-NEXT: br i1 [[CMP_NOT_NOT_I]], label [[IF_THEN_I:%.*]], label [[IF_ELSE_I:%.*]] ; CHECK-NEXT: [[SPEC_SELECT_I:%.*]] = select i1 [[CMP_NOT_NOT_I]], i16 [[VAL1_CAST_I]], i16 [[VAL2]]
; CHECK: if.then.i: ; CHECK-NEXT: [[SPEC_SELECT1_I:%.*]] = select i1 [[CMP_NOT_NOT_I]], i16 [[VAL2]], i16 [[VAL1_CAST_I]]
; CHECK-NEXT: store half [[VAL1]], ptr [[F_VAL]], align 2 ; CHECK-NEXT: store i16 [[SPEC_SELECT_I]], ptr [[F_VAL]], align 2
; CHECK-NEXT: [[ADD_PTR_I_I_I_I_I:%.*]] = getelementptr inbounds i8, ptr [[F_VAL]], i64 16 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[F_VAL]], i64 16
; CHECK-NEXT: br label [[BADCHILD_EXIT:%.*]] ; CHECK-NEXT: store i16 [[SPEC_SELECT1_I]], ptr [[TMP1]], align 2
; CHECK: if.else.i:
; CHECK-NEXT: [[ADD_PTR_I_I_I_I7_I:%.*]] = getelementptr inbounds i8, ptr [[F_VAL]], i64 16
; CHECK-NEXT: store half [[VAL1]], ptr [[ADD_PTR_I_I_I_I7_I]], align 2
; CHECK-NEXT: br label [[BADCHILD_EXIT]]
; CHECK: badChild.exit:
; CHECK-NEXT: [[THIS_64_VAL_SINK_I:%.*]] = phi ptr [ [[F_VAL]], [[IF_ELSE_I]] ], [ [[ADD_PTR_I_I_I_I_I]], [[IF_THEN_I]] ]
; CHECK-NEXT: store i16 [[VAL2]], ptr [[THIS_64_VAL_SINK_I]], align 2
; CHECK-NEXT: ret ptr [[F]] ; CHECK-NEXT: ret ptr [[F]]
; ;
entry: entry:
call void @badChild(ptr align 8 dereferenceable(72) %f, half %val1, i16 %val2, i32 %val3) #4 call void @badChild(ptr align 8 dereferenceable(72) %f, half %val1, i16 %val2, i32 %val3) #4
ret ptr %f ret ptr %f
} }
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