[LegalizeTypes][RISCV] Add a special case for (add X, -1) to ExpandIntRes_ADDSUB

[liaolucy]

Summary

On targets without ADDCARRY or ADDE, we need to emit a separate
SETCC to determine carry from the low half to the high half.
The high half is calculated by a series of ADDs.

When RHSLo and RHSHi are -1, without this patch, we get:

Hi = (add (add LHSHi,(setult Lo, LHSLo), -1)

Where as with the patch we get:

Hi = (sub LHSHi, (seteq LHSLo, 0))

Only RHSLo is -1 we can instead do (setne Lo, 0).

Similar to gcc: https://godbolt.org/z/M83f6rz39

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

3048

This overwrites the Hi that was calculated above and is only correct if HiOps[1] is also all ones.

[liaolucy]

Address comment.
Add Only RHSLo is -1 we can instead do (setne Lo, 0) and more testcases, like gcc: https://godbolt.org/z/M83f6rz39

[craig.topper]

LGTM

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

if (N->getOpcode() == ISD::ADD) {
     Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
     Hi = DAG.getNode(ISD::ADD, dl, NVT, ArrayRef(HiOps, 2));
     SDValue Cmp;
     // Special case: X+1 has a carry out if X+1==0. This may reduce the live
     // range of X. We assume comparing with 0 is cheap.
     if (isOneConstant(LoOps[1]))
       Cmp = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo,
                          DAG.getConstant(0, dl, NVT), ISD::SETEQ);
+    else if (isAllOnesConstant(LoOps[1])) {
+      if (isAllOnesConstant(HiOps[1]))
+        Cmp = DAG.getSetCC(dl, getSetCCResultType(NVT), LoOps[0],
+                           DAG.getConstant(0, dl, NVT), ISD::SETEQ);
       else
+        Cmp = DAG.getSetCC(dl, getSetCCResultType(NVT), LoOps[0],
+                           DAG.getConstant(0, dl, NVT), ISD::SETNE);
+    } else
       Cmp = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
                          ISD::SETULT);
 
     SDValue Carry;
     if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent)
       Carry = DAG.getZExtOrTrunc(Cmp, dl, NVT);
     else
       Carry = DAG.getSelect(dl, NVT, Cmp, DAG.getConstant(1, dl, NVT),
                              DAG.getConstant(0, dl, NVT));
 
+    if (isAllOnesConstant(LoOps[1]) && isAllOnesConstant(HiOps[1]))
+      Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps[0], Carry);
+    else
       Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry);
   } else {
     Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
     Hi = DAG.getNode(ISD::SUB, dl, NVT, ArrayRef(HiOps, 2));
     SDValue Cmp =
       DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
                    LoOps[0], LoOps[1], ISD::SETULT);
 
     SDValue Borrow;

llvm/test/CodeGen/RISCV/alu64.ll

 ; RV32I-LABEL: sraw:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sra a0, a0, a2
 ; RV32I-NEXT:    ret
   %1 = trunc i64 %a to i32
   %2 = ashr i32 %1, %b
   ret i32 %2
 }
+
+define i64 @add_hi_and_lo_negone(i64 %0) {
+; RV64I-LABEL: add_hi_and_lo_negone:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a0, a0, -1
+; RV64I-NEXT:    ret
+;
+; RV32I-LABEL: add_hi_and_lo_negone:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    seqz a2, a0
+; RV32I-NEXT:    sub a1, a1, a2
+; RV32I-NEXT:    addi a0, a0, -1
+; RV32I-NEXT:    ret
+  %2 = add nsw i64 %0, -1
+  ret i64 %2
+}
+
+define i64 @add_hi_zero_lo_negone(i64 %0) {
+; RV64I-LABEL: add_hi_zero_lo_negone:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    li a1, -1
+; RV64I-NEXT:    srli a1, a1, 32
+; RV64I-NEXT:    add a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV32I-LABEL: add_hi_zero_lo_negone:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    snez a2, a0
+; RV32I-NEXT:    add a1, a1, a2
+; RV32I-NEXT:    addi a0, a0, -1
+; RV32I-NEXT:    ret
+  %2 = add i64 %0, 4294967295
+  ret i64 %2
+}
+
+define i64 @add_lo_negone(i64 %0) {
+; RV64I-LABEL: add_lo_negone:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    li a1, -1
+; RV64I-NEXT:    slli a1, a1, 32
+; RV64I-NEXT:    addi a1, a1, -1
+; RV64I-NEXT:    add a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV32I-LABEL: add_lo_negone:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    snez a2, a0
+; RV32I-NEXT:    add a1, a1, a2
+; RV32I-NEXT:    addi a1, a1, -2
+; RV32I-NEXT:    addi a0, a0, -1
+; RV32I-NEXT:    ret
+  %2 = add nsw i64 %0, -4294967297
+  ret i64 %2
+}
+
+define i64 @add_hi_one_lo_negone(i64 %0) {
+; RV64I-LABEL: add_hi_one_lo_negone:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    li a1, -1
+; RV64I-NEXT:    srli a1, a1, 31
+; RV64I-NEXT:    add a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV32I-LABEL: add_hi_one_lo_negone:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    snez a2, a0
+; RV32I-NEXT:    add a1, a1, a2
+; RV32I-NEXT:    addi a1, a1, 1
+; RV32I-NEXT:    addi a0, a0, -1
+; RV32I-NEXT:    ret
+  %2 = add nsw i64 %0, 8589934591
+  ret i64 %2
+}

llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll

 ; RV32I-NEXT:    or a1, a4, a5
 ; RV32I-NEXT:    seqz a1, a1
 ; RV32I-NEXT:    or a0, a1, a0
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:    mv a3, s1
 ; RV32I-NEXT:    bnez a0, .LBB7_1
 ; RV32I-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB7_2 Depth=1
+; RV32I-NEXT:    seqz a0, a4
+; RV32I-NEXT:    sub a3, a5, a0
 ; RV32I-NEXT:    addi a2, a4, -1
-; RV32I-NEXT:    sltu a0, a2, a4
-; RV32I-NEXT:    add a0, a5, a0
-; RV32I-NEXT:    addi a3, a0, -1
 ; RV32I-NEXT:    j .LBB7_1
 ; RV32I-NEXT:  .LBB7_7: # %atomicrmw.end
 ; RV32I-NEXT:    mv a0, a4
 ; RV32I-NEXT:    mv a1, a5
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload

 ; RV32IA-NEXT:    or a1, a4, a5
 ; RV32IA-NEXT:    seqz a1, a1
 ; RV32IA-NEXT:    or a0, a1, a0
 ; RV32IA-NEXT:    mv a2, s2
 ; RV32IA-NEXT:    mv a3, s1
 ; RV32IA-NEXT:    bnez a0, .LBB7_1
 ; RV32IA-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB7_2 Depth=1
+; RV32IA-NEXT:    seqz a0, a4
+; RV32IA-NEXT:    sub a3, a5, a0
 ; RV32IA-NEXT:    addi a2, a4, -1
-; RV32IA-NEXT:    sltu a0, a2, a4
-; RV32IA-NEXT:    add a0, a5, a0
-; RV32IA-NEXT:    addi a3, a0, -1
 ; RV32IA-NEXT:    j .LBB7_1
 ; RV32IA-NEXT:  .LBB7_7: # %atomicrmw.end
 ; RV32IA-NEXT:    mv a0, a4
 ; RV32IA-NEXT:    mv a1, a5
 ; RV32IA-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IA-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32IA-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32IA-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload

llvm/test/CodeGen/RISCV/overflow-intrinsics.ll

; RV64-NEXT:    ret
   ret i1 %ov
 }
 
 ; The overflow check may be against the input rather than the sum.
 
 define i1 @uaddo_i64_decrement_alt(i64 %x, ptr %p) {
 ; RV32-LABEL: uaddo_i64_decrement_alt:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    addi a3, a0, -1
-; RV32-NEXT:    sltu a4, a3, a0
-; RV32-NEXT:    add a4, a1, a4
-; RV32-NEXT:    addi a4, a4, -1
-; RV32-NEXT:    sw a3, 0(a2)
+; RV32-NEXT:    seqz a3, a0
+; RV32-NEXT:    sub a3, a1, a3
+; RV32-NEXT:    addi a4, a0, -1
+; RV32-NEXT:    sw a4, 0(a2)
 ; RV32-NEXT:    or a0, a0, a1
 ; RV32-NEXT:    snez a0, a0
-; RV32-NEXT:    sw a4, 4(a2)
+; RV32-NEXT:    sw a3, 4(a2)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: uaddo_i64_decrement_alt:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a2, a0, -1
 ; RV64-NEXT:    snez a0, a0
 ; RV64-NEXT:    sd a2, 0(a1)
 ; RV64-NEXT:    ret
   %a = add i64 %x, -1
   store i64 %a, ptr %p
   %ov = icmp ne i64 %x, 0
   ret i1 %ov
 }
 
 ; Make sure insertion is done correctly based on dominance.
 
 define i1 @uaddo_i64_decrement_alt_dom(i64 %x, ptr %p) {
 ; RV32-LABEL: uaddo_i64_decrement_alt_dom:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    or a3, a0, a1
 ; RV32-NEXT:    snez a3, a3
-; RV32-NEXT:    addi a4, a0, -1
-; RV32-NEXT:    sltu a0, a4, a0
-; RV32-NEXT:    add a0, a1, a0
+; RV32-NEXT:    seqz a4, a0
+; RV32-NEXT:    sub a1, a1, a4
 ; RV32-NEXT:    addi a0, a0, -1
-; RV32-NEXT:    sw a4, 0(a2)
-; RV32-NEXT:    sw a0, 4(a2)
+; RV32-NEXT:    sw a0, 0(a2)
+; RV32-NEXT:    sw a1, 4(a2)
 ; RV32-NEXT:    mv a0, a3
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: uaddo_i64_decrement_alt_dom:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    snez a2, a0
 ; RV64-NEXT:    addi a0, a0, -1
 ; RV64-NEXT:    sd a0, 0(a1)

 }
 
 ; Avoid hoisting a math op into a dominating block which would
 ; increase the critical path.
 
 define void @PR41129(ptr %p64) {
 ; RV32-LABEL: PR41129:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    lw a1, 4(a0)
-; RV32-NEXT:    lw a2, 0(a0)
-; RV32-NEXT:    or a3, a2, a1
+; RV32-NEXT:    lw a2, 4(a0)
+; RV32-NEXT:    lw a1, 0(a0)
+; RV32-NEXT:    or a3, a1, a2
 ; RV32-NEXT:    beqz a3, .LBB36_2
 ; RV32-NEXT:  # %bb.1: # %false
-; RV32-NEXT:    andi a2, a2, 7
+; RV32-NEXT:    andi a1, a1, 7
 ; RV32-NEXT:    sw zero, 4(a0)
-; RV32-NEXT:    sw a2, 0(a0)
+; RV32-NEXT:    sw a1, 0(a0)
 ; RV32-NEXT:    ret
 ; RV32-NEXT:  .LBB36_2: # %true
-; RV32-NEXT:    addi a3, a2, -1
-; RV32-NEXT:    sltu a2, a3, a2
-; RV32-NEXT:    add a1, a1, a2
+; RV32-NEXT:    seqz a3, a1
+; RV32-NEXT:    sub a2, a2, a3
 ; RV32-NEXT:    addi a1, a1, -1
-; RV32-NEXT:    sw a3, 0(a0)
-; RV32-NEXT:    sw a1, 4(a0)
+; RV32-NEXT:    sw a1, 0(a0)
+; RV32-NEXT:    sw a2, 4(a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: PR41129:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    ld a1, 0(a0)
 ; RV64-NEXT:    beqz a1, .LBB36_2
 ; RV64-NEXT:  # %bb.1: # %false
 ; RV64-NEXT:    andi a1, a1, 7

llvm/test/CodeGen/RISCV/sext-zext-trunc.ll

; RV64I-NEXT:    ret
   %xor = xor i1 %x, 1
   %sext = sext i1 %xor to i32
   ret i32 %sext
 }
 
 define i64 @sext_of_not_i64(i1 %x) {
 ; RV32I-LABEL: sext_of_not_i64:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    andi a1, a0, 1
-; RV32I-NEXT:    addi a0, a1, -1
-; RV32I-NEXT:    sltu a1, a0, a1
-; RV32I-NEXT:    addi a1, a1, -1
+; RV32I-NEXT:    andi a0, a0, 1
+; RV32I-NEXT:    addi a0, a0, -1
+; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: sext_of_not_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    andi a0, a0, 1
 ; RV64I-NEXT:    addi a0, a0, -1
 ; RV64I-NEXT:    ret
   %xor = xor i1 %x, 1
; RV64I-NEXT:    ret
   ret i32 %dec
 }
 
 define i64 @dec_of_zexted_cmp_i64(i64 %x) {
 ; RV32I-LABEL: dec_of_zexted_cmp_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    xori a0, a0, 7
 ; RV32I-NEXT:    or a0, a0, a1
-; RV32I-NEXT:    seqz a1, a0
-; RV32I-NEXT:    addi a0, a1, -1
-; RV32I-NEXT:    sltu a1, a0, a1
-; RV32I-NEXT:    addi a1, a1, -1
+; RV32I-NEXT:    seqz a0, a0
+; RV32I-NEXT:    addi a0, a0, -1
+; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: dec_of_zexted_cmp_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a0, a0, -7
 ; RV64I-NEXT:    seqz a0, a0
 ; RV64I-NEXT:    addi a0, a0, -1
 ; RV64I-NEXT:    ret
   %cmp = icmp eq i64 %x, 7
   %zext = zext i1 %cmp to i64
   %dec = sub i64 %zext, 1
   ret i64 %dec
 }