AMDGPU: Fix missing MIR serialization for PSInputAddr/PSInputEnable

[arsenm]

Summary

Resuming any mir test for a pixel shader would assert in the AsmPrinter.

[arsenm]

ping

[critson]

LGTM, but one question about the diff preparation.

llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h

282

I don't understand this part of the diff, since this is how the header is already defined.

[arsenm]

llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h

282

You’re probably confusing the actual MFI definition and the yaml mirror, which is what this is

[critson]

LGTM

llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h

282

Correct, I had not appreciated there were two definitions with the same name in different namespaces.

[arsenm]

7ac3ab34cb7aa3da1ff1b0c024a8767e089519cd

llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h

struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {
   StringValue ScratchRSrcReg = "$private_rsrc_reg";
   StringValue FrameOffsetReg = "$fp_reg";
   StringValue StackPtrOffsetReg = "$sp_reg";
 
   unsigned BytesInStackArgArea = 0;
   bool ReturnsVoid = true;
 
   std::optional<SIArgumentInfo> ArgInfo;
+
+  unsigned PSInputAddr = 0;
+  unsigned PSInputEnable = 0;
+
   SIMode Mode;
   std::optional<FrameIndex> ScavengeFI;
   StringValue VGPRForAGPRCopy;
 
   SIMachineFunctionInfo() = default;
   SIMachineFunctionInfo(const llvm::SIMachineFunctionInfo &,
                         const TargetRegisterInfo &TRI,
                         const llvm::MachineFunction &MF);
YamlIO.mapOptional("scratchRSrcReg", MFI.ScratchRSrcReg,
                        StringValue("$private_rsrc_reg"));
     YamlIO.mapOptional("frameOffsetReg", MFI.FrameOffsetReg,
                        StringValue("$fp_reg"));
     YamlIO.mapOptional("stackPtrOffsetReg", MFI.StackPtrOffsetReg,
                        StringValue("$sp_reg"));
     YamlIO.mapOptional("bytesInStackArgArea", MFI.BytesInStackArgArea, 0u);
     YamlIO.mapOptional("returnsVoid", MFI.ReturnsVoid, true);
     YamlIO.mapOptional("argumentInfo", MFI.ArgInfo);
+    YamlIO.mapOptional("psInputAddr", MFI.PSInputAddr, 0u);
+    YamlIO.mapOptional("psInputEnable", MFI.PSInputEnable, 0u);
     YamlIO.mapOptional("mode", MFI.Mode, SIMode());
     YamlIO.mapOptional("highBitsOf32BitAddress",
                        MFI.HighBitsOf32BitAddress, 0u);
     YamlIO.mapOptional("occupancy", MFI.Occupancy, 0);
     YamlIO.mapOptional("wwmReservedRegs", MFI.WWMReservedRegs);
     YamlIO.mapOptional("scavengeFI", MFI.ScavengeFI);
     YamlIO.mapOptional("vgprForAGPRCopy", MFI.VGPRForAGPRCopy,
                        StringValue()); // Don't print out when it's empty.

llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

: ExplicitKernArgSize(MFI.getExplicitKernArgSize()),
       HasSpilledVGPRs(MFI.hasSpilledVGPRs()),
       HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()),
       Occupancy(MFI.getOccupancy()),
       ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
       FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
       StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
       BytesInStackArgArea(MFI.getBytesInStackArgArea()),
       ReturnsVoid(MFI.returnsVoid()),
-      ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)), Mode(MFI.getMode()) {
+      ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)),
+      PSInputAddr(MFI.getPSInputAddr()),
+      PSInputEnable(MFI.getPSInputEnable()),
+      Mode(MFI.getMode()) {
   for (Register Reg : MFI.getWWMReservedRegs())
     WWMReservedRegs.push_back(regToString(Reg, TRI));
 
   if (MFI.getVGPRForAGPRCopy())
     VGPRForAGPRCopy = regToString(MFI.getVGPRForAGPRCopy(), TRI);
   auto SFI = MFI.getOptionalScavengeFI();
   if (SFI)
     ScavengeFI = yaml::FrameIndex(*SFI, MF.getFrameInfo());
 }
 
 void yaml::SIMachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) {
   MappingTraits<SIMachineFunctionInfo>::mapping(YamlIO, *this);
 }
 
 bool SIMachineFunctionInfo::initializeBaseYamlFields(
     const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF,
     PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) {
   ExplicitKernArgSize = YamlMFI.ExplicitKernArgSize;
   MaxKernArgAlign = YamlMFI.MaxKernArgAlign;
   LDSSize = YamlMFI.LDSSize;
   GDSSize = YamlMFI.GDSSize;
   DynLDSAlign = YamlMFI.DynLDSAlign;
+  PSInputAddr = YamlMFI.PSInputAddr;
+  PSInputEnable = YamlMFI.PSInputEnable;
   HighBitsOf32BitAddress = YamlMFI.HighBitsOf32BitAddress;
   Occupancy = YamlMFI.Occupancy;
   IsEntryFunction = YamlMFI.IsEntryFunction;
   NoSignedZerosFPMath = YamlMFI.NoSignedZerosFPMath;
   MemoryBound = YamlMFI.MemoryBound;
   WaveLimiter = YamlMFI.WaveLimiter;
   HasSpilledSGPRs = YamlMFI.HasSpilledSGPRs;
   HasSpilledVGPRs = YamlMFI.HasSpilledVGPRs;

llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll

 ; AFTER-PEI-NEXT: bytesInStackArgArea: 0
 ; AFTER-PEI-NEXT: returnsVoid: true
 ; AFTER-PEI-NEXT: argumentInfo:
 ; AFTER-PEI-NEXT:   privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
 ; AFTER-PEI-NEXT:   kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }
 ; AFTER-PEI-NEXT:   workGroupIDX:    { reg: '$sgpr6' }
 ; AFTER-PEI-NEXT:   privateSegmentWaveByteOffset: { reg: '$sgpr7' }
 ; AFTER-PEI-NEXT:   workItemIDX:     { reg: '$vgpr0' }
+; AFTER-PEI-NEXT: psInputAddr:     0
+; AFTER-PEI-NEXT: psInputEnable:   0
 ; AFTER-PEI-NEXT: mode:
 ; AFTER-PEI-NEXT:   ieee:            true
 ; AFTER-PEI-NEXT:   dx10-clamp:      true
 ; AFTER-PEI-NEXT:   fp32-input-denormals: true
 ; AFTER-PEI-NEXT:   fp32-output-denormals: true
 ; AFTER-PEI-NEXT:   fp64-fp16-input-denormals: true
 ; AFTER-PEI-NEXT:   fp64-fp16-output-denormals: true
 ; AFTER-PEI-NEXT: highBitsOf32BitAddress: 0

llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir

 # FULL-NEXT: workGroupIDY:    { reg: '$sgpr13' }
 # FULL-NEXT: workGroupIDZ:    { reg: '$sgpr14' }
 # FULL-NEXT: LDSKernelId:     { reg: '$sgpr15' }
 # FULL-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr7' }
 # FULL-NEXT: implicitArgPtr:  { reg: '$sgpr8_sgpr9' }
 # FULL-NEXT: workItemIDX:     { reg: '$vgpr0' }
 # FULL-NEXT: workItemIDY:     { reg: '$vgpr31', mask: 1047552 }
 # FULL-NEXT: workItemIDZ:     { reg: '$vgpr31', mask: 1072693248 }
+# FULL-NEXT: psInputAddr:     0
+# FULL-NEXT: psInputEnable:   0
 # FULL-NEXT: mode:
 # FULL-NEXT: ieee: true
 # FULL-NEXT: dx10-clamp: true
 # FULL-NEXT: fp32-input-denormals: true
 # FULL-NEXT: fp32-output-denormals: true
 # FULL-NEXT: fp64-fp16-input-denormals: true
 # FULL-NEXT: fp64-fp16-output-denormals: true
 # FULL-NEXT:  highBitsOf32BitAddress: 0

 # FULL-NEXT: workGroupIDX:    { reg: '$sgpr12' }
 # FULL-NEXT: workGroupIDY:    { reg: '$sgpr13' }
 # FULL-NEXT: workGroupIDZ:    { reg: '$sgpr14' }
 # FULL-NEXT: LDSKernelId:     { reg: '$sgpr15' }
 # FULL-NEXT: implicitArgPtr:  { reg: '$sgpr8_sgpr9' }
 # FULL-NEXT: workItemIDX:     { reg: '$vgpr31', mask: 1023 }
 # FULL-NEXT: workItemIDY:     { reg: '$vgpr31', mask: 1047552 }
 # FULL-NEXT: workItemIDZ:     { reg: '$vgpr31', mask: 1072693248 }
+# FULL-NEXT: psInputAddr:     0
+# FULL-NEXT: psInputEnable:   0
 # FULL-NEXT: mode:
 # FULL-NEXT: ieee: true
 # FULL-NEXT: dx10-clamp: true
 # FULL-NEXT: fp32-input-denormals: true
 # FULL-NEXT: fp32-output-denormals: true
 # FULL-NEXT: fp64-fp16-input-denormals: true
 # FULL-NEXT: fp64-fp16-output-denormals: true
 # FULL-NEXT:  highBitsOf32BitAddress: 0

 # FULL-NEXT: workGroupIDX:    { reg: '$sgpr12' }
 # FULL-NEXT: workGroupIDY:    { reg: '$sgpr13' }
 # FULL-NEXT: workGroupIDZ:    { reg: '$sgpr14' }
 # FULL-NEXT: LDSKernelId:     { reg: '$sgpr15' }
 # FULL-NEXT: implicitArgPtr:  { reg: '$sgpr8_sgpr9' }
 # FULL-NEXT: workItemIDX:     { reg: '$vgpr31', mask: 1023 }
 # FULL-NEXT: workItemIDY:     { reg: '$vgpr31', mask: 1047552 }
 # FULL-NEXT: workItemIDZ:     { reg: '$vgpr31', mask: 1072693248 }
+# FULL-NEXT: psInputAddr:     0
+# FULL-NEXT: psInputEnable:   0
 # FULL-NEXT: mode:
 # FULL-NEXT: ieee: true
 # FULL-NEXT: dx10-clamp: true
 # FULL-NEXT: fp32-input-denormals: true
 # FULL-NEXT: fp32-output-denormals: true
 # FULL-NEXT: fp64-fp16-input-denormals: true
 # FULL-NEXT: fp64-fp16-output-denormals: true
 # FULL-NEXT:  highBitsOf32BitAddress: 0

 # FULL-NEXT: workGroupIDX:    { reg: '$sgpr12' }
 # FULL-NEXT: workGroupIDY:    { reg: '$sgpr13' }
 # FULL-NEXT: workGroupIDZ:    { reg: '$sgpr14' }
 # FULL-NEXT: LDSKernelId:     { reg: '$sgpr15' }
 # FULL-NEXT: implicitArgPtr:  { reg: '$sgpr8_sgpr9' }
 # FULL-NEXT: workItemIDX:     { reg: '$vgpr31', mask: 1023 }
 # FULL-NEXT: workItemIDY:     { reg: '$vgpr31', mask: 1047552 }
 # FULL-NEXT: workItemIDZ:     { reg: '$vgpr31', mask: 1072693248 }
+# FULL-NEXT: psInputAddr:     0
+# FULL-NEXT: psInputEnable:   0
 # FULL-NEXT: mode:
 # FULL-NEXT: ieee: true
 # FULL-NEXT: dx10-clamp: true
 # FULL-NEXT: fp32-input-denormals: true
 # FULL-NEXT: fp32-output-denormals: true
 # FULL-NEXT: fp64-fp16-input-denormals: true
 # FULL-NEXT: fp64-fp16-output-denormals: true
 # FULL-NEXT:  highBitsOf32BitAddress: 0

llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll

 ; CHECK-NEXT: bytesInStackArgArea: 0
 ; CHECK-NEXT: returnsVoid: true
 ; CHECK-NEXT: argumentInfo:
 ; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
 ; CHECK-NEXT: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }
 ; CHECK-NEXT: workGroupIDX: { reg: '$sgpr6' }
 ; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr7' }
 ; CHECK-NEXT: workItemIDX: { reg: '$vgpr0' }
+; CHECK-NEXT: psInputAddr: 0
+; CHECK-NEXT: psInputEnable: 0
 ; CHECK-NEXT: mode:
 ; CHECK-NEXT: ieee: true
 ; CHECK-NEXT: dx10-clamp: true
 ; CHECK-NEXT: fp32-input-denormals: true
 ; CHECK-NEXT: fp32-output-denormals: true
 ; CHECK-NEXT: fp64-fp16-input-denormals: true
 ; CHECK-NEXT: fp64-fp16-output-denormals: true
 ; CHECK-NEXT: highBitsOf32BitAddress: 0

 ; CHECK-NEXT: scratchRSrcReg:  '$sgpr96_sgpr97_sgpr98_sgpr99'
 ; CHECK-NEXT: frameOffsetReg:  '$fp_reg'
 ; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'
 ; CHECK-NEXT: bytesInStackArgArea: 0
 ; CHECK-NEXT: returnsVoid: true
 ; CHECK-NEXT: argumentInfo:
 ; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr3' }
 ; CHECK-NEXT: implicitBufferPtr: { reg: '$sgpr0_sgpr1' }
+; CHECK-NEXT: psInputAddr: 1
+; CHECK-NEXT: psInputEnable: 1
 ; CHECK-NEXT: mode:
 ; CHECK-NEXT: ieee: false
 ; CHECK-NEXT: dx10-clamp: true
 ; CHECK-NEXT: fp32-input-denormals: true
 ; CHECK-NEXT: fp32-output-denormals: true
 ; CHECK-NEXT: fp64-fp16-input-denormals: true
 ; CHECK-NEXT: fp64-fp16-output-denormals: true
 ; CHECK-NEXT: highBitsOf32BitAddress: 0
 ; CHECK-NEXT: occupancy: 10
 ; CHECK-NEXT: vgprForAGPRCopy: ''
 ; CHECK-NEXT: body:
 define amdgpu_ps void @ps_shader(i32 %arg0, i32 inreg %arg1) {
   %gep = getelementptr inbounds [128 x i32], ptr addrspace(2) @gds, i32 0, i32 %arg0
   atomicrmw add ptr addrspace(2) %gep, i32 8 seq_cst
   ret void
 }
 
+; CHECK-LABEL: {{^}}name: ps_shader_ps_input_enable
+; CHECK: machineFunctionInfo:
+; CHECK: psInputAddr: 36983
+; CHECK-NEXT: psInputEnable: 1{{$}}
+define amdgpu_ps void @ps_shader_ps_input_enable(i32 %arg0, i32 inreg %arg1) #7 {
+  %gep = getelementptr inbounds [128 x i32], ptr addrspace(2) @gds, i32 0, i32 %arg0
+  atomicrmw add ptr addrspace(2) %gep, i32 8 seq_cst
+  ret void
+}
+
 ; CHECK-LABEL: {{^}}name: gds_size_shader
 ; CHECK: gdsSize: 4096
 define amdgpu_ps void @gds_size_shader(i32 %arg0, i32 inreg %arg1) #5 {
   ret void
 }
 
 ; CHECK-LABEL: {{^}}name: function
 ; CHECK: machineFunctionInfo:

 ; CHECK-NEXT: workGroupIDX:    { reg: '$sgpr12' }
 ; CHECK-NEXT: workGroupIDY:    { reg: '$sgpr13' }
 ; CHECK-NEXT: workGroupIDZ:    { reg: '$sgpr14' }
 ; CHECK-NEXT: LDSKernelId:     { reg: '$sgpr15' }
 ; CHECK-NEXT: implicitArgPtr:  { reg: '$sgpr8_sgpr9' }
 ; CHECK-NEXT: workItemIDX:     { reg: '$vgpr31', mask: 1023 }
 ; CHECK-NEXT: workItemIDY:     { reg: '$vgpr31', mask: 1047552 }
 ; CHECK-NEXT: workItemIDZ:     { reg: '$vgpr31', mask: 1072693248 }
+; CHECK-NEXT: psInputAddr: 0
+; CHECK-NEXT: psInputEnable: 0
 ; CHECK-NEXT: mode:
 ; CHECK-NEXT: ieee: true
 ; CHECK-NEXT: dx10-clamp: true
 ; CHECK-NEXT: fp32-input-denormals: true
 ; CHECK-NEXT: fp32-output-denormals: true
 ; CHECK-NEXT: fp64-fp16-input-denormals: true
 ; CHECK-NEXT: fp64-fp16-output-denormals: true
 ; CHECK-NEXT: highBitsOf32BitAddress: 0

 ; CHECK-NEXT: workGroupIDX:    { reg: '$sgpr12' }
 ; CHECK-NEXT: workGroupIDY:    { reg: '$sgpr13' }
 ; CHECK-NEXT: workGroupIDZ:    { reg: '$sgpr14' }
 ; CHECK-NEXT: LDSKernelId:     { reg: '$sgpr15' }
 ; CHECK-NEXT: implicitArgPtr:  { reg: '$sgpr8_sgpr9' }
 ; CHECK-NEXT: workItemIDX:     { reg: '$vgpr31', mask: 1023 }
 ; CHECK-NEXT: workItemIDY:     { reg: '$vgpr31', mask: 1047552 }
 ; CHECK-NEXT: workItemIDZ:     { reg: '$vgpr31', mask: 1072693248 }
+; CHECK-NEXT: psInputAddr: 0
+; CHECK-NEXT: psInputEnable: 0
 ; CHECK-NEXT: mode:
 ; CHECK-NEXT: ieee: true
 ; CHECK-NEXT: dx10-clamp: true
 ; CHECK-NEXT: fp32-input-denormals: true
 ; CHECK-NEXT: fp32-output-denormals: true
 ; CHECK-NEXT: fp64-fp16-input-denormals: true
 ; CHECK-NEXT: fp64-fp16-output-denormals: true
 ; CHECK-NEXT: highBitsOf32BitAddress: 0

 
 attributes #0 = { "no-signed-zeros-fp-math" = "true" }
 attributes #1 = { "amdgpu-dx10-clamp" = "false" }
 attributes #2 = { "amdgpu-ieee" = "false" }
 attributes #3 = { "amdgpu-dx10-clamp" = "false" "amdgpu-ieee" = "false" }
 attributes #4 = { "amdgpu-32bit-address-high-bits"="0xffff8000" }
 attributes #5 = { "amdgpu-gds-size"="4096" }
 attributes #6 = { convergent nounwind readnone willreturn }
+attributes #7 = { "InitialPSInputAddr"="36983" }