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Differential D145175

[ASAN] Support memory checks on scalable vector typed loads and stores
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Authored by reames on Mar 2 2023, 11:32 AM.

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Reviewers
kito-cheng
asb
craig.topper
usama54321
MaskRay
Commits
rG32188047fcf8: [ASAN] Support memory checks on scalable vector typed loads and stores
Summary

This only covers the common load/store case. There will be further patches required for masked load/store and some of the fast-path optimization cases.

Diff Detail

Event Timeline

reames created this revision.Mar 2 2023, 11:32 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 2 2023, 11:32 AM
Herald added subscribers: Enna1, bollu, hiraditya, mcrosier. · View Herald Transcript
reames requested review of this revision.Mar 2 2023, 11:32 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 2 2023, 11:32 AM
Herald added a subscriber: alextsao1999. · View Herald Transcript
craig.topper added inline comments.Mar 2 2023, 12:00 PM
llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
1425

Should we call TypeStoreSize.getFixedValue() while we're here instead of using implicit conversion to unsigned?

Harbormaster completed remote builds in B217022: Diff 501931.Mar 2 2023, 12:33 PM
reames added inline comments.Mar 2 2023, 12:42 PM
llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
1425

Honestly, it should probably be a switch inside a condition. Mind if I do that as a separate post commit? I'd like to keep the change isolated here.

craig.topper added inline comments.Mar 2 2023, 1:13 PM
llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
1425

Sure.

reames added a child revision: D145198: [ASAN] Support memory checks on scalable vector typed masked load and store.Mar 2 2023, 3:05 PM
kito-cheng added a comment.Mar 6 2023, 6:39 PM

Changes are look reasonable and good to me, but I am also new for ASan too, I guess we need few more eye to review.

asb accepted this revision.Mar 8 2023, 2:12 AM

My familiarity with ASan is also low, but this seems correct to me.

This revision is now accepted and ready to land.Mar 8 2023, 2:12 AM
This revision was landed with ongoing or failed builds.Mar 9 2023, 8:15 AM
Closed by commit rG32188047fcf8: [ASAN] Support memory checks on scalable vector typed loads and stores (authored by reames). · Explain Why
This revision was automatically updated to reflect the committed changes.
reames added a commit: rG32188047fcf8: [ASAN] Support memory checks on scalable vector typed loads and stores.
reames mentioned this in rGc24d44fd869a: [ASAN] Address a style issue noticed during review of D145175 [nfc].Mar 9 2023, 8:51 AM

Revision Contents

PathSize
llvm/
lib/
Transforms/
Instrumentation/
15 lines
test/
Instrumentation/
AddressSanitizer/
600 lines

Diff 503780

llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp

Show First 20 Lines • Show All 1,415 Lines • ▼ Show 20 Lines
static void doInstrumentAddress(AddressSanitizer *Pass, Instruction *I, static void doInstrumentAddress(AddressSanitizer *Pass, Instruction *I,
Instruction *InsertBefore, Value *Addr, Instruction *InsertBefore, Value *Addr,
MaybeAlign Alignment, unsigned Granularity, MaybeAlign Alignment, unsigned Granularity,
TypeSize TypeStoreSize, bool IsWrite, TypeSize TypeStoreSize, bool IsWrite,
Value *SizeArgument, bool UseCalls, Value *SizeArgument, bool UseCalls,
uint32_t Exp) { uint32_t Exp) {
// Instrument a 1-, 2-, 4-, 8-, or 16- byte access with one check // Instrument a 1-, 2-, 4-, 8-, or 16- byte access with one check
// if the data is properly aligned. // if the data is properly aligned.
if ((TypeStoreSize == 8 || TypeStoreSize == 16 || TypeStoreSize == 32 || TypeStoreSize == 64 || if (!TypeStoreSize.isScalable() &&
TypeStoreSize == 128) && (TypeStoreSize == 8 || TypeStoreSize == 16 || TypeStoreSize == 32 ||
craig.topperUnsubmitted
Not Done
ReplyInline Actions

Should we call TypeStoreSize.getFixedValue() while we're here instead of using implicit conversion to unsigned?

craig.topper: Should we call TypeStoreSize.getFixedValue() while we're here instead of using implicit…
reamesAuthorUnsubmitted
Done
ReplyInline Actions

Honestly, it should probably be a switch inside a condition. Mind if I do that as a separate post commit? I'd like to keep the change isolated here.

reames: Honestly, it should probably be a switch inside a condition. Mind if I do that as a separate…
craig.topperUnsubmitted
Not Done
ReplyInline Actions

Sure.

craig.topper: Sure.
TypeStoreSize == 64 || TypeStoreSize == 128) &&
(!Alignment || *Alignment >= Granularity || *Alignment >= TypeStoreSize / 8)) (!Alignment || *Alignment >= Granularity || *Alignment >= TypeStoreSize / 8))
return Pass->instrumentAddress(I, InsertBefore, Addr, TypeStoreSize, IsWrite, return Pass->instrumentAddress(I, InsertBefore, Addr, TypeStoreSize, IsWrite,
nullptr, UseCalls, Exp); nullptr, UseCalls, Exp);
Pass->instrumentUnusualSizeOrAlignment(I, InsertBefore, Addr, TypeStoreSize, Pass->instrumentUnusualSizeOrAlignment(I, InsertBefore, Addr, TypeStoreSize,
IsWrite, nullptr, UseCalls, Exp); IsWrite, nullptr, UseCalls, Exp);
} }
static void instrumentMaskedLoadOrStore(AddressSanitizer *Pass, static void instrumentMaskedLoadOrStore(AddressSanitizer *Pass,
▲ Show 20 Lines • Show All 237 Lines • ▼ Show 20 Lines
// Instrument unusual size or unusual alignment. // Instrument unusual size or unusual alignment.
// We can not do it with a single check, so we do 1-byte check for the first // We can not do it with a single check, so we do 1-byte check for the first
// and the last bytes. We call __asan_report_*_n(addr, real_size) to be able // and the last bytes. We call __asan_report_*_n(addr, real_size) to be able
// to report the actual access size. // to report the actual access size.
void AddressSanitizer::instrumentUnusualSizeOrAlignment( void AddressSanitizer::instrumentUnusualSizeOrAlignment(
Instruction *I, Instruction *InsertBefore, Value *Addr, TypeSize TypeStoreSize, Instruction *I, Instruction *InsertBefore, Value *Addr, TypeSize TypeStoreSize,
bool IsWrite, Value *SizeArgument, bool UseCalls, uint32_t Exp) { bool IsWrite, Value *SizeArgument, bool UseCalls, uint32_t Exp) {
IRBuilder<> IRB(InsertBefore); IRBuilder<> IRB(InsertBefore);
Value *Size = ConstantInt::get(IntptrTy, TypeStoreSize / 8); Constant *MinBits =
ConstantInt::get(IntptrTy, TypeStoreSize.getKnownMinValue());
Value *NumBits =
!TypeStoreSize.isScalable() ? MinBits : IRB.CreateVScale(MinBits);
Value *Size = IRB.CreateLShr(NumBits, ConstantInt::get(IntptrTy, 3));
Value *AddrLong = IRB.CreatePointerCast(Addr, IntptrTy); Value *AddrLong = IRB.CreatePointerCast(Addr, IntptrTy);
if (UseCalls) { if (UseCalls) {
if (Exp == 0) if (Exp == 0)
IRB.CreateCall(AsanMemoryAccessCallbackSized[IsWrite][0], IRB.CreateCall(AsanMemoryAccessCallbackSized[IsWrite][0],
{AddrLong, Size}); {AddrLong, Size});
else else
IRB.CreateCall(AsanMemoryAccessCallbackSized[IsWrite][1], IRB.CreateCall(AsanMemoryAccessCallbackSized[IsWrite][1],
{AddrLong, Size, ConstantInt::get(IRB.getInt32Ty(), Exp)}); {AddrLong, Size, ConstantInt::get(IRB.getInt32Ty(), Exp)});
} else { } else {
Value *SizeMinusOne = IRB.CreateSub(Size, ConstantInt::get(IntptrTy, 1));
Value *LastByte = IRB.CreateIntToPtr( Value *LastByte = IRB.CreateIntToPtr(
IRB.CreateAdd(AddrLong, ConstantInt::get(IntptrTy, TypeStoreSize / 8 - 1)), IRB.CreateAdd(AddrLong, SizeMinusOne),
Addr->getType()); Addr->getType());
instrumentAddress(I, InsertBefore, Addr, 8, IsWrite, Size, false, Exp); instrumentAddress(I, InsertBefore, Addr, 8, IsWrite, Size, false, Exp);
instrumentAddress(I, InsertBefore, LastByte, 8, IsWrite, Size, false, Exp); instrumentAddress(I, InsertBefore, LastByte, 8, IsWrite, Size, false, Exp);
} }
} }
void ModuleAddressSanitizer::poisonOneInitializer(Function &GlobalInit, void ModuleAddressSanitizer::poisonOneInitializer(Function &GlobalInit,
GlobalValue *ModuleName) { GlobalValue *ModuleName) {
▲ Show 20 Lines • Show All 1,801 Lines • Show Last 20 Lines

llvm/test/Instrumentation/AddressSanitizer/vector-load-store.ll

Show All 16 Lines
; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP13:%.*]], !prof [[PROF0:![0-9]+]] ; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP13:%.*]], !prof [[PROF0:![0-9]+]]
; CHECK: 7: ; CHECK: 7:
; CHECK-NEXT: [[TMP8:%.*]] = and i64 [[TMP1]], 7 ; CHECK-NEXT: [[TMP8:%.*]] = and i64 [[TMP1]], 7
; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[TMP8]], 3 ; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[TMP8]], 3
; CHECK-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i8 ; CHECK-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i8
; CHECK-NEXT: [[TMP11:%.*]] = icmp sge i8 [[TMP10]], [[TMP5]] ; CHECK-NEXT: [[TMP11:%.*]] = icmp sge i8 [[TMP10]], [[TMP5]]
; CHECK-NEXT: br i1 [[TMP11]], label [[TMP12:%.*]], label [[TMP13]] ; CHECK-NEXT: br i1 [[TMP11]], label [[TMP12:%.*]], label [[TMP13]]
; CHECK: 12: ; CHECK: 12:
; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP1]]) #[[ATTR3:[0-9]+]] ; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP1]]) #[[ATTR4:[0-9]+]]
; CHECK-NEXT: unreachable ; CHECK-NEXT: unreachable
; CHECK: 13: ; CHECK: 13:
; CHECK-NEXT: [[TMP14:%.*]] = load <1 x i32>, ptr [[P]], align 4 ; CHECK-NEXT: [[TMP14:%.*]] = load <1 x i32>, ptr [[P]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; CALLS-LABEL: @load.v1i32( ; CALLS-LABEL: @load.v1i32(
; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64 ; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CALLS-NEXT: call void @__asan_load4(i64 [[TMP1]]) ; CALLS-NEXT: call void @__asan_load4(i64 [[TMP1]])
Show All 9 Lines
; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP2]], 17592186044416 ; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP2]], 17592186044416
; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr ; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1 ; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i8 [[TMP5]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i8 [[TMP5]], 0
; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP8:%.*]] ; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP8:%.*]]
; CHECK: 7: ; CHECK: 7:
; CHECK-NEXT: call void @__asan_report_load8(i64 [[TMP1]]) #[[ATTR3]] ; CHECK-NEXT: call void @__asan_report_load8(i64 [[TMP1]]) #[[ATTR4]]
; CHECK-NEXT: unreachable ; CHECK-NEXT: unreachable
; CHECK: 8: ; CHECK: 8:
; CHECK-NEXT: [[TMP9:%.*]] = load <2 x i32>, ptr [[P]], align 8 ; CHECK-NEXT: [[TMP9:%.*]] = load <2 x i32>, ptr [[P]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; CALLS-LABEL: @load.v2i32( ; CALLS-LABEL: @load.v2i32(
; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64 ; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CALLS-NEXT: call void @__asan_load8(i64 [[TMP1]]) ; CALLS-NEXT: call void @__asan_load8(i64 [[TMP1]])
Show All 9 Lines
; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP2]], 17592186044416 ; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP2]], 17592186044416
; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr ; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 2 ; CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 2
; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i16 [[TMP5]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i16 [[TMP5]], 0
; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP8:%.*]] ; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP8:%.*]]
; CHECK: 7: ; CHECK: 7:
; CHECK-NEXT: call void @__asan_report_load16(i64 [[TMP1]]) #[[ATTR3]] ; CHECK-NEXT: call void @__asan_report_load16(i64 [[TMP1]]) #[[ATTR4]]
; CHECK-NEXT: unreachable ; CHECK-NEXT: unreachable
; CHECK: 8: ; CHECK: 8:
; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i32>, ptr [[P]], align 16 ; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i32>, ptr [[P]], align 16
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; CALLS-LABEL: @load.v4i32( ; CALLS-LABEL: @load.v4i32(
; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64 ; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CALLS-NEXT: call void @__asan_load16(i64 [[TMP1]]) ; CALLS-NEXT: call void @__asan_load16(i64 [[TMP1]])
Show All 17 Lines
; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i8 [[TMP8]], 0 ; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i8 [[TMP8]], 0
; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP15:%.*]], !prof [[PROF0]] ; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP15:%.*]], !prof [[PROF0]]
; CHECK: 10: ; CHECK: 10:
; CHECK-NEXT: [[TMP11:%.*]] = and i64 [[TMP4]], 7 ; CHECK-NEXT: [[TMP11:%.*]] = and i64 [[TMP4]], 7
; CHECK-NEXT: [[TMP12:%.*]] = trunc i64 [[TMP11]] to i8 ; CHECK-NEXT: [[TMP12:%.*]] = trunc i64 [[TMP11]] to i8
; CHECK-NEXT: [[TMP13:%.*]] = icmp sge i8 [[TMP12]], [[TMP8]] ; CHECK-NEXT: [[TMP13:%.*]] = icmp sge i8 [[TMP12]], [[TMP8]]
; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP15]] ; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP15]]
; CHECK: 14: ; CHECK: 14:
; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP4]], i64 32) #[[ATTR3]] ; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP4]], i64 32) #[[ATTR4]]
; CHECK-NEXT: unreachable ; CHECK-NEXT: unreachable
; CHECK: 15: ; CHECK: 15:
; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[TMP3]] to i64 ; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[TMP3]] to i64
; CHECK-NEXT: [[TMP17:%.*]] = lshr i64 [[TMP16]], 3 ; CHECK-NEXT: [[TMP17:%.*]] = lshr i64 [[TMP16]], 3
; CHECK-NEXT: [[TMP18:%.*]] = or i64 [[TMP17]], 17592186044416 ; CHECK-NEXT: [[TMP18:%.*]] = or i64 [[TMP17]], 17592186044416
; CHECK-NEXT: [[TMP19:%.*]] = inttoptr i64 [[TMP18]] to ptr ; CHECK-NEXT: [[TMP19:%.*]] = inttoptr i64 [[TMP18]] to ptr
; CHECK-NEXT: [[TMP20:%.*]] = load i8, ptr [[TMP19]], align 1 ; CHECK-NEXT: [[TMP20:%.*]] = load i8, ptr [[TMP19]], align 1
; CHECK-NEXT: [[TMP21:%.*]] = icmp ne i8 [[TMP20]], 0 ; CHECK-NEXT: [[TMP21:%.*]] = icmp ne i8 [[TMP20]], 0
; CHECK-NEXT: br i1 [[TMP21]], label [[TMP22:%.*]], label [[TMP27:%.*]], !prof [[PROF0]] ; CHECK-NEXT: br i1 [[TMP21]], label [[TMP22:%.*]], label [[TMP27:%.*]], !prof [[PROF0]]
; CHECK: 22: ; CHECK: 22:
; CHECK-NEXT: [[TMP23:%.*]] = and i64 [[TMP16]], 7 ; CHECK-NEXT: [[TMP23:%.*]] = and i64 [[TMP16]], 7
; CHECK-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP23]] to i8 ; CHECK-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP23]] to i8
; CHECK-NEXT: [[TMP25:%.*]] = icmp sge i8 [[TMP24]], [[TMP20]] ; CHECK-NEXT: [[TMP25:%.*]] = icmp sge i8 [[TMP24]], [[TMP20]]
; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP27]] ; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP27]]
; CHECK: 26: ; CHECK: 26:
; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP16]], i64 32) #[[ATTR3]] ; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP16]], i64 32) #[[ATTR4]]
; CHECK-NEXT: unreachable ; CHECK-NEXT: unreachable
; CHECK: 27: ; CHECK: 27:
; CHECK-NEXT: [[TMP28:%.*]] = load <8 x i32>, ptr [[P]], align 32 ; CHECK-NEXT: [[TMP28:%.*]] = load <8 x i32>, ptr [[P]], align 32
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; CALLS-LABEL: @load.v8i32( ; CALLS-LABEL: @load.v8i32(
; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64 ; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CALLS-NEXT: call void @__asan_loadN(i64 [[TMP1]], i64 32) ; CALLS-NEXT: call void @__asan_loadN(i64 [[TMP1]], i64 32)
Show All 17 Lines
; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i8 [[TMP8]], 0 ; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i8 [[TMP8]], 0
; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP15:%.*]], !prof [[PROF0]] ; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP15:%.*]], !prof [[PROF0]]
; CHECK: 10: ; CHECK: 10:
; CHECK-NEXT: [[TMP11:%.*]] = and i64 [[TMP4]], 7 ; CHECK-NEXT: [[TMP11:%.*]] = and i64 [[TMP4]], 7
; CHECK-NEXT: [[TMP12:%.*]] = trunc i64 [[TMP11]] to i8 ; CHECK-NEXT: [[TMP12:%.*]] = trunc i64 [[TMP11]] to i8
; CHECK-NEXT: [[TMP13:%.*]] = icmp sge i8 [[TMP12]], [[TMP8]] ; CHECK-NEXT: [[TMP13:%.*]] = icmp sge i8 [[TMP12]], [[TMP8]]
; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP15]] ; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP15]]
; CHECK: 14: ; CHECK: 14:
; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP4]], i64 64) #[[ATTR3]] ; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP4]], i64 64) #[[ATTR4]]
; CHECK-NEXT: unreachable ; CHECK-NEXT: unreachable
; CHECK: 15: ; CHECK: 15:
; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[TMP3]] to i64 ; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[TMP3]] to i64
; CHECK-NEXT: [[TMP17:%.*]] = lshr i64 [[TMP16]], 3 ; CHECK-NEXT: [[TMP17:%.*]] = lshr i64 [[TMP16]], 3
; CHECK-NEXT: [[TMP18:%.*]] = or i64 [[TMP17]], 17592186044416 ; CHECK-NEXT: [[TMP18:%.*]] = or i64 [[TMP17]], 17592186044416
; CHECK-NEXT: [[TMP19:%.*]] = inttoptr i64 [[TMP18]] to ptr ; CHECK-NEXT: [[TMP19:%.*]] = inttoptr i64 [[TMP18]] to ptr
; CHECK-NEXT: [[TMP20:%.*]] = load i8, ptr [[TMP19]], align 1 ; CHECK-NEXT: [[TMP20:%.*]] = load i8, ptr [[TMP19]], align 1
; CHECK-NEXT: [[TMP21:%.*]] = icmp ne i8 [[TMP20]], 0 ; CHECK-NEXT: [[TMP21:%.*]] = icmp ne i8 [[TMP20]], 0
; CHECK-NEXT: br i1 [[TMP21]], label [[TMP22:%.*]], label [[TMP27:%.*]], !prof [[PROF0]] ; CHECK-NEXT: br i1 [[TMP21]], label [[TMP22:%.*]], label [[TMP27:%.*]], !prof [[PROF0]]
; CHECK: 22: ; CHECK: 22:
; CHECK-NEXT: [[TMP23:%.*]] = and i64 [[TMP16]], 7 ; CHECK-NEXT: [[TMP23:%.*]] = and i64 [[TMP16]], 7
; CHECK-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP23]] to i8 ; CHECK-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP23]] to i8
; CHECK-NEXT: [[TMP25:%.*]] = icmp sge i8 [[TMP24]], [[TMP20]] ; CHECK-NEXT: [[TMP25:%.*]] = icmp sge i8 [[TMP24]], [[TMP20]]
; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP27]] ; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP27]]
; CHECK: 26: ; CHECK: 26:
; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP16]], i64 64) #[[ATTR3]] ; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP16]], i64 64) #[[ATTR4]]
; CHECK-NEXT: unreachable ; CHECK-NEXT: unreachable
; CHECK: 27: ; CHECK: 27:
; CHECK-NEXT: [[TMP28:%.*]] = load <16 x i32>, ptr [[P]], align 64 ; CHECK-NEXT: [[TMP28:%.*]] = load <16 x i32>, ptr [[P]], align 64
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; CALLS-LABEL: @load.v16i32( ; CALLS-LABEL: @load.v16i32(
; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64 ; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CALLS-NEXT: call void @__asan_loadN(i64 [[TMP1]], i64 64) ; CALLS-NEXT: call void @__asan_loadN(i64 [[TMP1]], i64 64)
Show All 16 Lines
; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP13:%.*]], !prof [[PROF0]] ; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP13:%.*]], !prof [[PROF0]]
; CHECK: 7: ; CHECK: 7:
; CHECK-NEXT: [[TMP8:%.*]] = and i64 [[TMP1]], 7 ; CHECK-NEXT: [[TMP8:%.*]] = and i64 [[TMP1]], 7
; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[TMP8]], 3 ; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[TMP8]], 3
; CHECK-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i8 ; CHECK-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i8
; CHECK-NEXT: [[TMP11:%.*]] = icmp sge i8 [[TMP10]], [[TMP5]] ; CHECK-NEXT: [[TMP11:%.*]] = icmp sge i8 [[TMP10]], [[TMP5]]
; CHECK-NEXT: br i1 [[TMP11]], label [[TMP12:%.*]], label [[TMP13]] ; CHECK-NEXT: br i1 [[TMP11]], label [[TMP12:%.*]], label [[TMP13]]
; CHECK: 12: ; CHECK: 12:
; CHECK-NEXT: call void @__asan_report_store4(i64 [[TMP1]]) #[[ATTR3]] ; CHECK-NEXT: call void @__asan_report_store4(i64 [[TMP1]]) #[[ATTR4]]
; CHECK-NEXT: unreachable ; CHECK-NEXT: unreachable
; CHECK: 13: ; CHECK: 13:
; CHECK-NEXT: store <1 x i32> zeroinitializer, ptr [[P]], align 4 ; CHECK-NEXT: store <1 x i32> zeroinitializer, ptr [[P]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; CALLS-LABEL: @store.v1i32( ; CALLS-LABEL: @store.v1i32(
; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64 ; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CALLS-NEXT: call void @__asan_store4(i64 [[TMP1]]) ; CALLS-NEXT: call void @__asan_store4(i64 [[TMP1]])
Show All 9 Lines
; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP2]], 17592186044416 ; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP2]], 17592186044416
; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr ; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1 ; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1
; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i8 [[TMP5]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i8 [[TMP5]], 0
; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP8:%.*]] ; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP8:%.*]]
; CHECK: 7: ; CHECK: 7:
; CHECK-NEXT: call void @__asan_report_store8(i64 [[TMP1]]) #[[ATTR3]] ; CHECK-NEXT: call void @__asan_report_store8(i64 [[TMP1]]) #[[ATTR4]]
; CHECK-NEXT: unreachable ; CHECK-NEXT: unreachable
; CHECK: 8: ; CHECK: 8:
; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr [[P]], align 8 ; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr [[P]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; CALLS-LABEL: @store.v2i32( ; CALLS-LABEL: @store.v2i32(
; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64 ; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CALLS-NEXT: call void @__asan_store8(i64 [[TMP1]]) ; CALLS-NEXT: call void @__asan_store8(i64 [[TMP1]])
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; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP2]], 17592186044416 ; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP2]], 17592186044416
; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr ; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 2 ; CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 2
; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i16 [[TMP5]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i16 [[TMP5]], 0
; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP8:%.*]] ; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP8:%.*]]
; CHECK: 7: ; CHECK: 7:
; CHECK-NEXT: call void @__asan_report_store16(i64 [[TMP1]]) #[[ATTR3]] ; CHECK-NEXT: call void @__asan_report_store16(i64 [[TMP1]]) #[[ATTR4]]
; CHECK-NEXT: unreachable ; CHECK-NEXT: unreachable
; CHECK: 8: ; CHECK: 8:
; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr [[P]], align 16 ; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr [[P]], align 16
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; CALLS-LABEL: @store.v4i32( ; CALLS-LABEL: @store.v4i32(
; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64 ; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CALLS-NEXT: call void @__asan_store16(i64 [[TMP1]]) ; CALLS-NEXT: call void @__asan_store16(i64 [[TMP1]])
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; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i8 [[TMP8]], 0 ; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i8 [[TMP8]], 0
; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP15:%.*]], !prof [[PROF0]] ; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP15:%.*]], !prof [[PROF0]]
; CHECK: 10: ; CHECK: 10:
; CHECK-NEXT: [[TMP11:%.*]] = and i64 [[TMP4]], 7 ; CHECK-NEXT: [[TMP11:%.*]] = and i64 [[TMP4]], 7
; CHECK-NEXT: [[TMP12:%.*]] = trunc i64 [[TMP11]] to i8 ; CHECK-NEXT: [[TMP12:%.*]] = trunc i64 [[TMP11]] to i8
; CHECK-NEXT: [[TMP13:%.*]] = icmp sge i8 [[TMP12]], [[TMP8]] ; CHECK-NEXT: [[TMP13:%.*]] = icmp sge i8 [[TMP12]], [[TMP8]]
; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP15]] ; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP15]]
; CHECK: 14: ; CHECK: 14:
; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP4]], i64 32) #[[ATTR3]] ; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP4]], i64 32) #[[ATTR4]]
; CHECK-NEXT: unreachable ; CHECK-NEXT: unreachable
; CHECK: 15: ; CHECK: 15:
; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[TMP3]] to i64 ; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[TMP3]] to i64
; CHECK-NEXT: [[TMP17:%.*]] = lshr i64 [[TMP16]], 3 ; CHECK-NEXT: [[TMP17:%.*]] = lshr i64 [[TMP16]], 3
; CHECK-NEXT: [[TMP18:%.*]] = or i64 [[TMP17]], 17592186044416 ; CHECK-NEXT: [[TMP18:%.*]] = or i64 [[TMP17]], 17592186044416
; CHECK-NEXT: [[TMP19:%.*]] = inttoptr i64 [[TMP18]] to ptr ; CHECK-NEXT: [[TMP19:%.*]] = inttoptr i64 [[TMP18]] to ptr
; CHECK-NEXT: [[TMP20:%.*]] = load i8, ptr [[TMP19]], align 1 ; CHECK-NEXT: [[TMP20:%.*]] = load i8, ptr [[TMP19]], align 1
; CHECK-NEXT: [[TMP21:%.*]] = icmp ne i8 [[TMP20]], 0 ; CHECK-NEXT: [[TMP21:%.*]] = icmp ne i8 [[TMP20]], 0
; CHECK-NEXT: br i1 [[TMP21]], label [[TMP22:%.*]], label [[TMP27:%.*]], !prof [[PROF0]] ; CHECK-NEXT: br i1 [[TMP21]], label [[TMP22:%.*]], label [[TMP27:%.*]], !prof [[PROF0]]
; CHECK: 22: ; CHECK: 22:
; CHECK-NEXT: [[TMP23:%.*]] = and i64 [[TMP16]], 7 ; CHECK-NEXT: [[TMP23:%.*]] = and i64 [[TMP16]], 7
; CHECK-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP23]] to i8 ; CHECK-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP23]] to i8
; CHECK-NEXT: [[TMP25:%.*]] = icmp sge i8 [[TMP24]], [[TMP20]] ; CHECK-NEXT: [[TMP25:%.*]] = icmp sge i8 [[TMP24]], [[TMP20]]
; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP27]] ; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP27]]
; CHECK: 26: ; CHECK: 26:
; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP16]], i64 32) #[[ATTR3]] ; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP16]], i64 32) #[[ATTR4]]
; CHECK-NEXT: unreachable ; CHECK-NEXT: unreachable
; CHECK: 27: ; CHECK: 27:
; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr [[P]], align 32 ; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr [[P]], align 32
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; CALLS-LABEL: @store.v8i32( ; CALLS-LABEL: @store.v8i32(
; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64 ; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CALLS-NEXT: call void @__asan_storeN(i64 [[TMP1]], i64 32) ; CALLS-NEXT: call void @__asan_storeN(i64 [[TMP1]], i64 32)
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; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i8 [[TMP8]], 0 ; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i8 [[TMP8]], 0
; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP15:%.*]], !prof [[PROF0]] ; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP15:%.*]], !prof [[PROF0]]
; CHECK: 10: ; CHECK: 10:
; CHECK-NEXT: [[TMP11:%.*]] = and i64 [[TMP4]], 7 ; CHECK-NEXT: [[TMP11:%.*]] = and i64 [[TMP4]], 7
; CHECK-NEXT: [[TMP12:%.*]] = trunc i64 [[TMP11]] to i8 ; CHECK-NEXT: [[TMP12:%.*]] = trunc i64 [[TMP11]] to i8
; CHECK-NEXT: [[TMP13:%.*]] = icmp sge i8 [[TMP12]], [[TMP8]] ; CHECK-NEXT: [[TMP13:%.*]] = icmp sge i8 [[TMP12]], [[TMP8]]
; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP15]] ; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP15]]
; CHECK: 14: ; CHECK: 14:
; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP4]], i64 64) #[[ATTR3]] ; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP4]], i64 64) #[[ATTR4]]
; CHECK-NEXT: unreachable ; CHECK-NEXT: unreachable
; CHECK: 15: ; CHECK: 15:
; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[TMP3]] to i64 ; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[TMP3]] to i64
; CHECK-NEXT: [[TMP17:%.*]] = lshr i64 [[TMP16]], 3 ; CHECK-NEXT: [[TMP17:%.*]] = lshr i64 [[TMP16]], 3
; CHECK-NEXT: [[TMP18:%.*]] = or i64 [[TMP17]], 17592186044416 ; CHECK-NEXT: [[TMP18:%.*]] = or i64 [[TMP17]], 17592186044416
; CHECK-NEXT: [[TMP19:%.*]] = inttoptr i64 [[TMP18]] to ptr ; CHECK-NEXT: [[TMP19:%.*]] = inttoptr i64 [[TMP18]] to ptr
; CHECK-NEXT: [[TMP20:%.*]] = load i8, ptr [[TMP19]], align 1 ; CHECK-NEXT: [[TMP20:%.*]] = load i8, ptr [[TMP19]], align 1
; CHECK-NEXT: [[TMP21:%.*]] = icmp ne i8 [[TMP20]], 0 ; CHECK-NEXT: [[TMP21:%.*]] = icmp ne i8 [[TMP20]], 0
; CHECK-NEXT: br i1 [[TMP21]], label [[TMP22:%.*]], label [[TMP27:%.*]], !prof [[PROF0]] ; CHECK-NEXT: br i1 [[TMP21]], label [[TMP22:%.*]], label [[TMP27:%.*]], !prof [[PROF0]]
; CHECK: 22: ; CHECK: 22:
; CHECK-NEXT: [[TMP23:%.*]] = and i64 [[TMP16]], 7 ; CHECK-NEXT: [[TMP23:%.*]] = and i64 [[TMP16]], 7
; CHECK-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP23]] to i8 ; CHECK-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP23]] to i8
; CHECK-NEXT: [[TMP25:%.*]] = icmp sge i8 [[TMP24]], [[TMP20]] ; CHECK-NEXT: [[TMP25:%.*]] = icmp sge i8 [[TMP24]], [[TMP20]]
; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP27]] ; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP27]]
; CHECK: 26: ; CHECK: 26:
; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP16]], i64 64) #[[ATTR3]] ; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP16]], i64 64) #[[ATTR4]]
; CHECK-NEXT: unreachable ; CHECK-NEXT: unreachable
; CHECK: 27: ; CHECK: 27:
; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr [[P]], align 64 ; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr [[P]], align 64
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; CALLS-LABEL: @store.v16i32( ; CALLS-LABEL: @store.v16i32(
; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64 ; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CALLS-NEXT: call void @__asan_storeN(i64 [[TMP1]], i64 64) ; CALLS-NEXT: call void @__asan_storeN(i64 [[TMP1]], i64 64)
; CALLS-NEXT: store <16 x i32> zeroinitializer, ptr [[P]], align 64 ; CALLS-NEXT: store <16 x i32> zeroinitializer, ptr [[P]], align 64
; CALLS-NEXT: ret void ; CALLS-NEXT: ret void
; ;
store <16 x i32> zeroinitializer, ptr %p store <16 x i32> zeroinitializer, ptr %p
ret void ret void
} }
define void @load.nxv1i32(ptr %p) sanitize_address {
; CHECK-LABEL: @load.nxv1i32(
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 32
; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3
; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[TMP3]], 1
; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr
; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[P]] to i64
; CHECK-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP8]], 3
; CHECK-NEXT: [[TMP10:%.*]] = or i64 [[TMP9]], 17592186044416
; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr
; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP11]], align 1
; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0
; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP19:%.*]], !prof [[PROF0]]
; CHECK: 14:
; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP8]], 7
; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i8
; CHECK-NEXT: [[TMP17:%.*]] = icmp sge i8 [[TMP16]], [[TMP12]]
; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP19]]
; CHECK: 18:
; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP8]], i64 [[TMP3]]) #[[ATTR4]]
; CHECK-NEXT: unreachable
; CHECK: 19:
; CHECK-NEXT: [[TMP20:%.*]] = ptrtoint ptr [[TMP7]] to i64
; CHECK-NEXT: [[TMP21:%.*]] = lshr i64 [[TMP20]], 3
; CHECK-NEXT: [[TMP22:%.*]] = or i64 [[TMP21]], 17592186044416
; CHECK-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP22]] to ptr
; CHECK-NEXT: [[TMP24:%.*]] = load i8, ptr [[TMP23]], align 1
; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i8 [[TMP24]], 0
; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP31:%.*]], !prof [[PROF0]]
; CHECK: 26:
; CHECK-NEXT: [[TMP27:%.*]] = and i64 [[TMP20]], 7
; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i8
; CHECK-NEXT: [[TMP29:%.*]] = icmp sge i8 [[TMP28]], [[TMP24]]
; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP31]]
; CHECK: 30:
; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP20]], i64 [[TMP3]]) #[[ATTR4]]
; CHECK-NEXT: unreachable
; CHECK: 31:
; CHECK-NEXT: [[TMP32:%.*]] = load <vscale x 1 x i32>, ptr [[P]], align 4
; CHECK-NEXT: ret void
;
; CALLS-LABEL: @load.nxv1i32(
; CALLS-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CALLS-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 32
; CALLS-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3
; CALLS-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CALLS-NEXT: call void @__asan_loadN(i64 [[TMP4]], i64 [[TMP3]])
; CALLS-NEXT: [[TMP5:%.*]] = load <vscale x 1 x i32>, ptr [[P]], align 4
; CALLS-NEXT: ret void
;
load <vscale x 1 x i32>, ptr %p
ret void
}
define void @load.nxv2i32(ptr %p) sanitize_address {
; CHECK-LABEL: @load.nxv2i32(
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 64
; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3
; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[TMP3]], 1
; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr
; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[P]] to i64
; CHECK-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP8]], 3
; CHECK-NEXT: [[TMP10:%.*]] = or i64 [[TMP9]], 17592186044416
; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr
; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP11]], align 1
; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0
; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP19:%.*]], !prof [[PROF0]]
; CHECK: 14:
; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP8]], 7
; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i8
; CHECK-NEXT: [[TMP17:%.*]] = icmp sge i8 [[TMP16]], [[TMP12]]
; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP19]]
; CHECK: 18:
; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP8]], i64 [[TMP3]]) #[[ATTR4]]
; CHECK-NEXT: unreachable
; CHECK: 19:
; CHECK-NEXT: [[TMP20:%.*]] = ptrtoint ptr [[TMP7]] to i64
; CHECK-NEXT: [[TMP21:%.*]] = lshr i64 [[TMP20]], 3
; CHECK-NEXT: [[TMP22:%.*]] = or i64 [[TMP21]], 17592186044416
; CHECK-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP22]] to ptr
; CHECK-NEXT: [[TMP24:%.*]] = load i8, ptr [[TMP23]], align 1
; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i8 [[TMP24]], 0
; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP31:%.*]], !prof [[PROF0]]
; CHECK: 26:
; CHECK-NEXT: [[TMP27:%.*]] = and i64 [[TMP20]], 7
; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i8
; CHECK-NEXT: [[TMP29:%.*]] = icmp sge i8 [[TMP28]], [[TMP24]]
; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP31]]
; CHECK: 30:
; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP20]], i64 [[TMP3]]) #[[ATTR4]]
; CHECK-NEXT: unreachable
; CHECK: 31:
; CHECK-NEXT: [[TMP32:%.*]] = load <vscale x 2 x i32>, ptr [[P]], align 8
; CHECK-NEXT: ret void
;
; CALLS-LABEL: @load.nxv2i32(
; CALLS-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CALLS-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 64
; CALLS-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3
; CALLS-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CALLS-NEXT: call void @__asan_loadN(i64 [[TMP4]], i64 [[TMP3]])
; CALLS-NEXT: [[TMP5:%.*]] = load <vscale x 2 x i32>, ptr [[P]], align 8
; CALLS-NEXT: ret void
;
load <vscale x 2 x i32>, ptr %p
ret void
}
define void @load.nxv4i32(ptr %p) sanitize_address {
; CHECK-LABEL: @load.nxv4i32(
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 128
; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3
; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[TMP3]], 1
; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr
; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[P]] to i64
; CHECK-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP8]], 3
; CHECK-NEXT: [[TMP10:%.*]] = or i64 [[TMP9]], 17592186044416
; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr
; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP11]], align 1
; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0
; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP19:%.*]], !prof [[PROF0]]
; CHECK: 14:
; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP8]], 7
; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i8
; CHECK-NEXT: [[TMP17:%.*]] = icmp sge i8 [[TMP16]], [[TMP12]]
; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP19]]
; CHECK: 18:
; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP8]], i64 [[TMP3]]) #[[ATTR4]]
; CHECK-NEXT: unreachable
; CHECK: 19:
; CHECK-NEXT: [[TMP20:%.*]] = ptrtoint ptr [[TMP7]] to i64
; CHECK-NEXT: [[TMP21:%.*]] = lshr i64 [[TMP20]], 3
; CHECK-NEXT: [[TMP22:%.*]] = or i64 [[TMP21]], 17592186044416
; CHECK-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP22]] to ptr
; CHECK-NEXT: [[TMP24:%.*]] = load i8, ptr [[TMP23]], align 1
; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i8 [[TMP24]], 0
; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP31:%.*]], !prof [[PROF0]]
; CHECK: 26:
; CHECK-NEXT: [[TMP27:%.*]] = and i64 [[TMP20]], 7
; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i8
; CHECK-NEXT: [[TMP29:%.*]] = icmp sge i8 [[TMP28]], [[TMP24]]
; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP31]]
; CHECK: 30:
; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP20]], i64 [[TMP3]]) #[[ATTR4]]
; CHECK-NEXT: unreachable
; CHECK: 31:
; CHECK-NEXT: [[TMP32:%.*]] = load <vscale x 4 x i32>, ptr [[P]], align 16
; CHECK-NEXT: ret void
;
; CALLS-LABEL: @load.nxv4i32(
; CALLS-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CALLS-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 128
; CALLS-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3
; CALLS-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CALLS-NEXT: call void @__asan_loadN(i64 [[TMP4]], i64 [[TMP3]])
; CALLS-NEXT: [[TMP5:%.*]] = load <vscale x 4 x i32>, ptr [[P]], align 16
; CALLS-NEXT: ret void
;
load <vscale x 4 x i32>, ptr %p
ret void
}
define void @load.nxv8i32(ptr %p) sanitize_address {
; CHECK-LABEL: @load.nxv8i32(
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 256
; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3
; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[TMP3]], 1
; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr
; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[P]] to i64
; CHECK-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP8]], 3
; CHECK-NEXT: [[TMP10:%.*]] = or i64 [[TMP9]], 17592186044416
; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr
; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP11]], align 1
; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0
; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP19:%.*]], !prof [[PROF0]]
; CHECK: 14:
; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP8]], 7
; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i8
; CHECK-NEXT: [[TMP17:%.*]] = icmp sge i8 [[TMP16]], [[TMP12]]
; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP19]]
; CHECK: 18:
; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP8]], i64 [[TMP3]]) #[[ATTR4]]
; CHECK-NEXT: unreachable
; CHECK: 19:
; CHECK-NEXT: [[TMP20:%.*]] = ptrtoint ptr [[TMP7]] to i64
; CHECK-NEXT: [[TMP21:%.*]] = lshr i64 [[TMP20]], 3
; CHECK-NEXT: [[TMP22:%.*]] = or i64 [[TMP21]], 17592186044416
; CHECK-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP22]] to ptr
; CHECK-NEXT: [[TMP24:%.*]] = load i8, ptr [[TMP23]], align 1
; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i8 [[TMP24]], 0
; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP31:%.*]], !prof [[PROF0]]
; CHECK: 26:
; CHECK-NEXT: [[TMP27:%.*]] = and i64 [[TMP20]], 7
; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i8
; CHECK-NEXT: [[TMP29:%.*]] = icmp sge i8 [[TMP28]], [[TMP24]]
; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP31]]
; CHECK: 30:
; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP20]], i64 [[TMP3]]) #[[ATTR4]]
; CHECK-NEXT: unreachable
; CHECK: 31:
; CHECK-NEXT: [[TMP32:%.*]] = load <vscale x 8 x i32>, ptr [[P]], align 32
; CHECK-NEXT: ret void
;
; CALLS-LABEL: @load.nxv8i32(
; CALLS-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CALLS-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 256
; CALLS-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3
; CALLS-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CALLS-NEXT: call void @__asan_loadN(i64 [[TMP4]], i64 [[TMP3]])
; CALLS-NEXT: [[TMP5:%.*]] = load <vscale x 8 x i32>, ptr [[P]], align 32
; CALLS-NEXT: ret void
;
load <vscale x 8 x i32>, ptr %p
ret void
}
define void @load.nxv16i32(ptr %p) sanitize_address {
; CHECK-LABEL: @load.nxv16i32(
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 512
; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3
; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[TMP3]], 1
; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr
; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[P]] to i64
; CHECK-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP8]], 3
; CHECK-NEXT: [[TMP10:%.*]] = or i64 [[TMP9]], 17592186044416
; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr
; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP11]], align 1
; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0
; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP19:%.*]], !prof [[PROF0]]
; CHECK: 14:
; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP8]], 7
; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i8
; CHECK-NEXT: [[TMP17:%.*]] = icmp sge i8 [[TMP16]], [[TMP12]]
; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP19]]
; CHECK: 18:
; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP8]], i64 [[TMP3]]) #[[ATTR4]]
; CHECK-NEXT: unreachable
; CHECK: 19:
; CHECK-NEXT: [[TMP20:%.*]] = ptrtoint ptr [[TMP7]] to i64
; CHECK-NEXT: [[TMP21:%.*]] = lshr i64 [[TMP20]], 3
; CHECK-NEXT: [[TMP22:%.*]] = or i64 [[TMP21]], 17592186044416
; CHECK-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP22]] to ptr
; CHECK-NEXT: [[TMP24:%.*]] = load i8, ptr [[TMP23]], align 1
; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i8 [[TMP24]], 0
; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP31:%.*]], !prof [[PROF0]]
; CHECK: 26:
; CHECK-NEXT: [[TMP27:%.*]] = and i64 [[TMP20]], 7
; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i8
; CHECK-NEXT: [[TMP29:%.*]] = icmp sge i8 [[TMP28]], [[TMP24]]
; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP31]]
; CHECK: 30:
; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP20]], i64 [[TMP3]]) #[[ATTR4]]
; CHECK-NEXT: unreachable
; CHECK: 31:
; CHECK-NEXT: [[TMP32:%.*]] = load <vscale x 16 x i32>, ptr [[P]], align 64
; CHECK-NEXT: ret void
;
; CALLS-LABEL: @load.nxv16i32(
; CALLS-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CALLS-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 512
; CALLS-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3
; CALLS-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CALLS-NEXT: call void @__asan_loadN(i64 [[TMP4]], i64 [[TMP3]])
; CALLS-NEXT: [[TMP5:%.*]] = load <vscale x 16 x i32>, ptr [[P]], align 64
; CALLS-NEXT: ret void
;
load <vscale x 16 x i32>, ptr %p
ret void
}
define void @store.nxv1i32(ptr %p) sanitize_address {
; CHECK-LABEL: @store.nxv1i32(
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 32
; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3
; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[TMP3]], 1
; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr
; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[P]] to i64
; CHECK-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP8]], 3
; CHECK-NEXT: [[TMP10:%.*]] = or i64 [[TMP9]], 17592186044416
; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr
; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP11]], align 1
; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0
; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP19:%.*]], !prof [[PROF0]]
; CHECK: 14:
; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP8]], 7
; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i8
; CHECK-NEXT: [[TMP17:%.*]] = icmp sge i8 [[TMP16]], [[TMP12]]
; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP19]]
; CHECK: 18:
; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP8]], i64 [[TMP3]]) #[[ATTR4]]
; CHECK-NEXT: unreachable
; CHECK: 19:
; CHECK-NEXT: [[TMP20:%.*]] = ptrtoint ptr [[TMP7]] to i64
; CHECK-NEXT: [[TMP21:%.*]] = lshr i64 [[TMP20]], 3
; CHECK-NEXT: [[TMP22:%.*]] = or i64 [[TMP21]], 17592186044416
; CHECK-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP22]] to ptr
; CHECK-NEXT: [[TMP24:%.*]] = load i8, ptr [[TMP23]], align 1
; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i8 [[TMP24]], 0
; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP31:%.*]], !prof [[PROF0]]
; CHECK: 26:
; CHECK-NEXT: [[TMP27:%.*]] = and i64 [[TMP20]], 7
; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i8
; CHECK-NEXT: [[TMP29:%.*]] = icmp sge i8 [[TMP28]], [[TMP24]]
; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP31]]
; CHECK: 30:
; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP20]], i64 [[TMP3]]) #[[ATTR4]]
; CHECK-NEXT: unreachable
; CHECK: 31:
; CHECK-NEXT: store <vscale x 1 x i32> zeroinitializer, ptr [[P]], align 4
; CHECK-NEXT: ret void
;
; CALLS-LABEL: @store.nxv1i32(
; CALLS-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CALLS-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 32
; CALLS-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3
; CALLS-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CALLS-NEXT: call void @__asan_storeN(i64 [[TMP4]], i64 [[TMP3]])
; CALLS-NEXT: store <vscale x 1 x i32> zeroinitializer, ptr [[P]], align 4
; CALLS-NEXT: ret void
;
store <vscale x 1 x i32> zeroinitializer, ptr %p
ret void
}
define void @store.nxv2i32(ptr %p) sanitize_address {
; CHECK-LABEL: @store.nxv2i32(
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 64
; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3
; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[TMP3]], 1
; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr
; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[P]] to i64
; CHECK-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP8]], 3
; CHECK-NEXT: [[TMP10:%.*]] = or i64 [[TMP9]], 17592186044416
; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr
; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP11]], align 1
; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0
; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP19:%.*]], !prof [[PROF0]]
; CHECK: 14:
; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP8]], 7
; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i8
; CHECK-NEXT: [[TMP17:%.*]] = icmp sge i8 [[TMP16]], [[TMP12]]
; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP19]]
; CHECK: 18:
; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP8]], i64 [[TMP3]]) #[[ATTR4]]
; CHECK-NEXT: unreachable
; CHECK: 19:
; CHECK-NEXT: [[TMP20:%.*]] = ptrtoint ptr [[TMP7]] to i64
; CHECK-NEXT: [[TMP21:%.*]] = lshr i64 [[TMP20]], 3
; CHECK-NEXT: [[TMP22:%.*]] = or i64 [[TMP21]], 17592186044416
; CHECK-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP22]] to ptr
; CHECK-NEXT: [[TMP24:%.*]] = load i8, ptr [[TMP23]], align 1
; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i8 [[TMP24]], 0
; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP31:%.*]], !prof [[PROF0]]
; CHECK: 26:
; CHECK-NEXT: [[TMP27:%.*]] = and i64 [[TMP20]], 7
; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i8
; CHECK-NEXT: [[TMP29:%.*]] = icmp sge i8 [[TMP28]], [[TMP24]]
; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP31]]
; CHECK: 30:
; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP20]], i64 [[TMP3]]) #[[ATTR4]]
; CHECK-NEXT: unreachable
; CHECK: 31:
; CHECK-NEXT: store <vscale x 2 x i32> zeroinitializer, ptr [[P]], align 8
; CHECK-NEXT: ret void
;
; CALLS-LABEL: @store.nxv2i32(
; CALLS-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CALLS-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 64
; CALLS-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3
; CALLS-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CALLS-NEXT: call void @__asan_storeN(i64 [[TMP4]], i64 [[TMP3]])
; CALLS-NEXT: store <vscale x 2 x i32> zeroinitializer, ptr [[P]], align 8
; CALLS-NEXT: ret void
;
store <vscale x 2 x i32> zeroinitializer, ptr %p
ret void
}
define void @store.nxv4i32(ptr %p) sanitize_address {
; CHECK-LABEL: @store.nxv4i32(
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 128
; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3
; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[TMP3]], 1
; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr
; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[P]] to i64
; CHECK-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP8]], 3
; CHECK-NEXT: [[TMP10:%.*]] = or i64 [[TMP9]], 17592186044416
; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr
; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP11]], align 1
; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0
; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP19:%.*]], !prof [[PROF0]]
; CHECK: 14:
; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP8]], 7
; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i8
; CHECK-NEXT: [[TMP17:%.*]] = icmp sge i8 [[TMP16]], [[TMP12]]
; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP19]]
; CHECK: 18:
; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP8]], i64 [[TMP3]]) #[[ATTR4]]
; CHECK-NEXT: unreachable
; CHECK: 19:
; CHECK-NEXT: [[TMP20:%.*]] = ptrtoint ptr [[TMP7]] to i64
; CHECK-NEXT: [[TMP21:%.*]] = lshr i64 [[TMP20]], 3
; CHECK-NEXT: [[TMP22:%.*]] = or i64 [[TMP21]], 17592186044416
; CHECK-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP22]] to ptr
; CHECK-NEXT: [[TMP24:%.*]] = load i8, ptr [[TMP23]], align 1
; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i8 [[TMP24]], 0
; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP31:%.*]], !prof [[PROF0]]
; CHECK: 26:
; CHECK-NEXT: [[TMP27:%.*]] = and i64 [[TMP20]], 7
; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i8
; CHECK-NEXT: [[TMP29:%.*]] = icmp sge i8 [[TMP28]], [[TMP24]]
; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP31]]
; CHECK: 30:
; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP20]], i64 [[TMP3]]) #[[ATTR4]]
; CHECK-NEXT: unreachable
; CHECK: 31:
; CHECK-NEXT: store <vscale x 4 x i32> zeroinitializer, ptr [[P]], align 16
; CHECK-NEXT: ret void
;
; CALLS-LABEL: @store.nxv4i32(
; CALLS-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CALLS-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 128
; CALLS-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3
; CALLS-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CALLS-NEXT: call void @__asan_storeN(i64 [[TMP4]], i64 [[TMP3]])
; CALLS-NEXT: store <vscale x 4 x i32> zeroinitializer, ptr [[P]], align 16
; CALLS-NEXT: ret void
;
store <vscale x 4 x i32> zeroinitializer, ptr %p
ret void
}
define void @store.nxv8i32(ptr %p) sanitize_address {
; CHECK-LABEL: @store.nxv8i32(
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 256
; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3
; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[TMP3]], 1
; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr
; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[P]] to i64
; CHECK-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP8]], 3
; CHECK-NEXT: [[TMP10:%.*]] = or i64 [[TMP9]], 17592186044416
; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr
; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP11]], align 1
; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0
; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP19:%.*]], !prof [[PROF0]]
; CHECK: 14:
; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP8]], 7
; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i8
; CHECK-NEXT: [[TMP17:%.*]] = icmp sge i8 [[TMP16]], [[TMP12]]
; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP19]]
; CHECK: 18:
; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP8]], i64 [[TMP3]]) #[[ATTR4]]
; CHECK-NEXT: unreachable
; CHECK: 19:
; CHECK-NEXT: [[TMP20:%.*]] = ptrtoint ptr [[TMP7]] to i64
; CHECK-NEXT: [[TMP21:%.*]] = lshr i64 [[TMP20]], 3
; CHECK-NEXT: [[TMP22:%.*]] = or i64 [[TMP21]], 17592186044416
; CHECK-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP22]] to ptr
; CHECK-NEXT: [[TMP24:%.*]] = load i8, ptr [[TMP23]], align 1
; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i8 [[TMP24]], 0
; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP31:%.*]], !prof [[PROF0]]
; CHECK: 26:
; CHECK-NEXT: [[TMP27:%.*]] = and i64 [[TMP20]], 7
; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i8
; CHECK-NEXT: [[TMP29:%.*]] = icmp sge i8 [[TMP28]], [[TMP24]]
; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP31]]
; CHECK: 30:
; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP20]], i64 [[TMP3]]) #[[ATTR4]]
; CHECK-NEXT: unreachable
; CHECK: 31:
; CHECK-NEXT: store <vscale x 8 x i32> zeroinitializer, ptr [[P]], align 32
; CHECK-NEXT: ret void
;
; CALLS-LABEL: @store.nxv8i32(
; CALLS-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CALLS-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 256
; CALLS-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3
; CALLS-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CALLS-NEXT: call void @__asan_storeN(i64 [[TMP4]], i64 [[TMP3]])
; CALLS-NEXT: store <vscale x 8 x i32> zeroinitializer, ptr [[P]], align 32
; CALLS-NEXT: ret void
;
store <vscale x 8 x i32> zeroinitializer, ptr %p
ret void
}
define void @store.nxv16i32(ptr %p) sanitize_address {
; CHECK-LABEL: @store.nxv16i32(
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 512
; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3
; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[TMP3]], 1
; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr
; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[P]] to i64
; CHECK-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP8]], 3
; CHECK-NEXT: [[TMP10:%.*]] = or i64 [[TMP9]], 17592186044416
; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr
; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP11]], align 1
; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0
; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP19:%.*]], !prof [[PROF0]]
; CHECK: 14:
; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP8]], 7
; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i8
; CHECK-NEXT: [[TMP17:%.*]] = icmp sge i8 [[TMP16]], [[TMP12]]
; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP19]]
; CHECK: 18:
; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP8]], i64 [[TMP3]]) #[[ATTR4]]
; CHECK-NEXT: unreachable
; CHECK: 19:
; CHECK-NEXT: [[TMP20:%.*]] = ptrtoint ptr [[TMP7]] to i64
; CHECK-NEXT: [[TMP21:%.*]] = lshr i64 [[TMP20]], 3
; CHECK-NEXT: [[TMP22:%.*]] = or i64 [[TMP21]], 17592186044416
; CHECK-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP22]] to ptr
; CHECK-NEXT: [[TMP24:%.*]] = load i8, ptr [[TMP23]], align 1
; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i8 [[TMP24]], 0
; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP31:%.*]], !prof [[PROF0]]
; CHECK: 26:
; CHECK-NEXT: [[TMP27:%.*]] = and i64 [[TMP20]], 7
; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i8
; CHECK-NEXT: [[TMP29:%.*]] = icmp sge i8 [[TMP28]], [[TMP24]]
; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP31]]
; CHECK: 30:
; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP20]], i64 [[TMP3]]) #[[ATTR4]]
; CHECK-NEXT: unreachable
; CHECK: 31:
; CHECK-NEXT: store <vscale x 16 x i32> zeroinitializer, ptr [[P]], align 64
; CHECK-NEXT: ret void
;
; CALLS-LABEL: @store.nxv16i32(
; CALLS-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CALLS-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 512
; CALLS-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3
; CALLS-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CALLS-NEXT: call void @__asan_storeN(i64 [[TMP4]], i64 [[TMP3]])
; CALLS-NEXT: store <vscale x 16 x i32> zeroinitializer, ptr [[P]], align 64
; CALLS-NEXT: ret void
;
store <vscale x 16 x i32> zeroinitializer, ptr %p
ret void
}