[SPIR-V] Promote arbitrary width ints to regular width

[mpaszkowski]

Summary

After this patch all arbitrary size integers (smaller than 64 bits) in LLVM IR will be promoted to regular size type in SPIR-V (OpTypeInt 8/16/32/64).

Support for generating arbitrary size integer types in SPIR-V with SPV_INTEL_arbitrary_precision_integers extension will be added in the following patch.

[iliya-diyachkov]

It looks good to me.

[arsenm]

Why is this not changing any legalizer rules?

[mpaszkowski]

In D145137#4182622, @arsenm wrote:

Why is this not changing any legalizer rules?

@arsenm In MIR still only legal int widths are 8/16/32/64 bits. I assume that the next patch adding the support for SPV_INTEL_arbitrary_precision_integers extension should change the legalizer rules.

llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp

 SPIRVType *SPIRVGlobalRegistry::getOpTypeBool(MachineIRBuilder &MIRBuilder) {
   return MIRBuilder.buildInstr(SPIRV::OpTypeBool)
       .addDef(createTypeVReg(MIRBuilder));
 }
 
 SPIRVType *SPIRVGlobalRegistry::getOpTypeInt(uint32_t Width,
                                              MachineIRBuilder &MIRBuilder,
                                              bool IsSigned) {
+  assert(Width <= 64 && "Unsupported integer width!");
+  if (Width <= 8)
+    Width = 8;
+  else if (Width <= 16)
+    Width = 16;
+  else if (Width <= 32)
+    Width = 32;
+  else if (Width <= 64)
+    Width = 64;
+
   auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeInt)
                  .addDef(createTypeVReg(MIRBuilder))
                  .addImm(Width)
                  .addImm(IsSigned ? 1 : 0);
   return MIB;
 }
 
 SPIRVType *SPIRVGlobalRegistry::getOpTypeFloat(uint32_t Width,

llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp

unsigned SPIRVTargetLowering::getNumRegistersForCallingConv(
     LLVMContext &Context, CallingConv::ID CC, EVT VT) const {
   // This code avoids CallLowering fail inside getVectorTypeBreakdown
   // on v3i1 arguments. Maybe we need to return 1 for all types.
   // TODO: remove it once this case is supported by the default implementation.
   if (VT.isVector() && VT.getVectorNumElements() == 3 &&
       (VT.getVectorElementType() == MVT::i1 ||
        VT.getVectorElementType() == MVT::i8))
     return 1;
+  if (!VT.isVector() && VT.isInteger() && VT.getSizeInBits() <= 64)
+    return 1;
   return getNumRegisters(Context, VT);
 }
 
 MVT SPIRVTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
                                                        CallingConv::ID CC,
                                                        EVT VT) const {
   // This code avoids CallLowering fail inside getVectorTypeBreakdown
   // on v3i1 arguments. Maybe we need to return i32 for all types.

llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

bool SPIRVInstructionSelector::selectConst(Register ResVReg,
   MachineBasicBlock &BB = *I.getParent();
   if ((TyOpcode == SPIRV::OpTypePointer || TyOpcode == SPIRV::OpTypeEvent) &&
       Imm.isZero())
     return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantNull))
         .addDef(ResVReg)
         .addUse(GR.getSPIRVTypeID(ResType))
         .constrainAllUses(TII, TRI, RBI);
   if (TyOpcode == SPIRV::OpTypeInt) {
+    assert(Imm.getBitWidth() <= 64 && "Unsupported integer width!");
     Register Reg = GR.getOrCreateConstInt(Imm.getZExtValue(), I, ResType, TII);
     if (Reg == ResVReg)
       return true;
     return BuildMI(BB, I, I.getDebugLoc(), TII.get(TargetOpcode::COPY))
         .addDef(ResVReg)
         .addUse(Reg)
         .constrainAllUses(TII, TRI, RBI);
   }

llvm/lib/Target/SPIRV/SPIRVUtils.cpp

 }
 
 std::string getStringImm(const MachineInstr &MI, unsigned StartIndex) {
   return getSPIRVStringOperand(MI, StartIndex);
 }
 
 void addNumImm(const APInt &Imm, MachineInstrBuilder &MIB) {
   const auto Bitwidth = Imm.getBitWidth();
-  switch (Bitwidth) {
-  case 1:
-    break; // Already handled.
-  case 8:
-  case 16:
-  case 32:
+  if (Bitwidth == 1)
+    return; // Already handled
+  else if (Bitwidth <= 32) {
     MIB.addImm(Imm.getZExtValue());
-    break;
-  case 64: {
+    return;
+  } else if (Bitwidth <= 64) {
     uint64_t FullImm = Imm.getZExtValue();
     uint32_t LowBits = FullImm & 0xffffffff;
     uint32_t HighBits = (FullImm >> 32) & 0xffffffff;
     MIB.addImm(LowBits).addImm(HighBits);
-    break;
+    return;
   }
-  default:
-    report_fatal_error("Unsupported constant bitwidth");
-  }
-}
 
 void buildOpName(Register Target, const StringRef &Name,
                  MachineIRBuilder &MIRBuilder) {
   if (!Name.empty()) {
     auto MIB = MIRBuilder.buildInstr(SPIRV::OpName).addUse(Target);
     addStringImm(Name, MIB);
   }
 }

llvm/test/CodeGen/SPIRV/constant/local-arbitrary-width-integers-constants-type-promotion.ll

+; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
+
+define i4 @getConstantI4() {
+  ret i4 2 ; i4 => OpTypeInt 8
+}
+
+define i11 @getConstantI11() {
+  ret i11 7 ; i11 => OpTypeInt 16
+}
+
+define i24 @getConstantI24() {
+  ret i24 42 ; i24 => OpTypeInt 32
+}
+
+define i63 @getConstantI63() {
+  ret i63 5705 ; i63 => OpTypeInt 64
+}
+
+;; Capabilities:
+; CHECK-DAG: OpCapability Int8
+; CHECK-DAG: OpCapability Int16
+; CHECK-DAG: OpCapability Int64
+
+; CHECK-NOT: DAG-FENCE
+
+;; Names:
+; CHECK-DAG: OpName %[[#GET_I4:]] "getConstantI4"
+; CHECK-DAG: OpName %[[#GET_I11:]] "getConstantI11"
+; CHECK-DAG: OpName %[[#GET_I24:]] "getConstantI24"
+; CHECK-DAG: OpName %[[#GET_I63:]] "getConstantI63"
+
+; CHECK-NOT: DAG-FENCE
+
+;; Types and Constants:
+; CHECK-DAG: %[[#I8:]] = OpTypeInt 8 0
+; CHECK-DAG: %[[#I16:]] = OpTypeInt 16 0
+; CHECK-DAG: %[[#I32:]] = OpTypeInt 32 0
+; CHECK-DAG: %[[#I64:]] = OpTypeInt 64 0
+; CHECK-DAG: %[[#CST_I8:]] = OpConstant %[[#I8]] 2
+; CHECK-DAG: %[[#CST_I16:]] = OpConstant %[[#I16]] 7
+; CHECK-DAG: %[[#CST_I32:]] = OpConstant %[[#I32]] 42
+; CHECK-DAG: %[[#CST_I64:]] = OpConstant %[[#I64]] 5705
+
+; CHECK: %[[#GET_I4]] = OpFunction %[[#I8]]
+; CHECK: OpReturnValue %[[#CST_I8]]
+; CHECK: OpFunctionEnd
+
+; CHECK: %[[#GET_I11]] = OpFunction %[[#I16]]
+; CHECK: OpReturnValue %[[#CST_I16]]
+; CHECK: OpFunctionEnd
+
+; CHECK: %[[#GET_I24]] = OpFunction %[[#I32]]
+; CHECK: OpReturnValue %[[#CST_I32]]
+; CHECK: OpFunctionEnd
+
+; CHECK: %[[#GET_I63]] = OpFunction %[[#I64]]
+; CHECK: OpReturnValue %[[#CST_I64]]
+; CHECK: OpFunctionEnd

llvm/test/CodeGen/SPIRV/constant/local-integers-constants.ll

 ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
 
+define i8 @getConstantI8() {
+  ret i8 2
+}
+
 define i16 @getConstantI16() {
   ret i16 -58
 }
 
 define i32 @getConstantI32() {
   ret i32 42
 }
 
 define i64 @getConstantI64() {
   ret i64 123456789
 }
 
 define i64 @getLargeConstantI64() {
   ret i64 34359738368
 }
 
 ;; Capabilities:
+; CHECK-DAG: OpCapability Int8
 ; CHECK-DAG: OpCapability Int16
 ; CHECK-DAG: OpCapability Int64
 
 ; CHECK-NOT: DAG-FENCE
 
 ;; Names:
+; CHECK-DAG: OpName %[[#GET_I8:]] "getConstantI8"
 ; CHECK-DAG: OpName %[[#GET_I16:]] "getConstantI16"
 ; CHECK-DAG: OpName %[[#GET_I32:]] "getConstantI32"
 ; CHECK-DAG: OpName %[[#GET_I64:]] "getConstantI64"
 ; CHECK-DAG: OpName %[[#GET_LARGE_I64:]] "getLargeConstantI64"
 
 ; CHECK-NOT: DAG-FENCE
 
 ;; Types and Constants:
+; CHECK-DAG: %[[#I8:]] = OpTypeInt 8 0
 ; CHECK-DAG: %[[#I16:]] = OpTypeInt 16 0
 ; CHECK-DAG: %[[#I32:]] = OpTypeInt 32 0
 ; CHECK-DAG: %[[#I64:]] = OpTypeInt 64 0
+; CHECK-DAG: %[[#CST_I8:]] = OpConstant %[[#I8]] 2
 ; CHECK-DAG: %[[#CST_I16:]] = OpConstant %[[#I16]] 65478
 ; CHECK-DAG: %[[#CST_I32:]] = OpConstant %[[#I32]] 42
 ; CHECK-DAG: %[[#CST_I64:]] = OpConstant %[[#I64]] 123456789 0
 ; CHECK-DAG: %[[#CST_LARGE_I64:]] = OpConstant %[[#I64]] 0 8
 
+; CHECK: %[[#GET_I8]] = OpFunction %[[#I8]]
+; CHECK: OpReturnValue %[[#CST_I8]]
+; CHECK: OpFunctionEnd
+
 ; CHECK: %[[#GET_I16]] = OpFunction %[[#I16]]
 ; CHECK: OpReturnValue %[[#CST_I16]]
 ; CHECK: OpFunctionEnd
 
 ; CHECK: %[[#GET_I32]] = OpFunction %[[#I32]]
 ; CHECK: OpReturnValue %[[#CST_I32]]
 ; CHECK: OpFunctionEnd
 
 ; CHECK: %[[#GET_I64]] = OpFunction %[[#I64]]
 ; CHECK: OpReturnValue %[[#CST_I64]]
 ; CHECK: OpFunctionEnd
 
 ; CHECK: %[[#GET_LARGE_I64]] = OpFunction %[[#I64]]
 ; CHECK: OpReturnValue %[[#CST_LARGE_I64]]
 ; CHECK: OpFunctionEnd