Recommit "[X86] Add `TuningPreferShiftShuffle` for when Shifts are preferable to shuffles." (2nd Try)

[goldstein.w.n]

Summary

Move the opcode checks to after we have already verified we found a
valid shift instruction (0 < ShiftAmt) in matchUnaryPermuteShuffle
and lowerShuffleAsShift.

[goldstein.w.n]

Cover second case

[rupprecht]

Thanks! This seems to fix all the errors I was seeing before.

[goldstein.w.n]

Make full recommit

[pengfei]

I'm confused. Isn't the patch identical to D143786?

llvm/lib/Target/X86/X86ISelLowering.cpp

     // Attempt to match against byte/bit shifts.
     if (AllowIntDomain &&
         ((MaskVT.is128BitVector() && Subtarget.hasSSE2()) ||
          (MaskVT.is256BitVector() && Subtarget.hasAVX2()) ||
          (MaskVT.is512BitVector() && Subtarget.hasAVX512()))) {
       int ShiftAmt =
           matchShuffleAsShift(ShuffleVT, Shuffle, MaskScalarSizeInBits, Mask, 0,
                               Zeroable, Subtarget);
-      // Byte shifts can be slower so only match them on second attempt.
-      if (Order == 0 &&
-          (Shuffle == X86ISD::VSHLDQ || Shuffle == X86ISD::VSRLDQ))
-        continue;
       if (0 < ShiftAmt && (!ShuffleVT.is512BitVector() || Subtarget.hasBWI() ||
                            32 <= ShuffleVT.getScalarSizeInBits())) {
+        // Byte shifts can be slower so only match them on second attempt.
+        if (Order == 0 &&
+            (Shuffle == X86ISD::VSHLDQ || Shuffle == X86ISD::VSRLDQ))
+          continue;
+
         PermuteImm = (unsigned)ShiftAmt;
         return true;
       }
 
     }
   }
 
   return false;