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Differential D144954

[AMDGPU][AsmParser][NFC] Simplify parsing cache policies.
ClosedPublic

Authored by kosarev on Feb 28 2023, 4:39 AM.

Details

Reviewers
dp
arsenm
rampitec
foad
Commits
rGb06e5ad8a659: [AMDGPU][AsmParser][NFC] Simplify parsing cache policies.

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Event Timeline

kosarev created this revision.Feb 28 2023, 4:39 AM
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kosarev requested review of this revision.Feb 28 2023, 4:39 AM
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foad accepted this revision.Feb 28 2023, 5:46 AM

Seems obvious

This revision is now accepted and ready to land.Feb 28 2023, 5:46 AM
Harbormaster completed remote builds in B216437: Diff 501089.Feb 28 2023, 5:46 AM
This revision was landed with ongoing or failed builds.Mar 1 2023, 4:34 AM
Closed by commit rGb06e5ad8a659: [AMDGPU][AsmParser][NFC] Simplify parsing cache policies. (authored by kosarev). · Explain Why
This revision was automatically updated to reflect the committed changes.
kosarev added a commit: rGb06e5ad8a659: [AMDGPU][AsmParser][NFC] Simplify parsing cache policies..

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
AsmParser/
9 lines

Diff 501460

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 6,021 Lines • ▼ Show 20 Lines if (isGFX9() && ImmTy == AMDGPUOperand::ImmTyA16)
ImmTy = AMDGPUOperand::ImmTyR128A16; ImmTy = AMDGPUOperand::ImmTyR128A16;
Operands.push_back(AMDGPUOperand::CreateImm(this, Bit, S, ImmTy)); Operands.push_back(AMDGPUOperand::CreateImm(this, Bit, S, ImmTy));
return MatchOperand_Success; return MatchOperand_Success;
} }
unsigned AMDGPUAsmParser::getCPolKind(StringRef Id, StringRef Mnemo, unsigned AMDGPUAsmParser::getCPolKind(StringRef Id, StringRef Mnemo,
bool &Disabling) const { bool &Disabling) const {
Disabling = Id.startswith("no"); Disabling = Id.consume_front("no");
if (isGFX940() && !Mnemo.startswith("s_")) { if (isGFX940() && !Mnemo.startswith("s_")) {
return StringSwitch<unsigned>(Id) return StringSwitch<unsigned>(Id)
.Case("nt", AMDGPU::CPol::NT) .Case("nt", AMDGPU::CPol::NT)
.Case("nont", AMDGPU::CPol::NT)
.Case("sc0", AMDGPU::CPol::SC0) .Case("sc0", AMDGPU::CPol::SC0)
.Case("nosc0", AMDGPU::CPol::SC0)
.Case("sc1", AMDGPU::CPol::SC1) .Case("sc1", AMDGPU::CPol::SC1)
.Case("nosc1", AMDGPU::CPol::SC1)
.Default(0); .Default(0);
} }
return StringSwitch<unsigned>(Id) return StringSwitch<unsigned>(Id)
.Case("dlc", AMDGPU::CPol::DLC) .Case("dlc", AMDGPU::CPol::DLC)
.Case("nodlc", AMDGPU::CPol::DLC)
.Case("glc", AMDGPU::CPol::GLC) .Case("glc", AMDGPU::CPol::GLC)
.Case("noglc", AMDGPU::CPol::GLC)
.Case("scc", AMDGPU::CPol::SCC) .Case("scc", AMDGPU::CPol::SCC)
.Case("noscc", AMDGPU::CPol::SCC)
.Case("slc", AMDGPU::CPol::SLC) .Case("slc", AMDGPU::CPol::SLC)
.Case("noslc", AMDGPU::CPol::SLC)
.Default(0); .Default(0);
} }
OperandMatchResultTy OperandMatchResultTy
AMDGPUAsmParser::parseCPol(OperandVector &Operands) { AMDGPUAsmParser::parseCPol(OperandVector &Operands) {
StringRef Mnemo = ((AMDGPUOperand &)*Operands[0]).getToken(); StringRef Mnemo = ((AMDGPUOperand &)*Operands[0]).getToken();
SMLoc OpLoc = getLoc(); SMLoc OpLoc = getLoc();
unsigned Enabled = 0, Seen = 0; unsigned Enabled = 0, Seen = 0;
▲ Show 20 Lines • Show All 3,227 Lines • Show Last 20 Lines